AMIS-49200 Fieldbus MAU Data Sheet AMIS-49200 Fieldbus MAU Chip AMI Semiconductor – Jan. 07, M-20532-003 www.amis.com 1 AMIS-49200 Fieldbus MAU Data Sheet Table of Contents 1.0 Introduction........................................................................................................................................................................................... 3 1.1 Overview........................................................................................................................................................................................... 3 1.2 Definitions, Acronyms and Abbreviations.......................................................................................................................................... 3 1.3 References ....................................................................................................................................................................................... 3 2.0 AMIS-49200 Fieldbus MAU Description ............................................................................................................................................... 3 2.1 Features............................................................................................................................................................................................ 3 2.2 Block Diagram .................................................................................................................................................................................. 4 2.3 Package Information ......................................................................................................................................................................... 5 3.0 Electrical Characteristics ...................................................................................................................................................................... 8 3.1 Operating Conditions ........................................................................................................................................................................ 8 3.2 Power Supply Blocks ........................................................................................................................................................................ 9 3.3 Transmitter Blocks ............................................................................................................................................................................ 9 3.4 Receiver Block ................................................................................................................................................................................ 11 4.0 Theory of Operation ........................................................................................................................................................................... 12 4.1 Overview......................................................................................................................................................................................... 12 4.2 Power Supply Block ........................................................................................................................................................................ 12 4.2.1. Shunt Regulator ...................................................................................................................................................................... 12 4.2.2. Series Regulator...................................................................................................................................................................... 13 4.2.3. Low Voltage Detectors ............................................................................................................................................................ 13 4.2.4. Voltage Reference................................................................................................................................................................... 14 4.3 Transmit Block ................................................................................................................................................................................ 15 4.3.1. MDS-interface ......................................................................................................................................................................... 15 4.3.2. Tri-level Modulator................................................................................................................................................................... 15 4.3.3. Slew Rate Controller ............................................................................................................................................................... 16 4.3.4. Current Drive Amplifier ............................................................................................................................................................ 16 4.4 Receive Block ................................................................................................................................................................................. 16 4.4.1. Band Pass Filter ...................................................................................................................................................................... 17 4.4.2. Receive Signal Detection ........................................................................................................................................................ 17 5.0 AMIS-49200 as Replacement for Yokogawa µSAA22Q..................................................................................................................... 18 5.1 Functional Differences Between the µSAA22Q and the AMIS-49200............................................................................................. 18 5.1.1. Jabber Inhibit........................................................................................................................................................................... 18 5.1.2. Low Power Mode..................................................................................................................................................................... 18 5.2 Pin Differences Between the µSAA22Q and the AMIS-49200 ........................................................................................................ 19 5.3 External Circuitry............................................................................................................................................................................. 20 5.4 Active Components......................................................................................................................................................................... 21 5.5 Alternative Designs ......................................................................................................................................................................... 21 5.6 Verification ...................................................................................................................................................................................... 21 6.0 Appendix (A) – Manchester Encoding ................................................................................................................................................ 22 7.0 Company or Product Inquiries ............................................................................................................................................................ 22 AMI Semiconductor – Jan. 07, M-20532-003 www.amis.com 2 AMIS-49200 Fieldbus MAU Data Sheet 1.0 Introduction 1.1 Overview AMIS-49200 Fieldbus MAU (media access unit) is a transceiver chip for low speed FOUNDATION Fieldbus® and Profibus® PA devices. It was designed to be a near pin-for-pin replacement of the Yokogawa µSAA22Q MAU. “Near pin-for-pin” means that associated component values may change, but no board changes are required. 1.2 Definitions, Acronyms and Abbreviations IC ESD ICFF LQFP Manchester MAU MDS - Integrated circuit - Electrostatic discharge - FOUNDATION Fieldbus - Low profile quad flat pack - Communications encoding scheme implemented in FOUNDATION Fieldbus - Medium attachment unit - Medium dependent sub-layer µSAA22Q - Name of Yokogawa’s MAU IC 1.3 References • Fieldbus Medium Attachment Unit (MAU) Chip, µSAA22Q, Yokogawa Electric Corporation, June 12, 1998, Document No.: SS-96-01 (Rev.3). • Fieldbus Standard for Use in Industrial Control Systems Part 2: Physical Layer Specification and Service Definition, Amendment to Clause 22 ISA/SP50 –1996-544B, dS50.02, Part 2, Draft Standard. • Profibus PA specifications EN 50170 (formerly DIN 19245) covers all of Profibus and includes PA (31.25 kbps Intrinsically Safe Physical Layer), references IEC 61158-2. 2.0 AMIS-49200 Fieldbus MAU Description 2.1 Features AMIS-49200 Fieldbus MAU is a transceiver IC for low speed FOUNDATION Fieldbus and Profibus PA devices. It incorporates the following features: • • • • • • • • • • • • • • • Current consumption 500uA (typ) VCC voltage: 6.2V to 4.75V VDD voltage: 5.5V to 2.7V Compatible to IEC 1158-2 and ISA 50.02 Shunt regulator Voltage reference (internal only) Series regulator Band-pass filter Slew rate control Segment current control Low voltage detection Carrier detect Data rate: 31.25kbps voltage mode Dual voltage supply 3-6.2V 44-pin LQFP package AMI Semiconductor – Jan. 07, M-20532-003 www.amis.com 3 AMIS-49200 Fieldbus MAU Data Sheet 2.2 Block Diagram 33 Receive Block 35 31 VSS 30 FLTOUT FLT Zero-Cross Detector RXS HPF SIGIN Bandpass Filter 34 32 LPF Carrier Detector RXA 28 27 29 CCD Transmit Block 26 MDS_CTRL 38 POL 36 TXE 37 TXS 1 41 42 43 VDRV Tri-Level Modulator & Slew Control MDS Interface CRT VSS VSS VSS CCINP VSS CCINM Current Driver VSS CCOUT VSS 39 VSS 40 VSS Power Supply Block Vmid Reference Vmid 19 20 22 23 24 25 3 VCC VCC 44 VCC 21 VCC VCC Bias Circuitry 18 Vmid Vref Bandgap 2 Vref VDD 17 VCC 13 VO Series Regulator SRSET VSS 11 SRTR SRAO 15 14 Shunt Regulator Low Voltage Detectors SRSETIN N_PFail2 12 5 N_PFail1 4 SHSETIN SHSET SGND 6 7 Figure 1: AMIS-49200 Fieldbus MAU Block Diagram AMI Semiconductor – Jan. 07, M-20532-003 www.amis.com 4 SHUNT 9 VSS 16 10 8 AMIS-49200 Fieldbus MAU Data Sheet 2.3 Package Information The IC will be packaged in a 44-pin LQFP package as shown below. Figure 2: Package Dimensions (44-pin LQFP) AMI Semiconductor – Jan. 07, M-20532-003 www.amis.com 5 CCINP CCINM CCOUT NC1 SIGN HPF FLT LPF Data Sheet FLOUT CCD VSS AMIS-49200 Fieldbus MAU 33 32 31 30 29 28 27 26 25 24 23 22 35 21 20 36 37 19 AMIS-49200 Fieldbus MAU 44 pin LQFP 38 39 18 17 Pin Information 4 5 6 7 8 9 10 11 VSS VDRV VSS CRT VCC VDD VO SRTR SRAO SRSET SRSETIN VSS 3 VSS 2 SGND 1 SHSET 12 SHUNT 13 44 SHSETIN 43 N_PFAIL2 15 14 N_PFAIL1 42 VMID 16 41 VREF 40 VSS RxA RxS TxE TxS POL VSS VSS VSS VSS VSS VCC 34 Figure 3: AMIS 49200 Fieldbus MAU Pin Out Table 1: Pin Numbers and Signal Description Signal Name Pin No. I/O (Note 1) Description VSS 1 Ground VREF 2 AO Connect to ground VMID 3 AO 2V bias voltage for AC signals Internal bandgap voltage (1.18V) N_PFAIL1 4 AI/O Power fail alarm at VCC input. This pin is an open-drain output of negative logic. N_PFAIL2 5 AI/O Power fail alarm at VDD input. This pin is an open-drain output of negative logic. SHSETIN 6 AI Feedback (non-inverting) input for the shunt regulator SHSET 7 AO Divided voltage of VCC input. Feeding this voltage to SHSETIN pin results in 5V voltage at VCC. SHUNT 8 AI Control pin of the shunt regulator. Its sink current (25mA max) is controlled so that the voltage at SHSETIN is equal to VREF (1.18V). VSS/ SGND 9 Ground The current absorbed by SHUNT pin (25mA max) is fed to this pin, which must be connected to the ground level VSS 10 Ground Ground VSS 11 Ground Ground SRSETIN 12 AI Feedback (inverting) input for the series regulator. The series regulator controls its output (SRAO) to make this input voltage is equal to VREF (1.18V). SRSET 13 AO Divided voltage of VO output. Feeding this voltage into SRSETIN pin results in 3V at VO pin. SRAO 14 AO Output pin of an operational amplifier for the series regulator SRTR 15 AI Gate of a PMOS transistor for the series regulator VO 16 AO Output pin of the series regulator. (20mA max) AMI Semiconductor – Jan. 07, M-20532-003 www.amis.com 6 AMIS-49200 Fieldbus MAU Data Sheet Table 1: Pin Numbers and Signal Description (Continued) Signal Name Pin No. I/O (Note 1) Description VDD 17 Digital Supply Supply voltage input for digital block VCC 18 Analog Supply Analog supply voltage CRT 19 AI/O VSS 20 Ground VDRV 21 AO VSS 22 Ground Current integration to limit output slew rate Ground Output of an operational amplifier for slew rate control. This signal can be fed to current driver. Ground CCINP 23 AI Non-inverting input of an operational amplifier for transmission current driver CCINM 24 AI Inverting input of an operational amplifier for transmission current driver CCOUT 25 AO Output of an operational amplifier for transmission current driver MDS_CTRL 26 AI For POL = VDD MDS_CTRL should = VSS FOR POL = VSS MDS_CTRL can be tied to VDD or used as a not reset to control when transmit communications will be enabled SIGIN 27 AI Input pin of the band-pass filter. This pin is connected to VMID bias level with 270K resister. HPF 28 AI Feedback signal of high-pass filter. This pin is connected to the output of an opamp for high pass filter with 75K resistor. LPF 29 AI Non-inverting input of an operational amplifier for the low-pass filter FLT 30 AI Input pin of low-pass filter for feedback. This pin is connected to the output of the high-pass filter through 20kΩ and the non-inverting input of the low-pass filter through 54kΩ resisters. FLTOUT 31 AO Output of the operational amplifier for the low-pass filter. This signal is internally connected to non-inverting input to form a voltage-follower. CCD 32 AO VSS 33 Ground Current integration (for carrier detect circuit) RXA 34 DO MDS-MAU interface signal for received signal activity. This pin is a push-pull output. RXS 35 DO MDS-MAU interface signal for received signal. This pin is a push-pull output. TXE 36 DIS MDS-MAU interface signal for enable signal transmission (Schmitt Trigger Input) TXS 37 DIS MDS-MAU interface signal for signal to be transmitted (Schmitt Trigger Input) Selects polarity of TxE input. When this pin is connected to GND, TxE is active high. When this pin is connected to VDD, TxE is active low. Ground POL 38 DIS VSS 39 Ground Ground VSS 40 Ground Ground VSS 41 Ground Connect to ground VSS 42 Ground Connect to ground VSS 43 Ground Connect to ground 44 Analog Supply Analog supply voltage VCC Note: 1. AI = Analog Input, AO = Analog Output, AI/O = Analog Input/Output, DIS = CMOS Digital Input (Schmitt Trigger), DO = CMOS Digital Output. AMI Semiconductor – Jan. 07, M-20532-003 www.amis.com 7 AMIS-49200 Fieldbus MAU Data Sheet 3.0 Electrical Characteristics 3.1 Operating Conditions o Unless otherwise noted, all block and sub-block specifications apply over the operating temperature (-40 to 85 C) Table 2: Absolute Maximum Ratings Parameter Symbol Min. Max. Units Analog block supply voltage VCC -0.3 6.5 V Digital block supply voltage VDD -0.3 6.0 V Digital input pin voltage VIN -0.3 VDD + 0.3 V VOUT -0.3 VDD + 0.3 V IIN - ±5 mA Not for shunt pin IOUT - 30 mA For shunt, SGND and VO TStorage -55 125 °C Digital output pin voltage Input pin current Output pin current Storage temperature Table 3: Normal Operating Conditions Parameter Symbol Min. Typ. Max. Units Analog supply voltage VCC 4.75 5 6.2 V Digital supply voltage VDD 2.7 3 VCC - 1.1V V Storage temperature TOperating -40 85 °C Current consumption ICC 800 µA Table 4: CMOS Input Specifications Parameter Input high voltage 500 25°C, SHUNT current = 1mA, No current from series regulator Max. VDD Input low voltage VIL 0 0.3•VDD V Input high current IIH 1 µA -1 µA 0.8•VDD V IIL Vt- Schmitt positive threshold Vt+ Schmitt hysteresis Vh AMI Semiconductor – Jan. 07, M-20532-003 www.amis.com Units V V 0.2•VDD 1 V 8 (RxS and RxA pins) Supply voltages are configurable, or can be supplied from off-chip Min. 0.7•VDD Schmitt negative threshold (TxS, TxE, & POL pins) Conditions Symbol VIH Input low current Conditions AMIS-49200 Fieldbus MAU Data Sheet 3.2 Power Supply Blocks Table 5: Regulator Specifications Parameter Shunt Regulator Symbol Min. Typ. Max. Units VCC 4.85 4.75 5.0 5.15 6.2 V V Sink current ISH 0.001 25 mA Load capacitance Load regulation Temperature coefficient Series Regulator CSH 5 0 4 ±200 µF % ppm/°C 6.2 V Internally tied to VCC pin 3.09 V Preset, ISR = 0 3.5 V External setting & N-JFET 20 mA 2 ±200 4 µF % ppm/°C 90 95 % Vref Output voltage Input voltage 1.6 TCVcc VCC Output voltage VO Output current ISR 4.75 2.91 Load capacitance CSR 5 Load regulation 0 Temperature coefficient TCVo Low Voltage Detectors (applies to N_PFail1 and N_PFail2) Threshold VTH9 85 Hysteresis VHYS5 .012 Output sink current IOL 30 Output leakage current IL Table 6: Voltage Reference Specifications Parameter Symbol Bandgap Voltage Reference Output voltage tolerance VREF Temperature drift 3.0 2.85 .025 Conditions Preset, ISH = 1 to 5mA External setting Internal pass transistor N-ch & pad ISH = 1 to 25mA No load capacitance Internal pass transistor P-ch & pad For stability use Cap w/ ESR ISR = 0 to 20mA SxSETIN > VTH9 (output: L Æ H) .038 V 135 µA SxSETIN < (VTH9 - VHYS5) (output: H Æ L ) VOL=0.4V (open drain) 1 µA VOH = 5V Min. Typ. Max. Units Conditions 1.157 1.185 50 1.205 V ppm/°C VREFHYS - 100 - µV Supply voltage VCCREF 4.75 5 6.2 V Load current VMID voltage reference Output voltage Output current Load capacitance Temperature coefficient IREFOUT - - 0 µA VMID IMID CMID TCMID 1.95 -30 0.01 2.0 2.05 100 1 ± 200 V µA µF ppm/°C Hysteresis Notes: 1. 1 0.1 Equates to: +/- 2 percent Note 1 No load during operation DVC6000F uses 1uF Hysteresis is defined as the change in the 25°C reading after 85°C to 25°C cycle and –40°C to 25°C cycle. 3.3 Transmitter Blocks Table 7: MDS-MAU Interface Parameter MDS-MAU Interface POL input pin Symbol Min. Typ. POL TxE input pin TxE TxS input pin TxS AMI Semiconductor – Jan. 07, M-20532-003 Units V See Schmitt Trigger Input Specs. V V Note: The associated MDS chip must handle the jabber detect function. www.amis.com Max. 9 Conditions AMIS-49200 Fieldbus MAU Table 8: Tri-level Modulator Parameter Symbol Min. Data Sheet Typ. Max. Units 3.02 +120 V µA |∆V| 10mV Tri-level Modulator and Slew Control Output voltage Load current Output for silence 1 Output for high level Output for low level 1 1 Asymmetry of VH and VL Rise and fall times Notes: 1. 2. 2 Conditions (Output is at VDRV) VO IO VMID -35 VS VMID+0.485 VMID+0.500 VMID+0.515 V TXE disabled VH VS+0.380 VS+0.400 VS+0.420 V TXE active VL VS-0.420 VS-0.400 VS-0.380 V TXE active ∆VHL -0.02 0.02 V tf, tr µsec 4.7 Note 2 (CRT=22pF) Nominal values are: VS = 2.5V, VH=2.9V and VL=2.1V. By adding an external capacitor between the CRT pin and ground, slew rate at VDRV output can be controlled. The controlling equation is tf or tr =2us + (0.123us/pF * CRT). CRT is nominally 22pF, yielding tf=tr=4.7us. The constant comes from an internal capacitor. The hot side of the capacitor and the CRT pin should have a guard pattern around them to avoid unnecessary interference. Table 9: Current Control Amplifier Parameter Current Control Amplifier Input common mode voltage range Output voltage swing Max. Units 0 VCC – 1 V VO 1 VCC – 0.5 V Io -2300 100 µA Input offset voltage VOS -3 +3 mV Slew rate SR 0.54 V/µs GBW 1.15 MHz PM 66 Deg Load current Gain bandwidth product Phase margin Symbol Min. VCM AMI Semiconductor – Jan. 07, M-20532-003 www.amis.com Typ. 10 Conditions (Output is at CCOUT) CL=10pf RL=200k AMIS-49200 Fieldbus MAU Data Sheet 3.4 Receiver Block Table 10: Receiver Sub-blocks Parameter Band Pass Filter Input voltage Output voltage swing Output slew rate Input offset voltage Filter resistors 1 Symbol Min. Typ. Max. Units VBP 1 4 V FLTOUT 1 4 V SR 0.6 SIGIN pin to GND V/µs ±5 mV RF1 60 75 90 kΩ RF2 216 270 324 kΩ VOS Conditions RF3 16 20 24 kΩ RF4 43 54 65 kΩ Carrier Detector VTH+ 40 50 60 mV VTH- -60 -50 -40 mV Output high voltage VOH VDD-0.6 Output low voltage VOL Output high current IOH 50 Output low current IOL 50 µA VO ≤ 0.6V Output rising time tR 0.3 µs CL = 10pF Output leak current tF 0.3 µs CL = 10pF Threshold voltage 0.3 Relative to VMID V IOH = 0 mA V IOL = 0 mA µA VDD-VO ≤ 0.6V Zero-cross Detector VTH+ VMID+0.025 VMID+0.040 VMID+0.058 V No carrier VTH- VMID VMID VMID V Carrier active Output high voltage VOH VDD-0.6 V IOH = 0 mA Output low voltage VOL V IOL = 0 mA Output high current IOH 50 µA VDD-VO ≤ 0.6V Output low current IOL 50 µA VO ≤ 0.6V Output rising time tR 0.3 µs CL = 10pF Output leak current tF 0.3 µs CL = 10pF Threshold voltage Notes: 1. 0.3 The band pass filter is made up of a two pole high pass filter in series with a two pole low pass filter. The filter consists of four resistors internal to AMIS-49200, and four external capacitors. The active part of each filter is an amplifier connected in a follower configuration. AMI Semiconductor – Jan. 07, M-20532-003 www.amis.com 11 AMIS-49200 Fieldbus MAU Data Sheet 4.0 Theory of Operation 4.1 Overview AMIS-49200 incorporates two different power supply circuits. Both derive their power from the bus. Using the internal configuration, the shunt regulator is set for 5V and the series regulator is set for 3V. Users can modify either power supply by adding external components. AMIS-49200 Fieldbus can also monitor these power supply voltages and generate power-fail signals if they fall below a specified value. AMIS-49200 Fieldbus MAU transmits a Manchester-encoded signal provided from a standard MDS-MAU interface. The output driver makes it possible to design various signal circuits, which depend on the power requirements of your device. The slew rate of the signal can be controlled to minimize unnecessary radiation as specified in IEC/ISA standards. AMIS-49200 Fieldbus MAU has a built-in band-pass filter which makes it easy to design your own receiver. The receive block operates on a Manchester-encoded signal. It decodes the signal and verifies proper amplitude with a zero-cross and carrier detect circuit, respectively. Detected signals are then passed on to a controller with the standard MDS-MAU interface. 4.2 Power Supply Block The power supply block contains four sub-blocks: 1. 2. 3. 4. A shunt regulator - for establishing a supply voltage of VCC (typ. = 5V) used by the analog circuitry A series regulator - for establishing a supply voltage of VDD (typ. = 3V) used for digital circuitry Two low voltage detectors - for monitoring the two supply voltages A bandgap voltage reference - which is used internally for generating a bias level for AC signals 4.2.1. Shunt Regulator The shunt regulator controls its sink current to the SHUNT pin so that the voltage applied to the SHSETIN pin is equal to VREF. The VCC input is divided by an internal network to provide a voltage equal to Vref at the SHSET pin. If SHSET and SHSETIN pins are tied together, and VCC and SHUNT pins are connected to a power source of high impedance (e.g., current mirror circuit of signal driver), the Shunt regulator provides 5V power to itself and external circuits. A capacitor of 5µF or larger capacity is necessary to stabilize this regulator. It is possible to increase the VCC voltage up to 6.2V by dividing VCC with an external network to supply the appropriate voltage to SHSETIN pin. In this case, SHSET pin must be kept open. The output voltage is determined by the following equation: VCC = VREF × (1 + R1 / R2) Shunt Regulator (Internal Configuration ) 16Meg VCC 18 6 SHSETIN 9 16Meg 8 7 SGND SHSET Figure 4: Shunt Regulator www.amis.com 12 6 SHSETIN 8 25mA (Max) A6 Rsh R1 SHUNT 50pF VREF N/C AMI Semiconductor – Jan. 07, M-20532-003 Cfb SHUNT 25mA (Max) A6 Rsh SHSET VCC 3.25Rsh 50pF VREF System VCC 18 Cfb 3.25Rsh 7 Shunt Regulator (External Configuration ) System VCC 9 SGND R2 AMIS-49200 Fieldbus MAU Data Sheet The SHUNT pin is normally connected to VCC. It is possible to insert a resister between VCC and SHUNT to measure the shunt current. Its value should be small enough to keep VDS (voltage between SHUNT pin and SGND pin) larger than 2.5V (i.e., resistor must be less than 100Ω.). Since the internal transistor can sink as much as 25mA, no additional circuit is necessary in most cases. Note that the drain current must not exceed 25mA because no protection is implemented for the internal transistor. If you do not need the shunt regulator, you should connect SHUNT and SHSETIN pins to GND and open SHSET pin. Then VCC must be supplied from another source. 4.2.2. Series Regulator The series regulator produces a regulated voltage at the VO pin from VCC. If you connect SRAO and SRTR pins together, the internal amplifier will regulate the input voltage at SRSETIN pin to equal VREF. An internal feedback signal is generated to produce a voltage equal to VREF at pin SRSET. If you connect SRSET and SRSETIN pins, the series regulator supplies 3V at pin VO. A capacitor of 5µF or larger capacity is necessary to stabilize this regulator. The capacitor is expected to have an ESR resistor for the circuit to be stable. If the capacitor is low, a series resistor with the cap load will help stabilize the circuit). Series Regulator (Internal Configuration) May Supply VDD Series Regulator (External Configuration) VO 16 CD SRSET 20mA (Max) May Supply VDD VCC Cfb1 VO 40pF 16 Cc2 20pF CD 1.54Rsr R4 VREF A7 SRSET 13 N/C R5 Rsr SRTR 15 14 SRAO 12 VCC Cfb1 SRSETIN 20mA (Max) 40pF Cc2 20pF 1.54Rsr VREF A7 13 Rsr SRTR 15 14 SRAO 12 SRSETIN Figure 5: Series Regulator The supply current must not exceed 20mA because no current limiting is applied to the internal transistor. You can increase VO voltage up to 3.5V by dividing VO with an external network to supply the appropriate voltage to pin SRSETIN. In this case, pin SRSET must be kept open. The drain-source voltage of the internal transistor must be larger or equal to 2V. If this condition is not satisfied, you may need an external P-channel JFET to create the desired low voltage-drop regulator. The output voltage is determined by the following equation. VO = VREF × (1 + R4/R5) 4.2.3. Low Voltage Detectors Low voltage detectors are included to monitor supply voltages and generate “Power Fail” signals. The low voltage alarms are detected by sensing the voltage on pins SHSETIN and SRSETIN. These pins also provide feedback for the shunt and series regulators. If the voltage on the SHSETIN pin is lower than the threshold, VTH9 (90 percent VREF), N_PFAIL1 goes low. Typically SHSETIN monitors the analog rail voltage VCC. If the voltage on the SRSETIN pin is lower than the threshold, VTH9, N_PFAIL2 goes low. Typically SRSETIN monitors the digital rail voltage VDD. Both outputs are open drain, so a resistor will be required. If you do not use one of these pins, it should be connected to GND. You can also add capacitors to delay these signals. In this case, sink current must not exceed the maximum value. If you do not wish to use one of the low voltage detectors its corresponding output pin should be connected to GND. AMI Semiconductor – Jan. 07, M-20532-003 www.amis.com 13 AMIS-49200 Fieldbus MAU Data Sheet Low Voltage Detectors VDD R1 N_PFail1 VCC2 4 0.9*VREF C3 C1 SHSETIN VDD R2 N_PFail2 VCC2 5 0.9*VREF C4 C2 SRSETIN Figure 6: Low Voltage Detectors If you do not use one of the regulators, the corresponding alarm signal can potentially be used to monitor another signal. For example, if the series regulator is not used, SRAO should be left open, SRTR tied to VCC, VO grounded and SRSET left open. Then SRSETIN can be the input for monitoring another voltage signal with N_PFAIL2. 4.2.4. Voltage Reference The voltage reference circuitry generates two voltage signals, VREF and VMID. VREF comes from a bandgap circuit and is used as the reference voltage for all circuits in AMIS-49200 Fieldbus MAU. The typical value for VREF is 1.181V. VREF also passes through an analog switch, which is controlled by the test-mux control signals MS0-MS3. When MS0-MS3 are all at GND the analog switch is closed and VREF is connected to Pin 2. If any of the signals MS0-MS3 are not at GND, the analog switch is open and Pin 2 will be floating. When the analog switch controlling Pin 2 is closed and VREF is present at Pin 2, no load should be connected to this pin (internal use only). See Figure 7 for the details. An operational amplifier is regulating VMID to provide a bias (common) level for the AC signals. Its typical voltage is 2V. A capacitor larger than 0.01µF is necessary on VMID to remove high-frequency ripple. Voltage Reference To Test Mux Control Inputs 41 42 43 MS0 2 VREF VCC Vmid Reference R MS1 237K MS2 VREFBG 39 Vmid 3 A5 VREFBG VSS Vmid Bandgap should have its own ground trace or star connection to system ground. Figure 7: Bandgap and VMID Voltage Reference AMI Semiconductor – Jan. 07, M-20532-003 www.amis.com 163.1K VCC Bandgap Vref=1.185V (typ) Tol. = +/- 2% 0.688R 14 AMIS-49200 Fieldbus MAU Data Sheet 4.3 Transmit Block The transmit block contains four sub-blocks: 1. 2. 3. 4. MDS-interface – decodes input signals to generate internal control signals. Tri-level modulator – generates current signals used as inputs to the slew-rate controller. Slew rate controller – converts current to three distinct VDRV voltage levels (VS, VH, VL). Current drive amplifier – op amp designed to drive current drivers for 31.25kbps voltage-mode medium. 4.3.1. MDS-interface The MDS-interface decodes input signals to generate internal control signals. The POL pin, is used to select the polarity of TxE (transmit enable). The TxE and TxS (transmit signal) are the MDS-MAU interface signals. These three signals are CMOS logic signals powered by the VDD supply voltage. When POL is connected to GND, TxE is assumed to be active high (positive logic). Likewise, if POL is connected to VDD, TxE is assumed to be active low (negative logic). See Table 11 to see how MDS_CTRL Pin 26 can be used to control MDS interface operation. The following table shows the resulting VDRV output for the various combinations of interface signals. Table 11: MDS-interface Logic POL TxE TxS Low Low High Low Low High High Low Low High High Low High High VDRV VS VH VL VH VL VS 4.3.2. Tri-level Modulator The tri-level modulator switches current signals into a summing node. The slew rate controller converts the current to a voltage signal, VDRV. The DC level of silence (VS) is nominally 2.5V. Transmission high (VH ) is nominally 2.9V and transmission low (VL) is nominally 2.1V, yielding an amplitude of 0.8V. Tri-Level Modulator & Slew Control N_VL N_Vs Active Low Active Low 4R 4R R 80K 80K 20K VCC 20R 400K A3 VDRV 1.2K CRT 1.2K Figure 8: Tri-level Modulator AMI Semiconductor – Jan. 07, M-20532-003 www.amis.com 15 21 1.2K VMID 19 AMIS-49200 Fieldbus MAU Data Sheet 4.3.3. Slew Rate Controller Amplifier (A3), shown in the above figure, controls the slew rate. The amplifier converts the current signals from the tri-level modulator to a voltage signal, VDRV. It controls its slew rate with a capacitor (CRT) connected to the CRT pin. The waveform at the VDRV pin is symmetric and the fall/rise times are determined by the following equation: tF, tR = 2.0[µs] + 0.12 [µs/pF] × CRT The constant part comes from the internal capacitor (not shown). It is recommended to make a guard pattern on your circuit board around the CRT pin and the hot side of CRT to avoid unnecessary interference. 4.3.4. Current Drive Amplifier The drive amplifier is an operational amplifier optimized to drive current drivers for 31.25kbps voltage-mode medium. Its input and output signals are exposed to allow flexible design of the external driver. Note that this amplifier cannot directly sink the necessary current from the medium. In the following drive circuit the current (IBUS) through the current-detect resister (RF) is determined by the following equation. IBUS = (1/RF) × (VDRV - VMID) × (RB/RA). A diode and/or a resister connected to the emitter are necessary to shift the DC level of CCOUT and to suppress the loop gain. The resistance value depends on your design (overall gain and emitter current). Vmid Current Control Circuit VDRV RA RA VCC CCINP 23 CCOUT A4 24 25 CCINM RB RB IBUS Rf Figure 9: Current Control Circuit 4.4 Receive Block The receive block contains three sub-blocks, which are internally connected: 1. 2. 3. A band pass filter – to filter the desired incoming communication signal. Carrier detector – generates the RxA signal by detecting the signal amplitude. Zero-cross detector generates the RxS signal by detecting the high/low transitions of the Manchester code. AMI Semiconductor – Jan. 07, M-20532-003 www.amis.com 16 AMIS-49200 Fieldbus MAU Data Sheet 4.4.1. Band Pass Filter The band pass filter is a series connection of a high-pass and a low-pass filters each having two poles. Each filter is comprised of a voltage follower and on chip resisters, so only four external capacitors are necessary. The following figure shows an internal circuit and the connection of external capacitors. Cut-off frequency, fL, of the high-pass filter is determined by C1 and C2 while cut-off frequency, fH, of the low-pass filter is determined by C3 and C4. fL = fH = 1 2π 1 2π QL = 1 R F1 *R F 2 *C1 *C 2 1 2 R F2 R F1 Q L = 0.44 * 1 R F 3 *R F 4 *C 3 *C 4 =0.95 C3 C4 =0.95 The possible ranges of fL and fH are 1kHz ~ 10kHz and 10kHz ~ 100kHz, respectively. recommended to obtain 1kHz and 47.6kHz cut-off frequencies. 31 The values in the following figure are Bandpass Filter C3=220pf 30 FLT FLTOUT HPF RF1 To Detectors 28 75K VCC VCC A2 RF4 RF3 54K 20K SIGIN A1 C2 C1 Signal Input 27 RF2 270K 1000pf 1000pf Vmid 29 C4=47pf Figure 10: Band Pass Filter 4.4.2. Receive Signal Detection The carrier detector generates the receive activity (RxA) signal by detecting the input signal amplitude. Minimum amplitude is 100mVpp (TYP). A delay, determined by the capacitor connected between the CCD pin and GND, is added to avoid detection of transient noise. The recommended value of CCD is 100pF. The output can drive a CMOS input of VDD supply voltage. The zero-cross detector generates the receive signal (RxS) with minimum phase error (jitter) by detecting the transition between high and low levels of the incoming Manchester code. Hysteresis of +40mV (TYP) is applied to avoid unnecessary switching by noise. Once the carrier-detect goes active the hysteresis is removed and the switching point threshold is set to Vmid. The output can drive a CMOS input of VDD supply voltage. AMI Semiconductor – Jan. 07, M-20532-003 www.amis.com 17 AMIS-49200 Fieldbus MAU Data Sheet Zero-Cross Detector RXS 35 VDD VCC Level Convert C1 ZC Tript Pt Vtrip = Vmid Vhyst = + 40mV Vmid R (1Meg) Carrier Detector RxSig VCC RXA 34 CCD VDD VCC C2 Level Convert CD_Output VHi50 Filtered received signal from Bandpass Filter VHi50 = Vmid + 50mV VLo50 = Vmid - 50mV VCC 32 C (60pF) VLo50 C2 Figure 11: Receive Signal Detectors 5.0 AMIS-49200 as Replacement for Yokogawa µSAA22Q The AMIS-49200 is a near pin-for-pin compatible replacement for the Yokogawa µSAA22Q Fieldbus MAU. There are some differences between the two chips both in the internal operation, the required external connections and the value (or existence) of some of the external components. These differences are small and those who used the µSAA22Q would most likely be able to use the AMIS-49200 in designs with only some component value changes. 5.1 Functional Differences Between the µSAA22Q and the AMIS-49200 5.1.1. Jabber Inhibit The AMIS-49200 does not implement the Jabber Inhibit function in the µSAA22Q. Typically the AMIS-49200 will be connected with a Link Controller chip such as the Yokogawa FIND1. This link controller has a Jabber Inhibit function so the absence of this function in the AMIS-49200 should not be a problem. As can be seen in Table 12, MDS_CTRL is only connected to ground if POL is connected to VDD. See Table 1 for a detailed description of the interaction between MDS_CTRL and POL. In Table 12, the µSAA22Q recommends that the JAB/ signal (pin 39) be connected to ground if the signal is not used. On AMIS-49200, pin 39 must be connected to ground. 5.1.2. Low Power Mode The low power mode on the µSAA22Q allows the user to have a quiescent current draw of less than 10mA yet still communicate at the proper IEC 61158-2 signal levels. Very few, if any, Fieldbus devices are capable of operating at such a low current level so this capability was not included in the AMIS-49200. AMI Semiconductor – Jan. 07, M-20532-003 www.amis.com 18 AMIS-49200 Fieldbus MAU Data Sheet The pins affected by this are 41, 42, and 43. If the low power mode is not being used on the µSAA22Q, these three pins are grounded. On the AMIS-49200 it is required that these pins be grounded. 5.2 Pin Differences Between the µSAA22Q and the AMIS-49200 Table 12: Pin Connection Differences Between the µSAA22Q and the AMIS-49200 AMIS-49200 µSAA22Q Pin Num Signal Name Recommended Connection Signal Name 1 NC Ground VSS Ground 11 22 26 NC NC NC Ground Ground Ground VSS VSS MDS_CTRL Ground Ground Ground* 33 NC Ground VSS Ground 39 JAB/ Ground if not used VSS Ground 41 CJB 1 µf cap VSS Ground 42 VTX Ground VSS Ground 43 VSL Ground VSS Ground Required Connection * MDS_CTRL is only connected to ground if POL is connected to VDD. See Table 1 for a detailed description of the interaction between MDS_CTRL and POL. AMI Semiconductor – Jan. 07, M-20532-003 www.amis.com 19 AMIS-49200 Fieldbus MAU Data Sheet 5.3 External Circuitry Figure 12 shows the external circuitry required to connect the AMIS-49200 to an IEC 61158-2 conformant network. This schematic is the circuit that was used to pass the Fieldbus Foundation Physical Layer Conformance test as specified in Fieldbus Foundation specification FF830, Rev 1.5. This circuit is similar but not identical to the circuit recommended by Yokogawa for the µSAA22Q. Figure 12: AMIS-49200 Reference Circuit Implementation Table 13 below lists the four external component values that need to be changed with using the AMIS-49200 in a circuit that previously used the µSAA22Q. Table 13: Passive External Component Value Differences Between the µSAA22Q and the AMIS-49200 Component AMIS-49200 Value µSAA22Q Value C1 100pf C3 100pf 150pf 47pf C4 470pf 220pf C8 10nf 1µf C1 connects to signal CCD (pin 32) and controls the carrier detect assert and drop-out timing. Particular implementations may require that the value of C1 be changed to accommodate received signal level changes introduced by the addition of intrinsic safety components added to the external circuitry. C3 and C4 are part of the receive filter and determine the band pass characteristics of the AMI Semiconductor – Jan. 07, M-20532-003 www.amis.com 20 AMIS-49200 Fieldbus MAU Data Sheet receive filter. It is unlikely that these would need to be changed. C8 is a noise filter for VMID. It is important that VMID have as little noise as possible as it is used as a reference for many sub-circuits in the AMIS-49200. There is one other minor difference in the recommended external circuitry between the µSAA22Q and the AMIS-49200. Figure 13 shows the startup circuits recommended for the µSAA22Q and the AMIS-49200. The circuit shown for the AMIS-49200 is different from that shown for the µSAA22Q but either one will work. Both are current sources that turn on when power is applied to the H1 segment terminals so that the AMIS-49200 can turn on without any turn-on transients on the network. µSAA 22Q Startup Circuit AMIS 49200 Startup Circuit R5 100 k Loop + Loop + R6 1k Q1 D3 5.1 V V Shunt V Shunt Figure 13: Recommended Start-up Circuits 5.4 Active Components Transistors Q1 – Q4 are ordinary small signal transistors. Diodes D1 and D2 are similarly ordinary small signal diodes. Users desiring to replace a µSAA22Q with the AMIS-49200 in an existing design should be able to use whatever transistors and diodes were used with the µSAA22Q. For new designs, the specified transistors can be used or other devices may be chosen. 5.5 Alternative Designs Some users of the Yokogawa µSAA22Q did not use the exact recommended external circuit for the media interface circuit (see Figure 12). Using the AMIS-49200 that did not follow the Yokogawa recommended external circuit may result in some compatibility problems. There are an almost infinite number of alternative designs and it is beyond the scope of this document to identify the possible designs and their possible compatibility problems. 5.6 Verification All designs using the AMIS-49200 should re-run the entire physical layer conformance test as defined in Fieldbus Foundation document FF-830, FOUNDATION™ Specification 31.25 kbit/s Physical Layer Conformance Test. Board layout can alter the behavior of all circuit implementations, even designs that follow the recommended implementation. AMI Semiconductor – Jan. 07, M-20532-003 www.amis.com 21 AMIS-49200 Fieldbus MAU Data Sheet 6.0 Appendix (A) – Manchester Encoding All Fieldbus devices transmit the data onto the media as a Manchester-encoded baseband signal. With Manchester encoding, zeros and ones are represented by transitions that occur in the middle of the bit period (see below). For Foundation Fieldbus H1 and Profibus PA, the nominal bit time is 32µsec, with the transition occurring at 16µsec. The Manchester encoding rules have been extended to include two additional symbols, non-data plus (N+) and non-data minus (N-). The symbol encoding rules are shown below. 32 usec T 2 -T 2 Logical "0" Logical "1" T 2 -T 2 T 2 -T 2 T 2 -T 2 "N+" "N-" Figure 14: Manchester Encoding 7.0 Company or Product Inquiries For more information about AMI Semiconductor, our technology and our product, visit our Web site at: http://www.amis.com North America Tel: +1.208.233.4690 Fax: +1.208.234.6795 Europe Tel: +32 (0) 55.33.22.11 Fax: +32 (0) 55.31.81.12 Devices sold by AMIS are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. AMIS makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. AMIS makes no warranty of merchantability or fitness for any purposes. AMIS reserves the right to discontinue production and change specifications and prices at any time and without notice. AMI Semiconductor's products are intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment, are specifically not recommended without additional processing by AMIS for such applications. Copyright ©2007 AMI Semiconductor, Inc. AMI Semiconductor – Jan. 07, M-20532-003 www.amis.com 22