PRELIMINARY DS1904 RTC iButton www.iButton.com SPECIAL FEATURES Real-Time Clock/calendar in binary format Uses the same binary time/date representation as the DS1994 but with 1 second resolution Clock accuracy is better than ± 2 minutes per month at 25°C Operating temperature range from -40°C to +70°C Over 10 years of operation Presence detector acknowledges when reader first applies voltage Meets UL#913 (4th Edit.); Intrinsically Safe Apparatus, Approved under Entity Concept for use in Class I, Division 1, Group A, B, C and D Locations (application pending) F5 MicroCan 5.89 COMMON iButton FEATURES Unique, factory–lasered and tested 64-bit registration number (8-bit family code + 48bit serial number + 8-bit CRC tester) assures absolute traceability because no two parts are alike Multidrop controller for MicroLAN Digital identification and information by momentary contact Chip-based data carrier compactly stores information Data can be accessed while affixed to object Economically communicates to host with a single digital signal at 16.3k bits per second Standard 16 mm diameter and 1-Wire protocol ensure compatibility with iButton Device family Button shape is self-aligning with cup-shaped probes Durable stainless steel case engraved with registration number withstands harsh environments Easily affixed with self-stick adhesive backing, latched by its flange, or locked with a ring pressed onto its rim 0.36 0.51 16.25 YYWW REGISTERED RR 40 24 17.35 000000FBC52B DATA GROUND All dimensions are shown in millimeters ORDERING INFORMATION DS1904L-F5 F5 MicroCan EXAMPLES OF ACCESSORIES DS9096P DS9101 DS9093RA DS9093A DS9092 Self-Stick Adhesive Pad Multi-Purpose Clip Mounting Lock Ring Snap-In Fob iButton Probe iButton DESCRIPTION The DS1904 RTC iButton is a rugged real-time clock module that can be accessed with minimal hardware. Data is transferred serially via the 1-Wire protocol, which requires only a single data lead and a ground return. The DS1904 contains a unique 64-bit factory-lasered ROM and a real-time clock/calendar implemented as a binary counter. The durable MicroCan package is highly resistant to environmental 1 of 12 022400 DS1904 hazards such as dirt, moisture, and shock. Accessories permit the DS1904 to be mounted on almost any surface including printed circuit boards and plastic key fobs. The DS1904 adds functions such as calendar, time and date stamp, stopwatch, hour meter, interval timer, and logbook to any type of electronic device or embedded application that uses a microcontroller. OVERVIEW The DS1904 has two main data components: 1) 64-bit lasered ROM, and 2) real-time clock counter (Figure 1). The real-time clock utilizes an on-chip oscillator that is connected to a 32.768 kHz crystal. The hierarchical structure of the 1-Wire protocol is shown in Figure 2. The bus master must first provide one of four ROM function commands: 1) Read ROM, 2) Match ROM, 3) Search ROM, 4) Skip ROM. The protocol for these ROM functions is described in Figure 7. After a ROM function command is successfully executed, the real-time clock functions become accessible and the master may then provide one of the real-time clock function commands. The protocol for these commands is described in Figure 5. All data is read and written least significant bit first. BLOCK DIAGRAM Figure 1 LID CONTACT DATA ROM FUNCTION CONTROL 64-BIT LASERED ROM CLOCK FUNCTION CONTROL READ/WRITE BUFFER 3V LITHIUM RTC COUNTER (32-BIT) OSCILLATOR CONTROL 32.768 kHz OSCILLATOR 1 Hz DIVIDER 64-BIT LASERED ROM Each DS1904 contains a unique ROM code that is 64 bits long. The first eight bits are a 1-Wire family code. The next 48 bits are a unique serial number. The last eight bits are a CRC of the first 56 bits. (See Figure 3.) The 1-Wire CRC is generated using a polynomial generator consisting of a shift register and XOR gates as shown in Figure 4. The polynomial is X8 + X5 + X4 + 1. Additional information about the Dallas Semiconductor 1-Wire Cyclic Redundancy Check is available in the Book of DS19xx iButton Standards. The shift register bits are initialized to zero. Then starting with the least significant bit of the family code, one bit at a time is shifted in. After the 8th bit of the family code has been entered, then the serial number is entered. After the 48th bit of the serial number has been entered, the shift register contains the CRC value. Shifting in the eight bits of CRC should return the shift register to all zeros. The 64-bit ROM and ROM Function Control section allow the DS1904 to operate as a 1-Wire device and follow the 1-Wire protocol detailed in the section "1-Wire Bus System". 2 of 12 DS1904 HIERARCHICAL STRUCTURE FOR 1-WIRE PROTOCOL Figure 2 1-Wire Bus Bus Master Other Devices DS1904 Command Level 1-Wire ROM Commands (see Figure DS1904 Function (see Figure Available Commands Data Fields Affected Read Match Search Skip 64-bit 64-bit 64-bit N/A Write Read RTC Counter, Device RTC Counter, Device 64-BIT LASERED ROM Figure 3 MSB LSB 8-Bit CRC Code MSB 48-Bit Serial Number LSB MSB 8-Bit Family Code (24h) LSB MSB LSB 1-WIRE CRC GENERATOR Figure 4 Polynomial = X8 + X5 + X4 + 1 R 1ST STAGE X0 2ND STAGE X1 X2 3RD STAGE 4TH STAGE X3 5TH STAGE X4 S 6TH STAGE X5 X6 7TH STAGE 8TH STAGE X7 INPUT DATA 3 of 12 X8 DS1904 TIMEKEEPING A 32.768 kHz crystal oscillator is used as the time base for the real-time clock counter. The oscillator can be turned on or off under software control. The oscillator must be on for the real time clock to function. The real-time clock counter is double buffered. This allows the master to read time without the data changing while it is being read. To accomplish this, a snapshot of the counter data is transferred to a read/write buffer, which the user accesses. DEVICE CONTROL BYTE The on/off control of the 32.768 kHz crystal oscillator is done through the device control byte. This byte can be read and written through the Clock Function commands. Device Control Byte 7 6 5 U4 U3 U2 Bit 0 - 1 0 4 U1 3 OSC 2 OSC 1 0 0 0 No function Bits 0 and 1 are hard-wired to read all 0’s. Bit 2 - 3 OSC Oscillator Enable/Disable These bits control/report whether the 32.768 kHz crystal oscillator is running. If the oscillator is running, both OSC bits will read 1. If the oscillator is turned off these bits will all read 0. When writing the device control byte both occurrences of the OSC bit should have identical data. Otherwise the value in bit address 3 (bold) takes precedence. Bit 4 - 7 Un General-purpose user flags These non-volatile bits have no particular function within the chip. They can be read and written under the control of the application software. REAL-TIME CLOCK The real-time clock is a 32-bit binary counter. It is incremented once per second. The real-time clock can accumulate 136 years of seconds before rolling over. Time/date is represented by the number of seconds since a reference point, which is determined by the user. For example, 12:00 a.m., January 1, 1970 could be a reference point. CLOCK FUNCTION COMMANDS The “Clock Function Flow Chart” (Figure 5) describes the protocols necessary for accessing the real-time clock. With only four bytes of real-time clock and one control byte the DS1904 does not provide random access. Reading and writing always starts with the device control byte followed by the least significant byte of the time data. 4 of 12 DS1904 CLOCK FUNCTION COMMAND FLOW CHART Figure 5 Master TX Control Function Command 66H Read Clock ? Y 99H Write Clock ? Y N DS1904 copies RTC Counter to R/W Buffer N Bus Master TX Device Control Byte Bus Master RX Device Control Byte Bus Master TX LS Byte (7:0) Bus Master RX LS Byte (7:0) Bus Master TX next Byte (15:8) Bus Master RX next Byte (15:8) Bus Master TX next Byte (23:16) Bus Master RX next Byte (23:16) Bus Master TX MS Byte (31:24) Bus Master RX MS Byte (31:24) N N Bus Master TX Reset ? Y Bus Master TX Reset ? Y DS1904 copies R/W Buffer to RTC Counter DS1904 TX Presence Pulse 5 of 12 N Bus Master TX Reset ? Y DS1904 READ CLOCK [66h] The read clock command is used to read the device control byte and the contents of the real-time clock counter. After having received the most significant bit of the command code the device copies the actual contents of the real-time clock counter to the read/write buffer. Now the bus master reads data beginning with the device control byte followed by the least significant byte through the most significant byte of the real-time clock. After this the bus master may continue reading from the DS1904. The data received will be the same as in the first pass through the command flow. The read clock command can be ended at any point by issuing a Reset Pulse. WRITE CLOCK [99h] The write clock command is used to set the real-time clock counter and to write the device control byte. After issuing the command, the bus master writes first the device control byte, which becomes immediately effective. After this the bus master sends the least significant byte through the most significant byte to be written to the real-time clock counter. The new time data is copied from the read/write buffer to the real-time clock counter and becomes effective as the bus master generates a reset pulse. If the oscillator is intentionally stopped, the real-time clock counter behaves as a four-byte non-volatile memory. 1-WIRE BUS SYSTEM The 1-Wire bus is a system, which has a single bus master and one or more slaves. In all instances the DS1904 is a slave device. The bus master is typically a microcontroller. The discussion of this bus system is broken down into three topics: hardware configuration, transaction sequence, and 1-Wire signaling (signal types and timing). A 1-Wire protocol defines bus transactions in terms of the bus state during specified time slots that are initiated on the falling edge of sync pulses from the bus master. For a more detailed protocol description, refer to Chapter 4 of the Book of DS19xx iButton Standards. HARDWARE CONFIGURATION Figure 6 BUS MASTER Open Drain Port Pin VPUP DS1904 1-WIRE PORT 5 kΩ Typ. DATA RX TX TX RX = RECEIVE TX = TRANSMIT RX 5 µA Typ. 100 Ω MOSFET Hardware Configuration The 1-Wire bus has only a single line by definition; it is important that each device on the bus be able to drive it at the appropriate time. To facilitate this, each device attached to the 1-Wire bus must have open drain or 3-state outputs. The 1-Wire input of the DS1904 is open drain with an internal circuit equivalent to that shown in Figure 6. A multidrop bus consists of a 1-Wire bus with multiple slaves attached. The 1Wire bus has a maximum data rate of 16.3k bits per second and requires a pull-up resistor of approximately 5kΩ. 6 of 12 DS1904 The idle state for the 1-Wire bus is high. If for any reason a transaction needs to be suspended, the bus MUST be left in the idle state if the transaction is to resume. If this does not occur and the bus is left low for more than 120 µs, one or more of the devices on the bus may be reset. Since the DS1904 gets all its energy for operation through its VDD pin it will NOT perform a power-on reset if the 1-Wire bus is low for an extended time period. Transaction Sequence The protocol for accessing the DS1904 via the 1-Wire port is as follows: • Initialization • ROM Function Command • Clock Function Command INITIALIZATION All transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence consists of a reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by the slave(s). The presence pulse lets the bus master know that the DS1904 is on the bus and is ready to operate. For more details, see the “1-Wire Signaling” section. ROM FUNCTION COMMANDS Once the bus master has detected a presence, it can issue one of the four ROM function commands that the DS1904 supports. All ROM function commands are eight bits long. A list of these commands follows (refer to flowchart in Figure 7): Read ROM [33h] This command allows the bus master to read the DS1904’s 8-bit family code, unique 48-bit serial number, and 8-bit CRC. This command should only be used if there is a single slave on the bus. If more than one slave is present on the bus, a data collision will occur when all slaves try to transmit at the same time (open drain will produce a wired-AND result). The resultant family code and 48-bit serial number read by the master will be invalid. Match ROM [55h] The match ROM command, followed by a 64-bit ROM sequence, allows the bus master to address a specific DS1904 on a multidrop bus. Only the DS1904 that exactly matches the 64-bit ROM sequence will respond to the following clock function command. All slaves that do not match the 64-bit ROM sequence will wait for a reset pulse. This command can be used with a single or multiple devices on the bus. SEARCH ROM [F0h] When a system is initially brought up, the bus master might not know the number of devices on the 1Wire bus or their 64-bit ROM codes. The search ROM command allows the bus master to use a process of elimination to identify the 64-bit ROM codes of all slave devices on the bus. The search ROM process is the repetition of a simple 3-step routine: read a bit, read the complement of the bit, then write the desired value of that bit. The bus master performs this 3-step routine on each bit of the ROM. After one complete pass, the bus master knows the 64-bit ROM code of one device. Additional passes will identify the ROM codes of the remaining devices. See Chapter 5 of the Book of DS19xx iButton Standards for a comprehensive discussion of a search ROM, including an actual example. 7 of 12 DS1904 ROM FUNCTIONS FLOW CHART Figure 7 Master TX Reset Pulse DS1904 TX Presence Pulse Master TX ROM Function Command 33H Read ROM Command ? Y DS1904 TX Family Code 1 Byte N 55H Match ROM Command ? F0H Search ROM Command ? Y N Y DS1904 TX Bit 0 Master TX Bit 0 DS1904 TX Bit 0 Master TX Bit 0 N Bit 0 Match ? N Bit 0 Match ? Y Y DS1904 TX Serial Number 6 Bytes DS1904 TX Bit 1 Master TX Bit 1 DS1904 TX Bit 1 Master TX Bit 1 N Bit 1 Match ? N Bit 1 Match ? Y Y DS1904 TX Bit 63 DS1904 TX CRC Byte Master TX Bit 63 DS1904 TX Bit 63 Master TX Bit 63 Bit 63 Match ? N N Bit 63 Match ? Y Y Master TX Control Function Command (SEE FIGURE 5) 8 of 12 N CCH Skip ROM Command ? Y N DS1904 Skip ROM [CCh] This command can save time in a single drop bus system by allowing the bus master to access the clock functions without providing the 64-bit ROM code. If more than one slave is present on the bus and, for example, a read command is issued following the Skip ROM command, data collision will occur on the bus as multiple slaves transmit simultaneously (open drain pull-downs will produce a wired-AND result). 1–WIRE SIGNALING The DS1904 requires strict protocols to ensure data integrity. The protocol consists of four types of signaling on one line: Reset Sequence with Reset Pulse and Presence Pulse, Write 0, Write 1 and Read Data. Except for the presence pulse the bus master initiates all these signals. The initialization sequence required to begin any communication with the DS1904 is shown in Figure 8. A reset pulse followed by a presence pulse indicates the DS1904 is ready to send or receive data. The bus master transmits (TX) a reset pulse (tRSTL, minimum 480 µs). The bus master then releases the line and goes into receive mode (RX). The 1-Wire bus is pulled to a high state via the pull-up resistor. After detecting the rising edge on the data line, the DS1904 waits (tPDH, 15-60 µs) and then transmits the presence pulse (tPDL, 60-240 µs). INITIALIZATION PROCEDURE “RESET AND PRESENCE PULSES” Figure 8 MASTER TX "RESET PULSE" MASTER RX "PRESENCE PULSE" tRSTH VPULLUP VPULLUP MIN VIH MIN VIL MAX 0V tRSTL RESISTOR MASTER DS1904 * ** tR tPDH tPDL 480 µs ≤ tRSTL < ∞* 480 µs ≤ tRSTH < ∞** 15 µs ≤ tPDH < 60 µs 60 ≤ tPDL < 240 µs In order not to mask interrupt signaling by other devices on the 1-Wire bus tRSTL + tR should always be less than 960 µs. Includes recovery time READ/WRITE TIME SLOTS The definitions of write and read time slots are illustrated in Figure 9. The master initiates all time slots by driving the data line low. The falling edge of the data line synchronizes the DS1904 to the master by triggering an internal delay circuit. During write time slots, the delay circuit determines when the DS1904 will sample the data line. For a read data time slot, if a “0” is to be transmitted, the delay circuit determines how long the DS1904 will hold the data line low. If the data bit is a “1”, the DS1904 will not hold the data line low at all. 9 of 12 DS1904 READ/WRITE TIMING DIAGRAM Figure 9 Write-one Time Slot tSLOT VPULLUP tREC VPULLUP MIN VIH MIN DS1904 Sampling VIL MAX 0V tLOW1 15µs (OD: 2µs) (OD: 6µs) 60µs 60 µs≤ tSLOT < 120 1 µs ≤ tLOW1 < 15 µs 1 µs ≤ tREC < ∞ RESISTO MASTER Write-zero Time Slot tREC tSLOT VPULLUP VPULLUP MIN VIH MIN DS1904 Sampling Window VIL MAX 0V 15µs (OD: 2µs) (OD: 6µs) 60µs t LOW0 RESISTOR 60 µs ≤ tLOW0 < tSLOT < 120 µs MASTER 1 µs ≤ tREC < ∞ Read-data Time Slot tREC tSLOT VPULLUP VPULLUP MIN VIH MIN Master Sampling Window VIL MAX 0V tSU tRELEASE tLOWR tRDV RESISTOR MASTER DS1904 60 µs ≤ tSLOT < 120 µs 1 µs ≤ tLOWR < 15 µs 0 ≤ tRELEASE < 45 µs 10 of 12 1 µs ≤ tREC < ∞ tRDV = 15 µs tSU < 1 µs DS1904 PHYSICAL SPECIFICATION Size Weight Humidity Altitude Expected Service Life Safety See mechanical drawing 3.3 grams 90% RH at 50°C 10000 feet 10 years at 25°C Meets UL#913 (4th Edit.); Intrinsically Safe Apparatus, Approval under Entity Concept for use in Class I, Division 1, Group A, B, C and D Locations (application pending) ABSOLUTE MAXIMUM RATINGS* Voltage on 1-Wire to Ground Operating Temperature Storage Temperature -0.5V to +7.0V -40°C to +70°C -40°C to +70°C * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. DC ELECTRICAL CHARACTERISTICS PARAMETER Logic 1 Logic 0 Output Logic Low @ 4 mA Output Logic High Input Load Current SYMBOL VIH VIL VOL VOH IL (VPUP=2.8V to 6.0V; -40°C to +70°C) MIN 2.2 -0.3 TYP MAX 6.0 0.8 0.4 VPUP 5 CAPACITANCE PARAMETER Capacitance 1-Wire NOTES 1 1,5 1 1,2 3 (tA = 25°C) SYMBOL CIN MIN AC ELECTRICAL CHARACTERISTICS PARAMETER Time Slot Write 1 Low Time Write 0 Low Time Read Low Time Read Data Valid Release Time Read Data Setup Recovery Time Reset High Time Reset Low Time Presence Detect High Presence Detect Low UNITS V V V V µA SYMBOL tSLOT tLOW1 tLOW0 tLOWR tRDV tRELEASE tSU tREC tRSTH tRSTL tPDH tPDL TYP MAX 50 UNITS pF NOTES (VPUP=2.8V to 6.0V; -40°C to +70°C) MIN 60 1 60 1 0 1 480 480 15 60 11 of 12 TYP exactly 15 15 MAX 120 15 120 15 45 1 960 60 240 UNITS µs µs µs µs µs µs µs µs µs µs µs µs NOTES 7 4 6 DS1904 NOTES: 1. 2. 3. 4. All voltages are referenced to ground. VPUP = external pull-up voltage. Input load is to ground. Read data setup time refers to the time the host must pull the 1-Wire bus low to read a bit. Data is guaranteed to be valid within 1 µs of this falling edge. 5. Under certain low voltage conditions VIL1MAX may have to be reduced to as much as 0.5V to always guarantee a presence pulse. 6. The reset low time (tRSTL) should be restricted to a maximum of 960 µs, to allow interrupt signaling, otherwise, it could mask or conceal interrupt pulses. 7. The master must read while the data is valid. 12 of 12