DtSheet

ASIX AX88170L Usb to fast ethernet/homepna controller Datasheet

AX88170 L
USB to Fast Ethernet/HomePNA Controller
USB to Fast Ethernet/HomePNA Controller
Document No.: AX170-12 / V1.2 / Apr. 11 ’01
Features
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•
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Single chip USB to 10/100Mbps Fast Ethernet and
1/10Mbps HomePNA Network Controller
Compliant with USB specification 1.0 and 1.1
Full Speed USB Device with bus power capability
USB Communication Class Spec 1.0 Compliant
Support 4 endpoints on USB
IEEE 802.3u 100BASE-T, TX, and T4 Compatible
Embedded 5K*16 bit SRAM
Support both full-duplex or half-duplex operation on
Fast Ethernet
Provides a MII port for both Ethernet and
HomePNA PHY interface
Supports suspended mode and remote wakeup
(link_up or magic packet)
Optional PHY power down mode for power saving
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Provides optional MII/RMII interface with PHY
mode for multiple ports USB-to-USB bridge
application.
Support 256/512 bytes serial EEPROM (used for
saving USB Descriptors)
Support automatic loading of Ethernet ID, USB
Descriptors and Adapter Configuration from
EEPROM on power-on initialization
External PHY loop-back diagnostic capability
Small form factor 64-pin LQFP package
48MHz and 25MHz Operation, pure 3.3V operation
with I/O 5V tolerance
*IEEE is a registered trademark of the Institute of Electrical and
Electronic Engineers, Inc.
*All other trademarks and registered trademark are the property of
their respect ive holders.
Product description
The AX88170 USB to Fast Ethernet/HomePNA Controller is a high performance and highly integrated Controller with
embedded 5K*16 bit SRAM. The AX88170 contains a USB interface to host CPU and compliant with USB Standard V1.0 and
V1.1. The interface between AX88170 and PC Host is compliant with USB Communication Class Specification 1.0. The
AX88170 could be used for both 10M/100Mbps Fast Ethernet function based on IEEE802.3 / IEEE802.3u LAN standard and
1M/10M HomePNA standard. The AX88170 supports media-independent interface (MII) or RMII (Reduce MII) interface to
simplify the design on implementing Fast Ethernet and HomePNA functions. The chip also provides an optional MII/RMII
interface with PHY mode, combine with Ethernet repeater or switch IC can build a multiple ports USB-to-USB bridge
application.
System Block Diagram
RJ45
RJ11
MAGNETIC
10/100 Mbps Ethernet
PHY/TxRx
AX88170
MAGNETIC
1/10 Mbps
Home LAN PHY
EEPROM
USB I/F
Always contact ASIX for possible updates before starting a design.
This data sheet contains new products information. ASIX ELECTRONICS reserves the rights to modify product specification without
notice. No liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product.
ASIX ELECTRONICS CORPORATION
Frist Released Date : Sep/11/2000
2F, NO.13, Industry East Rd. II, Science-based Industrial Park, Hsin-Chu City, Taiwan, R.O.C.
TEL: 886-3-579-9500
FAX: 886-3-579-9558
http://www.asix.com.tw
CONFIDENTIAL
AX88170
PRELIMINARY
CONTENTS
1.0 INTRODUCTION ...........................................................................................................................................................................4
1.1 GENERAL DESCRIPTION:............................................................................................................................................................ 4
1.2 AX88170 BLOCK DIAGRAM: ...................................................................................................................................................... 4
1.3 AX88170 PIN CONNECTION DIAGRAM WITH MII INTERFACE ........................................................................................... 5
1.4 AX88170 PIN CONNECTION DIAGRAM WITH RMII INTERFACE ......................................................................................... 6
2.0 SIGNAL DESCRIPTION...............................................................................................................................................................7
2.1 USB BUS INTERFACE SIGNALS GROUP .................................................................................................................................... 7
2.2 EEPROM SIGNALS GROUP ......................................................................................................................................................... 7
2.3A MII INTERFACE SIGNALS GROUP (MAC MODE) .................................................................................................................. 7
2.3B MII INTERFACE SIGNALS GROUP (PHY MODE)..................................................................................................................... 8
2.4 RMII INTERFACE SIGNAL PINS (PHY MODE) .......................................................................................................................... 9
2.5 M ISCELLANEOUS PINS GROUP ................................................................................................................................................... 9
3.0 EEPROM MEMORY MAPPING...............................................................................................................................................11
4.0 USB COMMANDS .......................................................................................................................................................................12
4.1 USB STANDARD COMMANDS................................................................................................................................................... 12
4.2 USB COMMUNICATION CLASS COMMANDS ......................................................................................................................... 13
4.3 USB VENDOR COMMANDS....................................................................................................................................................... 14
5.0 USB CONFIGURATION STRUCTURE...................................................................................................................................16
5.1 USB CONFIGURATION. ............................................................................................................................................................. 16
5.2 USB INTERFACE CLASS. ........................................................................................................................................................... 16
5.3 USB ENDPOINTS........................................................................................................................................................................ 16
6.0 ELECTRICAL SPECIFICATION AND TIMINGS .................................................................................................................17
6.1 A BSOLUTE M AXIMUM RATINGS ............................................................................................................................................ 17
6.2 GENERAL OPERATION CONDITIONS...................................................................................................................................... 17
6.3 DC CHARACTERISTICS.............................................................................................................................................................. 17
6.4 A.C. TIMING CHARACTERISTICS............................................................................................................................................. 18
6.4.1 25M_XIN............................................................................................................................................................................18
6.4.2 48M_XIN............................................................................................................................................................................18
6.4.3 Reset Timing......................................................................................................................................................................18
6.4.4 MII Timing of MAC mode................................................................................................................................................20
6.4.5 MII Timing of PHY mode .................................................................................................................................................21
6.4.6 RMII Interface Timing of PHY Mode.............................................................................................................................22
6.4.7 STATION MANAGEMENT TIMING..............................................................................................................................23
6.4.8 SERIAL EEPROM TIMING.............................................................................................................................................24
7.0 PACKAGE INFORMATION.......................................................................................................................................................25
APPENDIX A: SYSTEM APPLICATIONS ....................................................................................................................................26
A.1 USB TO FAST ETHERNET CONVERTER................................................................................................................................ 26
A.2 USB TO FAST ETHERNET AND/OR HOMELAN COMBO SOLUTION ................................................................................ 27
A.3 USB-T O-USB OR USB-T O-ETHERNET BRIDGE THROUGH ETHERNET REPEATER CONTROLLER ............................ 28
A.4 USB-T O-USB OR USB-T O-ETHERNET BRIDGE THROUGH ET HERNET SWITCH CONTROLLER................................. 28
DEMONSTRATION CIRCUIT A: AX88170 + ETHERNET PHY.............................................................................................29
DEMONSTRATION CIRCUIT B: AX88170 + HOMEPNA 1M8 PHY ....................................................................................31
DEMONSTRATION CIRCUIT C: 4 USB PORTS + 1 ETHERNET PORT BRIDGE AP.....................................................33
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AX88170
PRELIMINARY
FIGURES
FIG - 1 AX88170 BLOCK DIAGRAM ..................................................................................................................................................... 4
FIG - 2 AX88170 PIN CONNECTION DIAGRAM WITH MII INTERFACE ......................................................................................... 5
FIG - 3 AX88170 PIN CONNECTION DIAGRAM RMII INTERFACE .................................................................................................. 6
TABLES
TAB - 1 USB BUS INTERFACE SIGNALS GROUP .................................................................................................................................. 7
TAB - 2 EEPROM BUS INTERFACE SIGNALS GROUP ......................................................................................................................... 7
TAB - 3 MII INTERFACE SIGNALS GROUP (MAC MODE) ................................................................................................................. 8
TAB - 4 MII INTERFACE SIGNALS GROUP (PHY MODE) ................................................................................................................... 8
TAB - 5 RMII INTERFACE SIGNAL PINS (PHY MODE)....................................................................................................................... 9
TAB - 6 M ISCELLANEOUS PINS GROUP ............................................................................................................................................. 10
TAB - 7 EEPROM M EMORY M APPING............................................................................................................................................. 11
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ASIX ELECTRONICS CORPORATION
CONFIDENTIAL
AX88170
PRELIMINARY
1.0 Introduction
1.1 General Description:
The AX88170 USB to Fast Ethernet Controller is a high performance and highly integrated USB busEthernet Controller with
embedded 5K*16 bit SRAM. The AX88170 contains a full speed USB interface to host CPU and compliant with USB
Communication Class Spec. 1.0. The AX88170 implements both 10Mbps and 100Mbps Ethernet function based on
IEEE802.3 / IEEE802.3u LAN standard. The AX88170 supports media-independent interface (MII) or RMII (Reduce MII)
interface to simplify the design on implementing Fast Ethernet and HomePNA functions. The chip also provides an optional
MII/RMII interface with PHY mode, combines with Ethernet repeater or switch IC can build a multiple ports USB-to-USB
bridge application.
AX88170 uses 64-pin LQFP low profile package, 48MHz operation for USB and 25MHz operation for Ethernet, CMOS
process with pure 3.3V operation and 5 Volt I/O tolerance.
1.2 AX88170 Block Diagram:
SMDC
SMDIO
STA
5K* 16
SRAM
EECS
EECK
EEDI
EEDO
SEEPROM
Loader I/F
Memory Arbiter
USB to
Ethernet
Bridge
MAC
Core
MII I/F
Or
RMII I/F
USB Core and Interface
D-/D+
Fig – 1 AX88170 Block Diagram
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AX88170
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1.3 AX88170 Pin Connection Diagram with MII Interface
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
EEDO
EEDI
EECK
EECS
VDD
/S_RMII
VSS
/HomeLink
GPIO1
/PHY_RST
GPIO0
VDD
25M_XOUT
25M_XIN
VSS
25M_CLKO
The AX88170 is housed in the 64-pin plastic light quad flat pack. See Fig – 2 AX88170 Pin Connection
Diagram.
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
ASIX
AX88170
(MII Interface)
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
RX_DV
RX_ER
VDD
RXD3
RXD2
RXD1
RXD0
VSS
RX_CLK
VDD
TX_EN
TXD3
TXD2
TXD1
TXD0
VSS
D+
DVDD
/RST
VSS
SPD_UP
S_EXT
/S_FDPX
/S_MAC
VDD
VSS
MDC
COL
MDIO
CRS
TX_CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VSS
VDD
48M_XOUT
48M_XIN
VSS
VDD
TEST0
TEST1
TEST2
TEST3
VDD
TEST_OUT
TEST4
LD_RDY
ACT/LINK
VSS
Fig – 2 AX88170 Pin Connection Diagram with MII Interface
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1.4 AX88170 Pin Connection Diagram with RMII Interface
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
EEDO
EEDI
EECK
EECS
VDD
/S_RMII
VSS
/HomeLink
GPIO1
/PHY_RST
GPIO0
VDD
25M_XOUT
25M_XIN
VSS
25M_CLKO
The AX88170 is housed in the 64-pin plastic light quad flat pack. See Fig – 3 AX88170 Pin Connection
Diagram RMII Interface.
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
ASIX
AX88170
(RMII Interface)
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
NC
NC
VDD
NC
NC
RXD1
RXD0
VSS
NC
VDD
TX_EN
NC
NC
TXD1
TXD0
VSS
D+
DVDD
/RST
VSS
SPD_UP
S_EXT
/S_FDPX
/S_MAC
VDD
VSS
MDC
COL
MDIO
CRS_DV
REF_CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VSS
VDD
48M_XOUT
48M_XIN
VSS
VDD
TEST0
TEST1
TEST2
TEST3
VDD
TEST_OUT
TEST4
LD_RDY
ACT/LINK
VSS
Fig – 3 AX88170 Pin Connection Diagram RMII Interface
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2.0 Signal Description
The following terms describe the AX88170 pin-out:
All pin names with the “/” suffix are asserted low.
The following abbreviations are used in following Tables.
I
O
I/O
OD
Input
Output
Input/Output
Open Drain
PU
PD
P
Pull Up
Pull Down
Power Pin
2.1 USB Bus Interface Signals Group
SIGNAL
D+
D-
TYPE
I/O
I/O
PIN NO.
1
2
DESCRIPTION
USB Data Plus Pin
USB Data Minus Pin
Tab – 1 USB bus interface signals group
2.2 EEPROM Signals Group
SIGNAL
EECS
EECK
EEDI
EEDO
TYPE
O
O
O
I/PU
PIN NO.
45
46
47
48
DESCRIPTION
EEPROM Chip Select : EEPROM chip select signal.
EEPROM Clock : Signal connected to EEPROM clock pin.
EEPROM Data In : Signal connected to EEPROM data input pin.
EEPROM Data Out : Signal connected to EEPROM data output pin.
Tab – 2 EEPROM bus interface signals group
2.3a MII interface signals group (MAC mode)
When /S_RMII=1 and /S_MAC=0
SIGNAL
TYPE
PIN NO.
RXD[3:0]
I/PU
29, 28
27, 26
CRS
I/PD
15
RX_DV
I/PD
32
RX_ER
I/PD
31
RX_CLK
I/PU
24
COL
TX_EN
I/PD
O
13
22
DESCRIPTION
Receive Data: RXD[3:0] is driven by the PHY synchronously with respect
to RX_CLK.
Carrier Sense: Asynchronous signal CRS is asserted by the PHY when
either the transmit or receive medium is non-idle.
Receive Data Valid: RX_DV is driven by the PHY synchronously with
respect to RX_CLK. Asserted high when valid data is present on RXD
[3:0].
Receive Error: RX_ER is driven by PHY and synchronous to RX_CLK, is
asserted for one or more RX_CLK periods to indicate to the port that an
error has detected.
Receive Clock: RX_CLK is a continuous clock that provides the timing
reference for the transfer of the RX_DV,RXD[3:0] and RX_ER signals from
the PHY to the MII port of the MAC.
Collision: this signal is driven by PHY when collision is detected.
Transmit Enable: TX_EN is transition synchronously with respect to the
rising edge of TX_CLK. TX_EN indicates that the port is presenting
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AX88170
SIGNAL
PRELIMINARY
TYPE
PIN NO.
TXD[3:0]
O
21, 20
19, 18
TX_CLK
I
16
MDC
O
12
MDIO
I/O/PU
14
DESCRIPTION
nibbles on TXD [3:0] for transmission.
Transmit Data: TXD[3:0] is transition synchronously with respect to the
rising edge of TX_CLK. For each TX_CLK period in which TX_EN is
asserted ,TXD[3:0] are accepted for transmission by the PHY.
Transmit Clock: TX_CLK is a continuous clock from PHY. It provides the
timing reference for the transfer of the TX_EN and TXD[3:0] signals from
the MII port to the PHY.
Station Management Data Clock: The timing reference for MDIO. All data
transfers on MDIO are synchronized to the rising edge of this clock. MDC
is a 2.5MHz frequency clock output.
Station Management Data Input/Output: Serial data input/output transfers
from/to the PHYs. The transfer protocol conforms to the IEEE 802.3u MII
specification.
Tab – 3 MII interface signals group (MAC mode)
2.3b MII interface signals group (PHY mode)
When /S_RMII=1 and /S_MAC=1
SIGNAL
TYPE
PIN NO.
RXD[3:0]
O
29, 28
27, 26
CRS
O
15
RX_DV
O
32
RX_ER
RX_CLK
O
O
31
24
COL
O
13
TX_EN
I/PD
22
TXD[3:0]
I/PU
TX_CLK
O
21, 20
19, 18
16
DESCRIPTION
Receive Data: Basically RXD[3:0] is transformed from TXD[3:0] of MAC
mode of MII interface.
Carrier Sense: Basically CRS is transformed from TX_EN of MAC mode of
MII interface.
Receive Data Valid: Basically RX_DV is transformed from TX_EN of MAC
mode of MII interface.
Receive Error: No used
Receive Clock: Basically RX_CLK is sourced from internal 25MHz local
clock.
Collision: this signal is generated by internal logic when collision is
detected.
Transmit Enable: Basically TX_EN is simulation from RX_DV of MAC
mode of MII interface.
Transmit Data: Basically TXD[3:0] is simulation from RXD[3:0] of MAC
mode of MII interface.
Transmit Clock: Basically TX_CLK is sourced from internal 25MHz local
clock.
Tab – 4 MII interface signals group (PHY mode)
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PRELIMINARY
2.4 RMII interface signal pins (PHY mode)
When /S_RMII=0 and /S_MAC=1
SIGNAL
TYPE
PIN NO.
RXD[1:0]
O
27, 26
CRS_DV
O
15
TXD[1:0]
I/PU
19, 18
TX_EN
I/PD
22
I
16
REF_CLK
DESCRIPTION
Receive Data : Basically RXD[1:0] is transformed from TXD[1:0] of MAC
mode of RMII interface.
Carrier Sense _ Data Valid : Basically CRS_DV is transformed of TX_EN
from MAC mode of RMII interface.
Transmit Data : Basically TXD[1:0] is transformed from RXD[1:0] of MAC
mode of RMII interface.
Transmit Enable : Basically TX_EN is transformed from RX_DV from MAC
mode of RMII interface.
Reference clock : The input is a continue clock at 50Mhz for timing
reference with RMII interface.
Tab – 5 RMII interface signal pins (PHY mode)
2.5 Miscellaneous pins group
SIGNAL
25M_XIN
TYPE
I
PIN NO.
35
25M_XOUT
O
36
48M_XIN
I
52
48M_XOUT
O
51
25M_CLKO
/RST
O
I/PD
33
4
/S_RMII
I/PU
43
/S_MAC
I/PD
9
/S_FDPX
I/PD
8
S_EXT
I/PD
7
ID
6
SPD_UP
DESCRIPTION
CMOS Local Clock : Typical a 25Mhz clock, +/- 100 ppm, 40%-60% duty
cycle. ( See application note also )
Crystal Oscillator Input : Typical a 25Mhz crystal, +/- 25 ppm can be
connected across 25M_XIN and 25M_XOUT.
Crystal Oscillator Output : Typical a 25Mhz crystal, +/- 25 ppm can be
connected across 25M_XIN and 25M_XOUT. If a single-ended external
clock is connected to 25M_XIN, the crystal output pin should be left
floating.
48Mhz CMOS Clock In : Typical a 48Mhz clock, +/- 500 ppm, 40%-60% duty
cycle. ( See application note also )
48Mhz Crystal Oscillator Input: Typical a 48Mhz crystal, +/- 100 ppm can be
connected across 48M_XIN and 48M_XOUT.
48Mhz Crystal Oscillator Output: Typical a 48Mhz crystal, +/- 100 ppm can
be connected across 48M_XIN and 48M_XOUT. If a single-ended external
clock is connected to 48M_XIN, the crystal output pin should be left
floating.
Clock Output : This clock is source from 25M_XIN.
Reset:
Reset is active low then place AX88170 into reset mode immediately.
During Rising edge the AX88170 loads the EEPROM data.
Set to RMII mode:
0: RMII mode is selected.
1: MII mode is selected. (default)
Set MII/RMII interface to MAC mode:
0: MAC mode is selected. (default)
1: PHY mode is selected.
Set duplex mode when PHY mode is selected or When S_EXT is set and
MAC mode is selected:
0: full-duplex mode is selected. (default)
1: half-duplex mode is selected.
Select where duplex mode is sourced from when MAC mode:
0: duplex mode depands on internal register. (default)
1: duplex mode depands on external signal /S_FDPX
The setting is enable speed up test mode:
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AX88170
TEST0
I/PD
TEST1
I/PD
TEST2
I
TEST3
I/PD
TEST4
I/PD
TEST_OUT
LDRDY
ACT/LINK
O
O
O
/PHY_RST
GPIO0
GPIO1
/HOMELINK
VDD
O
B/PD
B/PD
I/PU
P
VSS
P
PRELIMINARY
0: Normal operation mode.
1: Speed up test mode enable.
55
Test Pin: This pin for test purpose only.
Pull down the pin or keep no connection for normal operation.
56
Test Pin: This pin for test purpose only.
Pull down the pin or keep no connection for normal operation.
57
Test Pin: This pin for test purpose only.
Pull down the pin for normal operation.
58
Test Pin: This pin for test purpose only.
Pull down the pin or keep no connection for normal operation.
61
Test Pin: This pin for test purpose only.
Pull down the pin or keep no connection for normal operation.
60
Test Output Pin: This pin for test purpose only.
62
Load EEPROM data completed indicator. Active high.
63
LED indicator: When link fail, drives logic high always. When link OK, the
pin drives logic low and will drives high a period when line has activity
(data transfer).
39
PHY Reset: This pin is used to reset PHY and is an active low signal.
38
General Purpose I/O 0: Refer to section 4.3 USB Vendor Commands
40
General Purpose I/O 1: Refer to section 4.3 USB Vendor Commands
41
Link Status: For external HomePHY link state input active low
3, 10, 23, 30 Power Supply: +3.3V DC.
37, 44, 50
54,59
5, 11
Power Supply: +0V DC or Ground Power.
17, 25, 34
42, 49, 53
64
Tab - 6 Miscellaneous pins group
MII/RMII interface Cross Reference Table
MII
RXD[0]
RXD[1]
RXD[2]
RXD[3]
CRS
RX_DV
RX_CLK
RX_ER
TX_EN
TX_CLK
TXD[0]
TXD[1]
TXD[2]
TXD[3]
COL
RMII
RXD[0]
RXD[1]
CRS_DV
TX_EN
REF_CLK (50MHz)
TXD[0]
TXD[1]
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3.0 EEPROM Memory Mapping
EEPROM
OFFSET
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H-18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H-4FH
50H-FFH
HIGH BYTE
LOW BYTE
RESERVED
WORD COUNT FOR PRELOAD
*FLAG
LENGTH OF DEVICE DESCRIPTOR (BYTE)
EEPROM OFFSET OF DEVICE
DESCRIPTOR
LENGTH OF CONFIGURATION DESCRIPTOR
EEPROM OFFSET OF CONFIGURATION
(BYTE)
DESCRIPTOR
NODE ID 1
NODE ID 0
NODE ID 3
NODE ID 2
NODE ID 5
NODE ID 4
LANGUAGE ID HIGH BYTE
LANGUAGE ID LOW BYTE
LENGTH OF STRING INDEX 1
EEPROM OFFSET OF STRING INDEX 1
LENGTH OF STRING INDEX 2
EEPROM OFFSET OF STRING INDEX 2
LENGTH OF STRING INDEX 3
EEPROM OFFSET OF STRING INDEX 3
LENGTH OF STRING INDEX 4
EEPROM OFFSET OF STRING INDEX 4
LENGTH OF STRING INDEX 5
EEPROM OFFSET OF STRING INDEX 5
LENGTH OF STRING INDEX 6
EEPROM OFFSET OF STRING INDEX 6
LENGTH OF STRING INDEX 7
EEPROM OFFSET OF STRING INDEX 7
LENGTH OF STRING INDEX 8
EEPROM OFFSET OF STRING INDEX 8 (19H)
MAX PACKETSIZE HIGH BYTE
MAX PACKET LOW BYTE
HOMEPNA PHY ID
ETHERNET PHY ID
PAUSE PACKET HIGH WATER LEVEL
PAUSE PACKET LOW WATER LEVEL
RESERVED
03H
0CH
BYTE 2 OF UNICODE MAC ADDRESS
**BYTE 1 OF UNICODE MAC ADDRESS
BYTE 4 OF UNICODE MAC ADDRESS
BYTE 3 OF UNICODE MAC ADDRESS
BYTE 6 OF UNICODE MAC ADDRESS
BYTE 5 OF UNICODE MAC ADDRESS
BYTE 8 OF UNICODE MAC ADDRESS
BYTE 7 OF UNICODE MAC ADDRESS
BYTE 10 OF UNICODE MAC ADDRESS
BYTE 9 OF UNICODE MAC ADDRESS
BYTE 12 OF UNICODE MAC ADDRESS
BYTE 11 OF UNICODE MAC ADDRESS
DEVICE /CONFIGURATION /INTERFACE /ENDPOINT DESCRIPTOR
STRINGS
Tab - 7 EEPROM Memory Mapping
Note:
*Flag:
Bit 0 è Self Powered (for USB GetStatus) Bit 1 è Bus Powered (Reserved)
Bit 2 è Remote Wakeup (for USB GetStatus) Bit 3 è Interrupt Endpoint Enaable (Reserved)
Bit 4 è ClkNoStop (for Self Power only)
Bit 5 è Reserved
Bit 6 è Reserved
Bit 7 è Reserved
Bit 8 è Capture Effective Mode
Bit 9 è Flow Control selector (1: software, o: read from PHY)
Bit A – F è Reserved
Bit 4 also effect LED display, if high then LED display USB active only otherwise display USB link and activity.
(In Self power mode Bit_4 set to high)
**Unicode MAC Address:
If the MAC’s NODE ID is 01,23,45,67,89,ABh respect to NODE ID 0, NODE ID 1, … NODE ID5
Then
the unicode will be 30-31,32-33,34-35,36-37,38-39,41-42h respects to BYTE 1 OF UNICODE MAC ADDRESS- BYTE
2 OF UNICODE MAC ADDRESS, … -BYTE 12 OF UNICODE MAC ADDRESS.
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4.0 USB Commands
There are three command groups for Endpoint 0 in AX88170:
l The USB standard commands
l USB Communication Class commands
l USB vendor commands.
4.1 USB standard commands
** The Language ID is 0x0904 for English
** PPLL means buffer length
** CC means configuration number
** I I means Interface number
SETUP COMMAND
80 06 00 01 00 00 LL PP
80 06 00 02 00 00 LL PP
80 06 00 03 00 00 LL PP
80 06 01 03 09 04 LL PP
80 06 02 03 09 04 LL PP
80 06 03 03 09 04 LL PP
80 06 04 03 09 04 LL PP
80 06 05 03 09 04 LL PP
80 06 06 03 09 04 LL PP
80 06 07 03 09 04 LL PP
80 06 08 03 09 04 LL PP
80 08 00 00 00 00 01 00
00 09 CC 00 00 00 00 00
81 0A 00 00 I I 00 01 00
01 0B AS 00 01 00 00 00
DATA IN/OUT
Data PPLL bytes
Data PPLL bytes
Data 2 bytes
Data PPLL bytes
Data PPLL bytes
Data PPLL bytes
Data PPLL bytes
Data PPLL bytes
Data PPLL bytes
Data PPLL bytes
Data 12 bytes
Data 1 bytes
No Data
Data 1 byte
No Data
12
DESCRIPTION
Get Device Descriptor
Get Configuration Descriptor
Get Supported Language ID
Get Manufacture String
Get Product String
Get Serial Number String
Get Configuration String
Get Interface 0 String
Get Interface 1/0 String
Get Interface 1/1 Stirng
Get Ethernet Address String
Get Configuration
Set Configuration
Get Interface
Set Interface
ASIX ELECTRONICS CORPORATION
CONFIDENTIAL
AX88170
PRELIMINARY
4.2 USB Communication Class Commands
** NN: number of multicast addresses
** BBAA: Ethernet Packet Filter
** TTSS: Number of Ethernet Statics
SETUP COMMAND
21 40 NN 00 00 00 6*N 00
21 41 00 00 00 00 10 00
A1 42 00 00 00 00 02 00
21 43 AA BB 00 00 00 00
DATA IN/OUT
Data 6*N bytes
Data 16 bytes
Data 2 bytes
No Data
DESCRIPTION
Set Ethernet Multicast Filters
Set Ethernet Power Management Pattern
Get Ethernet Power Management Pattern
Set Ethernet Packet Filter (AA BB)
Description of Ethernet Packet Filter (AA BB) Bitmap
BB = [D15:D8]
AA = [D7:D0]
Bit position
D15..D5
D4
D3
D2
D1
D0
DESCRIPTION
RESERVED (Reset to Zero)
PACKET_TYPE_MULTICAST
1: All multicast packets enumerated in the device’s multicast address list are
forwarded up to the host.
0: Disabled.
PACKET_TYPE_BROADCAST
1: All broadcast packet packets received by the networking device are forwarded
up to the host.
0: Disable.
PACKET_TYPE_DIRECTED
1: Directed packets received containing a destination address equal to the MAC
address of the networking device are forwarded up to the host.
0: Always not set to Zero.
PACKET_TYPE_ALL_MULTICAST
1 : ALL multicast frames received by the networking device are forwarded up to
the host, not just the ones enumerated in the device’s multicast address list.
0: Disabled.
PACKET_TYPE_PROMISCUOUS
1: ALL frames received by the networking device are forwarded up to the host.
0: Disabled.
Tab - 9 Ethernet Packet Filter Bitmap
13
ASIX ELECTRONICS CORPORATION
CONFIDENTIAL
AX88170
PRELIMINARY
4.3 USB Vendor Commands
SETUP COMMAND
C0 02 XX YY 00 0M 02 00
DATA IN/OUT
Data 2 bytes
40 03 XX YY PP QQ 00 00
40 04 XX YY PP QQ 00 00
40 06 00 00 00 00 00 00
C0 07 PI 00 RG 00 02 00
40 08 PI 00 RG 00 02 00
C0 09 00 00 00 00 01 00
40 0A 00 00 00 00 00 00
C0 0B DR 00 00 00 02 00
40 0C DR 00 MM SS 00 00
40 0D 00 00 00 00 00 00
40 0E 00 00 00 00 00 00
C0 0F 00 00 00 00 02 00
40 10 RR 00 00 00 00 00
C0 11 00 00 00 00 03 00
40 12 II 00 00 00 00 00
40 13 II 00 00 00 00 00
40 14 II 00 00 00 00 00
C0 15 00 00 00 00 08 00
40 16 00 00 00 00 08 00
C0 17 00 00 00 00 06 00
C0 19 00 00 00 00 02 00
C0 1A 00 00 00 00 01 00
40 1B MM 00 00 00 00 00
C0 1C 00 00 00 00 01 00
40 1D MM 00 00 00 00 00
No Data
No Data
No Data
Data 2 Bytes
Data 2 Bytes
Data 1 Bytes
No Data
Data 2 Bytes
No Data
No Data
No Data
Data 2 Bytes
No Data
Data 3 Bytes
No Data
No Data
No Data
Data 8 Bytes
Data 8 Bytes
Data 6 Bytes
Data 2 Bytes
Data 1 Byte
No Data
Data 1 Byte
No Data
DESCRIPTION
Read Rx/Tx SRAM
M = 0 : Rx, M=1 : Tx
Write Rx SRAM
Write Tx SRAM
Disable H/W MII Operation
Read MII Register
Write MII Register
Read MII Operation Mode
Enable H/W MII Operation
Read SROM
Write SROM
Write SROM Enable
Write SROM Disable
Read Rx Control Register
Write Rx Control Register
Read IPG/IPG1/IPG2 Register
Write IPG Register
Write IPG1 Register
Write IPG2 Register
Read Multi-Filter Array
Write Multi-Filter Array
Read Node ID
Read Ethernet/HomePNA PhyID
Read Medium Status(*)
Write Medium Mode(*)
Get Monitor Mode Status(**)
Set Monitor Mode On/Off(**)
Notes:
* Read / Write Medium status
Bit7
Bit6
Read
GPI1
X
Write
GPO1
GPO1EN
Bit5
GPI0
GPO0
Bit4
X
GPO0EN
** Read / Write Monitor Mode
Bit7-5
Bit4
Bit3
Read
Reserved
Flow_Contron_En X
(Hardware_Version
for ASIX only)
Write
X
Flow_Contron_En X
Bit3
Bit2
Home_Link 100MHz
FRBI
100MHz
Bit1
Bit0
Full_Duplex Link
Full_Duplex Link
Bit2
Bit1
Bit0
Magic_Packet_En Link_UP_Wake Monitor_Mode
Magic_Packet_En Link_UP_Wake Monitor_Mode
14
ASIX ELECTRONICS CORPORATION
CONFIDENTIAL
AX88170
PRELIMINARY
Interrupt Endpoint report link status format
Byte Number
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
A1
00
NN
00
NN
NN
NN
00
Fixed value
Fixed value
Bit_0 : Ethernet Link state, Bit_1 : Home PHY Link state (active high)
Fixed value
Bit_0 : 100MHz speed detect
Reserved (Hardware version for ASIX only)
Bit_0 : Full Duplex
Fixed value
15
ASIX ELECTRONICS CORPORATION
CONFIDENTIAL
AX88170
PRELIMINARY
5.0 USB Configuration Structure
5.1 USB Configuration.
The AX88170 supports 1 Configuration only.
5.2 USB Interface Class.
The AX88170 supports 2 interfaces, the interface 0 is Data Interface and interface 1 is for Communication Interface.
5.3 USB Endpoints.
The AX88170 supports 4 endpoints.
Endpoint 0 è Control endpoint, it is for configuring device.
Endpoint 1 è (optional) Interrupt endpoint, it is for reporting status change
Endpoint 2è Bulk Out endpoint, it is for Transmitting Ethernet Packet.
Endpoint 3 è Bulk In endpoint, it is for Receiving Ethernet Packet.
16
ASIX ELECTRONICS CORPORATION
CONFIDENTIAL
AX88170
PRELIMINARY
6.0 Electrical Specification and Timings
6.1 Absolute Maximum Ratings
Description
SYM
Min
Max
Units
Operating Temperature
Ta
0
+85
°C
Storage Temperature
Ts
-55
+150
°C
Supply Voltage
Vdd
-0.3
+3.6
V
Input Voltage
Vin
-0.3
Vdd+0.3
V
Output Voltage
Vout
-0.3
Vdd+0.3
V
Lead Temperature (soldering 10 seconds maximum)
Tl
-55
+240
°C
Note: Stress above those listed under Absolute M aximum Ratings may cause permanent damage to the device. Exposure to
Absolute Maximum Ratings conditions for extended period, adversely affect device life and reliability.
6.2 General Operation Conditions
Description
Operating Temperature
Supply Voltage
SYM
Min
Ta
0
Vdd
+3.0
Tpy
25
+3.30
Max
+70
+3.6
Units
°C
V
Tpy
Max
0.3*Vdd
0.4
+1
+10
Units
V
V
V
V
uA
uA
K ohm
Tpy
Max
6.3 DC Characteristics
(Vdd=3.0V to 3.6V, Vss=0V, Ta=0°C to 70°C)
Description
Low Input Voltage
High Input Voltage
Low Output Voltage
High Output Voltage
Input Leakage Current
Output Leakage Current
Input Pull-up / down resistance
SYM
Vil
Vih
Vol
Voh
Iil
Iol
Ri
Min
0.7*Vdd
2.4
-1
-10
Description
Power Consumption (3.3V)
SYM
SPt3v
Min
17
75
40
Units
mA
ASIX ELECTRONICS CORPORATION
CONFIDENTIAL
AX88170
PRELIMINARY
6.4 A.C. Timing Characteristics
6.4.1 25M_XIN
Thigh
25M_XIN
Tr
Tf
Tlow
Tcyc
25M_CLKO
Tod
Symbol
Tcyc
Thigh
Tlow
Tr/Tf
Tod
Description
Min
CYCLE TIME
CLK HIGH TIME
CLK LOW TIME
CLK SLEW RATE
LCLK/XTALIN TO 25M_CLKO OUT DELAY
Typ.
40
20
20
-
Max
Max
8.3
8.3
1
Typ.
20.83
10.42
10.42
-
Min
100
Typ.
-
Max
-
16
16
1
8
24
24
4
29
Units
ns
ns
ns
ns
ns
6.4.2 48M_XIN
Thigh
48M_XIN
Tr
Tf
Tlow
Tcyc
Symbol
Tcyc
Thigh
Tlow
Tr/Tf
Description
Min
CYCLE TIME
CLK HIGH TIME
CLK LOW TIME
CLK SLEW RATE
12.5
12.5
4
Units
ns
ns
ns
ns
6.4.3 Reset Timing
25M_XIN
/RST
Symbol
Trst
Description
Reset pulse width
18
Units
25M
_XIN
ASIX ELECTRONICS CORPORATION
CONFIDENTIAL
AX88170
PRELIMINARY
19
ASIX ELECTRONICS CORPORATION
CONFIDENTIAL
AX88170
PRELIMINARY
6.4.4 MII Timing of MAC mode
Ttclk
Ttch Ttcl
TXCLK(in)
Ttv
Tth
TXD<3:0>(out)
TXEN(out)
Trclk
Trch Trcl
RXCLK(in)
Trs
Trh
RXD<3:0>(in)
RXDV(in)
Trs1
RXER(in)
CRS(in)
Symbol
Ttclk
Ttclk
Ttch
Ttch
Trch
Trch
Ttv
Tth
Trclk
Trclk
Trch
Trch
Trcl
Trcl
Trs
Trh
Trs1
Description
Min
14
140
14
140
5
14
140
14
140
6
10
10
Cycle time(100Mbps)
Cycle time(10Mbps)
high time(100Mbps)
high time(10Mbps)
low time(100Mbps)
low time(10Mbps)
Clock to data valid
Data output hold time
Cycle time(100Mbps)
Cycle time(10Mbps)
high time(100Mbps)
high time(10Mbps)
low time(100Mbps)
low time(10Mbps)
data setup time
data hold time
RXER data setup time
20
Typ.
40
400
40
400
-
Max
26
260
26
260
20
26
260
26
260
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ASIX ELECTRONICS CORPORATION
CONFIDENTIAL
AX88170
PRELIMINARY
6.4.5 MII Timing of PHY mode
Ttclk
Ttch Ttcl
TXCLK(out)
Tts
Tth
TXD<3:0>(in)
TXEN(in)
Trclk
Trch Trcl
RXCLK(out)
Trs
Trh
RXD<3:0>(out)
RXDV(out)
Tcrsh
CRS(out)
Symbol
Ttclk
Ttclk
Ttch
Ttch
Trch
Trch
Tts
Tth
Trclk
Trclk
Trch
Trch
Trcl
Trcl
Trv
Trh
Tcrsh
Description
Min
14
140
14
140
15
0
14
140
14
140
10
10
10
Cycle time(100Mbps)
Cycle time(10Mbps)
high time(100Mbps)
high time(10Mbps)
low time(100Mbps)
low time(10Mbps)
TXD, TXEN setup to TXCLK high
TXD, TXEN hold to TXCLK high
Cycle time(100Mbps)
Cycle time(10Mbps)
high time(100Mbps)
high time(10Mbps)
low time(100Mbps)
low time(10Mbps)
RXD, RXDV valid to RXCLK high
RXCLK high to RXD, RXDV invalid
RXCLK high to CRS invalid
21
Typ.
40
400
40
400
-
Max
26
260
26
260
26
260
26
260
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ASIX ELECTRONICS CORPORATION
CONFIDENTIAL
AX88170
PRELIMINARY
6.4.6 RMII Interface Timing of PHY Mode
Tclk
Tch
Tcl
REF_CLK
Ts
Th
TX_EN
(in)
TXD
(in)
CRS_DV
(out)
Tod
Tod
RXD
(out)
Symbol
Tclk
Tch
Tcl
Ts
Th
Tod
Description
REF_CLK Clock Cycle Time
REF_CLK Clock High Time
REF_CLK Clock Low Time
TXEN and TXD data setup to REF_CLK high
TXEN and TXD data hold from REF_CLK high
REF_CLK rising edge to CRS_DV, RXD delay
Min
19.998
7
7
4
2
4
22
Typ.
20
10
10
Max
20.002
13
13
Units
ns
ns
ns
ns
ns
ns
ASIX ELECTRONICS CORPORATION
CONFIDENTIAL
AX88170
PRELIMINARY
6.4.7 STATION MANAGEMENT TIMING
Tclk
MDC
Tch
Tcl
Tod
MDIO
(output)
Ts
Th
MDIO
(input)
Symbol
Tclk
Tch
Tcl
Tod
Ts
Th
Description
MDC Clock Cycle Time
MDC Clock High Time
MDC Clock Low Time
Clock Falling Edge to Output Valid Delay
Data In Setup Time
Data In Hold Time
Min
2
10
100
23
Typ.
2560
1280
1280
Max
9
Units
ns
ns
ns
ns
ns
ns
ASIX ELECTRONICS CORPORATION
CONFIDENTIAL
AX88170
PRELIMINARY
6.4.8 SERIAL EEPROM TIMING
Tclk
EECK
Tch
Tcl
Tdv
EEDI
(output)
Tod
VALID
VALID
Tsc
s
Thcs
Tlcs
EECS
Ts
EEDO
(input)
Symbol
Tclk
Tch
Tcl
Tdv
Tod
Tscs
Thcs
Tlcs
Ts
Th
Th
DATA VA LID
Description
EECK Clock Cycle Time
EECK Clock High Time
EECK Clock Low Time
EEDI Data Valid Output to EECK High Time
EECK High to EEDI Data Output Delay Time
EECS Valid to EECK High Time
EECK Low to EECS Invalid Time
Minimum EECS Low Time
Data Input Setup Time
Data Input Hold Time
Min
2500
2500
500
500
300
0
2500
10
100
24
Typ.
5120
Max
9
9
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ASIX ELECTRONICS CORPORATION
CONFIDENTIAL
AX88170
PRELIMINARY
7.0 Package Information
A
A2
A1
L
L1
D
Hd
He
E
pin 1
e
b
θ
25
ASIX ELECTRONICS CORPORATION
CONFIDENTIAL
AX88170
PRELIMINARY
SYMBOL
MILIMETER
MIN.
NOM
MAX
A1
0.05
0.1
0.15
A2
1.35
1.40
1.45
A
1.60
b
0.17
0.22
D
10.00
E
10.00
e
0.5
Hd
12.00
He
12.00
L
0.45
0.60
L1
0.27
0.75
1.00
θ
0°
3.5°
7°
Appendix A: System Applications
Some typical applications for AX88170 are illustrated bellow.
A.1 USB to Fast Ethernet Converter
RJ45
MAGNETIC
10/100 PHY/TxRx
AX88170
EEPROM
USB I/F
26
ASIX ELECTRONICS CORPORATION
CONFIDENTIAL
AX88170
PRELIMINARY
A.2 USB to Fast Ethernet and/or HomeLAN Combo solution
RJ11
RJ45
MAGNETIC
MAGNETIC
10/100 Mbps
Ethernet PHY/TxRx
1/10 Mbps
Home LAN PHY
AX88170
EEPROM
USB I/F
27
ASIX ELECTRONICS CORPORATION
CONFIDENTIAL
AX88170
PRELIMINARY
A.3 USB-to-USB or USB-to-Ethernet Bridge through Ethernet Repeater Controller
AX88875
Repeater Controller
MII I/F
MII I/F
AX88170
USB I/F
Client
PC A
MII I/F
AX88170
MII I/F
AX88170
USB I/F
Client
PC B
MII I/F
AX88170
USB I/F
Ethernet PHY for
Up-link
USB I/F
Client
PC C
Client
PC D
To Ethernet Backend
Note : Using AX88871 for 8-port or less then 8-port solutions.
A.4 USB-to-USB or USB-to-Ethernet Bridge through Ethernet Switch Controller
AX88615
Switch Controller
MII I/F
MII I/F
AX88170
USB I/F
Client
PC A
MII I/F
AX88170
USB I/F
Client
PC B
MII I/F
AX88170
MII I/F
AX88170
USB I/F
Ethernet PHY for
Up-link
USB I/F
Client
PC C
Client
PC D
28
To Ethernet Backend
ASIX ELECTRONICS CORPORATION
AX88170
USB to Fast Ethernet/HomePNA Controller
Demonstration Circuit A: AX88170 + Ethernet PHY
R1
AX88710 L Application for
10BASE-T/100BASE-TX
20K
R2
R3
Y1
48M_XIN
1M
48M_XOUT
Y2
25M_XOUT
25M_XIN
L1
2.2uH
0
48M
C1
8p
C2
8p
C5
22p
25M
C3
20P
*1 USB Port Link/Act LED
U1
VDD3
VDD3
R4
330
D1
48M_XOUT
48M_XIN
51
52
ACT/LINK#
63
LED
RST#
USB-CON
4
3
2
1
R6
R7
18
18
62
1
2
D+
D-
3
4
1
2
S
DD+
VDD5
GND
4
R5
1.5K
S
J1
C6
C7
20P
20P
R8
55
56
57
58
61
60
4.7K
VDD3
U2
C8
0.01u
L2
VDD3
VCC
RESET#
GND
FUSE
1
2
3
VDD3
RST#
GND
VDD3
VDD3
VDD3
V6300C
VDD3
L3
F.B.
C9
C10
C11
C12
C13
0.1u
0.1u
0.1u
0.1u
0.1u
3
10
23
30
37
44
50
54
59
5
11
17
25
34
42
49
53
64
L4
F.B.
D2
C4
20P
R9
10K
1N4148
48M_XOUT
48M_XIN
ACT/LINK
/RST
LEERDY
D+
DTEST0
TEST1
TEST2
/EP78DIS TEST3
TEST4
TEST_OUT
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
/HOMELINK
GPIO1
/PHY_RST
GPIO0
RX_DV
RX_ER
RXD3
RXD2
RXD1
RXD0
RX_CLK
TX_EN
TXD3
TXD2
TXD1
TXD0
TX_CLK
CRS
COL
MDIO
MDC
25M_CLKO
25M_XIN
25M_XOUT
EEDO
EEDI
EECK
EECS
/S_RMII
/S_MAC
/S_FDPX
S_EXT
SPD_UP
41
40
39
38
PRST#
32
31
29
28
27
26
24
22
21
20
19
18
16
15
13
RXDV
RXER
RXD3
RXD2
RXD1
RXD0
RXCLK
TXEN
TXD3
TXD2
TXD1
TXD0
TXCLK
CRS
COL
14
12
MDIO
MDC
33
25MHZ
35
36
25M_XIN
25M_XOUT
48
47
46
45
EEDO
EEDI
EECK
EECS
PRST#
RXDV
RXER
RXD3
RXD2
RXD1
RXD0
RXCLK
TXEN
TXD3
TXD2
TXD1
TXD0
TXCLK
CRS
COL
MDIO
MDC
25MHZ
43
9
8
7
6
RST#
AX88170 L
*2 RC reset (option)
U3
C14
0.47u
EECS
EECK
EEDI
EEDO
1
2
3
4
CS
SK
DI
DO
VCC
NC
NC
GND
8
7
6
5
VDD3
VDD3
5V
93C56R
U4
3
VOUT
VIN
ADJ/GND
+ C16
10u/16V
VDD3
2
1
+ C15
AMS1117 - 3.3
C19
1000P
VDD3
10u/16V
C17
C18
0.1u
0.01u
GND
GND
ASIX ELECTRONIC CORPORATION
Title
AX88170
Size
B
Document Number
170AP1A.SCH
Date:
29
Monday, February 26, 2001
Rev
2.0
Sheet
1
of
2
ASIX ELECTRONICS CORPORATION
AX88170
USB to Fast Ethernet/HomePNA Controller
RXDV
RXER
RXD3
RXD2
RXD1
RXD0
RXCLK
TXEN
TXD3
TXD2
TXD1
TXD0
TXCLK
GND
R22
4.7K
18
19
20
21
22
23
24
27
29
30
31
32
33
28
34
39
CRS
COL
VDD3 R25
2K
35
45
MDIO
MDC
9
PRST#
25MHZ
GND
VDD3 R30
GND R31
4.7K
4.7K
VDD3
VDD3
VDD3
VDD3
VDD3
47
48
16
12
10
7
13
15
25
37
38
46
C33
C34
C35
C36
0.1u
0.1u
0.1u 0.1u
0.1u
1:1
1:1
U6
RXDV
RXER
RXD3
RXD2
RXD1
RXD0
RXCLK
TXEN
TXD3
TXD2
TXD1
TXD0
TXCLK
TXER
CRS/PHY[3]
COL/PHY[4]
MDIO
MDC
RSTZ
XIN
XOUT
TPTX+
TPTXTPRX+
TPRXAUTONEN
100FDEN
100HDEN
LEDSP/10FDEN
LEDFD/10HDEN
LNKLED/BPALIGN
LEDRX
LEDCOL/BP4B5B
LEDTX/ACTLED/BPSCR
REF100
REF10
RESV
RESV
TPTXTR
MDIOINTZ/PHY[2]
PHY[1]
PHY[0]
CSVDD
CSVDD
EQVDD1
VDD5
VDD1
VDD8
VDD4
VDD6
XTLVDD
CSGND
53
TDP
54
TDN
61
RDP
62
RDN
4
2
11
17
43
44
40
42
41
1
2
3
6
7
8
SPDLED
FULLED
R12
R13
R14
R15
R23
4.7K
4.7K
4.7K
4.7K
4.7K
LNKLED
R24
4.7K
ACTLED
R26
4.7K
R27
R28
301
4.65K
VDD3
J2
1
2
3
16
15
14
6
7
8
11
10
9
16
15
14
4
5
7
8
TS6121A
R17
49.9
R16
49.9
R18
75
R19
75
R20
75
R21
75
RJ45
C20
C21
0.01u
0.01u
C24
0.01u
0.01u
GND
GND
GND
58
57
R29
1
C22
0.01u/2KV
VDD3
VDD3
C27
56
1
2
3
6
11
10
9
C23
50
49
8
1
5
TX+
TXRX+
RX-
0.1u
+ C25
C26
1000P
4.7u/16V
FULLED
R32
510 LED
D3
FULL DUPLEX LED
SPDLED
R33
510 LED
D4
SPEED LED
ACTLED
R34
510
D5
LED
ACTIVITY LED
LNKLED
R35
510
D6
LED
LINK LED
L5
TXVDD1
TXVDD2
TXGND1
C32
TX
RX
R11
49.9
S
R10
49.9
U5
S
Set PHY Address to 00010：
VDD3
51
55
52
C30
C31
0.1u
0.1u
+ C28
F.B.
C29
1000P
4.7u/16V
L6
3
6
14
26
36
GND9
EQGND1
GND1
GND8
GND4
RXVDD1
RXVDD2
RXGND1
RXGND2
VDD3
59
64
60
63
C39
C40
0.1u
0.1u
+ C37
F.B.
C38
1000P
4.7u/16V
LU3X31T-T64
VDD3
VDD3
VDD3
+ C41
4.7u/16V
GND
C42
0.1u
GND
ASIX ELECTRONIC CORPORATION
Title
LU3X31
30
Size
B
Document Number
170AP1A1.SCH
Date:
Monday, February 26, 2001
Rev
2.0
Sheet
2
of
2
ASIX ELECTRONICS CORPORATION
AX88170
USB to Fast Ethernet/HomePNA Controller
Demonstration Circuit B: AX88170 + HomePNA 1M8 PHY
R18
AX88710 Application for 1M8 HomePNA
20k
R19
R20
Y1
Y2
48M_XIN
48M_XOUT
L3
2.2uH
25M_XIN
25M_XOUT
0
48M
C15
8p
1M
25M
C16
8p
C17
20P
C18
20P
C19
22pF
*1 USB Port Link/Act LED
VDD3
VDD3
R21
330
D5
U3
48M_XOUT
48M_XIN
51
52
ACT/LINK#
63
LED
RST#
USB-CON
R22
1.5K
S
J2
4
3
2
1
R24
R25
18
18
C20
C21
20P
20P
R26
VDD3
1
2
3
VCC
RESET#
GND
F1
FUSE
VDD3
VDD3
RST#
GND
VDD3
VDD3
VDD3
V6300C
C23
VDD3
L4
F.B.
55
56
57
58
61
60
4.7K
3
4
1
2
U4
C22
0.01u
62
1
2
D+
D-
S
DD+
VDD5
GND
4
0.1u
C24
0.1u
C25
C26
0.1u
0.1u
5
11
17
25
34
42
49
53
64
0.1u
F.B.
R29
10K
1N4148
ACT/LINK
/RST
LEERDY
D+
DTEST0
TEST1
TEST2
/EP78DIS TEST3
TEST4
TEST_OUT
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
C27
L5
D6
3
10
23
30
37
44
50
54
59
48M_XOUT
48M_XIN
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
/PHY_PWN
PHY_PWN
/PHY_RST
PHY_RST
RX_DV
RX_ER
RXD3
RXD2
RXD1
RXD0
RX_CLK
TX_EN
TXD3
TXD2
TXD1
TXD0
TX_CLK
CRS
COL
MDIO
MDC
25M_CLKO
25M_XIN
25M_XOUT
EEDO
EEDI
EECK
EECS
/S_RMII
/S_MAC
/S_FDPX
S_EXT
SPD_UP
41
40
39
38
PRST#
32
31
29
28
27
26
24
22
21
20
19
18
16
15
13
RXDV
14
12
MDIO
MDC
33
25MHZ
35
36
25M_XIN
25M_XOUT
48
47
46
45
EEDO
EEDI
EECK
EECS
PRST#
RXDV
RXD3
RXD2
RXD1
RXD0
RXCLK
TXEN
TXD3
TXD2
TXD1
TXD0
TXCLK
CRS
COL
RXD3
RXD2
RXD1
RXD0
RXCLK
TXEN
TXD3
TXD2
TXD1
TXD0
TXCLK
CRS
COL
R23
4.7K
MDIO
MDC
25MHZ
VDD3
VDD3
R27
4.7K
R28
4.7K
43
9
8
7
6
RST#
AX88170 L
*2 RC reset (option)
C28
0.47u
U5
VDD3
5V
EECS
EECK
EEDI
EEDO
U6
3
VOUT
VIN
ADJ/GND
+ C30
47u/16V
2
VDD3
1
+ C29
AMS1117
C33
1000P
VDD3
47u/16V
C31
C32
0.1u
0.01u
GND
1
2
3
4
CS
SK
DI
DO
VCC
NC
NC
GND
8
7
6
5
VDD3
93C56R
GND
ASIX ELECTRONIC CORPORATION
Title
AX88170
31
Size
B
Document Number
170AP2A.SCH
Date:
Monday, February 26, 2001
Rev
2.0
Sheet
2
of
2
ASIX ELECTRONICS CORPORATION
AX88170
USB to Fast Ethernet/HomePNA Controller
Set PHY Address TO 00001 and LED DISPLAY C.K.T. ：
TXD0
TXD1
TXD2
TXD3
TXCLK
TXEN
TXD0
TXD1
TXD2
TXD3
TXCLK
TXEN
VDD3
U1
R2
4.7K
RXD0
RXD1
RXD2
RXD3
RXCLK
RXDV
COL
CRS
RXD0
RXD1
RXD2
RXD3
RXCLK
RXDV
COL
CRS
VDD3
R9
4.7K
MDC
MDIO
MDC
MDIO
VDD3
GND
VDD3
GND
36
35
34
33
32
31
R4
20
25MHZ
PRST#
25MHZ
PRST#
TXD3
TXD2
TXD1
TXD0
TXEN
TXCLK
RXD3
RXD2
RXD1
RXD0
RXDV
RXCLK R7
23
24
25
26
27
28
20
COL
CRS
37
38
MDIO
MDC
21
22
25MHZ
45
46
VDD3
VDD3
+ C1
47u/16V
19
29
C2
C3
0.1u
0.01u
C4
0.1u
39
AVDD3_1
L1
48
5
11
VDD3
+ C5
47u/16V
C7
F.B.
+ C6
C8
47u/16V 0.01u
0.01u
AVDD3_2
47u/16V
C12 F.B.
0.01u
+ C11
C13
47u/16V 0.01u
40
41
0.1u
47
3
6
10
1
2
9
R3
10K
R5
330
R6
10K
R8
330
R10
10K
R11
330
R13
10K
YELLOW LED
D3
SPEEDLED#
RING
7
TIP
8
RING
YELLOW LED
D4
MDIO
MDC
POWERLED#
RBIAS
4
RED LED
X1
X2
R12
9.31K
1%
IO_VDD1
IO_VDD2
CORE_VDD
ANA_VDD1
ANA_VDD2
ANA_VDD3
LED_COL/PHYAD2
LED_ACT/PHYAD1
LED_SPEED/PHYAD3
LED_POWER/PHYAD4
C14
330
D2
COLLED#
TIP
COL/MDIO_INT_EN#
CRS/PIN_INTRP_EN#
R1
GREEN LED
0.1u
L2
+ C10
ACTLED#
RXD3/PHYAD0
RXD2/CMDDIS#
RXD1/HI_POWER_EN#
RXD0/RXD/LOW_SPEED_EN#
RX_DV/GPSI_SEL#
RX_CLK
C9
20
30
VDD3
D1
TXD3
TXD2
TXD1
TXD0/TXD
TX_EN
TX_CLK
RESET#
17
18
COLLED#
ACTLED#
VDD3
16
15
SPEEDLED#
POWERLED#
44
PRST#
R14
49.9
IO_GND1
IO_GND2
CORE_GND
CORE_SUB(0V)
ANA_GND1
ANA_GND2
ANA_GND3
ANA_GND4
SUB_GND1
SUB_GND2
SUB_GND3
R15
49.9
U2
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
12
13
14
42
43
TIP
RING
R16
4.7K
R17
0
DP83851C
1
2
3
4
5
6
7
8
J1
+
GND
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
TIP
RING
16
15
14
13
12
11
10
9
1
2
3
4
5
6
NC
A1
TIP
RING
A2
NC
RJ11
HR002
Title
HOMENET PHY C.K.T.
Size
B
Document Number
170AP2A1.SCH
Date:
32
Monday, February 26, 2001
Rev
2.0
Sheet
1
of
2
ASIX ELECTRONICS CORPORATION
AX88170
USB to Fast Ethernet/HomePNA Controller
Demonstration Circuit C: 4 USB Ports + 1 Ethernet Port Bridge AP
AX88170 L PHY mode application (MII Interface)
VDD5
JP1
U1
L1
+5V
1
+
2
C1
200u/16V
3
VDD5
F.B.
C4
0.1u
C5
1000p
VDD5
+
C2
200u/16V
L2
C6
0.1u
C7
1000p
C8
C11
47u/16V
0.1u
VIN
VDD3
1
ADJ/GND
C3
C9
C10
47u/16V
0.1u
0.01u
GND
+
AMS1084-3.3V
+
GND
GND5
2
VOUT
3
F.B.
4
POWER CONNECTOR
(POWER IN: 5V/3A)
VDD5
VDD5
U2A
1
U2B
2
3
74LV04
4
R2
20
25M_USB0
U4A
VCC
RESET#
GND
74LV04
U2C
5
R1
10K
U3
1
2
3
1
R3
20
2
3
4
RST_EN#
6
RST_USB#
GND
V6300F
6
U4B
74HC04
74HC04
25M_USB1
VDD3
U5
R4
OUT
L3
8
VCC
GND
5
51
74LV04
25MHZ
U4C
U2D
4
5
9
8
R5
20
25M_USB2
F.B.
C12
0.1u
C13
1000p
OSC 25MHZ
74HC04
74LV04
U2E
11
10
R6
20
25M_USB3
74LV04
VDD5
R7
20
U6A
1
VDD3
2
3
GND
*1 R7 & R8 : Adjust ax88875AP
LCLK to AX88170 L TXCLK
U6B
4
R8
20
25M_USB0
25M_REP
25M_USB1
74F04
25M_USB2
74F04
25M_USB3
U6C
25M_REP
5
6
R9
20
25M_PHY
25M_PHY
*2 R9 & R10 : Adjust DM9191F
LCLK to AX88875AP LCLK
74F04
RST_EN#
RST_USB#
R10
20
VDD5
VDD3
GND
25M_USB0
25M_USB1
25M_USB2
25M_USB3
25M_REP
25M_PHY
RST_EN#
RST_USB#
Title
POWER & RESET C.K.T.
Size
B
Document Number
170AP5A.SCH
Date:
33
Monday, February 26, 2001
Rev
2.0
Sheet
1
of
7
ASIX ELECTRONICS CORPORATION
AX88170
USB to Fast Ethernet/HomePNA Controller
VDD3
VDD3
VDD3
GND
GND
VDD3
*3 USB Port Link/Act LED
R11
VDD3
U7
48M_XOUT
48M_XIN
51
52
ACT/LINK#
63
Q1
R12
2SC2412K
330
D1
LED
1K
R13
USB-CON
4
3
2
1
R14
R15
L4
ALDONE
D+
D-
18
18
F.B.
4
2
3
1
S
DD+
VDD5
GND
RST#
RST_USB#
4
/HOMELINK
GPIO1
ACT/LINK
/PHY_RST
GPIO0
/RST
1.5K
S
J1
48M_XOUT
48M_XIN
C14
C15
20P
20P
R16
55
56
57
58
61
60
4.7K
VDD3
VDD3
C16
0.01u
VDD3
VDD3
VDD3
R17
C22
8p
C19
C20
C21
0.1u
0.1u
0.1u
0.1u
0.1u
3
10
23
30
37
44
50
54
59
5
11
17
25
34
42
49
53
64
R20
48M_XOUT
LEERDY
D+
DTEST0
TEST1
TEST2
/EP78DIS TEST3
TEST4
TEST_OUT
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
39
38
32
31
29
28
27
26
24
22
21
20
19
18
16
15
13
MDIO
MDC
14
12
25M_CLKO
33
25M_XIN
25M_XOUT
35
36
EEDO
EEDI
EECK
EECS
/S_RMII
/S_MAC
/S_FDPX
S_EXT
SPD_UP
48
47
46
45
43
9
8
7
6
RXDV
RXDV0
RXD3
RXD2
RXD1
RXD0
RXCLK
TXEN
TXD3
TXD2
TXD1
TXD0
RXD03
RXD02
RXD01
RXD00
RXCLK0
TXEN0
TXD03
TXD02
TXD01
TXD00
CRS
CRS0
25M_USB0
EEDO
EEDI
EECK
EECS
VDD3
R18
R19
10K
10K
0
48M
L5
2.2uH
C18
20k
Y1
48M_XIN
C17
62
1
2
RX_DV
RX_ER
RXD3
RXD2
RXD1
RXD0
RX_CLK
TX_EN
TXD3
TXD2
TXD1
TXD0
TX_CLK
CRS
COL
41
40
C23
8p
AX88170 L
C24
22pF
U8
EECS
EECK
EEDI
EEDO
1
2
3
4
CS
SK
DI
DO
VCC
NC
NC
GND
8
7
6
5
VDD3
93C56R
ASIX ELECTRONIC CORPORATION
Title
AX88170 CIRCUIT 1
34
Size
B
Document Number
170AP5A1.SCH
Date:
Monday, February 26, 2001
Rev
2.0
Sheet
2
of
7
ASIX ELECTRONICS CORPORATION
AX88170
USB to Fast Ethernet/HomePNA Controller
VDD3
VDD3
VDD3
GND
GND
VDD3
*4 USB Port Link/Act LED
R21
VDD3
U9
48M_XOUT
48M_XIN
51
52
ACT/LINK#
63
Q2
R22
2SC2412K
330
D2
LED
1K
R23
USB-CON
4
3
2
1
R24
R25
L6
ALDONE
D+
D-
18
18
F.B.
4
2
3
1
S
DD+
VDD5
GND
RST#
RST_USB#
4
/HOMELINK
GPIO1
ACT/LINK
/PHY_RST
GPIO0
/RST
1.5K
S
J2
48M_XOUT
48M_XIN
C25
C26
20P
20P
R26
55
56
57
58
61
60
4.7K
VDD3
VDD3
C27
0.01u
VDD3
VDD3
VDD3
R27
C33
8p
C30
C31
C32
0.1u
0.1u
0.1u
0.1u
0.1u
3
10
23
30
37
44
50
54
59
5
11
17
25
34
42
49
53
64
R30
48M_XOUT
LEERDY
D+
DTEST0
TEST1
TEST2
/EP78DIS TEST3
TEST4
TEST_OUT
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
39
38
32
31
29
28
27
26
24
22
21
20
19
18
16
15
13
MDIO
MDC
14
12
25M_CLKO
33
25M_XIN
25M_XOUT
35
36
EEDO
EEDI
EECK
EECS
/S_RMII
/S_MAC
/S_FDPX
S_EXT
SPD_UP
48
47
46
45
43
9
8
7
6
RXDV
RXDV1
RXD3
RXD2
RXD1
RXD0
RXCLK
TXEN
TXD3
TXD2
TXD1
TXD0
RXD13
RXD12
RXD11
RXD10
RXCLK1
TXEN1
TXD13
TXD12
TXD11
TXD10
CRS
CRS1
25M_USB1
EEDO
EEDI
EECK
EECS
VDD3
R28
R29
10K
10K
0
48M
L7
2.2uH
C29
20k
Y2
48M_XIN
C28
62
1
2
RX_DV
RX_ER
RXD3
RXD2
RXD1
RXD0
RX_CLK
TX_EN
TXD3
TXD2
TXD1
TXD0
TX_CLK
CRS
COL
41
40
C34
8p
AX88170 L
C35
22pF
U10
EECS
EECK
EEDI
EEDO
1
2
3
4
CS
SK
DI
DO
VCC
NC
NC
GND
8
7
6
5
VDD3
93C56R
ASIX ELECTRONIC CORPORATION
Title
AX88170 CIRCUIT 2
35
Size
B
Document Number
170AP5A2.SCH
Date:
Monday, February 26, 2001
Rev
2.0
Sheet
3
of
7
ASIX ELECTRONICS CORPORATION
AX88170
USB to Fast Ethernet/HomePNA Controller
VDD3
VDD3
VDD3
GND
GND
VDD3
*5 USB Port Link/Act LED
R31
VDD3
U11
48M_XOUT
48M_XIN
51
52
ACT/LINK#
63
Q3
R32
2SC2412K
330
D3
LED
1K
R33
USB-CON
4
3
2
1
R34
R35
L8
ALDONE
D+
D-
18
18
F.B.
4
2
3
1
S
DD+
VDD5
GND
RST#
RST_USB#
4
ACT/LINK
/RST
1.5K
S
J3
48M_XOUT
48M_XIN
C36
C37
20P
20P
R36
55
56
57
58
61
60
4.7K
VDD3
VDD3
C38
0.01u
VDD3
VDD3
VDD3
R37
C44
8p
C41
C42
C43
0.1u
0.1u
0.1u
0.1u
0.1u
3
10
23
30
37
44
50
54
59
5
11
17
25
34
42
49
53
64
R40
48M_XOUT
LEERDY
D+
DTEST0
TEST1
TEST2
/EP78DIS TEST3
TEST4
TEST_OUT
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
/PHY_RST
GPIO0
RX_DV
RX_ER
RXD3
RXD2
RXD1
RXD0
RX_CLK
TX_EN
TXD3
TXD2
TXD1
TXD0
TX_CLK
CRS
COL
41
40
39
38
32
31
29
28
27
26
24
22
21
20
19
18
16
15
13
MDIO
MDC
14
12
25M_CLKO
33
25M_XIN 35
36
25M_XOUT
48
EEDO 47
EEDI 46
EECK 45
EECS
/S_RMII
/S_MAC
/S_FDPX
S_EXT
SPD_UP
43
9
8
7
6
RXDV
RXDV2
RXD3
RXD2
RXD1
RXD0
RXCLK
TXEN
TXD3
TXD2
TXD1
TXD0
RXD23
RXD22
RXD21
RXD20
RXCLK2
TXEN2
TXD23
TXD22
TXD21
TXD20
CRS
CRS2
25M_USB2
EEDO
EEDI
EECK
EECS
VDD3
R38
R39
10K
10K
0
48M
L9
2.2uH
C40
20k
Y3
48M_XIN
C39
62
1
2
/HOMELINK
GPIO1
C45
8p
AX88170 L
C46
22pF
U12
EECS
EECK
EEDI
EEDO
1
2
3
4
CS
SK
DI
DO
VCC
NC
NC
GND
8
7
6
5
VDD3
93C56R
ASIX ELECTRONIC CORPORATION
Title
AX88170 CIRCUIT 3
36
Size
B
Document Number
170AP5A3.SCH
Date:
Monday, February 26, 2001
Rev
2.0
Sheet
4
of
7
ASIX ELECTRONICS CORPORATION
AX88170
USB to Fast Ethernet/HomePNA Controller
VDD3
VDD3
VDD3
GND
GND
VDD3
*6 USB Port Link/Act LED
U13
R41
VDD3
Q4
R42
2SC2412K
330
D4
48M_XOUT
48M_XIN
51
52
ACT/LINK#
63
LED
48M_XOUT
48M_XIN
/HOMELINK
GPIO1
ACT/LINK
/PHY_RST
GPIO0
1K
R43
USB-CON
4
3
2
1
R44
R45
L10
ALDONE
D+
D-
18
18
F.B.
4
2
3
1
S
DD+
VDD5
GND
RST#
RST_USB#
4
/RST
1.5K
S
J4
C47
C48
20P
20P
R46
55
56
57
58
61
60
4.7K
VDD3
VDD3
C49
0.01u
VDD3
VDD3
VDD3
R47
C51
C52
C53
C54
0.1u
0.1u
0.1u
0.1u
0.1u
R50
48M_XOUT
48M
L11
2.2uH
C55
8p
3
10
23
30
37
44
50
54
59
5
11
17
25
34
42
49
53
64
20k
Y4
48M_XIN
C50
62
1
2
LEERDY
D+
DTEST0
TEST1
TEST2
/EP78DIS TEST3
TEST4
TEST_OUT
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
RX_DV
RX_ER
RXD3
RXD2
RXD1
RXD0
RX_CLK
TX_EN
TXD3
TXD2
TXD1
TXD0
TX_CLK
CRS
COL
MDIO
MDC
25M_CLKO
25M_XIN
25M_XOUT
EEDO
EEDI
EECK
EECS
/S_RMII
/S_MAC
/S_FDPX
S_EXT
SPD_UP
41
40
39
38
32
31
29
28
27
26
24
22
21
20
19
18
16
15
13
RXDV
RXDV3
RXD3
RXD2
RXD1
RXD0
RXCLK
TXEN
TXD3
TXD2
TXD1
TXD0
RXD33
RXD32
RXD31
RXD30
RXCLK3
TXEN3
TXD33
TXD32
TXD31
TXD30
CRS
CRS3
14
12
33
35
36
48
47
46
45
43
9
8
7
6
25M_USB3
EEDO
EEDI
EECK
EECS
VDD3
R48
R49
10K
10K
0
C56
8p
AX88170 L
C57
22pF
U14
EECS
EECK
EEDI
EEDO
1
2
3
4
CS
SK
DI
DO
VCC
NC
NC
GND
8
7
6
5
VDD3
93C56R
ASIX ELECTRONIC CORPORATION
Title
AX88170 CIRCUIT 4
Size
B
Date:
37
Document Number
170AP5A4.SCH
Monday, February 26, 2001
Rev
2.0
Sheet
5
of
7
ASIX ELECTRONICS CORPORATION
AX88170
USB to Fast Ethernet/HomePNA Controller
U15
VDD5
RXD12
RXD13
TXEN1
TXD10
TXD11
TXD12
TXD13
GND
R56
R57
10K
10K
VDD5
GND
R59
10K
RXDV2
CRS2
RXCLK2
R60
20
RXD20
RXD21
RXD22
RXD23
TXEN2
TXD20
TXD21
TXD22
TXD23
GND
R65
10K
RXDV3
CRS3
RXCLK3
R66
RXD30
RXD31
RXD32
RXD33
20
VDD5
TXEN3
TXD30
TXD31
TXD32
TXD33
GND
R67
10K
DISFC#
MODE0
R68
10K
VDD5
RXER4
RXDV4
CRS4
RXCLK4
GND
VDD5
R70
20
RXD40
RXD41
RXD42
RXD43
TXEN4
TXD40
TXD41
TXD42
TXD43
TXER4
MEMS0
MEMS1
ENTRY
ST_FW
GND
COL100#
R72
10K
MWR#
MA8
MA9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
VDD
RXD<1><2>
RXD<1><3>
TXEN<1>
TXD<1><0>
TXD<1><1>
TXD<1><2>
TXD<1><3>
TXER<1> COL<1>
VSS
PULL_DN
PULL_DN
VDD
VSS
RXER<2>
RXDV<2>
CRS<2>
RXCLK<2>
RXD<2><0>
RXD<2><1>
RXD<2><2>
RXD<2><3>
TXEN<2>
TXD<2><0>
TXD<2><1>
TXD<2><2>
TXD<2><3>
TXER<2> COL<2>
VSS
RXER<3>
RXDV<3>
CRS<3>
RXCLK<3>
RXD<3><0>
RXD<3><1>
RXD<3><2>
RXD<3><3>
VDD
TXEN<3>
TXD<3><0>
TXD<3><1>
TXD<3><2>
TXD<3><3>
TXER3<3> COL<3>
VSS
PULL_DN
EN_FLOW-CTL
MODE
TXE_DELAY
VDD
RXER<4>
RXDV<4>
CRS<4>
VSS
VDD
RXCLK<4>
RXD<4><0>
RXD<4><1>
RXD<4><2>
RXD<4><3>
TXEN<4>
TXD<4><0> MEM_SIZE<0>
TXD<4><1> MEM_SIZE<1>
TXD<4><2> ENTRIES
TXD<4><3> ST_FW
TXER<4> COL<4>
COL_O<4>
VSS
/LCOL100
MDC
MDO
MCLK
/BMA<15>
/LUTI<0>
/LUTI<1>
/LUTI<2>
/LUTI<3>
/BMWR /IR_ACT_EN
BMA<8>
BMA<9>
RXD<1><1>
RXD<1><0>
RXCLK<1>
CRS<1>
RXDV<1>
RXER<1>
COL<0> TXER<0>
TXD<0><3>
TXD<0><2>
TXD<0><1>
TXD<0><0>
TXEN<0>
VSS
RXD<0><3>
RXD<0><2>
RXD<0><1>
RXD<0><0>
RXCLK<0>
CRS<0>
RXDV<0>
RXER<0>
VSS
VDD
PULL_DN
PULL_DN
VDD
/HALF10
LCLK
VSS
/RST
TEST1
NC
/LACT<1>
/LACT<0>
NC
VDD
/LACT<3>
/LACT<2>
NC
/LACT<4>
VSS
/LPART<4>
LPART<3>
/LPART<2>
/LPART<1>
/LPART<0>
/TEST2
/LUTI<4>
/LUTI<5>
/LCOL10
/LSEL10
VDD
VSS
BMA<7>
BMA<6>
BMA<5>
BMA<4>
VDD
BMA<3>
BMA<2>
BMA<1>
BMA<0>
VSS
BMD<7>
BMD<6>
BMD<5>
BMD<4>
BMD<3>
BMD<2>
BMD<1>
BMD<0>
VSS
BMA<16>
BMA<15>
BMA<14>
BMA<13>
BMA<12>
BMA<11>
BMA<10>
VDD
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
R51
20
RXD11
RXD10
RXCLK1
CRS1
RXDV1
GND
TXD03
TXD02
TXD01
TXD00
TXEN0
R61
RXD03
RXD02
RXD01
RXD00
20
R52
10K
R53
10K
MEMS1
*7 Set memory size to 128KB
R54
10K
ENTRY
*8 ENTRIES Setting :
R55
10K
DISFC#
High : 256
Low : 1024
*9 LOW: DIS_FLOW-CONTROL
R58
10K
MODE0
*10 settingt to mode
0
RXCLK0
CRS0
RXDV0 R62
10K
GND
VDD5
VDD5
R63
R64
10K
10K
U16
LCLK
GND
RST#
25M_REP
RST_EN#
LLED4
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
MA16
MA14
MA12
MA7
MA6
MA5
MA4
MA3
MA2
MA1
MA0
MD0
MD1
MD2
GND
GND
N.C.
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
VSS
VCC
A15
CS2
WE_#
A13
A8
A9
A11
OE_#
A10
CS1_#
I/O8
I/O7
I/O6
I/O5
I/O4
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VDD5
MA15
VDD5
MWR#
MA13
MA8
MA9
MA11
GND
MA10
GND
MD7
MD6
MD5
MD4
MD3
HSRAM128*8
COL10#
VDD5
VDD5
GND
MA7
MA6
MA5
MA4
VDD5
MA3
MA2
MA1
MA0
GND
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0
GND
MA16
MA15
MA14
MA13
MA12
MA11
MA10
VDD5
D5
LED
D6
LED
R69
COL10#
10 GLOBAL COLLISION
510
R71
COL100#
100 GLOBAL COLLISION
510
VDD5
C58
C59
C60
C61
C62
C63
C64
C65
C66
C67
C68
C69
C70
C71
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
+
100u/16V
GND
Title
AX88875 AP C.K.T.
AX88875AP
Size
B
Date:
38
Document Number
170AP5A5.SCH
Monday, February 26, 2001
Rev
2.0
Sheet
6
of
7
ASIX ELECTRONICS CORPORATION
AX88170
VDD5
GND
LLED4
USB to Fast Ethernet/HomePNA Controller
VDD5
GND
AVDD5
25M_PHY
25M_PHY
RST_EN#
RST#
AGND
AVDD5
RDN
RDP
CRS4
RXER4
RXDV4
RXCLK4
CRS
RXDV
RXCLK
AGND
RXD40
RXD0
RXD41
RXD1
RXD42
AGND
TDN
TDP
AVDD5
RXER
AVDD5
RXD2
TXEN4
TXEN
AGND
TDN
TDP
AVDD5
TXER4
TXER
25M_PHY
TXD40
TXD0
TXD41
TXD1
TXD42
TXD2
RXD43
TXD43
RXD3
R81
AGND
AVDD5
AVDD5
AGND
AGND
TXD3
6.2K
(1%)
GND
VDD5
GND
GND
VDD5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
AVCC
NC
NC
NC
NC
AGND
AVCC
AVCC
RXIRXI+
AGND
AGND
10TXO10TXO+
AVCC
AVCC
AGND
AGND
NC
NC
AVCC
AVCC
AGND
AGND
100TXO100TXO+
AVCC
DVCC
OSC/X1
X2
DGND
OSC/XLT#
AVCC
AGND
BGRES
NC
DGND
DGND
AGND
AVCC
TRIDRV
UTP
SPEED10
RX_LOCK
DGND
NC
LINKSTS
CLK25M
DVCC
FDXLED#
AGND
AGND
10BTSER
BPSCR
BP4B5B
BPALIGN
RPTR/NODE#
OPMODE3
OPMODE2
OPMODE1
OPMODE0
PHYAD4
PHYAD3
DVCC
DGND
PHYAD2
PHYAD1
PHYAD0
TESTDOME
RESET#
RX_EN
RX_ER/RXD4
RX_DV
COL
CRS
RX_CLK
DVCC
DGND
RXD0
RXD1
RXD2
RXD3
DVCC
DGND
MDIO
MDC
TX_CLK
TX_EN
DVCC
DGND
TXD0
TXD1
TXD2
TXD3
TX_ER/TXD4
TXLED#
RXLED#
LINKLED#
DGND
COLLED#
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
TX 1CT:1CT
RX 1CT:1CT
AGND
JP2
1
2
3
4
5
6
7
8
RJ03
RJ06
RJ01
U17
LLED4
RJ02
GND
VDD5
VDD5
VDD5
VDD5
VDD5
GND
GND
VDD5
GND
VDD5
AVDD5
C72
0.1u
(ETHERNET PORT)
T1
TDP
16
14
15
TDN
RDP
GND
RST#
VDD5
RXER
RXDV
1
3
2
RDN
JP3
16
14
15
10
12
11
1
3
2
7
5
6
10
12
11
RJ03
7
5
6
RJ01
R75
49.9
RJ01
RJ02
RJ03
RJ06
1
2
3
4
5
6
7
8
RJ06
RJ02
16ST8515
CRS
RXCLK
VDD5
GND
RXD0
RXD1
RXD2
RXD3
VDD5
GND
UPLINK POART)
RJ45
R74
49.9
R73
49.9
(ETHERNET
75 75
R76
49.9
75
R77
75
RJ45
R80
C73
C74
0.1u
GND_E
C75
R78
R79
CHASSIS
0.01u/2KV
0.1u
C76
GND
0.01u
TXEN
VDD5
GND
TXD0
TXD1
TXD2
TXD3
TXER
LLED
GND
R82
510
D7 GREEN LED
LLED4
Ethernet
Port Link/Act LED
DM9191F
VDD5
L12
AVDD5
C77
F.B.
C78
1000p
C79
1000p
C80
C81
C82
C83
C84
C85
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
+
47u/16V
GND
AGND
VDD5
C86
C87
C88
C89
C90
C91
C92
C93
47u/16V
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
+
GND
Title
EtherNet PHY C.K.T.
Size
B
Date:
39
Document Number
170AP5A6.SCH
Monday, February 26, 2001
Rev
2.0
Sheet
7
of
7
ASIX ELECTRONICS CORPORATION
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