TI1 CDCEL937PWG4 Flexible low power lvcmos clock generator with ssc support for emi reduction Datasheet

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CDCE937, CDCEL937
SLAS564G – AUGUST 2007 – REVISED OCTOBER 2016
CDCEx937 Flexible Low Power LVCMOS Clock Generator
With SSC Support For EMI Reduction
1 Features
•
1
•
•
•
•
•
•
•
•
•
•
Member of Programmable Clock Generator
Family
– CDCEx913: 1-PLL, 3 Outputs
– CDCEx925: 2-PLL, 5 Outputs
– CDCEx937: 3-PLL, 7 Outputs
– CDCEx949: 4-PLL, 9 Outputs
In-System Programmability and EEPROM
– Serial Programmable Volatile Register
– Nonvolatile EEPROM to Store Customer
Setting
Flexible Input Clocking Concept
– External Crystal: 8 MHz to 32 MHz
– On-Chip VCXO: Pull Range ±150 ppm
– Single-Ended LVCMOS up to 160 MHz
Free Selectable Output Frequency up to 230 MHz
Low-Noise PLL Core
– PLL Loop Filter Components Integrated
– Low Period Jitter (Typical 60 ps)
Separate Output Supply Pins
– CDCE937: 3.3 V and 2.5 V
– CDCEL937: 1.8 V
Flexible Clock Driver
– Three User-Definable Control Inputs
[S0/S1/S2], for Example, SSC Selection,
Frequency Switching, Output Enable or Power
Down
– Generates Highly Accurate Clocks for Video,
Audio, USB, IEEE1394, RFID, Bluetooth™,
WLAN, Ethernet™, and GPS
– Generates Common Clock Frequencies Used
With TI-DaVinci™, OMAP™, DSPs
– Programmable SSC Modulation
– Enables 0-PPM Clock Generation
1.8-V Device Power Supply
Wide Temperature Range –40°C to 85°C
Packaged in TSSOP
Development and Programming Kit for Easy PLL
Design and Programming (TI Pro-Clock™)
2 Applications
D-TVs, STBs, IP-STBs, DVD Players, DVD
Recorders, and Printers
3 Description
The CDCE937 and CDCEL937 devices are modular
PLL-based
low
cost,
high-performance,
programmable clock synthesizers, multipliers and
dividers. They generate up to 7 output clocks from a
single input frequency. Each output can be
programmed in-system for any clock frequency up to
230 MHz, using up to three independent configurable
PLLs.
The CDCEx937 has separate output supply pins,
VDDOUT, which is 1.8 V for CDCEL937 and to 2.5 V
to 3.3 V for CDCE937.
The input accepts an external crystal or LVCMOS
clock signal. If an external crystal is used, an on-chip
load capacitor is adequate for most applications. The
value of the load capacitor is programmable from 0 to
20 pF. Additionally, an on-chip VCXO is selectable
which allows synchronization of the output frequency
to an external control signal, that is, PWM signal.
Device Information(1)
PART NUMBER
CDCE937,
CDCEL937
PACKAGE
TSSOP (20)
BODY SIZE (NOM)
6.50 mm x 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Typical Application Schematic
Ethernet PHY
CDCE(L)9xx Clock
WiFi
25 MHz
USB Controller
FPGA
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CDCE937, CDCEL937
SLAS564G – AUGUST 2007 – REVISED OCTOBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
4
5
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
5
5
5
6
6
8
8
8
9
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements: CLK_IN .................................
Timing Requirements: SDA/SCL ..............................
EEPROM Specification .............................................
Typical Characteristics ..............................................
Parameter Measurement Information ................ 10
Detailed Description ............................................ 11
8.1 Overview ................................................................. 11
8.2 Functional Block Diagram ....................................... 12
8.3 Feature Description................................................. 12
8.4 Device Functional Modes........................................ 15
8.5 Programming........................................................... 16
8.6 Register Maps ......................................................... 17
9
Application and Implementation ........................ 24
9.1 Application Information............................................ 24
9.2 Typical Application .................................................. 24
10 Power Supply Recommendations ..................... 29
11 Layout................................................................... 29
11.1 Layout Guidelines ................................................. 29
11.2 Layout Example .................................................... 30
12 Device and Documentation Support ................. 31
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Device Support......................................................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
31
31
31
31
31
31
31
13 Mechanical, Packaging, and Orderable
Information ........................................................... 32
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (March 2010) to Revision G
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
•
Changed Applications............................................................................................................................................................. 1
•
Changed Thermal Resistance Junction to Ambient, RθJA, values in Thermal Information From: 89 (0 lfm), 75 (150
lfm), 74 (200 lfm), 74 (250 lfm), and 69 (500 lfm) To: 89.04 .................................................................................................. 6
•
Deleted Input Capacitance figure ......................................................................................................................................... 19
Changes from Revision E (October 2009) to Revision F
Page
•
Added PLL settings limits: 16 ≤ q ≤ 63, 0 ≤ p ≤ 7, 0 ≤ r ≤ 511, 0 < N < 4096 foot to PLL1, PLL2, and PLL3 Configure
Register Table ...................................................................................................................................................................... 20
•
Changed 100 MHz < ƒVCO > 200 MHz; TO 80 MHz ≤ ƒVCO ≤ 230 MHz; and changed 0 ≤ p ≤ 7 TO 0 ≤ p ≤ 4 ................... 26
•
Changed under Example, fifth row, N", 2 places TO N' ....................................................................................................... 26
Changes from Revision D (September 2009) to Revision E
•
Page
Deleted sentence - A different default setting can be programmed on customer request. Contact Texas Instruments
sales or marketing representative for more information. ...................................................................................................... 14
Changes from Revision C (January 2009) to Revision D
•
2
Page
Added Note 3: SDA and SCL can go up to 3.6 V as stated in the Recommended Operating Conditions table ................... 5
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Changes from Revision B (December 2007) to Revision C
•
Page
Changed Generic Configuration Register table SLAVE_ADR default value From: 00b To: 01b ......................................... 18
Changes from Revision A (September 2007) to Revision B
Page
•
Changed Terminal Functions Table - the pin numbers to correspond with pin outs on the package.................................... 4
•
Changed Generic Configuration Register table RID default From: 0h To: Xb ..................................................................... 18
•
Added note to PWDN description to Generic Configuration Register table ......................................................................... 18
Changes from Original (August 2007) to Revision A
•
Page
Changed the data sheet status From: Product Preview To: Production data ........................................................................ 1
Copyright © 2007–2016, Texas Instruments Incorporated
Product Folder Links: CDCE937 CDCEL937
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SLAS564G – AUGUST 2007 – REVISED OCTOBER 2016
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5 Pin Configuration and Functions
PW Package
20-Pin TSSOP
Top View
Xin/CLK
1
20
Xout
S0
2
19
SDA/S1
VDD
3
18
SCL/S2
VCtrl
4
17
Y1
GND
5
16
GND
Vddout
6
15
Y2
Y4
7
14
Y3
Y5
8
13
Vddout
GND
9
12
Y6
10
11
Y7
Vddout
Not to scale
Pin Functions
PIN
NAME
NO.
GND
TYPE (1)
DESCRIPTION
5, 9, 16
G
Ground
SCL/S2
18
I
SCL: Serial clock input (default configuration), LVCMOS; Internal pullup 500k;
S2: User programmable control input; LVCMOS inputs; Internal pullup 500k
SDA/S1
19
I/O
S0
2
I
User programmable control input S0; LVCMOS inputs; Internal pullup 500k
VCtrl
4
I
VCXO control voltage, leave open or pullup (approximately 500k) when not used
VDD
3
P
1.8-V power supply for the device
Vddout
6, 10, 13
P
Xin/CLK
1
I
Crystal oscillator input or LVCMOS clock input (selectable through SDA/SCL bus)
Xout
20
O
Crystal oscillator output, leave open or pullup (~500k) when not used
Y1
17
O
LVCMOS outputs
Y2
15
O
LVCMOS outputs
Y3
14
O
LVCMOS outputs
Y4
7
O
LVCMOS outputs
Y5
8
O
LVCMOS outputs
Y6
12
O
LVCMOS outputs
Y7
11
O
LVCMOS outputs
(1)
4
SDA: Bi-directional serial data input/output (default configuration). LVCMOS; Internal pullup 500k;
S1: User programmable control input; LVCMOS inputs; Internal pullup 500k
CDCEL937: 1.8-V supply for all outputs
CDCE937: 3.3-V or 2.5-V supply for all outputs
G= Ground, I = Input, O = Output, P = Power
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Supply voltage, VDD
MIN
MAX
UNIT
–0.5
2.5
V
V
(2) (3)
–0.5
VDD + 0.5
Output voltage, VO (2)
–0.5
Vddout + 0.5
V
20
mA
Continuous output current, IO
50
mA
Junction temperature, TJ
125
°C
150
°C
Input voltage, VI
Input current, II (VI < 0, VI > VDD)
Storage temperature, Tstg
(1)
(2)
(3)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
SDA and SCL can go up to 3.6 V as stated in Recommended Operating Conditions.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
VDD
Device supply voltage
VO
Output Yx supply voltage, Vddout
VIL
Low-level input voltage LVCMOS
VIH
High-level input voltage LVCMOS
VI(thresh)
Input voltage threshold LVCMOS
VIS
Input voltage
VI(CLK)
Input voltage, CLK
IOH /IOL
Output current
CL
Output load LVCMOS
TA
Operating free-air temperature
MIN
NOM
MAX
1.7
1.8
1.9
CDCE937
2.3
3.6
CDCEL937
1.7
1.9
0.3 × VDD
0.7 × VDD
UNIT
V
V
V
V
0.5 × VDD
V
S0
0
1.9
S1, S2, SDA, SCL,
VI(thresh) = 0.5 VDD
0
3.6
0
1.9
Vddout = 3.3 V
±12
Vddout = 2.5 V
±10
Vddout = 1.8 V
±8
–40
V
V
mA
10
pF
85
°C
32
MHz
CRYSTAL AND VCXO (1)
fXtal
Crystal input frequency (fundamental mode)
ESR
Effective series resistance
fPR
Pulling (0 V ≤ Vctrl ≤ 1.8 V) (2)
(1)
(2)
27
100
±120
Frequency control voltage, Vctrl
C0/C1
8
0
Pullability ratio
±150
Ω
ppm
VDD
V
220
For more information about VCXO configuration, and crystal recommendation, see VCXO Application Guideline for CDCE(L)9xx Family
(SCAA085).
Pulling range depends on crystal-type, on-chip crystal load capacitance and PCB stray capacitance; pulling range of min ±120 ppm
applies for crystal listed in VCXO Application Guideline for CDCE(L)9xx Family (SCAA085).
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Recommended Operating Conditions (continued)
MIN
CL
On-chip load capacitance at Xin and Xout
NOM
MAX
0
UNIT
20
pF
6.4 Thermal Information
CDCE937,
CDCEL937
THERMAL METRIC (1)
PW (TSSOP)
UNIT
20 PINS
RθJA
Junction-to-ambient thermal resistance
89.04
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
31.33
°C/W
RθJB
Junction-to-board thermal resistance
54.6
°C/W
ψJT
Junction-to-top characterization parameter
0.8
°C/W
ψJB
Junction-to-board characterization parameter
48.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
All PLLS on
IDD
Supply current (see Figure 1)
All outputs off, f(CLK) = 27 MHz,
f(VCO) = 135 MHz
IDDOUT
Output supply current
(see Figure 2 and Figure 3)
No load, all outputs on,
fOUT = 27 MHz
IDD(PD)
Power-down current
Every circuit powered down except SDA/SCL,
fIN = 0 MHz, VDD = 1.9 V
V(PUC)
Supply voltage Vdd threshold for powerup control circuit
f(VCO)
VCO frequency range of PLL
fOUT
LVCMOS output frequency
TYP (1)
MAX
29
Per PLL
mA
9
CDCE937,
VDDOUT = 3.3 V
3.1
CDCEL937,
VDDOUT = 1.8 V
1.5
UNIT
mA
50
µA
0.85
1.45
V
80
230
MHz
Vddout = 3.3 V
230
Vddout = 1.8 V
230
MHz
LVCMOS PARAMETER
VIK
LVCMOS input voltage
VDD = 1.7 V, II = –18 mA
II
LVCMOS Input current
VI = 0 V or VDD, VDD = 1.9 V
IIH
LVCMOS Input current for S0/S1/S2
IIL
LVCMOS Input current for S0/S1/S2
Input capacitance at Xin/Clk
VI(Clk) = 0 V or VDD
6
Input capacitance at Xout
VI(Xout) = 0 V or VDD
2
Input capacitance at S0/S1/S2
VIS = 0 V or VDD
3
CI
–1.2
V
±5
µA
VI = VDD, VDD = 1.9 V
5
µA
VI = 0 V, VDD = 1.9 V
–4
µA
pF
CDCE937 – LVCMOS FOR Vddout = 3.3 V
VOH
LVCMOS high-level output voltage
VOL
LVCMOS low-level output voltage
Vddout = 3 V, IOH = –0.1 mA
2.9
Vddout = 3 V, IOH = –8 mA
2.4
Vddout = 3 V, IOH = –12 mA
2.2
V
Vddout = 3 V, IOL = 0.1 mA
0.1
Vddout = 3 V, IOL = 8 mA
0.5
Vddout = 3 V, IOL = 12 mA
0.8
V
tPLH, tPHL
Propagation delay
All PLL bypass
3.2
ns
tr/tf
Rise and fall time
Vddout = 3.3 V (20%–80%)
0.6
ns
(1)
6
All typical values are at respective nominal VDD.
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Electrical Characteristics (continued)
over recommended operating free-air temperature range (unless otherwise noted)
TYP (1)
MAX
1 PLL switching, Y2-to-Y3
60
90
3 PLL switching, Y2-to-Y7
100
150
1 PLL switching, Y2-to-Y3
70
100
3 PLL switching, Y2-to-Y7
120
180
PARAMETER
tjit(cc)
Cycle-to-cycle jitter (2) (3)
tjit(per)
Peak-to-peak period jitter (3)
tsk(o)
Output skew (4) (see Table 2)
odc
Output duty cycle (5)
TEST CONDITIONS
MIN
fOUT = 50 MHz, Y1-to-Y3
60
fOUT = 50 MHz, Y2-to-Y5
160
fVCO = 100 MHz, Pdiv = 1
45%
UNIT
ps
ps
ps
55%
CDCE937 – LVCMOS FOR Vddout = 2.5 V
VOH
LVCMOS high-level output voltage
VOL
LVCMOS low-level output voltage
Vddout = 2.3 V, IOH = –0.1 mA
2.2
Vddout = 2.3 V, IOH = –6 mA
1.7
Vddout = 2.3 V, IOH = –10 mA
1.6
V
Vddout = 2.3 V, IOL = 0.1 mA
0.1
Vddout = 2.3 V, IOL = 6 mA
0.5
Vddout = 2.3 V, IOL = 10 mA
0.7
tPLH, tPHL
Propagation delay
All PLL bypass
3.4
tr/tf
Rise and fall time
Vddout = 2.5 V (20%–80%)
0.8
1 PLL switching, Y2-to-Y3
60
90
3 PLL switching, Y2-to-Y7
100
150
1 PLL switching, Y2-to-Y3
70
100
3 PLL switching, Y2-to-Y7
120
180
ns
ns
tjit(cc)
Cycle-to-cycle jitter (2) (3)
tjit(per)
Peak-to-peak period jitter (4)
tsk(o)
Output skew (4)
(see Table 2)
fOUT = 50 MHz, Y1-to-Y3
60
fOUT = 50 MHz, Y2-to-Y5
160
odc
Output duty cycle (5)
f(VCO) = 100 MHz, Pdiv = 1
45%
V
ps
ps
ps
55%
CDCEL937 – LVCMOS FOR Vddout = 1.8 V
VOH
LVCMOS high-level output voltage
VOL
LVCMOS low-level output voltage
Vddout = 1.7 V, IOH = –0.1 mA
1.6
Vddout = 1.7 V, IOH = –4 mA
1.4
Vddout = 1.7 V, IOH = –8 mA
1.1
V
Vddout = 1.7 V, IOL = 0.1 mA
0.1
Vddout = 1.7 V, IOL = 4 mA
0.3
Vddout = 1.7 V, IOL = 8 mA
0.6
tPLH, tPHL
Propagation delay
All PLL bypass
2.6
tr/tf
Rise and fall time
Vddout= 1.8 V (20%–80%)
0.7
1 PLL switching, Y2-to-Y3
70
120
3 PLL switching, Y2-to-Y7
100
150
1 PLL switching, Y2-to-Y3
90
140
3 PLL switching, Y2-to-Y7
120
190
ns
ns
tjit(cc)
Cycle-to-cycle jitter (2) (3)
tjit(per)
Peak-to-peak period jitter (3)
tsk(o)
Output skew (4)
(see Table 2)
fOUT = 50 MHz, Y1-to-Y3
60
fOUT = 50 MHz, Y2-to-Y5
160
odc
Output duty cycle (5)
f(VCO) = 100 MHz, Pdiv = 1
45%
V
ps
ps
ps
55%
SDA AND SCL
VIK
SCL and SDA input clamp voltage
VDD = 1.7 V; II = –18 mA
–1.2
V
IIH
SCL and SDA input current
VI = VDD; VDD = 1.9 V
±10
µA
VIH
SDA/SCL input high voltage (6)
VIL
SDA/SCL input low voltage (6)
(2)
(3)
(4)
(5)
(6)
0.7 × VDD
V
0.3 × VDD
V
10000 cycles.
Jitter depends on configuration. Data is taken under the following conditions: 1-PLL is fIN = 27 MHz and Y2/3 = 27 MHz (measured at
Y2); 3-PLL is fIN = 27 MHz, Y2/3 = 27 MHz (measured at Y2), Y4/5 = 16.384 MHz, and Y6/7 = 74.25 MHz.
The tsk(o) specification is only valid for equal loading of each bank of outputs, and outputs are generated from the same divider; data
taking on rising edge (tr).
odc depends on output rise and fall time (tr/tf).
SDA and SCL pins are 3.3-V tolerant.
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Electrical Characteristics (continued)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VOL
SDA low-level output voltage
IOL = 3 mA, VDD = 1.7 V
CI
SCL/SDA Input capacitance
VI = 0 V or VDD
MIN
TYP (1)
MAX
UNIT
0.2 × VDD
V
10
pF
3
6.6 Timing Requirements: CLK_IN
over operating free-air temperature range (unless otherwise noted)
MIN
fCLK
LVCMOS clock input frequency
tr / tf
Rise and fall time CLK signal (20% to 80%)
dutyCLK
Duty cycle CLK at VDD/2
NOM
MAX
PLL bypass mode
0
160
PLL mode
8
160
40%
60%
3
UNIT
MHz
ns
6.7 Timing Requirements: SDA/SCL
over operating free-air temperature range (unless otherwise noted; see Figure 7)
MIN
fSCL
SCL clock frequency
tsu(START)
START setup time (SCL high before SDA low)
th(START)
START hold time (SCL low after SDA low)
tw(SCLL)
SCL low-pulse duration
tw(SCLH)
SCL high-pulse duration
th(SDA)
SDA hold time (SDA valid after SCL low)
tsu(SDA)
SDA setup time
tr
SCL/SDA input rise time
tf
SCL/SDA input fall time
NOM
MAX
Standard mode
0
100
Fast mode
0
400
Standard mode
4.7
Fast mode
0.6
Standard mode
0.6
Standard mode
4.7
Fast mode
1.3
Standard mode
µs
µs
4
Fast mode
µs
0.6
Standard mode
0
3.45
Fast mode
0
0.9
Standard mode
250
Fast mode
100
1000
Fast mode
300
300
tsu(STOP)
STOP setup time
tBUS
Bus free time between a STOP and START condition
4
Fast mode
0.6
Standard mode
4.7
Fast mode
1.3
µs
ns
Standard mode
Standard mode
kHz
µs
4
Fast mode
UNIT
ns
ns
µs
µs
6.8 EEPROM Specification
MIN
EEcyc
Programming cycles of EEPROM
EEret
Data retention
8
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TYP
MAX
UNIT
1000
cycles
10
years
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6.9 Typical Characteristics
30
80
VDD = 1.8 V
70
25
7 Outputs on
60
20
2 PLL on
50
IDDOUT - mA
IDD - Supply Current - mA
3 PLL on
VDD = 1.8 V,
VDDOUT = 3.3 V,
No Load
40
30
1 PLL on
5 Outputs on
15
1 Output on
10
3 Outputs on
20
all PLL off
5
10
0
10
60
110
160
fVCO - Frequency - MHz
0
10
210
Figure 1. CDCEx937 Supply Current vs PLL Frequency
All Outputs off
30
50 70 90 110 130 150 170 190 210 230
fOUT - Output Frequency - MHz
Figure 2. CDCE937 Output Current vs Output Frequency
12
10
VDD = 1.8 V,
VDDOUT = 1.8 V,
No Load
7 Outputs
IDDOUT - mA
8
5 Outputs on
6
3 Output on
4
1 Output on
2
0
10
all Outputs
30
50
70
90 110 130 150 170 190 210 230
fOUT - Output Frequency - MHz
Figure 3. CDCEL937 Output Current vs Output Frequency
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7 Parameter Measurement Information
CDCE937
CDCEL937
1k
LVCMOS
1k
10 pF
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Figure 4. Test Load
CDCE937
CDCEL937
LVCMOS
Typical Driver
Impedance
~ 32 :
LVCMOS
Series
Termination
~ 18 :
Line Impedance
Zo = 50 :
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Figure 5. Test Load for 50-Ω Board Environment
10
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8 Detailed Description
8.1 Overview
The CDCE937 and CDCEL937 devices are modular PLL-based, low-cost, high-performance, programmable
clock synthesizers, multipliers, and dividers. They generate up to seven output clocks from a single input
frequency. Each output can be programmed in-system for any clock frequency up to 230 MHz, using one of the
three integrated configurable PLLs. The CDCx937 has separate output supply pins, VDDOUT, which is 1.8 V for
CDCEL937 and 2.5 V to 3.3 V for CDCE937.
The input accepts an external crystal or LVCMOS clock signal. If an external crystal is used, an on-chip load
capacitor is adequate for most applications. The value of the load capacitor is programmable from 0 to 20 pF.
Additionally, a selectable on-chip VCXO allows synchronization of the output frequency to an external control
signal, that is, the PWM signal.
The deep M/N divider ratio allows the generation of 0 ppm audio/video, networking (WLAN, BlueTooth, Ethernet,
GPS) or Interface (USB, IEEE1394, Memory Stick) clocks from a reference input frequency such as 27 MHz.
All PLLs supports SSC (Spread-Spectrum Clocking). SSC can be Center-Spread or Down-Spread clocking which
is a common technique to reduce electro-magnetic interference (EMI).
Based on the PLL frequency and the divider settings, the internal loop filter components are automatically
adjusted to achieve high stability and optimized jitter transfer characteristic of each PLL.
The device supports non-volatile EEPROM programming for ease-customized application. It is preset to a factory
default configuration (see Default Device Setting). It can be reprogrammed to a different application configuration
before PCB assembly, or reprogrammed by in-system programming. All device settings are programmable
through SDA/SCL bus, a 2-wire serial interface.
Three programmable control inputs, S0, S1 and S2, can be used to control various aspects of operation including
frequency selection changing the SSC parameters to lower EMI, PLL bypass, power down, and choosing
between low level or 3-state for output-disable function.
The CDCx937 operates in a 1.8-V environment. It is characterized for operation from –40°C to 85°C.
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8.2 Functional Block Diagram
VDD
Vddout
GND
Input Clock
LV
CMOS
Y1
M2
LV
CMOS
Y2
M3
LV
CMOS
Y3
M4
LV
CMOS
Y4
M5
LV
CMOS
Y5
M6
Xin/CLK
LV
CMOS
Y6
M7
Pdiv1
M1
Vctr
LV
CMOS
Y7
10-Bit
VCXO
XO
Xout
Pdiv2
7-Bit
MUX1
PLL1
with SSC
LVCMOS
Pdiv3
Programming
and
SDA/SCL
Register
S0
S1/SDA
S2/SCL
PLL Bypass
7-Bit
PLL 2
Pdiv4
with SSC
7-Bit
MUX2
EEPROM
Pdiv5
7-Bit
PLL Bypass
Pdiv6
PLL 3
MUX3
with SSC
7-Bit
Pdiv7
7-Bit
PLL Bypass
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8.3 Feature Description
8.3.1 Control Terminal Setting
The CDCEx937 has three user-definable control terminals (S0, S1, and S2) which allow external control of
device settings. They can be programmed to any of the following setting:
• Spread spectrum clocking selection → spread type and spread amount selection
• Frequency selection → switching between any of two user-defined frequencies
• Output state selection → output configuration and power down control
The user can predefine up to eight different control settings. Table 1 and Table 2 explain these settings.
Table 1. Control Terminal Definition
EXTERNAL
CONTROL
BITS
Control
Function
PLL1 SETTING
PLL
Frequency
Selection
SSC
Selection
PLL2 SETTING
Output
Y2/Y3
Selection
PLL
Frequency
Selection
SSC
Selection
PLL3 SETTING
Output
Y4/Y5
Selection
PLL
Frequency
Selection
SSC
Selection
Y1 SETTING
Output
Y6/Y7
Selection
Output Y1
and Power-Down
Selection
Table 2. PLLx Setting (Can Be Selected for Each PLL Individual)
SSC SELECTION (CENTER/DOWN) (1)
SSCx [3-bits]
(1)
12
CENTER
DOWN
0
0
0
0% (off)
0% (off)
0
0
1
±0.25%
–0.25%
0
1
0
±0.5%
–0.5%
Center/Down-Spread, Frequency0/1 and State0/1 are user-definable in PLLx Configuration Register
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Table 2. PLLx Setting (Can Be Selected for Each PLL Individual) (continued)
SSC SELECTION (CENTER/DOWN) (1)
SSCx [3-bits]
CENTER
DOWN
–0.75%
0
1
1
±0.75%
1
0
0
±1%
–1%
1
0
1
±1.25%
–1.25%
1
1
0
±1.5%
–1.5%
1
1
1
±2%
–2%
FREQUENCY SELECTION (2)
FSx
FUNCTION
0
Frequency0
1
Frequency1
OUTPUT SELECTION (3) (Y2 ... Y7)
(2)
(3)
YxYx
FUNCTION
0
State0
1
State1
Frequency0 and Frequency1 can be any frequency within the specified fVCO range
State0/1 selection is valid for both outputs of the corresponding PLL module and can be power down,
3-state, low or active
Table 3. Y1 Setting (1)
Y1 SELECTION
(1)
Y1
FUNCTION
0
State 0
1
State 1
State0 and State1 are user definable in Generic Configuration
Register and can be power down, 3-state, low, or active.
S1/SDA and S2/SCL pins of the CDCEx937 are dual function pins. In default configuration they are defined as
SDA/SCL for the serial interface. They can be programmed as control-pins (S1/S2) by setting the relevant bits in
the EEPROM. Note that the changes to the Control register (Bit [6] of Byte [02]) have no effect until they are
written into the EEPROM.
Once they are set as control pins, the serial programming interface is no longer available. However, if VDDOUT is
forced to GND, the two control-pins, S1 and S2, temporally act as serial programming pins (SDA/SCL).
S0 is not a multi-use pin, it is a control pin only.
8.3.2 Default Device Setting
The internal EEPROM of CDCEx937 is preconfigured as shown in Figure 6. (The input frequency is passed
through to the output as a default.) This allows the device to operate in default mode without the extra production
step of program it. The default setting appears after power is supplied or after power-down or power-up
sequence until it is reprogrammed by the user to a different application configuration. A new register setting is
programmed through the serial SDA/SCL Interface.
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VDD
Vddout
GND
PLL 2
Pdiv4 = 1
power down
Pdiv5 = 1
PLL Bypass
PLL3
LV
CMOS
Y4 = 27 MHz
LV
CMOS
Y5 = 27 MHz
LV
CMOS
Y6 = 27 MHz
LV
CMOS
Y7 = 27 MHz
MUX3
Pdiv6 = 1
power down
M2
SCL
M3
SDA
Programming Bus
Y3 = 27 MHz
MUX2
“0” = outputs 3-State
LV
CMOS
M4
Programming
and
SDA/SCA
Register
S0
Pdiv3 = 1
PLL Bypass
EEPROM
“1” = outputs enabled
MUX1
Pdiv2 = 1
Xout
Y2 = 27 MHz
M5
PLL1
LV
CMOS
Pdiv1 =1
X-tal
power down
Y1 = 27MHz
M6
27 MHz
Crystal
LV
CMOS
M7
M1
Input Clock
Xin
Pdiv7 = 1
PLL Bypass
Figure 6. Default Device Setting
Table 4 shows the factory default setting for the Control Terminal Register (external control pins). In normal
operation, all 8 register settings are available, but in the default configuration only the first two settings (0 and 1)
can be selected with S0, as S1 and S2 configured as programming pins in default mode.
Table 4. Factory Default Setting for Control Terminal Register (1)
SSC SELECTION
Y1
FS1
SSC1
Y2Y3
FS2
SSC2
Y4Y5
FS3
SSC3
Y6Y7
0
3-state
fVCO1_0
off
3-state
fVCO2_0
off
3-state
fVCO1_0
off
3-state
SCL (I2C)
SDA (I2C)
1
enabled
fVCO1_0
off
enabled
fVCO2_0
off
enabled
fVCO1_0
off
enabled
(1)
OUTPUT SELECTION
FREQUENCY SELECTION
S0
OUTPUT SELECTION
S1
SDA (I2C)
EXTERNAL
CONTROL PINS
OUTPUT SELECTION
S2
SCL (I2C)
OUTPUT SELECTION
SSC SELECTION
PLL3 SETTINGS
FREQUENCY SELECTION
PLL2 SETTINGS
SSC SELECTION
PLL1 SETTINGS
FREQUENCY SELECTION
Y1
In default mode or when programmed respectively, S1 and S2 act as serial programming interface, SDA/SCL. They do not have any
control-pin function but they are internally interpreted as if S1=0 and S2=0. However, S0 is a control-pin which in the default mode
switches all outputs ON or OFF (as previously predefined).
8.3.3 SDA/SCL Serial Interface
The CDCEx937 operates as a slave device of the 2-wire serial SDA/SCL bus, compatible with the popular
SMBus or I2C specification. It operates in the standard-mode transfer (up to 100 kbit/s) and fast-mode transfer
(up to 400kbit/s) and supports 7-bit addressing.
The S1/SDA and S2/SCL pins of the CDC9xx are dual function pins. In the default configuration they are used as
SDA/SCL serial programming interface. They can be reprogrammed as general purpose control pins, S1 and S2,
by changing the corresponding EEPROM setting, Byte 02, Bit [6].
14
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P
S
tw(SCLL)
Bit 7 (MSB)
tw(SCLH)
Bit 6
tr
Bit 0 (LSB)
A
P
tf
VIH
SCL
VIL
tsu(START)
th(START)
tsu(SDA)
th(SDA)
t(BUS)
tsu(STOP)
tf
tr
VIH
SDA
VIL
Figure 7. Timing Diagram for SDA/SCL Serial Control Interface
8.3.4 Data Protocol
The device supports Byte Write and Byte Read and Block Write and Block Read operations.
For Byte Write/Read operations, the system controller can individually access addressed bytes.
For Block Write/Read operations, the bytes are accessed in sequential order from lowest to highest byte (with
most significant bit first) with the ability to stop after any complete byte has been transferred. The numbers of
Bytes read-out are defined by Byte Count in the Generic Configuration Register. At Block Read instruction all
bytes defined in the Byte Count has to be readout to correctly finish the read cycle.
Once a byte has been sent, it is written into the internal register and is effective immediately. This applies to
each transferred byte independent of whether this is a Byte Write or a Block Write sequence.
If the EEPROM Write Cycle is initiated, the internal SDA register contents are written into the EEPROM. During
this write cycle, data is not accepted at the SDA/SCL bus until the write cycle is completed. However, data can
be read during the programming sequence (Byte Read or Block Read). The programming status can be
monitored by reading EEPIP, Byte 01–Bit [6].
The offset of the indexed byte is encoded in the command code, as described in Table 5.
Table 5. Slave Receiver Address (7 Bits)
A6
A5
A4
A3
A2
A1 (1)
A0 (1)
R/W
CDCEx913
1
1
0
0
1
0
1
1/0
CDCEx925
1
1
0
0
1
0
0
1/0
CDCEx937
1
1
0
1
1
0
1
1/0
CDCEx949
1
1
0
1
1
0
0
1/0
DEVICE
(1)
Address bits A0 and A1 are programmable through the SDA/SCL bus (Byte 01, Bit [1:0]). This allows addressing up to 4 devices
connected to the same SDA/SCL bus. The least-significant bit of the address byte designates a write or read operation.
8.4 Device Functional Modes
8.4.1 SDA/SCL Hardware Interface
Figure 8 shows how the CDCEx937 clock synthesizer is connected to the SDA/SCL serial interface bus. Multiple
devices can be connected to the bus but the speed may require reduction (400 kHz is the maximum) if many
devices are connected.
Note that the pullup resistors (RP) depends on the supply voltage, bus capacitance, and number of connected
devices. The recommended pullup value is 4.7 kΩ. It must meet the minimum sink current of 3 mA at
VOLmax = 0.4 V for the output stages (for more details, see SMBus or I2C Bus specification).
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Device Functional Modes (continued)
CDCE937
CDCEL937
RP
RP
Slave
Master
SDA
SCL
CBUS
CBUS
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Figure 8. SDA/SCL Hardware Interface
8.5 Programming
Table 6. Command Code Definition
BIT
DESCRIPTION
0 = Block Read or Block Write operation
1 = Byte Read or Byte Write operation
7
(6:0)
Byte Offset for Byte Read, Block Read, Byte Write and Block Write operation.
1
S
7
Slave Address
1
R/W
MSB
LSB
S
Start Condition
Sr
Repeated Start Condition
R/W
1
A
8
Data Byte
1
A
MSB
1
P
LSB
1 = Read (Rd) From CDCE9xx Device; 0 = Write (Wr) to CDCE9xxx
A
Acknowledge (ACK = 0 and NACK =1)
P
Stop Condition
Master-to-Slave Transmission
Slave-to-Master Transmission
Figure 9. Generic Programming Sequence
1
S
7
Slave Address
1
Wr
1
A
8
CommandCode
1
A
8
Data Byte
1
A
1
P
Figure 10. Byte Write Protocol
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1
S
7
Slave Address
1
Wr
1
A
8
Data Byte
1
A
1
P
8
CommandCode
1
A
1
S
7
Slave Address
1
Rd
1
A
1
A
1
P
Figure 11. Byte Read Protocol
1
S
7
Slave Address
1
Wr
8
Data Byte 0
1
A
1
A
8
CommandCode
8
Data Byte 1
1
A
1
A
8
Byte Count = N
8
Data Byte N-1
…
1
A
Data byte 0 bits [7:0] is reserved for Revision Code and Vendor Identification. Also, it is used for internal test purpose
and must not be overwritten.
Figure 12. Block Write Protocol
1
S
7
Slave Address
1
Wr
8
Byte Count N
1
A
1
A
8
CommandCode
8
Data Byte 0
1
A
1
A
1
Sr
…
7
Slave Address
1
Rd
1
A
8
Data Byte N-1
1
A
1
P
Figure 13. Block Read Protocol
8.6 Register Maps
8.6.1 SDA/SCL Configuration Registers
The clock input, control pins, PLLs, and output stages are user configurable. The following tables and
explanations describe the programmable functions of the CDCEx937. All settings can be manually written into
the device through the SDA/SCL bus or easily programmed by using the TI Pro-Clock™ software. TI Pro-Clock™
software allows the user to quickly make all settings and automatically calculates the values for optimized
performance at lowest jitter.
Table 7. SDA and SCL Registers
ADDRESS OFFSET
REGISTER DESCRIPTION
TABLE
00h
Generic Configuration Register
Table 9
10h
PLL1 Configuration Register
Table 10
20h
PLL2 Configuration Register
Table 11
30h
PLL3 Configuration Register
Table 12
The grey-highlighted bits, described in the Configuration Registers tables in the following pages, belong to the
Control Terminal Register. The user can predefine up to eight different control settings. These settings then can
be selected by the external control pins, S0, S1, and S2 (see Control Terminal Setting).
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Table 8. Configuration Register, External Control Terminals
Y1
EXTERNAL
CONTROL
PINS
OUTPUT
SELECTION
PLL1 SETTINGS
FREQ.
SELECTION
SSC
SELECTION
PLL2 SETTINGS
OUTPUT
SELECTION
FREQ.
SELECTION
SSC
SELECTION
PLL3 SETTINGS
OUTPUT
SELECTION
FREQ.
SELECTION
SSC
SELECTION
OUTPUT
SELECTION
S2
S1
S0
Y1
FS1
SSC1
Y2Y3
FS2
SSC2
Y4Y5
FS3
SSC3
Y6Y7
0
0
0
0
Y1_0
FS1_0
SSC1_0
Y2Y3_0
FS2_0
SSC2_0
Y4Y5_0
FS3_0
SSC3_0
Y6Y7_0
1
0
0
1
Y1_1
FS1_1
SSC1_1
Y2Y3_1
FS2_1
SSC2_1
Y4Y5_1
FS3_1
SSC3_1
Y6Y7_1
2
0
1
0
Y1_2
FS1_2
SSC1_2
Y2Y3_2
FS2_2
SSC2_2
Y4Y5_2
FS3_2
SSC3_2
Y6Y7_2
3
0
1
1
Y1_3
FS1_3
SSC1_3
Y2Y3_3
FS2_3
SSC2_3
Y4Y5_3
FS3_3
SSC3_3
Y6Y7_3
4
1
0
0
Y1_4
FS1_4
SSC1_4
Y2Y3_4
FS2_4
SSC2_4
Y4Y5_4
FS3_4
SSC3_4
Y6Y7_4
5
1
0
1
Y1_5
FS1_5
SSC1_5
Y2Y3_5
FS2_5
SSC2_5
Y4Y5_5
FS3_5
SSC3_5
Y6Y7_5
6
1
1
0
Y1_6
FS1_6
SSC1_6
Y2Y3_6
FS2_6
SSC2_6
Y4Y5_6
FS3_6
SSC3_6
Y6Y7_6
7
1
1
1
Y1_7
FS1_7
SSC1_7
Y2Y3_7
FS2_7
SSC2_7
Y4Y5_7
FS3_7
SSC3_7
Y6Y7_7
04h
13h
10h–12h
15h
23h
20h–22h
25h
33h
30h–32h
35h
Address Offset (1)
(1)
Address Offset refers to the byte address in the Configuration Register in the following pages.
Table 9. Generic Configuration Register
OFFSET
00h
01h
(1)
BIT
(2)
ACRONYM
DEFAULT
(3)
DESCRIPTION
7
E_EL
Xb
Device identification (read-only): 1 is CDCE937 (3.3 V), 0 is CDCEL937 (1.8 V)
6:4
RID
Xb
Revision Identification Number (read only)
3:0
VID
1h
Vendor Identification Number (read only)
7
–
0b
Reserved – always write 0
6
EEPIP
0b
5
EELOCK
0b
4
PWDN
0b
3:2
INCLK
00b
Input clock
selection:
1:0
SLAVE_AD
R
01b
Programmable Address Bits A0 and A1 of the Slave Receiver Address
7
M1
1b
Clock source selection for output Y1:
EEPROM Programming Status: (4) (read only)
0 – EEPROM programming is completed
1 – EEPROM is in programming mode
Permanently Lock EEPROM Data (5)
0 – EEPROM is not locked
1 – EEPROM is permanently locked
Device Power Down (overwrites S0/S1/S2 setting; configuration register settings are unchanged)
Note: PWDN cannot be set to 1 in the EEPROM.
0 – device active (PLL1 and all outputs are enabled)
1 – device power down (PLL1 in power down and all outputs in 3-state)
00 – Xtal
01 – VCXO
10 – LVCMOS
0 – input clock
11 – reserved
1 – PLL1 clock
Operation mode selection for pin 18/19 (6)
02h
03h
(1)
(2)
(3)
(4)
(5)
(6)
18
6
SPICON
0b
5:4
Y1_ST1
11b
3:2
Y1_ST0
01b
1:0
Pdiv1 [9:8]
7:0
Pdiv1 [7:0]
001h
0 – serial programming interface SDA (pin 19) and SCL (pin 18)
1 – control pins S1 (pin 19) and S2 (pin 18)
Y1-State0/1 Definition
00 – device power down (all PLLs in power down and all
outputs in 3-State)
01 – Y1 disabled to 3-state
10-Bit Y1-Output-Divider Pdiv1:
10 – Y1 disabled to low
11 – Y1 enabled
0 – divider reset and stand-by
1-to-1023 – divider value
Writing data beyond ‘40h’ may affect device function.
All data transferred with the MSB first.
Unless customer-specific setting.
During EEPROM programming, no data is allowed to be sent to the device through the SDA/SCL bus until the programming sequence is
completed. However, data can be read out during the programming sequence (Byte Read or Block Read).
If this bit is set to high in the EEPROM, the actual data in the EEPROM is permanently locked. There is no further programming
possible. However, data can still be written through the SDA/SCL bus to the internal register to change device function on the fly. But
new data can no longer be saved to the EEPROM. EELOCK is effective only, if written into the EEPROM!
Selection of control pins is effective only if written into the EEPROM. Once written into the EEPROM, the serial programming pins are no
longer available. However, if VDDOUT is forced to GND, the two control pins, S1 and S2, temporally act as serial programming pins
(SDA/SCL), and the two slave receiver address bits are reset to A0 = 0 and A1 = 0.
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Table 9. Generic Configuration Register (continued)
OFFSET
(1)
04h
ACRONYM
DEFAULT (3)
7
Y1_7
0b
6
Y1_6
0b
5
Y1_5
0b
4
Y1_4
0b
3
Y1_3
0b
2
Y1_2
0b
1
Y1_1
1b
0
Y1_0
0b
BIT
(2)
7:3
05h
XCSEL
0Ah
2:0
(9)
00h → 0 pF
01h → 1 pF
02h → 2 pF
:
14h-to-1Fh → 20 pF
Crystal Load
Capacitor
Selection (8)
Reserved – do not write other than 0
7:1
BCOUNT
40h
7-Bit Byte Count (defines the number of bytes which is sent from this device at the next Block Read
transfer); all bytes have to be read out to correctly finish the read cycle.)
0
EEWRITE
0b
Initiate EEPROM
Write Cycle(4) (9)
—
0h
Unused address range
07h-0Fh
(8)
0 – State0 (predefined by Y1_ST0)
1 – State1 (predefined by Y1_ST1)
0b
06h
(7)
DESCRIPTION
Y1_ST0/Y1_ST1 State Selection (7)
0– no EEPROM write cycle
1 – start EEPROM write cycle (internal configuration register is saved to the
EEPROM)
These are the bits of the Control Terminal Register. The user can predefine up to eight different control settings. These settings then
can be selected by the external control pins, S0, S1, and S2.
The internal load capacitor (C1, C2) has to be used to achieve the best clock performance. External capacitors must be used only to
finely adjust CL by a few pF's. The value of CL can be programmed with a resolution of 1 pF for a crystal load range of 0 pF to 20 pF.
For CL > 20 pF, use additional external capacitors. Also, the value of the device input capacitance has to be considered which always
adds 1.5 pF (6 pF//2 pF) to the selected CL. For more information about VCXO configuration and crystal recommendation, see VCXO
Application Guideline for CDCE(L)9xx Family (SCAA085).
Note: The EEPROM WRITE bit must be sent last. This ensures that the content of all internal registers are stored in the EEPROM. The
EEWRITE cycle is initiated with the rising edge of the EEWRITE bit. A static level high does not trigger an EEPROM WRITE cycle. The
EEWRITE bit has to be reset to low after the programming is completed. The programming status can be monitored by reading out
EEPIP. If EELOCK is set to high, no EEPROM programming is possible.
Table 10. PLL1 Configuration Register
OFFSET
10h
11h
12h
13h
(1)
(2)
(3)
(4)
(1)
ACRONYM
DEFAULT (3)
7:5
SSC1_7 [2:0]
000b
4:2
SSC1_6 [2:0]
000b
1:0
SSC1_5 [2:1]
7
SSC1_5 [0]
6:4
SSC1_4 [2:0]
000b
3:1
SSC1_3 [2:0]
000b
0
SSC1_2 [2]
7:6
SSC1_2 [1:0]
5:3
SSC1_1 [2:0]
000b
2:0
SSC1_0 [2:0]
000b
7
FS1_7
0b
6
FS1_6
0b
5
FS1_5
0b
4
FS1_4
0b
3
FS1_3
0b
2
FS1_2
0b
1
FS1_1
0b
0
FS1_0
0b
BIT
(2)
000b
000b
DESCRIPTION
SSC1: PLL1 SSC Selection (Modulation Amount) (4)
Down
000 (off)
001 – 0.25%
010 – 0.5%
011 – 0.75%
100 – 1.0%
101 – 1.25%
110 – 1.5%
111 – 2.0%
Center
000 (off)
001 ± 0.25%
010 ± 0.5%
011 ± 0.75%
100 ± 1.0%
101 ± 1.25%
110 ± 1.5%
111 ± 2.0%
FS1_x: PLL1 Frequency Selection(4)
0 – fVCO1_0 (predefined by PLL1_0 – Multiplier/Divider value)
1 – fVCO1_1 (predefined by PLL1_1 – Multiplier/Divider value)
Writing data beyond 40h may adversely affect device function.
All data is transferred MSB-first.
Unless a custom setting is used
The user can predefine up to eight different control settings. In normal device operation, these settings can be selected by the external
control pins, S0, S1, and S2.
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Table 10. PLL1 Configuration Register (continued)
OFFSET
14h
15h
16h
17h
18h
19h
1Ah
(1)
BIT
(2)
ACRONYM
DEFAULT (3)
DESCRIPTION
7
MUX1
1b
PLL1 Multiplexer:
0 – PLL1
1 – PLL1 Bypass (PLL1 is in power down)
6
M2
1b
Output Y2 Multiplexer:
0 – Pdiv1
1 – Pdiv2
5:4
M3
10b
Output Y3 Multiplexer:
00 –
01 –
10 –
11 –
3:2
Y2Y3_ST1
11b
00 – Y2/Y3 disabled to 3-State (PLL1 is in power down)
01 – Y2/Y3 disabled to 3-State
10–Y2/Y3 disabled to low
11 – Y2/Y3 enabled
1:0
Y2Y3_ST0
01b
Y2, Y3State0/1definition:
7
Y2Y3_7
0b
Y2Y3_x Output State Selection(4)
6
Y2Y3_6
0b
5
Y2Y3_5
0b
4
Y2Y3_4
0b
3
Y2Y3_3
0b
2
Y2Y3_2
0b
1
Y2Y3_1
1b
0
Y2Y3_0
0b
7
SSC1DC
0b
PLL1 SSC down/center selection:
0 – down
6:0
Pdiv2
01h
7-Bit Y2-Output-Divider Pdiv2:
0 – reset and stand-by
7
—
0b
Reserved – do not write others than 0
6:0
Pdiv3
01h
7-Bit Y3-Output-Divider Pdiv3:
7:0
PLL1_0N [11:4]
7:4
PLL1_0N [3:0]
004h
PLL1_0 (5): 30-Bit Multiplier/Divider value for frequency fVCO1_0
(for more information, see PLL Frequency Planning).
3:0
PLL1_0R [8:5]
7:3
PLL1_0R[4:0]
2:0
PLL1_0Q [5:3]
7:5
PLL1_0Q [2:0]
4:2
PLL1_0P [2:0]
010b
1:0
VCO1_0_RANGE
00b
7:0
PLL1_1N [11:4]
7:4
PLL1_1N [3:0]
1Dh
3:0
PLL1_1R [8:5]
7:3
1Eh
PLL1_1R[4:0]
2:0
PLL1_1Q [5:3]
7:5
PLL1_1Q [2:0]
4:2
PLL1_1P [2:0]
010b
1:0
VCO1_1_RANGE
00b
20
1 – center
0 – reset and stand-by
1-to-127 is divider value
1-to-127 is divider value
10h
fVCO1_0 range selection:
004h
00 –
01 –
10 –
11 –
fVCO1_0 < 125 MHz
125 MHz ≤ fVCO1_0 < 150 MHz
150 MHz ≤ fVCO1_0 < 175 MHz
fVCO1_0 ≥ 175 MHz
PLL1_1 (5): 30-Bit Multiplier/Divider value for frequency fVCO1_1
(for more information see PLL Frequency Planning).
000h
10h
1Fh
(5)
0 – state0 (predefined by Y2Y3_ST0)
1 – state1 (predefined by Y2Y3_ST1)
000h
1Bh
1Ch
Pdiv1-Divider
Pdiv2-Divider
Pdiv3-Divider
reserved
fVCO1_1 range selection:
00 –
01 –
10 –
11 –
fVCO1_1 < 125 MHz
125 MHz ≤ fVCO1_1 < 150 MHz
150 MHz ≤ fVCO1_1 < 175 MHz
fVCO1_1 ≥ 175 MHz
PLL settings limits: 16 ≤ q ≤ 63, 0 ≤ p ≤ 7, 0 ≤ r ≤ 511, 0 < N < 4096
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Table 11. PLL2 Configuration Register
OFFSET (1)
20h
21h
22h
23h
24h
25h
DEFAULT (3
BIT (2)
ACRONYM
7:5
SSC2_7 [2:0]
000b
4:2
SSC2_6 [2:0]
000b
1:0
SSC2_5 [2:1]
7
SSC2_5 [0]
6:4
SSC2_4 [2:0]
000b
3:1
SSC2_3 [2:0]
000b
0
SSC2_2 [2]
7:6
SSC2_2 [1:0]
5:3
SSC2_1 [2:0]
000b
2:0
SSC2_0 [2:0]
000b
7
FS2_7
0b
6
FS2_6
0b
5
FS2_5
0b
4
FS2_4
0b
3
FS2_3
0b
2
FS2_2
0b
1
FS2_1
0b
0
FS2_0
0b
7
MUX2
1b
6
M4
1b
5:4
M5
10b
3:2
Y4Y5_ST1
11b
1:0
Y4Y5_ST0
01b
7
Y4Y5_7
0b
6
Y4Y5_6
0b
5
Y4Y5_5
0b
4
Y4Y5_4
0b
3
Y4Y5_3
0b
2
Y4Y5_2
0b
1
Y4Y5_1
1b
0
Y4Y5_0
0b
7
SSC2DC
0b
6:0
Pdiv4
01h
7
—
0b
6:0
Pdiv5
01h
000b
000b
26h
27h
(1)
(2)
(3)
(4)
DESCRIPTION
)
SSC2: PLL2 SSC Selection (Modulation Amount) (4)
Down
000 (off)
001 – 0.25%
010 – 0.5%
011 – 0.75%
100 – 1.0%
101 – 1.25%
110 – 1.5%
111 – 2.0%
Center
000 (off)
001 ± 0.25%
010 ± 0.5%
011 ± 0.75%
100 ± 1.0%
101 ± 1.25%
110 ± 1.5%
111 ± 2.0%
FS2_x: PLL2 Frequency Selection(4)
0 – fVCO2_0 (predefined by PLL2_0 – Multiplier/Divider value)
1 – fVCO2_1 (predefined by PLL2_1 – Multiplier/Divider value)
PLL2 Multiplexer:
0 – PLL2
1 – PLL2 Bypass (PLL2 is in power down)
Output Y4
Multiplexer:
0 – Pdiv2
1 – Pdiv4
Output Y5
Multiplexer:
00 –
01 –
10 –
11 –
Y4, Y5State0/1definition:
00 – Y4/Y5 disabled to 3-State (PLL2 is in power down)
01 – Y4/Y5 disabled to 3-State
10–Y4/Y5 disabled to low
11 – Y4/Y5 enabled
Pdiv2-Divider
Pdiv4-Divider
Pdiv5-Divider
reserved
Y4Y5_x Output State Selection(4)
0 – state0 (predefined by Y4Y5_ST0)
1 – state1 (predefined by Y4Y5_ST1)
PLL2 SSC down/center
selection:
0 – down
1 – center
7-Bit Y4-Output-Divider Pdiv4:
0 – reset and stand-by
value
1-to-127 – divider
Reserved – do not write others than 0
7-Bit Y5-Output-Divider Pdiv5:
0 – reset and stand-by
value
1-to-127 – divider
Writing data beyond 40h may adversely affect device function.
All data is transferred MSB-first.
Unless a custom setting is used
The user can predefine up to eight different control settings. In normal device operation, these settings can be selected by the external
control pins, S0, S1, and S2.
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Table 11. PLL2 Configuration Register (continued)
DEFAULT (3
OFFSET (1)
BIT (2)
ACRONYM
28h
7:0
PLL2_0N [11:4
7:4
PLL2_0N [3:0]
3:0
PLL2_0R [8:5]
7:3
PLL2_0R[4:0]
2:0
PLL2_0Q [5:3]
7:5
PLL2_0Q [2:0]
4:2
PLL2_0P [2:0]
010b
1:0
VCO2_0_RANGE
00b
7:0
PLL2_1N [11:4]
7:4
PLL2_1N [3:0]
3:0
PLL2_1R [8:5]
7:3
PLL2_1R[4:0]
2:0
PLL2_1Q [5:3]
7:5
PLL2_1Q [2:0]
4:2
PLL2_1P [2:0]
010b
1:0
VCO2_1_RANGE
00b
29h
2Ah
004h
2Dh
2Eh
10h
fVCO2_0 range selection:
004h
00 –
01 –
10 –
11 –
fVCO2_0 < 125 MHz
125 MHz ≤ fVCO2_0 < 150 MHz
150 MHz ≤ fVCO2_0 < 175 MHz
fVCO2_0 ≥ 175 MHz
PLL2_1 (5): 30-Bit Multiplier/Divider value for frequency fVCO2_1
(for more information see PLL Frequency Planning).
000h
10h
fVCO2_1 range selection:
2Fh
(5)
PLL2_0 (5): 30-Bit Multiplier/Divider value for frequency fVCO2_0
(for more information see PLL Frequency Planning).
000h
2Bh
2Ch
DESCRIPTION
)
00 –
01 –
10 –
11 –
fVCO2_1 < 125 MHz
125 MHz ≤ fVCO2_1 < 150 MHz
150 MHz ≤ fVCO2_1 < 175 MHz
fVCO2_1 ≥ 175 MHz
PLL settings limits: 16 ≤ q ≤ 63, 0 ≤ p ≤ 7, 0 ≤ r ≤ 511, 0 < N < 4096
Table 12. PLL3 Configuration Register
OFFSET (1)
30h
31h
32h
33h
(1)
(2)
(3)
(4)
22
BIT (2)
ACRONYM
DEFAULT (3)
7:5
SSC3_7 [2:0]
000b
4:2
SSC3_6 [2:0]
000b
1:0
SSC3_5 [2:1]
7
SSC3_5 [0]
6:4
SSC3_4 [2:0]
000b
3:1
SSC3_3 [2:0]
000b
0
SSC3_2 [2]
7:6
SSC3_2 [1:0]
5:3
SSC3_1 [2:0]
000b
2:0
SSC3_0 [2:0]
000b
7
FS3_7
0b
6
FS3_6
0b
5
FS3_5
0b
4
FS3_4
0b
3
FS3_3
0b
2
FS3_2
0b
1
FS3_1
0b
0
FS3_0
0b
000b
000b
DESCRIPTION
SSC3: PLL3 SSC Selection (Modulation Amount) (4)
Down
000 (off)
001 – 0.25%
010 – 0.5%
011 – 0.75%
100 – 1.0%
101 – 1.25%
110 – 1.5%
111 – 2.0%
Center
000 (off)
001 ± 0.25%
010 ± 0.5%
011 ± 0.75%
100 ± 1.0%
101 ± 1.25%
110 ± 1.5%
111 ± 2.0%
FS3_x: PLL3 Frequency Selection(4)
0 – fVCO3_0 (predefined by PLL3_0 – Multiplier/Divider value)
1 – fVCO3_1 (predefined by PLL3_1 – Multiplier/Divider value)
Writing data beyond 40h may affect device function.
All data is transferred MSB-first.
Unless a custom setting is used
These are the bits of the Control Terminal Register. The user can pre-define up to eight different control settings. At normal device
operation, these setting can be selected by the external control pins, S0, S1, and S2.
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Table 12. PLL3 Configuration Register (continued)
OFFSET
34h
35h
36h
37h
38h
39h
3Ah
(1)
BIT
(2)
ACRONYM
DEFAULT (3)
DESCRIPTION
7
MUX3
1b
PLL3 Multiplexer:
0 – PLL3
1 – PLL3 Bypass (PLL3 is in power down)
6
M6
1b
Output Y6 Multiplexer:
0 – Pdiv4
1 – Pdiv6
5:4
M7
10b
Output Y7 Multiplexer:
00 –
01 –
10 –
11 –
3:2
Y6Y7_ST1
11b
00 – Y6/Y7 disabled to 3-State and PLL3 power down
01 – Y6/Y7 disabled to 3-State
10 –Y6/Y7 disabled to low
11 – Y6/Y7 enabled
1:0
Y6Y7_ST0
01b
Y6, Y7State0/1definition:
7
Y6Y7_7
0b
Y6Y7_x Output State Selection(4)
6
Y6Y7_6
0b
5
Y6Y7_5
0b
4
Y6Y7_4
0b
3
Y6Y7_3
0b
2
Y6Y7_2
0b
1
Y6Y7_1
1b
0
Y6Y7_0
0b
7
SSC3DC
0b
PLL3 SSC down/center selection: 0 – down
6:0
Pdiv6
01h
7-Bit Y6-Output-Divider Pdiv6:
7
—
0b
Reserved – do not write others than 0
6:0
Pdiv7
01h
7-Bit Y7-Output-Divider Pdiv7:
7:0
PLL3_0N [11:4]
7:4
PLL3_0N [3:0]
004h
PLL3_0 (5): 30-Bit Multiplier/Divider value for frequency fVCO3_0
(for more information, see PLL Frequency Planning).
3:0
PLL3_0R [8:5]
7:3
PLL3_0R[4:0]
2:0
PLL3_0Q [5:3]
7:5
PLL3_0Q [2:0]
4:2
PLL3_0P [2:0]
010b
1:0
VCO3_0_RANGE
00b
7:0
PLL3_1N [11:4]
7:4
PLL3_1N [3:0]
3Dh
3:0
PLL3_1R [8:5]
7:3
3Eh
PLL3_1R[4:0]
2:0
PLL3_1Q [5:3]
7:5
PLL3_1Q [2:0]
4:2
PLL3_1P [2:0]
010b
1:0
VCO3_1_RANGE
00b
1 – center
0 – reset and stand-by
0 – reset and stand-by
1-to-127 – divider value
1-to-127 – divider value
10h
fVCO3_0 range selection:
004h
00 –
01 –
10 –
11 –
fVCO3_0 < 125 MHz
125 MHz ≤ fVCO3_0 < 150 MHz
150 MHz ≤ fVCO3_0 < 175 MHz
fVCO3_0 ≥ 175 MHz
PLL3_1 (5): 30-Bit Multiplier/Divider value for frequency fVCO3_1
(for more information, see PLL Frequency Planning).
000h
10h
3Fh
(5)
0 – state0 (predefined by Y6Y7_ST0)
1 – state1 (predefined by Y6Y7_ST1)
000h
3Bh
3Ch
Pdiv4-Divider
Pdiv6-Divider
Pdiv7-Divider
reserved
fVCO3_1 range selection:
00 –
01 –
10 –
11 –
fVCO3_1 < 125 MHz
125 MHz ≤ fVCO3_1 < 150 MHz
150 MHz ≤ fVCO3_1 < 175 MHz
fVCO3_1 ≥ 175 MHz
PLL settings limits: 16 ≤ q ≤ 63, 0 ≤ p ≤ 7, 0 ≤ r ≤ 511, 0 < N < 4096
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The CDCEx937 device is an easy-to-use, high-performance, programmable CMOS clock synthesizer. It can be
used as a crystal buffer, clock synthesizer with separate output supply pin. The CDCEx937 features an on-chip
loop filter and spread-spectrum modulation. Programming can be done through SPI, pin-mode, or using on-chip
EEPROM. The following section shows some examples of using CDCEx937 in various applications.
9.2 Typical Application
Figure 14 shows the use of the CDCEx937 devices for replacement of crystals and crystal oscillators on a
Gigabit Ethernet Switch application.
Crystals + Oscillators
1 x Crystal + 1 x Clock
Crystals:4
Oscillators: 2
Clock: None
Crystals: 1
Oscillators: None
Clock: 1
40 MHz
DP838xx
10/100 PHY
WiFi
25 MHz
DP838xx
10/100 PHY
CDCE(L)9xx
Clock
WiFi
25 MHz
100 MHz
25 MHz
FPGA
USB
Controller
FPGA
25 MHz
USB
Controller
48 MHz
Copyright © 2016, Texas Instruments Incorporated
Figure 14. Crystal and Oscillator Replacement Example
9.2.1 Design Requirements
CDCEx937 supports spread-spectrum clocking (SSC) with multiple control parameters:
• Modulation amount (%)
• Modulation frequency (>20 kHz)
• Modulation shape (triangular)
• Center spread / down spread (± or –)
24
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Typical Application (continued)
Figure 15. Modulation Frequency (fm) and Modulation Amount
9.2.2 Detailed Design Procedure
9.2.2.1 Spread Spectrum Clock (SSC)
Spread-spectrum modulation is a method to spread emitted energy over a larger bandwidth. In clocking, spread
spectrum can reduce Electromagnetic Interference (EMI) by reducing the level of emission from clock distribution
network.
CDCS502 with a 25-MHz Crystal, FS = 1, Fout = 100 MHz, and 0%, ±0.5, ±1%, and ±2% SSC
Figure 16. Comparison Between Typical Clock Power Spectrum and Spread-Spectrum Clock
9.2.2.2 PLL Frequency Planning
At a given input frequency (ƒIN), the output frequency (ƒOUT) of the CDCEx913 are calculated with Equation 1.
ƒ
N
ƒOUT = IN ´
Pdiv M
where
•
•
M (1 to 511) and N (1 to 4095) are the multiplier/divide values of the PLL
Pdiv (1 to 127) is the output divider
(1)
The target VCO frequency (ƒVCO) of each PLL is calculated with Equation 2.
N
ƒ VCO = ƒIN ´
M
(2)
The PLL internally operates as fractional divider and needs the following multiplier/divider settings:
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Typical Application (continued)
•
•
•
•
N
P = 4 – int(log2N/M; if P < 0 then P = 0
Q = int(N'/M)
R = N′ – M × Q
where
N′ = N × 2P
N ≥ M;
80 MHz ≤ ƒVCO ≤ 230 MHz
16 ≤ Q ≤ 63
0≤P≤4
0 ≤ R ≤ 51
Example:
for ƒIN = 27 MHz; M = 1; N = 4; Pdiv = 2
for ƒIN = 27 MHz; M = 2; N = 11; Pdiv = 2
→ fOUT = 54 MHz
→ fOUT = 74.25 MHz
→ fVCO = 108 MHz
→ fVCO = 148.50 MHz
→ P = 4 – int(log24) = 4 – 2 = 2
→ P = 4 – int(log25.5) = 4 – 2 = 2
2
→ N' = 4 × 2 = 16
→ N' = 11 × 22 = 44
→ Q = int(16) = 16
→ Q = int(22) = 22
→ R = 16 – 16 = 0
→ R = 44 – 44 = 0
The values for P, Q, R, and N’ are automatically calculated when using TI Pro-Clock™ software.
9.2.2.3 Crystal Oscillator Start-Up
When the CDCEx937 is used as a crystal buffer, crystal oscillator start-up dominates the start-up time compared
to the internal PLL lock time. Figure 17 shows the oscillator start-up sequence for a 27-MHz crystal input with an
8-pF load. The start-up time for the crystal is in the order of approximately 250 µs compared to approximately 10
µs of lock time. In general, lock time will be an order of magnitude less compared to the crystal start-up time.
Figure 17. Crystal Oscillator Start-Up vs PLL Lock Time
9.2.2.4 Frequency Adjustment With Crystal Oscillator Pulling
The frequency for the CDCEx937 is adjusted for media and other applications with the VCXO control input Vctrl.
If a PWM modulated signal is used as a control signal for the VCXO, an external filter is needed.
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Typical Application (continued)
LP
PWM
control
signal
Vctrl
CDCEx937
Xin/CLK
Xout
Copyright © 2016, Texas Instruments Incorporated
Figure 18. Frequency Adjustment Using PWM Input to the VCXO Control
9.2.2.5 Unused Inputs and Outputs
If VCXO pulling functionality is not required, Vctrl should be left floating. All other unused inputs should be set to
GND. Unused outputs should be left floating.
If one output block is not used, TI recommends disabling it. However, TI always recommends providing the
supply for the second output block even if it is disabled.
9.2.2.6 Switching Between XO and VCXO Mode
When the CDCEx937 is in crystal oscillator or in VCXO configuration, the internal capacitors require different
internal capacitance. The following steps are recommended to switch to VCXO mode when the configuration for
the on-chip capacitor is still set for XO mode. To center the output frequency to 0 ppm:
1. While in XO mode, put Vctrl = Vdd / 2
2. Switch from XO mode to VCXO mode
3. Program the internal capacitors in order to obtain 0 ppm at the output
9.2.3 Application Curves
Figure 19, Figure 20, Figure 21, and Figure 22 show CDCEx937 measurements with the SSC feature enabled.
Device configuration: 27-MHz input, 27-MHz output.
Figure 19. fout = 27 MHz, VCO frequency < 125 MHz, SSC
(2% center)
Figure 20. fout = 27 MHz, VCO frequency > 175 MHz, SSC
(1%, center)
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Typical Application (continued)
Figure 21. Output Spectrum With SSC Off
28
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Figure 22. Output Spectrum With SSC On, 2% Center
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CDCE937, CDCEL937
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SLAS564G – AUGUST 2007 – REVISED OCTOBER 2016
10 Power Supply Recommendations
There is no restriction on the power-up sequence. In case VDDOUT is applied first, TI recommends grounding
VDD. In case VDDOUT is powered while VDD is floating, there is a risk of high current flowing on the VDDOUT.
The device has a power-up control that is connected to the 1.8-V supply. This keeps the whole device disabled
until the 1.8-V supply reaches a sufficient voltage level. Then the device switches on all internal components,
including the outputs. If there is a 3.3-V Vddout available before the 1.8 V, the outputs remain disabled until the
1.8-V supply has reached a certain level.
11 Layout
11.1 Layout Guidelines
When the CDCEx937 is used as a crystal buffer, any parasitics across the crystal affects the pulling range of the
VCXO. Therefore, take care in placing the crystal units on the board. Crystals should be placed as close to the
device as possible, ensuring that the routing lines from the crystal terminals to XIN and XOUT have the same
length.
If possible, cut out both ground plane and power plane under the area where the crystal and the routing to the
device are placed. In this area, always avoid routing any other signal line, as it could be a source of noise
coupling.
Additional discrete capacitors can be required to meet the load capacitance specification of certain crystal. For
example, a 10.7-pF load capacitor is not fully programmable on the chip, because the internal capacitor can
range from 0 pF to 20 pF with steps of 1 pF. The 0.7-pF capacitor therefore can be discretely added on top of an
internal 10 pF.
To minimize the inductive influence of the trace, TI recommends placing this small capacitor as close to the
device as possible and symmetrically with respect to XIN and XOUT.
Figure 23 shows a conceptual layout detailing recommended placement of power supply bypass capacitors on
the basis of CDCEx937. For component side mounting, use 0402 body size capacitors to facilitate signal routing.
Keep the connections between the bypass capacitors and the power supply on the device as short as possible.
Ground the other side of the capacitor using a low-impedance connection to the ground plane.
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11.2 Layout Example
1
4
3
2
1
3
Place crystal with associated load
caps as close to the chip
Place bypass caps close to the device
pins, ensure wide freq. range
2
Place series termination resistors at
Clock outputs to improve signal integrity
4
Use ferrite beads to isolate the device
supply pins from board noise sources
Figure 23. Annotated Layout
30
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CDCE937, CDCEL937
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SLAS564G – AUGUST 2007 – REVISED OCTOBER 2016
12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.1.2 Development Support
For development support see the following:
• SMBus
• I2C Bus
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation see the following:
VCXO Application Guideline for CDCE(L)9xx Family (SCAA085)
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 Trademarks
TI-DaVinci, OMAP, Pro-Clock, E2E are trademarks of Texas Instruments.
Bluetooth is a trademark of Bluetooth SIG.
Ethernet is a trademark of Xerox Corporation.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Product Folder Links: CDCE937 CDCEL937
PACKAGE OPTION ADDENDUM
www.ti.com
15-Apr-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
CDCE937PW
ACTIVE
TSSOP
PW
20
70
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
CDCE937
CDCE937PWG4
ACTIVE
TSSOP
PW
20
70
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
CDCE937
CDCE937PWR
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
CDCE937
CDCE937PWRG4
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
CDCE937
CDCEL937PW
ACTIVE
TSSOP
PW
20
70
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
CDCEL937
CDCEL937PWG4
ACTIVE
TSSOP
PW
20
70
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
CDCEL937
CDCEL937PWR
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
CDCEL937
CDCEL937PWRG4
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
CDCEL937
HPA00406PWR
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
CDCE937
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
15-Apr-2017
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF CDCE937, CDCEL937 :
• Automotive: CDCE937-Q1, CDCEL937-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
CDCE937PWR
TSSOP
PW
20
2000
330.0
16.4
6.95
7.1
1.6
8.0
16.0
Q1
CDCEL937PWR
TSSOP
PW
20
2000
330.0
16.4
6.95
7.1
1.6
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CDCE937PWR
TSSOP
PW
20
2000
367.0
367.0
38.0
CDCEL937PWR
TSSOP
PW
20
2000
367.0
367.0
38.0
Pack Materials-Page 2
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