Cypress CY14B256L-SP35XCT 256 kbit (32k x 8) nvsram Datasheet

CY14B256L
256 Kbit (32K x 8) nvSRAM
Features
Functional Description
■
25 ns, 35 ns, and 45 ns access times
■
Pin compatible with STK14D88
■
Hands off automatic STORE on power down with only a small
capacitor
■
STORE to QuantumTrap™ nonvolatile elements is initiated by
software, hardware, or AutoStore™ on power down
■
RECALL to SRAM initiated by software or power up
■
Unlimited READ, WRITE, and RECALL cycles
■
200,000 STORE cycles to QuantumTrap
The Cypress CY14B256L is a fast static RAM with a nonvolatile
element in each memory cell. The embedded nonvolatile
elements incorporate QuantumTrap technology producing the
world’s most reliable nonvolatile memory. The SRAM provides
unlimited read and write cycles, while independent, nonvolatile
data resides in the highly reliable QuantumTrap cell. Data
transfers from the SRAM to the nonvolatile elements (the
STORE operation) takes place automatically at power down. On
power up, data is restored to the SRAM (the RECALL operation)
from the nonvolatile memory. Both the STORE and RECALL
operations are also available under software control. A hardware
STORE is initiated with the HSB pin.
■
20 year data retention at 55°C
■
Single 3V +20%, –10% operation
■
Commercial and industrial temperature
■
32-pin (300 mil) SOIC and 48-pin (300 mil) SSOP packages
■
RoHS compliance
Logic Block Diagram
VCC
Quantum Trap
512 X 512
A5
DQ 4
DQ 5
DQ 6
RECALL
STORE/
RECALL
CONTROL
HSB
A13 - A 0
COLUMN I/O
INPUT BUFFERS
DQ 2
DQ 3
STATIC RAM
ARRAY
512 X 512
SOFTWARE
DETECT
DQ 0
DQ 1
POWER
CONTROL
STORE
ROW DECODER
A6
A7
A8
A9
A 11
A 12
A 13
A 14
VCAP
COLUMN DEC
A 0 A 1 A 2 A 3 A 4 A 10
DQ 7
OE
CE
WE
Cypress Semiconductor Corporation
Document Number: 001-06422 Rev. *H
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised January 30, 2009
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CY14B256L
Pin Configurations
Figure 1. Pin Diagram - 32-Pin SOIC and 48-Pin SSOP
Pin Definitions
Pin Name
Alt
A0–A14
IO Type
Input
DQ0-DQ7
Description
Address Inputs. Used to select one of the 32,768 bytes of the nvSRAM.
Input or Output Bidirectional Data IO Lines. Used as input or output lines depending on operation.
WE
W
Input
Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the IO
pins is written to the specific address location.
CE
E
Input
Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
OE
G
Input
Output Enable, Active LOW. The active LOW OE input enables the data output buffers during
read cycles. Deasserting OE HIGH causes the IO pins to tri-state.
VSS
Ground
Ground for the Device. The device is connected to ground of the system.
VCC
Power Supply Power Supply Inputs to the Device.
HSB
Input or Output Hardware Store Busy (HSB). When LOW, this output indicates a Hardware Store is in progress.
When pulled low external to the chip, it initiates a nonvolatile STORE operation. A weak internal
pull up resistor keeps this pin high if not connected (connection optional).
VCAP
Power Supply AutoStore Capacitor. Supplies power to nvSRAM during power loss to store data from SRAM
to nonvolatile elements.
NC
No Connect
No Connect. This pin is not connected to the die.
Document Number: 001-06422 Rev. *H
Page 2 of 18
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CY14B256L
Figure 2. AutoStore Mode
V CC
V CC
0.1UF
V CAP
10k Ohm
The CY14B256L nvSRAM is made up of two functional components paired in the same physical cell. These are an SRAM
memory cell and a nonvolatile QuantumTrap cell. The SRAM
memory cell operates as a standard fast static RAM. Data in the
SRAM is transferred to the nonvolatile cell (the STORE
operation) or from the nonvolatile cell to SRAM (the RECALL
operation). This unique architecture enables the storage and
recall of all cells in parallel. During the STORE and RECALL
operations, SRAM READ and WRITE operations are inhibited.
The CY14B256L supports unlimited reads and writes similar to
a typical SRAM. In addition, it provides unlimited RECALL operations from the nonvolatile cells and up to 200K STORE operations.
the VCAP pin is driven to 5V by a charge pump internal to the chip.
A pull up is placed on WE to hold it inactive during power up.
V CAP
Device Operation
WE
SRAM Read
The CY14B256L performs a READ cycle whenever CE and OE
are LOW while WE and HSB are HIGH. The address specified
on pins A0–14 determines the 32,768 data bytes accessed. When
the READ is initiated by an address transition, the outputs are
valid after a delay of tAA (READ cycle 1). If the READ is initiated
by CE or OE, the outputs are valid at tACE or at tDOE, whichever
is later (READ cycle 2). The data outputs repeatedly respond to
address changes within the tAA access time without the need for
transitions on any control input pins, and remains valid until
another address change or until CE or OE is brought HIGH, or
WE or HSB is brought LOW.
SRAM Write
A WRITE cycle is performed whenever CE and WE are LOW and
HSB is HIGH. The address inputs must be stable prior to entering
the WRITE cycle and must remain stable until either CE or WE
goes HIGH at the end of the cycle. The data on the common IO
pins DQ0–7 are written into the memory if it has valid tSD, before
the end of a WE controlled WRITE or before the end of an CE
controlled WRITE. Keep OE HIGH during the entire WRITE cycle
to avoid data bus contention on common IO lines. If OE is left
LOW, internal circuitry turns off the output buffers tHZWE after WE
goes LOW.
AutoStore Operation
The CY14B256L stores data to nvSRAM using one of three
storage operations:
1. Hardware store activated by HSB
2. Software store activated by an address sequence
3. AutoStore on device power down
AutoStore operation is a unique feature of QuantumTrap
technology and is enabled by default on the CY14B256L.
During normal operation, the device draws current from VCC to
charge a capacitor connected to the VCAP pin. This stored
charge is used by the chip to perform a single STORE operation.
If the voltage on the VCC pin drops below VSWITCH, the part
automatically disconnects the VCAP pin from VCC. A STORE
operation is initiated with power provided by the VCAP capacitor.
Figure 2 shows the proper connection of the storage capacitor
(VCAP) for automatic store operation. Refer to the DC Electrical
Characteristics on page 7 for the size of VCAP. The voltage on
Document Number: 001-06422 Rev. *H
To reduce unnecessary nonvolatile stores, AutoStore and
Hardware Store operations are ignored, unless at least one
WRITE operation has taken place since the most recent STORE
or RECALL cycle. Software initiated STORE cycles are
performed regardless of whether a WRITE operation has taken
place. An optional pull-up resistor is shown connected to HSB.
The HSB signal is monitored by the system to detect if an
AutoStore cycle is in progress.
Hardware STORE (HSB) Operation
The CY14B256L provides the HSB pin for controlling and
acknowledging the STORE operations. The HSB pin is used to
request a hardware STORE cycle. When the HSB pin is driven
LOW, the CY14B256L conditionally initiates a STORE operation
after tDELAY. An actual STORE cycle only begins if a WRITE to
the SRAM takes place since the last STORE or RECALL cycle.
The HSB pin also acts as an open drain driver that is internally
driven LOW to indicate a busy condition, while the STORE
(initiated by any means) is in progress.
SRAM READ and WRITE operations, that are in progress when
HSB is driven LOW by any means, are given time to complete
before the STORE operation is initiated. After HSB goes LOW,
the CY14B256L continues SRAM operations for tDELAY. During
tDELAY, multiple SRAM READ operations take place. If a WRITE
is in progress when HSB is pulled LOW, it allows a time, tDELAY
to complete. However, any SRAM WRITE cycles requested after
HSB goes LOW are inhibited until HSB returns HIGH.
If HSB is not used, it is left unconnected.
Hardware RECALL (Power Up)
During power up or after any low power condition (VCC <
VSWITCH), an internal RECALL request is latched. When VCC
Page 3 of 18
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CY14B256L
once again exceeds the sense voltage of VSWITCH, a RECALL
cycle is automatically initiated and takes tHRECALL to complete.
Software STORE
Data is transferred from the SRAM to the nonvolatile memory by
a software address sequence. The CY14B256L software
STORE cycle is initiated by executing sequential CE controlled
READ cycles from six specific address locations in exact order.
During the STORE cycle, an erase of the previous nonvolatile
data is first performed followed by a program of the nonvolatile
elements. When a STORE cycle is initiated, input and output are
disabled until the cycle is completed.
Because a sequence of READs from specific addresses is used
for STORE initiation, it is important that no other READ or WRITE
accesses intervene in the sequence. If they intervene, the
sequence is aborted and no STORE or RECALL takes place.
To initiate the software STORE cycle, the following READ
sequence is performed:
1. Read address 0x0E38, Valid READ
2. Read address 0x31C7, Valid READ
3. Read address 0x03E0, Valid READ
4. Read address 0x3C1F, Valid READ
5. Read address 0x303F, Valid READ
6. Read address 0x0FC0, Initiate STORE cycle
The software sequence is clocked with CE controlled READs or
OE controlled READs. When the sixth address in the sequence
is entered, the STORE cycle commences and the chip is
disabled. It is important that READ cycles and not WRITE cycles
are used in the sequence. It is not necessary that OE is LOW for
a valid sequence. After the tSTORE cycle time is fulfilled, the
SRAM is again activated for READ and WRITE operation.
Software RECALL
Data is transferred from the nonvolatile memory to the SRAM by
a software address sequence. A software RECALL cycle is
initiated with a sequence of READ operations in a manner similar
to the software STORE initiation. To initiate the RECALL cycle,
the following sequence of CE controlled READ operations is
performed:
1. Read address 0x0E38, Valid READ
2. Read address 0x31C7, Valid READ
3. Read address 0x03E0, Valid READ
4. Read address 0x3C1F, Valid READ
5. Read address 0x303F, Valid READ
6. Read address 0x0C63, Initiate RECALL cycle
Data Protection
The CY14B256L protects data from corruption during low
voltage conditions by inhibiting all externally initiated STORE
and WRITE operations. The low voltage condition is detected
when VCC is less than VSWITCH. If the CY14B256L is in a WRITE
mode (both CE and WE are low) at power up after a RECALL or
after a STORE, the WRITE is inhibited until a negative transition
on CE or WE is detected. This protects against inadvertent writes
during power up or brown out conditions.
Noise Considerations
The CY14B256L is a high speed memory. It must have a high
frequency bypass capacitor of approximately 0.1 µF connected
between VCC and VSS, using leads and traces that are as short
as possible. As with all high speed CMOS ICs, careful routing of
power, ground, and signals reduce circuit noise.
Low Average Active Power
CMOS technology provides the CY14B256L the benefit of
drawing significantly less current when it is cycled at times longer
than 50 ns. Figure 3 shows the relationship between ICC and
READ or WRITE cycle time. Worst case current consumption is
shown for both CMOS and TTL input levels (commercial temperature range, VCC = 3.6V, 100% duty cycle on chip enable). Only
standby current is drawn when the chip is disabled. The overall
average current drawn by the CY14B256L depends on the
following items:
■
The duty cycle of chip enable
■
The overall cycle rate for accesses
■
The ratio of READs to WRITEs
■
CMOS versus TTL input levels
■
The operating temperature
■
The VCC level
■
IO loading
Figure 3. Current vs. Cycle Time
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared, and then the nonvolatile information is transferred into
the SRAM cells. After the tRECALL cycle time, the SRAM is once
again ready for READ and WRITE operations. The RECALL
operation does not alter the data in the nonvolatile elements. The
nonvolatile data can be recalled an unlimited number of times.
Document Number: 001-06422 Rev. *H
Page 4 of 18
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CY14B256L
Preventing Store
Best Practices
Disable the AutoStore function by initiating an AutoStore Disable
sequence. A sequence of READ operations is performed in a
manner similar to the software STORE initiation. To initiate the
AutoStore Disable sequence, perform the following sequence of
CE controlled or OE controlled READ operations:
1. Read Address 0x0E38 Valid READ
2. Read Address 0x31C7 Valid READ
3. Read Address 0x03E0 Valid READ
4. Read Address 0x3C1F Valid READ
5. Read Address 0x303F Valid READ
6. Read Address 0x03F8 AutoStore Disable
nvSRAM products have been used effectively for over 15 years.
While ease of use is one of the product’s main system values,
experience gained working with hundreds of applications has
resulted in the following suggestions as best practices:
Re-enable the AutoStore by initiating an AutoStore Enable
sequence. A sequence of READ operations is performed in a
manner similar to the software RECALL initiation. To initiate the
AutoStore Enable sequence, perform the following sequence of
CE controlled or OE controlled READ operations:
1. Read Address 0x0E38 Valid READ
2. Read Address 0x31C7 Valid READ
3. Read Address 0x03E0 Valid READ
4. Read Address 0x3C1F Valid READ
5. Read Address 0x303F Valid READ
6. Read Address 0x07F0 AutoStore Enable
■
The nonvolatile cells in an nvSRAM are programmed on the
test floor during final test and quality assurance. Incoming
inspection routines at customer or contract manufacturer’s
sites sometimes reprogram these values. Final NV patterns are
typically repeating patterns of AA, 55, 00, FF, A5, or 5A. End
product’s firmware should not assume an NV array is in a set
programmed state. Routines that check memory content
values to determine first time system configuration, cold or
warm boot status, and so on should always program a unique
NV pattern (for example, complex 4-byte pattern of 46 E6 49
53 hex or more random bytes) as part of the final system
manufacturing test to ensure these system routines work
consistently.
■
Power up boot firmware routines should rewrite the nvSRAM
into the desired state. While the nvSRAM is shipped in a preset
state, the best practice is to again rewrite the nvSRAM into the
desired state as a safeguard against events that might flip the
bit inadvertently (program bugs, incoming inspection routines,
and so on).
■
If autostore is firmware disabled, it does not reset to “autostore
enabled” on every power down event captured by the nvSRAM.
The application firmware should re-enable or re-disable
autostore on each reset sequence based on the behavior
desired.
■
The VCAP value specified in this data sheet includes a minimum
and a maximum value size. Best practice is to meet this
requirement and not exceed the maximum VCAP value because
higher inrush currents may reduce the reliability of the internal
pass transistor. Customers that want to use a larger VCAP value
to make sure there is extra store charge should discuss their
VCAP size selection with Cypress to understand any impact on
the VCAP voltage level at the end of a tRECALL period.
If the AutoStore function is disabled or re-enabled, a manual
STORE operation (Hardware or Software) is issued to save the
AutoStore state through subsequent power down cycles. The
part comes from the factory with AutoStore enabled.
Document Number: 001-06422 Rev. *H
Page 5 of 18
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CY14B256L
Table 1. Hardware Mode Selection
CE
H
L
L
L
WE
X
H
L
H
OE
X
L
X
L
L
H
L
L
H
L
L
H
L
A14 – A0
X
X
X
0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x03F8
0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x07F0
0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x0FC0
0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x0C63
Mode
Not Selected
Read SRAM
Write SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore Disable
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore Enable
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile Store
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile Recall
IO
Output High Z
Output Data
Input Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Power
Standby
Active
Active
Active[1, 2, 3]
Active[1, 2, 3]
Active ICC2[1, 2, 3]
Active[1, 2, 3]
Notes
1. The six consecutive address locations are in the order listed. WE is HIGH during all six cycles to enable a nonvolatile cycle.
2. While there are 15 address lines on the CY14B256L, only the lower 14 lines are used to control software modes.
3. IO state depends on the state of OE. The IO table shown is based on OE Low.
Document Number: 001-06422 Rev. *H
Page 6 of 18
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CY14B256L
Maximum Ratings
Package Power Dissipation
Capability (TA = 25°C) ................................................... 1.0W
Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.
Surface Mount Lead Soldering
Temperature (3 Seconds) .......................................... +260°C
Storage Temperature ................................. –65°C to +150°C
DC output Current (1 output at a time, 1s duration) .... 15 mA
Ambient Temperature with
Power Applied ............................................ –55°C to +125°C
Static Discharge Voltage.......................................... > 2001V
(MIL-STD-883, Method 3015)
Supply Voltage on VCC Relative to GND ..........–0.5V to 4.1V
Latch Up Current ................................................... > 200 mA
Voltage Applied to Outputs
in High Z State ....................................... –0.5V to VCC + 0.5V
Operating Range
Input Voltage...........................................–0.5V to Vcc + 0.5V
Range
Transient Voltage (<20 ns) on
Any Pin to Ground Potential .................. –2.0V to VCC + 2.0V
Commercial
Industrial
Ambient Temperature
VCC
0°C to +70°C
2.7V to 3.6V
-40°C to +85°C
2.7V to 3.6V
DC Electrical Characteristics
Over the operating range (VCC = 2.7V to 3.6V) [4]
Parameter
ICC1
Description
Average VCC Current
Test Conditions
tRC = 25 ns
tRC = 35 ns
tRC = 45 ns
Dependent on output loading and cycle rate.
Values obtained without output loads.
IOUT = 0 mA.
Min
Max
Unit
Commercial
65
55
50
mA
mA
Industrial
70
60
55
mA
mA
mA
ICC2
Average VCC Current
during STORE
All Inputs Do Not Care, VCC = Max
Average current for duration tSTORE
3
mA
ICC3
Average VCC Current at WE > (VCC – 0.2V). All other inputs cycling.
tRC= 200 ns, 5V, 25°C Dependent on output loading and cycle rate. Values obtained
without output loads.
Typical
10
mA
ICC4
Average VCAP Current All Inputs Do Not Care, VCC = Max
during AutoStore Cycle Average current for duration tSTORE
3
mA
ISB
VCC Standby Current
CE > (VCC – 0.2V). All others VIN < 0.2V or > (VCC – 0.2V).
Standby current level after nonvolatile cycle is complete.
Inputs are static. f = 0 MHz.
3
mA
IIX
Input Leakage Current
VCC = Max, VSS < VIN < VCC
-1
+1
μA
IOZ
Off State Output
Leakage Current
VCC = Max, VSS < VIN < VCC, CE or OE > VIH or WE < VIL
-1
+1
μA
VIH
Input HIGH Voltage
2.0
VCC +
0.5
V
VIL
Input LOW Voltage
VSS – 0.5
0.8
V
VOH
Output HIGH Voltage
IOUT = –2 mA
VOL
Output LOW Voltage
IOUT = 4 mA
VCAP
Storage Capacitor
Between VCAP pin and Vss, 6V rated.
2.4
17
V
0.4
V
120
uF
Data Retention and Endurance
Min
Unit
DATAR
Parameter
Data Retention at 55°C
Description
20
Years
NVC
Nonvolatile STORE Operations
200
K
Note
4. The HSB pin has IOUT = –10 μA for VOH of 2.4 V. This parameter is characterized but not tested.
Document Number: 001-06422 Rev. *H
Page 7 of 18
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CY14B256L
Capacitance
In the following table, the capacitance parameters are listed.[5]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
Max
Unit
7
pF
7
pF
TA = 25°C, f = 1 MHz,
VCC = 0 to 3.0V
Thermal Resistance
In the following table, the thermal resistance parameters are listed.[5]
Parameter
ΘJA
Description
Thermal Resistance
(Junction to Ambient)
ΘJC
Thermal Resistance
(Junction to Case)
Test Conditions
32-SOIC
48-SSOP
Unit
Test conditions follow standard test methods and
procedures for measuring thermal impedance, per
EIA / JESD51.
42.36
44.26
°C/W
21.41
25.56
°C/W
Figure 4. AC Test Loads
R1 577Ω For Tri-state Specs
R1 577Ω
3.0V
3.0V
Output
Output
30 pF
R2
789Ω
5 pF
R2
789Ω
AC Test Conditions
Input Pulse Levels .................................................... 0V to 3V
Input Rise and Fall Times (10% - 90%)........................ <5 ns
Input and Output Timing Reference Levels .................... 1.5V
Note
5. These parameters are guaranteed by design and are not tested.
Document Number: 001-06422 Rev. *H
Page 8 of 18
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CY14B256L
AC Switching Characteristics
SRAM Read Cycle
Parameter
Cypress
Alt
Parameter
tACE
tELQV
[6]
tAVAV, tELEH
tRC
tAA [7]
tAVQV
tDOE
tGLQV
tAXQX
tOHA [7]
tLZCE [8]
tELQX
tHZCE [8]
tEHQZ
[8]
tGLQX
tLZOE
tHZOE [8]
tGHQZ
tPU [5]
tELICCH
tEHICCL
tPD [5]
25 ns
Description
Min
Chip Enable Access Time
Read Cycle Time
Address Access Time
Output Enable to Data Valid
Output Hold After Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
35 ns
Max
Min
25
45 ns
Max
Min
35
25
45
35
25
12
45
35
15
3
3
45
20
3
3
10
3
3
13
0
15
0
10
0
13
0
15
0
25
Max
0
35
45
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Switching Waveforms
Figure 5. SRAM Read Cycle 1: Address Controlled [6, 7, 9]
W5&
$''5(66
W $$
W2+$
'4 '$7$287
'$7$9$/,'
Figure 6. SRAM Read Cycle 2: CE Controlled [6, 9]
W5&
$''5(66
W$&(
W3'
W/=&(
&(
W+=&(
2(
W+=2(
W'2(
W/=2(
'4 '$7$287
'$7$9$/,'
W 38
,&&
$&7,9(
67$1'%<
Notes
6. WE must be HIGH during SRAM Read cycles.
7. Device is continuously selected with CE and OE both Low.
8. Measured ±200 mV from steady state output voltage.
9. HSB must remain HIGH during SRAM Read and Write Cycles.
Document Number: 001-06422 Rev. *H
Page 9 of 18
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CY14B256L
SRAM Write Cycle
Parameter
Cypress
Alt
Parameter
tWC
tAVAV
tPWE
tWLWH, tWLEH
tELWH, tELEH
tSCE
tDVWH, tDVEH
tSD
tHD
tWHDX, tEHDX
tAVWH, tAVEH
tAW
tAVWL, tAVEL
tSA
tHA
tWHAX, tEHAX
tWLQZ
tHZWE [8,10]
tWHQX
tLZWE [8]
25 ns
Description
Min
Write Cycle Time
Write Pulse Width
Chip Enable To End of Write
Data Setup to End of Write
Data Hold After End of Write
Address Setup to End of Write
Address Setup to Start of Write
Address Hold After End of Write
Write Enable to Output Disable
Output Active After End of Write
35 ns
Max
Min
25
20
20
10
0
20
0
0
45 ns
Max
35
25
25
12
0
25
0
0
10
Min
45
30
30
15
0
30
0
0
13
3
Max
3
15
3
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Switching Waveforms
Figure 7. SRAM Write Cycle 1: WE Controlled [10, 11]
tWC
ADDRESS
tHA
tSCE
CE
tAW
tSA
tPWE
WE
tSD
tHD
DATA VALID
DATA IN
tHZWE
DATA OUT
tLZWE
HIGH IMPEDANCE
PREVIOUS DATA
Figure 8. SRAM Write Cycle 2: CE Controlled [10, 11]
tWC
ADDRESS
CE
WE
tHA
tSCE
tSA
tAW
tPWE
tSD
DATA IN
DATA OUT
tHD
DATA VALID
HIGH IMPEDANCE
Notes
10. If WE is Low when CE goes Low, the outputs remain in the high impedance state.
11. CE or WE must be greater than VIH during address transitions.
Document Number: 001-06422 Rev. *H
Page 10 of 18
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CY14B256L
AutoStore or Power Up RECALL
Parameter
Alt
tHRECALL [12]
tSTORE [13, 14]
VSWITCH
tVCCRISE
tRESTORE
tHLHZ
CY14B256L
Min
Max
20
12.5
2.65
150
Description
Power up RECALL Duration
STORE Cycle Duration
Low Voltage Trigger Level
VCC Rise Time
Unit
ms
ms
V
μs
Switching Waveforms
Figure 9. AutoStore/Power Up RECALL
No STORE occurs
without atleast one
SRAM write
STORE occurs only
if a SRAM write
has happened
VCC
VSWITCH
tVCCRISE
AutoStore
tSTORE
tSTORE
POWER-UP RECALL
tHRECALL
tHRECALL
Read & Write Inhibited
Note Read and Write cycles are ignored during STORE, RECALL, and while Vcc is below VSWITCH
Notes
12. tHRECALL starts from the time VCC rises above VSWITCH.
13. If an SRAM WRITE has not taken place since the last nonvolatile cycle, no STORE will take place.
14. Industrial grade devices requires 15 ms max.
Document Number: 001-06422 Rev. *H
Page 11 of 18
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CY14B256L
Software Controlled STORE/RECALL Cycle
The software controlled STORE/RECALL cycle follows. [15, 16]
Parameter
Alt
Description
25 ns
Min
35 ns
Max
Min
Max
45 ns
Min
Max
Unit
tRC[16]
tAVAV
STORE/RECALL Initiation Cycle Time
25
35
45
ns
tSA
tAVEL
Address Setup Time
0
0
0
ns
tCW
tELEH
Clock Pulse Width
20
25
30
ns
tHA
tGHAX, tELAX
Address Hold Time
1
1
1
ns
RECALL Duration
tRECALL
120
120
120
μs
Switching Waveforms
Figure 10. CE Controlled Software STORE/RECALL Cycle [16]
tRC
tRC
ADDRESS # 1
ADDRESS
tSA
ADDRESS # 6
tSCE
CE
tHA
OE
t STORE / t RECALL
DATA VALID
DATA VALID
DQ (DATA)
HIGH IMPEDANCE
Figure 11. OE Controlled Software STORE/RECALL Cycle [16]
tRC
tRC
ADDRESS # 1
ADDRESS
ADDRESS # 6
CE
tSA
tSCE
OE
tHA
DQ (DATA)
DATA VALID
t STORE / t RECALL
DATA VALID
HIGH IMPEDANCE
Notes
15. The software sequence is clocked on the falling edge of CE controlled READs or OE controlled READs.
16. The six consecutive addresses must be read in the order listed in the Mode Selection table. WE must be HIGH during all six consecutive cycles.
Document Number: 001-06422 Rev. *H
Page 12 of 18
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CY14B256L
Hardware STORE Cycle
Parameter
tPHSB
tDELAY
[17]
Alt
CY14B256L
Description
Min
tHLHX
Hardware STORE Pulse Width
15
tHLQZ , tBLQZ
Time Allowed to Complete SRAM Cycle
1
tss[18, 19]
Soft Sequence Processing Time
Max
Unit
ns
70
μs
70
us
Switching Waveforms
Figure 12. Hardware STORE Cycle
Figure 13. Soft Sequence Processing [18, 19]
6RIW6HTXHQFH
&RPPDQG
$GGUHVV
$GGUHVV
W6$
$GGUHVV
W&:
W66
6RIW6HTXHQFH
&RPPDQG
$GGUHVV
W66
$GGUHVV
W&:
&(
9&&
Notes
17. Read and Write cycles in progress before HSB are given this amount of time to complete.
18. This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register command.
19. Commands such as STORE and RECALL lock out IO until operation is complete which further increases this time. See specific command.
Document Number: 001-06422 Rev. *H
Page 13 of 18
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CY14B256L
Part Numbering Nomenclature
CY 14 B 256 L- SZ 25 X C T
Option:
T-Tape and Reel
Blank - Std.
Temperature:
C - Commercial (0 to 70°C)
I - Industrial (-40 to 85°C)
Pb-Free
Speed:
25 - 25 ns
35 - 35 ns
45 - 45 ns
Package:
SZ - 32-SOIC
SP - 48-SSOP
Data Bus:
L - x8
Density:
256 - 256 Kb
Voltage:
E - 5.0V
nvSRAM
14 - AutoStore + Software Store + Hardware Store
Cypress
Ordering Information
Speed
(ns)
25
35
Ordering Code
CY14B256L-SZ25XCT
Package Diagram
51-85127
Package Type
32-pin SOIC
CY14B256L-SZ25XC
51-85127
32-pin SOIC
CY14B256L-SP25XCT
51-85061
48-pin SSOP
CY14B256L-SP25XC
51-85061
48-pin SSOP
CY14B256L-SZ25XIT
51-85127
32-pin SOIC
CY14B256L-SZ25XI
51-85127
32-pin SOIC
CY14B256L-SP25XIT
51-85061
48-pin SSOP
CY14B256L-SP25XI
51-85061
48-pin SSOP
CY14B256L-SZ35XCT
51-85127
32-pin SOIC
CY14B256L-SZ35XC
51-85127
32-pin SOIC
CY14B256L-SP35XCT
51-85061
48-pin SSOP
CY14B256L-SP35XC
51-85061
48-pin SSOP
CY14B256L-SZ35XIT
51-85127
32-pin SOIC
CY14B256L-SZ35XI
51-85127
32-pin SOIC
CY14B256L-SP35XIT
51-85061
48-pin SSOP
CY14B256L-SP35XI
51-85061
48-pin SSOP
Document Number: 001-06422 Rev. *H
Operating
Range
Commercial
Industrial
Commercial
Industrial
Page 14 of 18
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CY14B256L
Ordering Information
Speed
(ns)
45
Ordering Code
Package Diagram
Operating
Range
Package Type
CY14B256L-SZ45XCT
51-85127
32-pin SOIC
CY14B256L-SZ45XC
51-85127
32-pin SOIC
CY14B256L-SP45XCT
51-85061
48-pin SSOP
CY14B256L-SP45XC
51-85061
48-pin SSOP
CY14B256L-SZ45XIT
51-85127
32-pin SOIC
CY14B256L-SZ45XI
51-85127
32-pin SOIC
CY14B256L-SP45XIT
51-85061
48-pin SSOP
CY14B256L-SP45XI
51-85061
48-pin SSOP
Commercial
Industrial
All parts are Pb-free. The above table contains Final information. Please contact your local Cypress sales representative for availability of these parts
Package Diagrams
Figure 14. 32-Pin (300 Mil) SOIC (51-85127)
PIN 1 ID
16
1
REFERENCE JEDEC MO-119
0.405[10.287]
0.419[10.642]
17
MIN.
MAX.
DIMENSIONS IN INCHES[MM]
0.292[7.416]
0.299[7.594]
PART #
S32.3 STANDARD PKG.
SZ32.3 LEAD FREE PKG.
32
SEATING PLANE
0.810[20.574]
0.822[20.878]
0.090[2.286]
0.100[2.540]
0.004[0.101]
0.050[1.270]
TYP.
0.026[0.660]
0.032[0.812]
0.014[0.355]
0.020[0.508]
Document Number: 001-06422 Rev. *H
0.004[0.101]
0.0100[0.254]
51-85058
0.021[0.533]
0.041[1.041]
*A
0.006[0.152]
0.012[0.304]
51-85127-*A
Page 15 of 18
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CY14B256L
Package Diagrams (continued)
Figure 15. 48-Pin (300 mil) Shrunk Small Outline Package (51-85061)
51-85061-*C
Document Number: 001-06422 Rev. *H
Page 16 of 18
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CY14B256L
Document History Page
Document Title: CY14B256L 256 Kbit (32K x 8) nvSRAM
Document Number: 001-06422
Rev.
ECN No.
Submission
Date
Orig. of
Change
Description of Change
**
425138
See ECN
TUP
New data sheet
*A
437321
See ECN
TUP
Show data sheet on External Web
*B
471966
See ECN
TUP
Changed VIH(min) from 2.2V to 2.0V
Changed tRECALL from 60 μs to 50 μs
Changed Endurance from one million cycles to 500K cycles
Changed Data Retention from 100 years to 20 years
Added Soft Sequence Processing Time Waveform
Updated Part Numbering Nomenclature and Ordering Information
*C
503277
See ECN
PCI
Changed from “Advance” to “Preliminary”
Changed the term “Unlimited” to “Infinite”
Changed endurance from 500K cycles to 200K cycles
Device operation: Tolerance limit changed from + 20% to + 15% in the
Features Section and Operating Range Table
Removed Icc1 values from the DC table for 25 ns and 35 ns industrial grade
Changed VSWITCH(min) from 2.55V to 2.45V
Added temperature specification to data retention - 20 years at 55°C
Changed the max value of Vcap storage capacitor from 120 μF to 57 μF
Updated Part Nomenclature Table and Ordering Information Table
*D
597004
See ECN
TUP
Removed VSWITCH(min) specification from the AutoStore/Power Up RECALL
table
Changed tGLAX specification from 20 ns to 1 ns
Added tDELAY(max) specification of 70 μs in the Hardware STORE Cycle table
Removed tHLBL specification
Changed tSS specification from 70 μs (min) to 70 μs (max)
Changed VCAP(max) from 57 μF to 120 μF
*E
696097
See ECN
VKN
Added footnote 6 related to HSB. Changed tGLAX to tGHAX
*F
1349963
See ECN
SFV
*G
2483006
See ECN
GVCH/PYRS
Changed tolerance from +15%, -10% to +20%, -10%
Changed Operating voltage range from 2.7V-3.45V to 2.7V-3.6V.
*H
2625139
01/30/09
GVCH/PYRS
Updated “features”
Updated WE pin description
Added data retention at 55oC
Added best practices
Added ICC1 spec for 25ns and 35ns access speed for industrial temperate
Updated VIH from Vcc+0.3 to Vcc+0.5
Removed footnote 4 and 5
Added Data retention and Endurance Table
Added Thermal resistance values
Changed parameter tAS to tSA
Changed tRECALL from 50us to 120us (Including tss of 70us)
Renamed tGLAX to tHA
Updated Figure 11 and 12
Renamed tHLHX to tPHSB
Updated Figure 12 and 13
Document Number: 001-06422 Rev. *H
Changed from Preliminary to Final. Updated Ordering Information Table
Page 17 of 18
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CY14B256L
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales
Products
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psoc.cypress.com/solutions
psoc.cypress.com/low-power
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wireless.cypress.com
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psoc.cypress.com/usb
Image Sensors
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© Cypress Semiconductor Corporation, 2006-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-06422 Rev. *H
Revised January 30, 2009
Page 18 of 18
AutoStore and QuantumTrap are registered trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective
holders.
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