Cypress CY2XP304BVC High-frequency programmable pecl clock generation module Datasheet

CY2XP304
High-Frequency Programmable PECL
Clock Generation Module
Features
• HSTL inputs—HSTL-to-LVPECL level translation
• 125- to 500-MHz output range for high-speed
applications
• Period jitter peak-peak 125MHz(max.) = 55 ps
• Four low-skew LVPECL outputs
• High-speed PLL bypass mode to 1.5 GHz
• Phase-locked loop (PLL) multiplier select
• 36-VFBGA, 6 × 8 × 1 mm
• Serially-configurable multiply ratios
• 3.3V operation
• Eight-bit feedback counter and six-bit reference
counter for high accuracy
Block Diagram
CLK0
PLL_MULT
CLK0B
CLK1
XIN
XTAL
OSCILLATOR
XOUT
0
PLL
xM
CLK1B
CLK2
1
SER CLK
CLK2B
CLK3
SER DATA
CLK3B
INA
INAB
CLK_SEL
Pin Configuration
C Y 2 X P 3 0 4 3 6 V F B G A P IN C O N F IG U R A T IO N
C LK 0
C LK 0B
6
5
4
3
2
1
VDDA
GND
GND
S E R_D
A TA
Xo u t
S E R_CL
K
Xi n
VDDB
A
CLK 1
T O P V IE W
C LK 2
CLK 1B
CLK 2B
T O P V IE W
GND
GND
V DDA
GND
V DDB
V DDA
GND
VDDB
NC
GND
VDDA
GND
P LL_M U L
T
CLK _S E
L
IN A
IN A B
VDDA
C
D
E
F
G
H
B
Cypress Semiconductor Corporation
Document #: 38-07589 Rev. *B
C LK 3B
GND
GND
VDDB
CLK 3
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised July 28, 2004
CY2XP304
Pin Definitions
Pin #
Pin Name
A1,B1,G3,G4
VDDB
Pin Description
3.3V Power Supply for Crystal Driver
A2
XIN
A3
XOUT
Reference Crystal Feedback
A4,B2,C1,C3,C4,F3,F4,G2,G5,B5
GND
Ground
A5,H1,H2,H4,H5
VDDA
3.3V Power Supply
A6
CLK0
LVPECL Clock Output
B6
CLK0B
C6
CLK1
D6
CLK1B
E6
CLK2
F6
CLK2B
G6
CLK3
H6
Reference Crystal Input
LVPECL Clock Output (Complement)
LVPECL Clock Output
LVPECL Clock Output (Complement)
LVPECL Clock Output
LVPECL Clock Output (Complement)
LVPECL Clock Output
CLK3B
LVPECL Clock Output (Complement)
B3
SER_CLK Serial Interface Clock
B4
SER_DATA Serial Interface Data
D1
PLL_MULT PLL Multiplier Select Input, Internal pull-up resistor, see Frequency Table
E1
CLK_SEL
F1,G1
INA,INAB
H3
NC
Clock Select Input, Internal Pull down. HIGH select INA/INAB, Internal PLL
is bypassed. LOW select internal PLL
Differential Clock Input pair, used in PLL-bypassed mode
No Connect
Frequency Table
M (PLL Multiplier)
Example Input Crystal Frequency
CLK[0:3],CLKB[0:3]
0
PLL_Mult
x16
25 MHz
400 MHz
31.25 MHz
500 MHz
1
x8
15.625 MHz
125 MHz
CY2XP304 Two-Wire Serial Interface
Introduction
The CY2XP304 has a two-wire serial interface designed for
data transfer operations, and is used for programming the P
and Q values for frequency generation. Sclk is the serial clock
line controlled by the master device. Sdata is a serial bidirectional data line. The CY2XP304 is a slave device and can
either read or write information on the dataline upon request
from the master device.
Figure 1 shows the basic bus connections between master
and slave device. The buses are shared by a number of
devices and are pulled HIGH by a pull-up resistor.
Serial Interface Specifications
Figure 2 shows the basic transmission specification. To begin
and end a transmission, the master device generates a start
signal (S) and a stop signal (P). Start (S) is defined as
switching the Sdata from HIGH to LOW while the Sclk is at
HIGH. Similarly, stop (P) is defined as switching the Sdata from
LOW to HIGH while holding the Sclk HIGH. Between these two
signals, data on Sdata is synchronous with the clock on the Sclk.
Document #: 38-07589 Rev. *B
Data is allowed to change only at LOW period of clock, and
must be stable at the HIGH period of clock. To acknowledge,
drive the Sdata LOW before the Sclk rising edge and hold it
LOW until the Sclk falling edge.
Serial Interface Format
Each slave carries an address. The data transfer is initiated by
a start signal (S). Each transfer segment is one byte in length.
The slave address and the read/write bit are first sent from the
master device after the start signal. The addressed slave
device must acknowledge (Ack) the master device. Depending
on the Read/Write bit, the master device will either write data
into (logic 0) or read data (logic 1) from the slave device. Each
time a byte of data is successfully transferred, the receiving
device must acknowledge. At the end of the transfer, the
master device will generate a stop signal (P).
Serial Interface Transfer Format
Figure 2 shows the serial interface transfer format used with
the CY2XP304. Two dummy bytes must be transferred before
the first data byte. The CY2XP304 has only three bytes of
latches to store information, and the third byte of data is
reserved. Extra data will be ignored.
Page 2 of 11
CY2XP304
Rp
S d a ta
S clk
V DD
Rp
S d ata _ C
S d ata _ C
S c lk _ C
S d ata _ in
S clk _ in
S d ata _ in
S clk _ in
M a s te r D e vic e
S lav e D ev ice
Figure 1. Device Connections
S clk
S data
Start (S)
valid data
Stop (P)
Acknowledge
Figure 2. Serial Interface Specifications
1 bit
7 bits
S
Slave Address
Data 1
1 bit
Ack
8 bits
R/W
1 bit
8 bits
Ack
1 bit
8 bits
1 bit
Ack Dummy Byte 1 Ack
Dummy Byte 0
8 bits
1 bit
Data 0
Ack
P
1 bit
Figure 3. CY2XP304 Transfer Format
Serial Interface Address for the CY2XP304
A6
A5
A4
A3
A2
A1
A0
R/W
1
1
0
0
1
0
1
0
Serial Interface Programming for the CY2XP304
b7
b6
b5
b4
b3
b2
b1
b0
Data0
QCNTBYP
SELPQ
Q<5>
Q<4>
Q<3>
Q<2>
Q<1>
Q<0>
Data1
P<7>
P<6>
P<5>
P<4>
P<3>
P<2>
P<1>
P<0>
Data2
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
To program the CY2XP304 using the two-wire serial interface,
set the SELPQ bit HIGH. The default setting of this bit is LOW.
The P and Q values are determined by the following formulas:
Pfinal = (P7..0 + 3) * 2
Qfinal = Q5..0 + 2
Document #: 38-07589 Rev. *B
If the QCNTBYP bit is set HIGH, then Qfinal defaults to a value
of 1. The default setting of this bit is LOW.
If the SELPQ bit is set LOW, the PLL multipliers will be set
using the values in the Select Function Table.
CyberClocks™ has been developed to generate P and Q
values for stable PLL operation. This software is downloadable
from www.cypress.com.
Page 3 of 11
CY2XP304
PLL Frequency = Reference x P/Q = Output
Reference
Q
Φ
Output
VCO
P
PLL
Figure 4. PLL Block Diagram
Functional Specifications
State Transition Characteristics
Crystal Input
Specifies the maximum settling time of the CLK and CLKB
outputs from device power-up. For VDD and VDDX any
sequences are allowed to power-up and power-down the
CY2XP304.
The CY2XP304 receives its reference from an external crystal.
Pin XIN is the reference crystal input, and pin XOUT is the
reference crystal feedback. The parameters for the crystal are
given on page 5 of this data sheet. The oscillator circuit
requires external capacitors. Please refer to the application
note entitled Crystal Oscillator Topics for details.
Select Input
There are two select input pins, the PLL_MULT and CLK_SEL.
PLL_MULT pin selects the frequency multiplier in the PLL, and
is a standard LVCMOS input. The S pin has an internal pull-up
resistor. The multiplier selection is given on page 2 of this data
sheet (see Frequency Table).
Document #: 38-07589 Rev. *B
State Transition Characteristics
From
To
VDD/VDD CLK/CLK
B Normal
X On
Transition Latency
3 ms
Description
Time from VDD/VDDX is
applied and settled to
CLK/CLKB outputs
settled.
Page 4 of 11
CY2XP304
Absolute Maximum Conditions
Parameter
Description
Condition
Min.
Max.
Unit
VCC
Supply Voltage
Non-functional
–0.3
4.6
V
VCC
Operating Voltage
Functional
3.135
3.465
V
VTT
Output Termination Voltage
Relative to VCC[1]
VIN
Input Voltage
Relative to VCC[1]
–0.3
VCC + 0.3
V
VOUT
Output Voltage
Relative to VCC[1]
–0.3
LUI
Latch Up Immunity
Functional
TS
Temperature, Storage
Non-functional
–65
+150
°C
TA
Temperature, Operating Ambient
Functional
–40
+85
°C
TJ
Temperature, Junction
Non-functional
ØJc
Dissipation, Junction to Case
Functional
11.38
°C/W
ØJa
Dissipation, Junction to Ambient
Functional
85.83
°C/W
ESDh
ESD Protection (Human Body Model)
2000
V
MSL
Moisture Sensitivity Level
3
N.A.
GATES
Total Functional Gate Count
50
Ea.
VCC – 2
V
VCC + 0.3
V
100
–
Assembled die
mA
150
°C
Crystal Requirements
Requirements to use parallel mode fundamental xtal. External
capacitors are required in the crystal oscillator circuit. Please
refer to the application note entitled Crystal Oscillator Topics
for details.
Crystal Requirements
Parameter
XF
Description
Frequency
Min.
Max.
Unit
10
31.25
MHz
Min.
Max.
Unit
DC Electrical Specifications
Parameter
Description
VDD
Supply voltage
3.135
3.465
V
VIL
Input signal low voltage at pin PLL_MULT
–
0.35
V
VIH
Input signal high voltage at pin PLL_MULT
0.65
–
V
RPUP
Internal pull-up resistance
10
100
kΩ
tPU
Power-up time for all VDDs to reach minimum specified voltage
(power ramps must be monotonic)
0.05
500
ms
Min.
Max.
Unit
0
70
°C
–40
85
°C
Operating Conditions
Parameter
TA
Description
Commercial Temperature
Industrial Temperature
Note:
1. Where VCC is 3.3V±5%
Document #: 38-07589 Rev. *B
Page 5 of 11
CY2XP304
DC Specifications (VCC = 3.3 V ± 5%, Commercial and Industrial temp.)
Parameter
Description
Condition
Min.
Max.
Unit
Clock Input Pair INA, INAB (HSTL differential signals)
VDIF
HSTL Differential Input Voltage[2]
0.4
1.9
V
VX
HSTL Differential Crosspoint
Voltage[3]
0.68
0.9
V
IIN
Input Current
|150|
uA
VIN = VX ± 0.2V
PECL Outputs CLK[0:3], CLK[0:3]B (PECL differential signals)
VOL
Output Low Voltage
VCC = 3.3V ± 5%
IOL = –5 mA[4]
VCC – 1.995
VCC – 1.5
V
VOH
Output High Voltage
IOH = –30 mA[4]
VCC – 1.25
VCC – 0.7
V
150
mA
Supply Current and VBB
IEE
Maximum Quiescent Supply Current
without Output Termination Current
CIN
Input Pin Capacitance
LIN
Pin Inductance
INA, INAB
3
pF
1
nH
AC Electrical Specifications–Input
Min.
Max.
Unit
fIN
Parameter
Input frequency with driven reference, crystal inputs
1
133
MHz
fXTAL,IN
Input frequency with crystal input
10
31.25
MHz
fINA_IN
Input Frequency with INA/INAB inputs
0
1500
MHz
pin[5]
–
10
pF
CIN,CMOS
Description
Input capacitance at PLL_MULT
AC Specifications–PECL Clock Outputs CLK[0:3], CLK[0:3]B
Parameter
Description
Min.
Max.
Unit
125
500
MHz
0
1500
MHz
0.375
–
V
VCC – 1.425
V
400-MHz 50% duty cycle Standard load
Differential Operation
–
50
ps
Part-to-part output skew
400-MHz 50% duty cycle Standard load
Differential Operation
–
150
ps
TR,TF
Output Rise / Fall time
400-MHz 50% duty cycle Differential 20%
to 80%
–
0.3
ns
DC
Long-term average output duty
cycle
45
55
%
tDC,ERR
Cycle-cycle duty cycle error at x8
with 15.625-MHz input
–
70
ps
Phase
Noise
Phase Noise at 10 kHz (x8
mode) @ 125 MHz
–107
–92
dBc
BWLOOP
PLL Loop Bandwidth
fO
Output Frequency
Vo(P-P)
Differential output voltage
(peak-to-peak)
VCMRO
Output Common Voltage Range
tsk(O)
Output-to-output skew
tsk(PP)
Conditions
CLK_SEL = 0
CLK_SEL = 1
fO < 1GHz
50
kHz (–3 dB)
Notes:
2. VDIF (DC) is the amplitude of the differential HSTL input voltage swing required for device functionality.
3. VX (DC) is the crosspoint of the differential HSTL input signal. Functional operations is obtained when the crosspoint is within the VX (DC) range and the input
swing lies within the VDIF (DC) specification.
4. Equivalent to a termination of 50Ω to VTT.
5. Capacitance measured at freq. = 1 MHz, DC Bias = 0.9V, and VAC < 100 mV.
Document #: 38-07589 Rev. *B
Page 6 of 11
CY2XP304
AC Specifications–PECL Clock Outputs CLK[0:3], CLK[0:3]B (continued)
Parameter
tJCRMS
tJCPK
tJPRMS
tJPPK
tJLT
tJLT
tJLT
Description
Cycle-to-cycle RMS jitter
Cycle-to-cycle jitter (pk-pk)
Period jitter RMS
Period jitter (pk-pk)
Min.
Max.
Unit
At 125-MHz frequency
Conditions
–
15
ps
At 400-MHz frequency
–
10
ps
At 500-MHz frequency
–
12
ps
At 125-MHz frequency
–
95
ps
At 200-MHz frequency, XF = 25 MHz
–
65
ps
At 400-MHz frequency
–
55
ps
At 500-MHz frequency
–
65
ps
At 125-MHz frequency
–
6.8
ps
At 400-MHz frequency
–
5.6
ps
At 500-MHz frequency
–
6.8
ps
At 125-MHz frequency
–
55
ps
At 200-MHz frequency, XF = 25 MHz
–
50
ps
At 400-MHz frequency
–
45
ps
At 500-MHz frequency
–
50
ps
At 125-MHz frequency
–
25
ps
At 400-MHz frequency
–
20
ps
At 500-MHz frequency
–
25
ps
Long term RMS Jitter (20 < P < 40) At 125-MHz frequency
–
55
ps
At 400-MHz frequency
–
65
ps
Long term RMS Jitter (P < 20)
At 500-MHz frequency
–
55
ps
Long-term RMS Jitter (40 < P < 60) At 125-MHz frequency
–
70
ps
At 400-MHz frequency
–
90
ps
At 500-MHz frequency
–
65
ps
AC Electrical Specifications–PECL Clock Outputs: PLL Bypass Mode
Parameter
Description
Conditions
Vo(P-P)
Differential output voltage (peak-to-peak) Differential PRBS
fo < 1.0 GHz
JP
Period Jitter
660 MHz 50% duty cycle
Standard load
TPD
Propagation delay (INA/INAB to output)
Min
Max
Unit
0.375
–
V
–
1.3
ps r.m.s.
PECL, 660MHz
280
650
ps
HSTL, <1 GHz
280
750
ps
tr, tf,
2 0 -8 0 %
VO
Figure 5. ECL/LVPECL Output
Document #: 38-07589 Rev. *B
Page 7 of 11
CY2XP304
Jitter
This section defines the specifications that relate to timing
uncertainty (or jitter) of the input and output waveforms.
Figure 6 shows the definition of period jitter with respect to the
falling edge of the CLK signal. Period jitter is the difference
between the minimum and maximum cycle times over many
cycles (typically 12800 cycles at 400 MHz). Equal requirements apply for rising edges of the CLK signal. tJP is defined
as the output period jitter.
Figure 7 shows the definition of cycle-to-cycle jitter with
respect to the falling edge of the CLK signal. Cycle-to-cycle
jitter is the difference between cycle times of adjacent cycles
over many cycles (typically 12800 cycles at 400 MHz). Equal
requirements apply for rising edges of the CLK signal. tJC is
defined as the clock output cycle-to-cycle jitter.
Figure 8 shows the definition of cycle-to-cycle duty cycle error.
Cycle-to-cycle duty cycle error is defined as the difference
between high-times of adjacent cycles over many cycles
(typically 12800 cycles at 400 MHz). Equal requirements apply
to the low-times. tDC,ERR is defined as the clock output
cycle-to-cycle duty cycle error.
Figure 9 shows the definition of long-term jitter error.
Long-term jitter is defined as the accumulated timing error over
many cycles (typically 12800 cycles at 400 MHz). It applies to
both rising and falling edges. tJLT is defined as the long-term
jitter.
CLK
CLKB
tCYCLE
tJP = tCYCLE,max – tCYCLE, min. over many cycles
Figure 6. Period Jitter
CLK
CLKB
tCYCLE,i
tCYCLE, i+1
tJC = tCYLCE,i – tCYCLE,i+1 over many consecutive cycles
Figure 7. Cycle-to-cycle Jitter
CLK
Cycle i
Cycle i+1
CLKB
tPW+,i+1
tCYCLE,i+1
tPW+,i
tCYCLE, i+1
tDC,ERR = tPW+,i – tPW+,i+1 over many consecutive cycles
Figure 8. Cycle-to-cycle Duty Cycle Error
CLK
CLKB
tmin
tmax
tJLT = tmax – tmin over many cycles
Figure 9. Long-term Jitter
Document #: 38-07589 Rev. *B
Page 8 of 11
CY2XP304
Test Configurations
Standard test load using a differential pulse generator and
differential measurement instrument.
VTT
DUT
XTAL
OSC
R T = 50 ohm
5"
PLL
Zo = 50 ohm
5"
VTT
R T = 50 ohm
VTT
Pulse
Generator
Z = 50 ohm
Zo = 50 ohm
VTT
CLK_SEL
Figure 10. CY2XP304 AC Test Reference
Applications Information
Termination Examples
1 .3 V
V C C = 3 .3 V
R T = 50 ohm
Zo = 50 ohm
XTAL
R T = 50 ohm
1 .3 V
C lo c k
VEE = 0V
Figure 11. Standard LVPECL–PECL Output Termination
3 .3 V
V C C = 3 .3 V
120 ohm
Zo = 50 ohm
XTAL
LVDS
33 ohm
( 2 p la c e s )
120 ohm
3 .3 V
51 ohm
( 2 p la c e s )
C lo c k
VEE = 0V
L V P E C L to
LVDS
Figure 12. Low-Voltage Positive Emitter-Coupled Logic (LVPECL) to a Low-voltage Differential
Signaling (LVDS) Interface
Document #: 38-07589 Rev. *B
Page 9 of 11
CY2XP304
Ordering Information
Ordering Code
Package Type
Operating Range
CY2XP304BVC
36-lead VFBGA
Commercial, to 400 MHz
Operating Voltage
3.3V
CY2XP304BVCT
36-lead VFBGA – Tape and Reel Commercial, to 400 MHz
3.3V
CY2XP304BVI
36-lead VFBGA
Industrial, to 400 MHz
3.3V
CY2XP304BVIT
36-lead VFBGA – Tape and Reel Industrial, to 400 MHz
3.3V
Package Drawing and Dimensions
36-Lead VFBGA (6 x 8 x 1 mm) BV36A
Dimensions are in mm.
51-85149-*B
CyberClocks is a trademark of Cypress Semiconductor. All product and company names mentioned in this document may be the
trademarks of their respective holders.
Document #: 38-07589 Rev. *B
Page 10 of 11
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY2XP304
Document History Page
Document Title: CY2XP304 High-Frequency Programmable PECL Clock Generation Module
Document Number: 38-07589
REV. ECN NO. Issue Date
Orig. of
Change
Description of Change
**
129898
12/02/03
RGL
New Data Sheet
*A
235868
See ECN
RGL
Updated Jitter spec based on the characterization report
*B
247601
See ECN
RGL/GGK
Document #: 38-07589 Rev. *B
Changed VOH and VOL to match the Char Data
Page 11 of 11
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