STMicroelectronics ETC5067N Serial interface codec/filter with receivepower amplifier Datasheet

ETC5064/64-X
ETC5067/67-X
®
SERIAL INTERFACE CODEC/FILTER WITH RECEIVE
POWER AMPLIFIER
.
..
.
..
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..
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..
COMPLETE CODEC AND FILTERING SYSTEM INCLUDING :
- Transmit high-pass and low-pass filtering.
- Receive low-pass filter with sin x/x correction.
- Active RC noise filter.
- µ-law or A-law compatible CODER and DECODER.
- Internal precision voltage reference.
I/O interface.
- Serial
Internal
auto-zero circuitry.
Receive
push-pull power amplifiers.
µ-LAW ETC5064
A-LAW ETC5067
MEETS OR EXCEEDS ALL D3/D4 AND CCITT
SPECIFICATIONS.
± 5 V OPERATION.
LOW OPERATING POWER-TYPICALLY 70 mW
POWER-DOWN STANDBY MODE-TYPICALLY
3 mW
AUTOMATIC POWER DOWN
TTL OR CMOS COMPATIBLE DIGITAL INTERFACES
MAXIMIZES LINE INTERFACE CARD CIRCUIT DENSITY
0°C TO 70°C OPERATION: ETC5064/67
–40°C TO 85°C OPERATION: ETC5064-X/67-X
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ORDERING NUMBERS:
ETC5064N
ETC5064N-X
ETC5067N
ETC5067N-X
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DESCRIPTION
DIP20
(Plastic) N
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PLCC20
FN
ORDERING NUMBERS:
ETC5064FN
ETC5064FN-X
ETC5067FN
ETC5067FN-X
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The ETC5064 (µ-law), ETC5067 (A-law) are monolithic PCM CODEC/FILTERS utilizing the A/D and
D/A conversion architecture shown in the Block Diagrams and a serial PCM interface. The devices are
fabricated using double-poly CMOS process.
Similar to the ETC505X family, these devices feature an additional Receive Power Amplifier to provide push-pull balanced output drive capability. The
receive gain can be adjusted by means of two external resistors for an output level of up to ± 6.6 V
across a balanced 600Ω load.
Also included is an Analog Loopback switch and
TSX output.
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September 2003
SO20
D
ORDERING NUMBERS:
ETC5064D
ETC5064D-X
ETC5067D
ETC5067D-X
1/18
ETC5064 - ETC5064-X - ETC5067 - ETC5067-X
PIN CONNECTIONS (Top views)
DIP20 &
SO20
PLCC20
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BLOCK DIAGRAM (ETC5064 - ETC5064-X - ETC5067 - ETC5067-X)
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2/18
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ETC5064 - ETC5064-X - ETC5067 - ETC5067-X
PIN DESCRIPTION
Pin
Type (*)
Name
+
N
Description
O
1
The Non-inverting Output of the Receive Power Amplifier
GND
2
Analog Ground. All signals are referenced to this pin.
VPOVPI
O
3
The Inverting Output of the Receive Power Amplifier
I
4
Inverting Input to the Receive Power Amplifier. Also powers down both
amplifiers when connected to VBB.
VFRO
O
5
Analog Output of the Receive Filter.
VCC
S
6
Positive Power Supply Pin. VCC = +5V ±5%
FSR
I
7
Receive Frame Sync Pulse which enable BCLKR to shift PCM data into
DR. FSR is an 8KHz pulse train. See figures 1 and 2 for timing details.
DR
I
8
Receive Data Input. PCM data is shifted into DR following the FSR leading
edge
BCLKR/CLKSEL
I
9
The bit Clock which shifts data into DR after the FSR leading edge. May
vary from 64KHz to 2.048MHz.
Alternatively, may be a logic input which selects either 1.536MHz/1.544MHz
or 2.048MHz for master clock in synchronous mode and BCLK X is used
for both transmit and receive directions (see table 1). This input has an
internal pull-up.
VPO
GNDA
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MCKLR/PDN
I
10
Receive Master Clock. Must be 1.536MHz, 1.544MHz or 2.048MHz. May
be asynchronous with MCLKX, but should be synchronous with MCLKX for
best performance. When MCLKR is connected continuously low, MCLKX is
selected for all internal timing. When MCLKR is connected continuously
high, the device is powered down.
MCLKX
I
11
Transmit Master Clock. Must be 1.536MHz, 1.544MHz or 2.048MHz. May
be asynchronous with MCLKR.
BCLKX
I
12
The bit clock which shifts out the PCM data on DX. May vary from 64KHz
to 2.048MHz, but must be synchronous with MCLKX.
DX
O
13
FSX
I
14
The TRI-STATEPCM data output which is enabled by FSX.
Transmit frame sync pulse input which enables BCLKX to shift out the
PCM data on DX. FSX is an 8KHz pulse train. See figures 1 and 2 for
timing details.
TSX
O
15
ANLB
I
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VFXI+
VBB
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GSX
VFXI-
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Open drain output which pulses low during the encoder time slot. Must to
be grounded if not used.
Analog Loopback Control Input. Must be set to logic ’0’ for normal
operation. When pulled to logic ’1’, the transmit filter input is disconnected
from the output of the transmit preamplifier and connected to the VPO +
output of the receive power amplifier.
O
I
17
18
Analog output of the transmit input amplifier. Used to set gain externally.
Inverting input of the transmit input amplifier.
I
S
19
20
Negative Power Supply Pin. VBB = -5V ±5%
Non-inverting input of the transmit input amplifier.
(*) I: Input, O: Output, S: Power Supply.
TRI-STATE is a trademark of National Semiconductor Corp.
3/18
ETC5064 - ETC5064-X - ETC5067 - ETC5067-X
FUNCTIONAL DESCRIPTION
POWER-UP
When power is first applied, power-on reset circuitry
initializes the device and places it into the powerdown mode. All non-essential circuits are deactivated and the DX and VFRO outputs are put in high
impedance states. To power-up the device, a logical
low level or clock must be applied to the
MCLKR/PDN pin and FSX and/or FSR pulses must
be present. Thus 2 power-down control modes are
available. The first is to pull the MCLKR/PDN pin
high; the alternative is to hold both FSX and FSR inputs continuously low. The device will power-down
approximately 2 ms after the last FSX pulse. The
TRI-STATE PCM data output, DX, will remain in the
high impedance state until the second FSX pulse.
SYNCHRONOUS OPERATION
For synchronous operation, the same master clock
and bit clock should be used for both the transmit
and receive directions. In this mode, a clock must be
applied to MCLKX and the MCLKR/PDN pin can be
used as a power-down control. A low level on
MCLKR/PDN powers up the device and a high level
powers down the device. In either case, MCLKX will
be selected as the master clock for both the transmit
and receive circuits. A bit clock must also be applied
to BCLKX and the BCLR/CLKSEL can be used to select the proper internal divider for a master clock of
1.536 MHz, 1.544 MHz or 2.048 MHz. For 1.544
MHz operation, the device automatically compensates for the 193 rd clock pulse each frame.
With a fixed level on the BCLKR/CKSEL pin, BCLKX
will be selected as the bit clock for both the transmit
and receive directions. Table 1 indicates the frequencies of operation which can be selected, depending on the state of BCLKR/CLKSEL. In this synchronous mode, the bit clock, BCLKX, may be from
64 kHz to 2.048 MHz, but must be synchronous with
MCLKX.
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Table 1: Selection of Master Clock Frequencies.
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BCLKR/CLKSEL
Clocked
0
1 (or open circuit)
4/18
ASYNCHRONOUS OPERATION
For asynchronous operation, separate transmit and
receive clocks may be applied. MCLKX and MCLKR
must be 2.048 MHz for the ETC5067 or 1.536 MHz,
1.544 MHz for the ETC5064, and need not be synchronous. For best transmission performance, however, MCLKR should be synchronous with MCLKX,
which is easily achieved by applying only static logic
levels to the MCLKR/PDN pin. This will automatically
connect MCLKX to all internal MCLKR functions (see
pin description). For 1.544 MHz operation, the device automatically compensates for the 193rd clock
pulse each frame. FSX starts each encoding cycle
and must be synchronous with MCLKX and BCLKX.
FSR starts each decoding cycle and must be synchronous with BCLKR. BCLKR must be a clock, the
logic levels shown in Table 1 are not valid in asynchronous mode. BCLKX and BCLKR may operate
from 64kHz to 2.048 MHz.
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Each FSX pulse begins the encoding cycle and the
PCM data from the previous encode cycle is shift out
of the enabled DX output on the positive edge of
BCLKX. After 8 bit clock periods, the TRISTATE DX
output is returned to a high impedance state. With an
FSR pulse, PCM data is latched via the DR input on
the negative edge of BCLKX (or on BCKLR if running).
FSX and FSR must be synchronous with MCLKX/R.
Master Clock
Frequency Selected
ETC5067
ETC5067-X
ETC5064
ETC5064-X
2.048MHz
1.536MHz or
1.544MHz
1.536MHz or
1.544MHz
2.048MHz
2.048MHz
1.536MHz or
1.544MHz
SHORT FRAME SYNC OPERATION
The device can utilize either a short frame sync
pulse or a long frame sync pulse. Upon power initialization, the device assumes a short frame mode. In
this mode, both frame sync pulses. FSX and FSR,
must be one bit clock period long, with timing relationships specified in figure 2. With FSX high during
a falling edge of BCLKR, the next rising edge of
BCLKX enables the DX TRI-STATE output buffer,
which will output the sign bit. The following seven rising edges clock out the remaining seven bits, and
the next falling edge disables the DX output. With
FSR high during a falling edge of BCLKR (BCLKX in
synchronous mode), the next falling edge of BCLKR
latches in the sign bit. The following seven falling
edges latch in the seven remaining bits. Both devices may utilize the short frame sync pulse in synchronous or asynchronous operating mode.
LONG FRAME SYNC OPERATION
To use the long frame mode, both the frame sync
pulses, FSX and FSR, must be three or more bit clock
periods long, with timing relationships specified in
figure 3. Based on the transmit frame sync FSX, the
device will sense whether short or long frame sync
ETC5064 - ETC5064-X - ETC5067 - ETC5067-X
pulses are being used. For 64 kHz operation, the
frame sync pulses must be kept low for a minimum
of 160 ns (see Fig 1). The DX TRI-STATE output
buffer is enabled with the rising edge of FSX or the
rising edge of BCLKX, whichever comes later, and
the first bit clocked out is the sign bit. The following
seven BCLKX rising edges clock out the remaining
seven bits. The DX output is disabled by the falling
BCLKX edge following the eighth rising edge, or by
FSX going low, whichever comes later. A rising edge
on the receive frame sync pulse, FSR, will cause the
PCM data at DR to be latched in on the next eight
falling edges of BCLKR (BCLKx in synchronous
mode). Both devices may utilize the long frame sync
pulse in synchronous or asynchronous mode.
TRANSMIT SECTION
The transmit section input is an operational amplifier
with provision for gain adjustment using two external
resistors, see figure 4. The low noise and wide bandwidth allow gains in excess of 20 dB across the
audio passband to be realized. The op amp drives
a unity gain filter consisting of RC active pre-filter,
followed by an eighth order switched-capacitor
bandpass filter directly drives the encoder sampleand-hold circuit. The A/D is of companding type according to A-law (ETC5067 and ETC5067-X) or µlaw (ETC5064 and ETC5064-X) coding conventions. A precision voltage reference is trimmed in
manufacturing to provide an input over load (tMAX)
of nominally 2.5V peak (see table of Transmission
Characteristics). The FSX frame sync pulse controls
the sampling of the filer output, and then the successive-approximation encoding cycle begins. The 8-bit
code is then loaded into a buffer and shifted out
through DX at the next FSX pulse. the total encoding
delay will be approximately 165 µs (due to the transmit filter) plus 125µs (due to encoding delay), which
totals 290µs. Any offset voltage due to the filters or
comparator is cancelled by sign bit integration.
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RECEIVE POWER AMPLIFIERS
Two inverting mode power amplifiers are provided
for directly driving a matched line interface transformer. The gain of the first power amplifier can be
adjusted to boost the ± 2.5V peak output signal from
the receive filter up ± 3.3V peak into an unbalanced
300Ω load, or ±4.0V into an unbalanced 15kΩ load.
The second power amplifier is internally connected
in unity-gain inverting mode to give 6dB of signal
gain for balanced loads. Maximum power transfer to
a 600Ω subscriber line termination is obtained by
differientially driving a balanced transformer with a
2 : 1 turns ratio, as shown in figure 4. A total peak
√
power of 15.6dBm can be delivered to the load plus
termination. Both power amplifier can be powered
down independently from the PDN input by connecting the VPI input to VBB saving approximately 12
mW of power.
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RECEIVE SECTION
The receive section consist of an expanding DAC
which drives a fifth order switched-capacitor low
pass filter clocked at 256kHz. The decoder is A-law
(ETC5067 and ETC5067-X) or µ–law (ETC5064
and ETC5064-X) and the 5 th order low pass filter
corrects for the sin x/x attenuation due to the 8kHz
sample and hold. The filter is then followed by a 2
nd order RC active post-filter and power amplifier
capable of driving a 600Ω load to a level of 7.2dBm.
The receive section is unity-gain. Upon the occurence of FSR, the data at the DR input is clocked
in on the falling edge of the next eight BCLKR
(BCKLX) periods. At the end of the decoder time slot,
the decoding cycle begins, and 10µs later the decoder DAC output is updated. The total decoder delay is about10µs (decoder up-date) plus 110µs (filter delay) plus 62.5µs (1/2 frame), which gives approximately 180µs.
ABSOLUTE MAXIMUM RATINGS
bs
Symbol
O
VCC
VBB
VIN, VOUT
Parameter
VCC to GNDA
VBB to GNDA
Voltage at any Analog Input or Output
Toper
Voltage at any Digital Input or Output
Operating Temperature Range: ETC5064/67
ETC5064-X/67-X
Tstg
Storage Temperature Range
Lead Temperature (soldering, 10 seconds)
Value
Unit
7
V
-7
VCC +0.3 to VBB -0.3
V
V
VCC +0.3 to GNDA -0.3
-25 to +125
-40 to +125
V
°C
°C
-65 to +150
°C
300
°C
5/18
ETC5064 - ETC5064-X - ETC5067 - ETC5067-X
ELECTRICAL OPERATING CHARACTERISTICS
VCC = 5.0V ±5%, VBB = -5V ±5%, GNDA = 0V, TA = 0°C to 70°C (ETC5064-X/67-X: TA = –40°C to 85°), unless
otherwise noted; typical characteristics specified at VCC = 5.0V, VBB =-5.0V, TA = 25°C; all signals are referenced to GNDA.
DIGITAL INTERFACE (All devices)
Symbol
Parameter
Min.
VIL
VIH
Input Low Voltage
VOL
Output Low Voltage
IL = 3.2 mA
IL = 3.2 mA, Open Drain
DX
TSX
Output High Voltage
IH = 3.2 mA
DX
VOH
Input High Voltage
Typ.
Max.
0.6
2.2
Unit
V
V
0.4
0.4
V
V
2.4
V
IIL
Input Low Current (GNDA ≤ VIN ≤ VIL )all digital inputs
Except BCLKR
– 10
10
µA
IIH
Input High Current (VIH ≤ VIN ≤ VCC) Except ANLB
– 10
10
µA
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ANALOG INTERFACE WITH TRANSMIT INPUT AMPLIFIER (all devices)
Symbol
IIXA
RIXA
Parameter
VFxI + or VFxI –
Input Leakage Current
(– 2.5 V ≤ V ≤ + 2.5 V)
ROXA
Input Resistance
(– 2.5 V ≤ V ≤ + 2.5 V)
Output Resistance (closed loop, unity gain)
RLXA
Load Resistance
CLXA
Load Capacitance
VOXA
AVXA
Output Dynamic Range (RL ≥ 10 kΩ)
Voltage Gain (VFXI + to GSX)
FUXA
Unity Gain Bandwidth
VOSXA
VCMXA
CMRRXA
PSRRXA
Offset Voltage
Common-mode Voltage
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VFXI + or VFXI –
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GSX
Typ.
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GSX
Max.
200
10
1
3
5000
pF
V
V/V
2
– 20
– 2.5
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Ω
kΩ
50
+2.8
– 2.8
1
Unit
nA
MΩ
10
GSX
Common-mode Rejection Ratio
Power Supply Rejection Ratio
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– 200
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20
2.5
60
60
mV
V
dB
dB
ANALOG INTERFACE WITH RECEIVE FILTER (all devices)
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Symbol
RORF
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Parameter
Output Resistance
RLRF
Load Resistance (VFRO = ± 2.5 V)
CLRF
Load Capacitance
VOSRO
6/18
Output DC Offset Voltage
Min.
VF RO
Typ.
1
Max.
3
10
– 200
Unit
Ω
25
kΩ
pF
200
mV
ETC5064 - ETC5064-X - ETC5067 - ETC5067-X
ELECTRICAL OPERATING CHARACTERISTICS (Continued)
ANALOG INTERFACE WITH POWER AMPLIFIERS (all devices)
Symbol
IPI
Parameter
Min.
Input Leakage Current (– 1.0 V ≤ VPI ≤ 1.0 V)
RIPI
Input Resistance (– 1.0 ≤ VPI ≤ 1.0 V)
VIOS
ROP
Input Offset Voltage
Output Resistance (inverting unity–gain at VPO + or VPO –)
FC
CL P
Unity–gain Bandwidth, Open Loop (VPO –)
GAp +
PSRRp
Typ.
– 100
Unit
100
nA
10
MΩ
– 25
25
mV
Ω
kHz
pF
1
400
Load Capacitance (VPO + or VPO – to GNDA)
RL ≥ 1500 Ω
RL = 600 Ω
RL = 300 Ω
100
500
1000
Gain VPO – to VPO + to GNDA, Level at VPO – = 1. 77 Vrms
(+ 3 dBmO)
–1
V/V
dB
Power Supply Rejection of VCC or VBB
(VPO– connected to VPI)
0 kHz – 4 kHz
0 kHz – 50 kHz
60
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POWER DISSIPATION (all devices)
Symbol
ICC0
Parameter
Power-down Current at ETC6064/67
ETC5064-X/67-X
IBB0
Power-down Current at ETC6064/67
ETC5064-X/67-X
ICC1
Active Current at ETC6064/67
ETC5064-X/67-X
IBB1
Active Current at ETC6064/67
ETC5064-X/67-X
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Max.
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Min.
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Typ.
0.5
0.5
Max.
1.5
Unit
mA
mA
0.05
0.05
7.0
7.0
0.3
0.4
10.0
12.0
mA
mA
mA
mA
7.0
7.0
10.0
12.0
mA
mA
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7/18
ETC5064 - ETC5064-X - ETC5067 - ETC5067-X
All TIMING SPECIFICATIONS
Symbol
1/tPM
tWMH
tWML
tRM
tFM
tPB
tWBH
tWBL
tRB
tFB
Parameter
Frequency of master clocks
MCLKX and MCLKR
Depends on the device used and the
BCLKR/CLKSEL Pin
Width of Master Clock High
Min.
MCLKX and MCLKR
160
Width of Master Clock Low
Rise Time of Master Clock
MCLKX and MCLKR
MCLKX and MCLKR
160
Fall Time of Master Clock
MCLKX and MCLKR
Period of Bit Clock
485
Width of Bit Clock High (VIH = 2.2 V)
Width of Bit Clock Low (VIL = 0.6 V)
160
160
ns
488
Holding Time from Bit Clock Low to the Frame Sync
(long frame only)
0
tSFB
Set-up Time from Frame Sync to Bit Clock (long frame only)
Hold Time from 3rd Period of Bit Clock
FSX or FSR
Low to Frame Sync (long frame only)
Delay Time to valid data from FSX or BCLKX, whichever
comes later and delay time from FSX to data output disabled
(CL = 0 pF to 150 pF)
Delay Time from BCLKX high to data valid
(load = 150 pF plus 2 LSTTL loads)
80
ns
ns
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-
ns
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100
ns
ns
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s
t(
ns
ns
ns
20
165
ns
0
150
ns
165
ns
tDZC
Delay Time from BCLKX low to data output disabled
50
tSDB
Set-up Time from DR valid to BCLKR/X low
Hold Time from BCLKR/X low to DR invalid
50
50
ns
ns
Holding Time from Bit Clock High to Frame Sync (short frame only)
Set-up Time from FSX/R to BCLKX/R Low
(short frame sync pulse) - Note 1
0
80
ns
ns
tHF
Hold Time from BCLKX/R Low to FSX/R Low
(short frame sync pulse) - Note 1
100
ns
tXDP
Delay Time to TSX low (load = 150 pF plus 2 LSTTI loads)
Minimum Width of the Frame Sync Pulse (low level)
(64 bit/s operating mode)
tHBD
tHOLD
tSF
tWFL
(s)
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140
160
Note : 1.For short frame sync timing. FSX and FS R must go high while their respective bit clocks are high.
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Figure 1 : 64 k bits/s TIMING DIAGRAM. (see next page for complete timing)
8/18
50
15.725
50
50
tHBF
ns
ns
ns
ns
Rise Time of Bit Clock (tPB = 488 ns)
Fall Time of Bit Clock (tPB = 488 ns)
100
tDBD
Unit
MHz
50
Set-up time from BCLKX high to MCLKX falling edge.
(first bit clock after the leading edge of FSX)
tDZF
Max.
1.544
tSBFM
tHBFI
Typ.
1.536
2.048
ns
ns
ETC5064 - ETC5064-X - ETC5067 - ETC5067-X
Figure 2 : Short Frame Sync Timing.
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9/18
ETC5064 - ETC5064-X - ETC5067 - ETC5067-X
Figure 3 : Long Frame Sync Timing.
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10/18
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ETC5064 - ETC5064-X - ETC5067 - ETC5067-X
TRANSMISSION CHARACTERISTICS
(all devices) TA = 0°C to 70°C (ETC5064-X/67-X: TA = –40°C to 85°), VCC = 5V ± 5%, VBB = – 5V ± 5%,
GNDA = 0V, f = 1.02kHz, VIN = 0dBm0 transmit input amplifier connected for unity–gain non–inverting. (unless
otherwise specified).
AMPLITUDE RESPONSE
Symbol
Parameter
Min.
Absolute Levels - Nominal 0 dBm0 is 4 dBm (600Ω).
0 dBm0
Typ.
tMAX
Max Overload Level
3.14 dBm0
3.17 dBm0
ETC5067
ETC5064
GXA
Transmit Gain, Absolute (TA = 25°C, VCC = 5V, VBB = -5V)
Input at GSX = 0dBm0 at 1020Hz
GXR
Transmit Gain, Relative to GXA
f = 16Hz
f = 50Hz
f = 60Hz
f = 180Hz
f = 200Hz
f = 300Hz -3000Hz
f = 3200Hz (ETC5064-X/67-X)
f = 3300Hz
f = 3400Hz
f = 4000Hz
f = 4600Hz and up, measure response from oHz to 4000Hz
GXAT
Absolute Transmit Gain Variation with Temperature
TA = 0°C to +70°C
TA = –40°C to +85°C (ETC5064-X/67-X)
VPK
0.15
dB
-2.8
-1.8
-0.15
-0.35
-0.35
-0.7
-40
-30
-26
-0.2
-0.1
0.15
0.20
0.05
0
-14
-32
dB
d
o
r
uc
)
s
t(
dB
0.05
dB
-0.2
-0.4
-1.2
0.2
0.4
1.2
dB
-0.15
0.15
dB
-0.15
-0.35
-0.35
-0.7
0.15
0.20
0.05
0
-14
-0.1
-0.15
0.1
0.15
dB
-0.05
0.05
dB
Receive Gain Variation with Level
Sinusoidal Test Method; Reference Input PCM code
corresponds to an ideally encoded -10dBm0 signal
PCM level = -40dBm0 to +3dBm0
PCM level = -50dBm0 to -40dBm0
PCM level = -55dBm0 to -50dBm0
-0.2
-0.4
-1.2
0.2
0.4
1.2
dB
Receive Filter Output at VFRO RL = 10KΩ
-2.5
2.5
V
c
u
d
(t s)
GRA
Receive Gain, Absolute (TA = 25°C, VCC = 5V, VBB = -5V)
Input = Digital Code Sequence for 0dBm0 Signal at 1020Hz
GRR
Receive Gain, Relative to GRA
f = 0Hz to 3000Hz
f = 3200Hz (ETC5064-X/67-X)
f = 3300Hz
f = 3400Hz
f = 4000Hz
o
r
P
e
t
e
l
o
VRO
2.492
2.501
-0.05
Transmit Gain Variation with Level
Sinusolidal Test Method Reference Level = -10dBm0
VFXI+ = -40dBm0 to +3dBm0
VFXI+ = -50dBm0 to -40dBm0
VFXI+ = -55dBm0 to -50dBm0
GRRL
Vrms
-0.15
P
e
let
o
s
b
O
-
GXRL
GRAV
1.2276
0.1
0.15
Absolute Transmit Gain Variation with Supply Voltage
(VCC = 5V ±5%, VBB = -5V ±5%)
GRAT
Unit
-0.1
-0.15
GXAV
s
b
O
Max.
Absolute Receive Gain Variation with Temeperature
TA = 0°C to +70°C
TA = –40°C to +85°C (ETC5064-X/67-X)
Absolute Receive Gain Variation with Supply Voltage
(VCC = 5V ±5%, VBB = -5V ±5%)
dB
11/18
ETC5064 - ETC5064-X - ETC5067 - ETC5067-X
TRANSMISSION CHARACTERISTICS (continued).
ENVELOPE DELAY DISTORTION WITH FREQUENCY
Symbol
Typ.
Max.
Unit
DXA
Transmit Delay, Absolute (f = 1600 Hz)
Parameter
Min.
290
315
µs
DXR
Transmit Delay, Relative to DXA
f = 500 Hz-600 Hz
f = 600 Hz-800 Hz
f = 800 Hz-1000 Hz
f = 1000 Hz-1600 Hz
f = 1600 Hz-2600Hz
f = 2600 Hz-2800 Hz
f = 2800 Hz-3000 Hz
195
120
50
20
55
80
130
220
145
75
40
75
105
155
DRA
Receive Delay, Absolute (f = 1600 Hz)
180
200
DRR
Receive Delay, Relative to DRA
f = 500 Hz-1000 Hz
f = 1000 Hz-1600 Hz
f = 1600 Hz-2600 Hz
f = 2600 Hz-2800 Hz
f = 2800 Hz-3000 Hz
– 25
– 20
70
100
145
90
125
175
– 40
– 30
c
u
d
NOISE
Symbol
NXP
NRP
NXC
NRC
NRS
PPSRX
NPSRX
PPSRR
Parameter
Transmit Noise, P Message (A-LAW, VFXI + = 0 V) Weighted 1)
ETC5064
ETC5064-X
Receive Noise, P Message Weighted
(A-LAW, PCM Code Equals Positive Zero)
Transmit Noise, C Message Weighted
(µ-LAW, VFxI + = 0 V)
e
t
le
o
s
b
O
-
ETC5064
ETC5064-X
Receive Noise, C Message Weighted
(µ-LAW, PCM Code Equals Alternating Positive and Negative Zero)
Noise, Single Frequency
f = 0 kHz to 100 kHz, Loop around Measurement, VFXI + = 0 V
(s)
t
c
u
Positive Power Supply Rejection, Transmit (note 2)
VCC = 5.0 VDC + 100 mVrms, f = 0 kHz-50 kHz
Negative Power Supply Rejection, Transmit (note 2)
VBB = 5.0 VDC + 100 mVrms, f = 0 kHz-50 kHz
d
o
r
P
e
Positive Power Supply Rejection, Receive (PCM code equals
positive zero, VCC = 5.0 VDC + 100 mVrms)
f = 0 Hz-4000Hz
A LAW
µ LAW
f = 4 kHz-25 kHz
f = 25 kHz-50 kHz
t
e
l
o
s
b
O
NPSRR
SOS
12/18
o
r
P
Min.
Negative Power Supply Rejection, Receive (PCM code equals
positive zero, VBB = – 5.0 VDC + 100 mVrms)
f = 0 Hz-4000Hz
A LAW
µ LAW
f = 4 kHz-25 kHz
f = 25 kHz-50 kHz
Spurious out-of-band Signals at the Channel Output
0 dBm0, 300 Hz-3400 Hz input PCM applied at DR
4600 Hz-7600 Hz
7600 Hz-8400 Hz
8400 Hz-100,000 Hz
µs
µs
µs
)
s
t(
Typ.
Max.
Unit
– 74
– 74
– 82
– 69
– 67
– 79
dBm0p
dBm0p
dBm0p
12
12
15
16
dBrnC0
dBrnC0
11
dBrnC0
– 53
dBm0
8
40
dBp
40
dBp
40
40
40
36
dBp
dBc
dB
dB
40
40
40
36
dBp
dBc
dB
dB
–32
–40
–32
dB
dB
dB
ETC5064 - ETC5064-X - ETC5067 - ETC5067-X
TRANSMISSION CHARACTERISTICS (continued).
DISTORTION
Symbol
STDX
or
STDR
Parameter
Signal to Total Distortion (sinusoidal test method)
Min.
Transmit or Receive Half-channel
Level = 3.0 dBm0
= 0 dBm0 to – 30 dBm0
= – 40 dBm0
XMT
RCV
XMT
RCV
= – 55 dBm0
SFDX
SFDR
IMD
Typ.
CTR-X
dBc
(µLAW)
Single Frequency Distortion, Transmit (TA = 25°C)
– 46
dB
Single Frequency Distortion, Receive (TA = 25°C)
– 46
dB
Intermodulation Distortion
Loop Around Measurement, VFXI + = – 4 dBm0 to
– 21 dBm0, two Frequencies in the Range 300 Hz-3400 Hz
– 41
dB
Parameter
Transmit to Receive Crosstalk, 0dBm0 Transmit
f = 300 Hz-3400 Hz, DR = Steady PCM Code ETC5064/67
ETC5064-X/67-X
e
t
le
Receive to Transmit Crosstalk, 0dBm0 Receive Level (note 2)
f = 300 Hz-3400 Hz, VFXI = 0 V
ETC5064/67
ETC5064-X/67-X
)
s
(
ct
POWER AMPLIFIERS
Symbol
VOL
s
b
O
Notes :
Min.
c
u
d
Parameter
Min.
Maximum 0 dBm0 Level for Better than ± 0.1 dB Linearity Over
the Range 10 dBm0 to + 3 dBm0
(balanced load, RL connected between VPO + and VPO –)
RL = 600 Ω
RL = 1200 Ω
RL = 30 kΩ
33
3.5
4.0
Signal/Distortion RL = 600 Ω, 0 dBm0
50
u
d
o
r
P
e
)
s
t(
Typ.
Max.
Unit
– 90
– 75
– 65
dB
dB
– 90
– 70
– 65
dB
dB
Typ.
Max.
Unit
Vrms
o
r
P
o
s
b
O
-
t
e
l
o
S/DP
Unit
dBp
(ALAW)
33
36
29
30
14
15
CROSSTALK
Symbol
CTX-R
Max.
dB
1. Measured by extrapolation from the distortion test results.
2. PPSRX, NPSRX, CTR–X measured with a –50dBm0 activating signal applied at VFXI +
ENCODING FORMAT AT DX OUTPUT
VIN (at GSX) = + Full-scale
VIN (at GSX) = 0 V
VIN (at GSX) = – Full-scale
µLaw
A-Law
(Including even bit inversion)
1 0 1 0 1 0 1 0
1 1 0 1 0 1 0 1
0 1 0 1 0 1 0 1
1 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
0 1 1 1 1 1 1 1
0 0 1 0 1 0 1 0
0 0 0 0 0 0 0 0
13/18
ETC5064 - ETC5064-X - ETC5067 - ETC5067-X
APPLICATION INFORMATION
Figure 4 : Typical Asynchronous Application.
POWER SUPPLIES
While the pins at the ETC506X family are well protected against electrical misure, it is recommended
that the standard CMOS practice be followed, ensuring that ground is connected to the device before
any other connections are made. In applications
where the printed circuit board may be plugged into
a "hot" socket with power and clocks already present, an extra long ground pin in the connector
should be used.
All ground connections to each device should meet
at a common point as close as possible to the GNDA
pin. This minimizes the interaction of ground return
currents flowing through a common bus impedance.
0.1µF supply decoupling capacitors should be connected from this common ground point to VCC and
VBB as close to the device as possible.
For best performance, the ground point of each
CODEC/FILTER on a card should be connected to
a common card ground in star formation, rather than
via a ground bus. This common ground point should
be decoupled to VCC and VBB with 10µF capacitors.
)
s
(
ct
u
d
o
r
P
e
t
e
l
o
s
b
O
14/18
c
u
d
o
s
b
O
-
e
t
le
o
r
P
)
s
t(
ETC5064 - ETC5064-X - ETC5067 - ETC5067-X
mm
inch
OUTLINE AND
MECHANICAL DATA
DIM.
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
A
2.35
2.65
0.093
0.104
A1
0.1
0.3
0.004
0.012
B
0.33
0.51
0.013
0.020
C
0.23
0.32
0.009
0.013
D
12.6
13
0.496
0.512
E
7.4
7.6
0.291
0.299
e
1.27
0.050
H
10
10.65
0.394
0.419
h
0.25
0.75
0.010
0.030
L
0.4
1.27
0.016
0.050
K
c
u
d
e
t
le
0˚ (min.)8˚ (max.)
(s)
t
c
u
d
o
r
P
e
B
s
b
O
t
e
l
o
o
s
b
O
-
L
)
s
t(
o
r
P
SO20
h x 45˚
A
e
A1
K
C
H
D
20
11
E
1
0
1
SO20MEC
15/18
ETC5064 - ETC5064-X - ETC5067 - ETC5067-X
mm
inch
OUTLINE AND
MECHANICAL DATA
DIM.
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
A
9.78
10.03
0.385
0.395
B
8.89
9.04
0.350
0.356
D
4.2
4.57
0.165
0.180
d1
2.54
0.100
d2
0.56
0.022
E
7.37
8.38
0.290
0.330
e
1.27
0.050
F
0.38
0.015
G
0.101
M
1.27
0.050
M1
1.14
0.045
e
t
le
)
s
(
ct
M1
t
e
l
o
bs
4
o
r
P
e
M1
du
2
1
20
o
s
b
O
18
M
F
17
6
16
7
15
e
8
O
M
19
5
9
o
r
P
PLCC20
B
3
c
u
d
0.004
10
11
A
12
E
14
13
d2
d1
PLCC20ME
16/18
)
s
t(
G (Seating Plane Coplanarity)
D
ETC5064 - ETC5064-X - ETC5067 - ETC5067-X
mm
DIM.
MIN.
a1
0.254
B
1.39
TYP.
inch
MAX.
MIN.
TYP.
MAX.
OUTLINE AND
MECHANICAL DATA
0.010
1.65
0.055
0.065
b
0.45
0.018
b1
0.25
0.010
D
25.4
1.000
E
8.5
0.335
e
2.54
0.100
e3
22.86
0.900
F
7.1
0.280
I
3.93
0.155
L
3.3
Z
c
u
d
0.130
1.34
e
t
le
0.053
)
s
(
ct
)
s
t(
o
r
P
DIP20
o
s
b
O
-
u
d
o
r
P
e
t
e
l
o
s
b
O
17/18
ETC5064 - ETC5064-X - ETC5067 - ETC5067-X
c
u
d
e
t
le
)
s
(
ct
)
s
t(
o
r
P
o
s
b
O
-
u
d
o
r
P
e
t
e
l
o
s
b
O
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this
publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written
approval of STMicroelectronics.
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All other names are the property of their respective owners
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18/18