AD ADSP-2186NBST-320 Dsp microcomputer Datasheet

a
DSP Microcomputer
ADSP-218xN Series
PERFORMANCE FEATURES
12.5 ns Instruction Cycle Time @1.8 V (Internal), 80 MIPS
Sustained Performance
Single-Cycle Instruction Execution
Single-Cycle Context Switch
3-Bus Architecture Allows Dual Operand Fetches in
Every Instruction Cycle
Multifunction Instructions
Power-Down Mode Featuring Low CMOS Standby
Power Dissipation with 200 CLKIN Cycle Recovery
from Power-Down Condition
Low Power Dissipation in Idle Mode
INTEGRATION FEATURES
ADSP-2100 Family Code Compatible (Easy to Use
Algebraic Syntax), with Instruction Set Extensions
Up to 256K Bytes of On-Chip RAM, Configured as
Up to 48K Words Program Memory RAM
Up to 56K Words Data Memory RAM
Dual-Purpose Program Memory for Both Instruction and
Data Storage
Independent ALU, Multiplier/Accumulator, and Barrel
Shifter Computational Units
Two Independent Data Address Generators
Powerful Program Sequencer Provides Zero Overhead
Looping Conditional Instruction Execution
Programmable 16-Bit Interval Timer with Prescaler
100-Lead LQFP and 144-Ball Mini-BGA
SYSTEM INTERFACE FEATURES
Flexible I/O Allows 1.8 V, 2.5 V or 3.3 V Operation
All Inputs Tolerate up to 3.6 V Regardless of Mode
16-Bit Internal DMA Port for High-Speed Access to OnChip Memory (Mode Selectable)
4M-Byte Memory Interface for Storage of Data Tables
and Program Overlays (Mode Selectable)
8-Bit DMA to Byte Memory for Transparent Program and
Data Memory Transfers (Mode Selectable)
Programmable Memory Strobe and Separate I/O
Memory Space Permits “Glueless” System Design
Programmable Wait State Generation
Two Double-Buffered Serial Ports with Companding
Hardware and Automatic Data Buffering
Automatic Booting of On-Chip Program Memory from
Byte-Wide External Memory, e.g., EPROM, or through
Internal DMA Port
Six External Interrupts
13 Programmable Flag Pins Provide Flexible System
Signaling
UART Emulation through Software SPORT
Reconfiguration
ICE-Port™ Emulator Interface Supports Debugging in
Final Systems
FUNCTIONAL BLOCK DIAGRAM
POWER-DOWN
CONTROL
FULL MEMORY MODE
MEMORY
DATA ADDRESS
GENERATORS
DAG1
DAG2
PROGRAM
SEQUENCER
blo
hip
c
ert
Ins
ck
MAC
DATA
MEMORY
UP TO
56K 16-BIT
re.
he
m
PROGRAM MEMORY ADDRESS
gra
dia
PROGRAMMABLE
I/O
AND
FLAGS
BYTE DMA
CONTROLLER
DATA MEMORY ADDRESS
OR
DATA MEMORY DATA
SHIFTER
SERIAL PORTS
SPORT0
ADSP-2100 BASE
ARCHITECTURE
SPORT1
EXTERNAL
ADDRESS
BUS
EXTERNAL
DATA
BUS
PROGRAM MEMORY DATA
ARITHMETIC UNITS
ALU
PROGRAM
MEMORY
UP TO
48K 24-BIT
EXTERNAL
DATA
BUS
TIMER
INTERNAL
DMA
PORT
HOST MODE
ICE-Port is a trademark of Analog Devices, Inc.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use,
nor for any infringements of patents or other rights of third parties that may
result from its use. No license is granted by implication or otherwise under
any patent or patent rights of Analog Devices.
One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel:781/329-4700
http://www.analog.com
Fax:781/326-8703
© Analog Devices, Inc., 2001
ADSP-218xN Series
GENERAL DESCRIPTION
This takes place while the processor continues to:
The ADSP-218xN series consists of six single chip microcomputers optimized for digital signal processing applications. The high-level block diagram for the ADSP-218xN
series members appears on the previous page. All series
members are pin-compatible and are differentiated solely by
the amount of on-chip SRAM. This feature, combined with
ADSP-21xx code compatibility, provides a great deal of
flexibility in the design decision. Specific family members
are shown in Table 1.
• Receive and transmit data through the two serial ports
• Receive and/or transmit data through the
internal DMA port
• Receive and/or transmit data through the byte DMA port
• Decrement timer
DEVELOPMENT SYSTEM
Analog Devices’ wide range of software and hardware
development tools supports the ADSP-218xN series. The
DSP tools include an integrated development environment,
an evaluation kit, and a serial port emulator.
Table 1. ADSP-218xN DSP Microcomputer Family
Device
Program
Memory
(K Words)
Data Memory
(K Words)
ADSP-2184N
ADSP-2185N
ADSP-2186N
ADSP-2187N
ADSP-2188N
ADSP-2189N
4
16
8
32
48
32
4
16
8
32
56
48
VisualDSP++™ is an integrated development environment,
allowing for fast and easy development, debug, and deployment. The VisualDSP++ project management environment
lets programmers develop and debug an application. This
environment includes an easy-to-use assembler that is based
on an algebraic syntax; an archiver (librarian/library builder); a linker; a PROM-splitter utility; a cycle-accurate,
instruction-level simulator; a C compiler; and a C run-time
library that
includes DSP and mathematical functions.
ADSP-218xN series members combine the ADSP-2100
family base architecture (three computational units, data
address generators, and a program sequencer) with two
serial ports, a 16-bit internal DMA port, a byte DMA port,
a programmable timer, Flag I/O, extensive interrupt capabilities, and on-chip program and data memory.
Debugging both C and assembly programs with the
VisualDSP++ debugger, programmers can:
ADSP-218xN series members integrate up to 256K bytes
of on-chip memory configured as up to 48K words (24-bit)
of program RAM, and up to 56K words (16-bit) of data
RAM. Power-down circuitry is also provided to meet the
low power needs of battery-operated portable equipment.
The ADSP-218xN is available in a 100-lead LQFP package
and 144-Ball Mini-BGA.
• Set conditional breakpoints on registers, memory, and
stacks
• View mixed C and assembly code (interleaved source and
object information)
• Insert break points
• Trace instruction execution
• Fill and dump memory
• Source level debugging
The VisualDSP++ IDE lets programmers define and
manage DSP software development. The dialog boxes and
property pages let programmers configure and manage all
of the ADSP-218xN development tools, including the
syntax highlighting in the VisualDSP++ editor. This capability controls how the development tools process inputs and
generate outputs.
Fabricated in a high-speed, low-power, 0.18 µm CMOS
process, ADSP-218xN series members operate with a
12.5 ns instruction cycle time. Every instruction can
execute in a single processor cycle.
The ADSP-218xN’s flexible architecture and comprehensive instruction set allow the processor to perform multiple
operations in parallel. In one processor cycle, ADSP-218xN
series members can:
The ADSP-2189M EZ-KIT Lite™ provides developers
with a cost-effective method for initial evaluation of the
powerful ADSP-218xN DSP family architecture. The
ADSP-2189M EZ-KIT Lite includes a stand-alone ADSP2189M DSP board supported by an evaluation suite of
VisualDSP++. With this EZ-KIT Lite, users can learn
about DSP hardware and software development and evaluate potential applications of the ADSP-218xN series. The
ADSP-2189M EZ-KIT Lite provides an evaluation suite of
the VisualDSP++ development environment with the
C compiler, assembler, and linker. The size of the DSP
erxecutable that can be built using the EZ-KIT Lite tools is
limited to 8K words.
• Generate the next program address
• Fetch the next instruction
• Perform one or two data moves
• Update one or two data address pointers
• Perform a computational operation
VisualDSP++ and EZ-KIT Lite are trademarks of Analog Devices, Inc.
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ADSP-218xN Series
The EZ-KIT Lite includes the following features:
units process 16-bit data directly and have provisions to
support multiprecision computations. The ALU performs
a standard set of arithmetic and logic operations; division
primitives are also supported. The MAC performs singlecycle multiply, multiply/add, and multiply/subtract operations with 40 bits of accumulation. The shifter performs
logical and arithmetic shifts, normalization, denormalization, and derive exponent operations.
• 75 MHz ADSP-2189M
• Full 16-Bit Stereo Audio I/O with AD73322 Codec
• RS-232 Interface
• EZ-ICE Connector for Emulator Control
• DSP Demonstration Programs
• Evaluation Suite of VisualDSP++
The shifter can be used to efficiently implement numeric
format control, including multiword and block floatingpoint representations.
The ADSP-218x EZ-ICE® Emulator provides an easier and
more cost-effective method for engineers to develop and
optimize DSP systems, shortening product development
cycles for faster time-to-market. ADSP-218xN series
members integrate on-chip emulation support with a 14-pin
ICE-Port interface. This interface provides a simpler target
board connection that requires fewer mechanical clearance
considerations than other ADSP-2100 Family EZ-ICEs.
ADSP-218xN series members need not be removed from
the target system when using the EZ-ICE, nor are any adapters needed. Due to the small footprint of the EZ-ICE connector, emulation can be supported in final board
designs.The EZ-ICE performs a full range of functions,
including:
The internal result (R) bus connects the computational
units so that the output of any unit may be the input of any
unit on the next cycle.
A powerful program sequencer and two dedicated data
address generators ensure efficient delivery of operands to
these computational units. The sequencer supports conditional jumps, subroutine calls, and returns in a single cycle.
With internal loop counters and loop stacks, ADSP-218xN
series members execute looped code with zero overhead; no
explicit jump instructions are required to maintain loops.
Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches (from data memory and
program memory). Each DAG maintains and updates four
address pointers. Whenever the pointer is used to access
data (indirect addressing), it is post-modified by the value
of one of four possible modify registers. A length value may
be associated with each pointer to implement automatic
modulo addressing for circular buffers.
• In-target operation
• Up to 20 breakpoints
• Single-step or full-speed operation
• Registers and memory values can be examined
and altered
• PC upload and download functions
• Instruction-level emulation of program booting
and execution
Five internal buses provide efficient data transfer:
• Program Memory Address (PMA) Bus
• Complete assembly and disassembly of instructions
• Program Memory Data (PMD) Bus
• C source-level debugging
• Data Memory Address (DMA) Bus
Additional Information
• Data Memory Data (DMD) Bus
This data sheet provides a general overview of ADSP218xN series functionality. For additional information on
the architecture and instruction set of the processor, refer
to the ADSP-218x DSP Hardware Reference and the ADSP218x DSP Instruction Set Reference.
• Result (R) Bus
The two address buses (PMA and DMA) share a single
external address bus, allowing memory to be expanded offchip, and the two data buses (PMD and DMD) share a
single external data bus. Byte memory space and I/O
memory space also share the external buses.
ARCHITECTURE OVERVIEW
The ADSP-218xN series instruction set provides flexible
data moves and multifunction (one or two data moves with
a computation) instructions. Every instruction can be executed in a single processor cycle. The ADSP-218xN assembly language uses an algebraic syntax for ease of coding and
readability. A comprehensive set of development tools supports program development.
Program memory can store both instructions and data, permitting ADSP-218xN series members to fetch two operands in a single cycle, one from program memory and one
from data memory. ADSP-218xN series members can fetch
an operand from program memory and the next instruction
in the same cycle.
In lieu of the address and data bus for external memory
connection, ADSP-218xN series members may be configured for 16-bit Internal DMA port (IDMA port) connection to external systems. The IDMA port is made up of 16
The functional block diagram is an overall block diagram of
the ADSP-218xN series. The processor contains three independent computational units: the ALU, the multiplier/
accumulator (MAC), and the shifter. The computational
EZ-ICE is a registered trademark of Analog Devices, Inc.
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–3–
ADSP-218xN Series
data/address pins and five control pins. The IDMA port
provides transparent, direct access to the DSP’s on-chip
program and data RAM.
• SPORTs have independent framing for the receive and
transmit sections. Sections run in a frameless mode or
with frame synchronization signals internally or externally
generated. Frame sync signals are active high or inverted,
with either of two pulsewidths and timings.
An interface to low-cost byte-wide memory is provided by
the Byte DMA port (BDMA port). The BDMA port is
bidirectional and can directly address up to four megabytes
of external RAM or ROM for off-chip storage of program
overlays or data tables.
• SPORTs support serial data word lengths from 3 to
16 bits and provide optional A-law and µ-law companding, according to CCITT recommendation G.711.
The byte memory and I/O memory space interface supports
slow memories and I/O memory-mapped peripherals with
programmable wait state generation. External devices can
gain control of external buses with bus request/grant signals
(BR, BGH, and BG). One execution mode (Go Mode)
allows the ADSP-218xN to continue running from on-chip
memory. Normal execution mode requires the processor to
halt while buses are granted.
• SPORT receive and transmit sections can generate
unique interrupts on completing a data word transfer.
ADSP-218xN series members can respond to eleven interrupts. There can be up to six external interrupts (one edgesensitive, two level-sensitive, and three configurable) and
seven internal interrupts generated by the timer, the serial
ports (SPORT), the Byte DMA port, and the power-down
circuitry. There is also a master RESET signal. The two
serial ports provide a complete synchronous serial interface
with optional companding in hardware and a wide variety
of framed or frameless data transmit and receive modes of
operation.
• SPORT1 can be configured to have two external interrupts (IRQ0 and IRQ1) and the FI and FO signals. The
internally generated serial clock may still be used in this
configuration.
• SPORTs can receive and transmit an entire circular buffer
of data with only one overhead cycle per data word. An
interrupt is generated after a data buffer transfer.
• SPORT0 has a multichannel interface to selectively
receive and transmit a 24 or 32 word, time-division multiplexed, serial bitstream.
PIN DESCRIPTIONS
ADSP-218xN series members are available in a 100-lead
LQFP package and a 144-Ball Mini-BGA package. In order
to maintain maximum functionality and reduce package size
and pin count, some serial port, programmable flag, interrupt and external bus pins have dual, multiplexed functionality. The external bus pins are configured during RESET
only, while serial port pins are software configurable during
program execution. Flag and interrupt functionality is
retained concurrently on multiplexed pins. In cases where
pin functionality is reconfigurable, the default state is shown
in plain text in Table 2, while alternate functionality is
shown in italics.
Each port can generate an internal programmable serial
clock or accept an external serial clock.
ADSP-218xN series members provide up to 13 generalpurpose flag pins. The data input and output pins on
SPORT1 can be alternatively configured as an input flag
and an output flag. In addition, eight flags are programmable as inputs or outputs, and three flags are always outputs.
A programmable interval timer generates periodic interrupts. A 16-bit count register (TCOUNT) decrements
every n processor cycle, where n is a scaling value stored
in an 8-bit register (TSCALE). When the value of the count
register reaches zero, an interrupt is generated and the
count register is reloaded from a 16-bit period register
(TPERIOD).
Serial Ports
ADSP-218xN series members incorporate two complete
synchronous serial ports (SPORT0 and SPORT1) for serial
communications and multiprocessor communication.
Following is a brief list of the capabilities of the ADSP218xN SPORTs. For additional information on Serial
Ports, refer to the ADSP-218x DSP Hardware Reference.
• SPORTs are bidirectional and have a separate, doublebuffered transmit and receive section.
• SPORTs can use an external serial clock or generate their
own serial clock internally.
–4–
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ADSP-218xN Series
Table 2. Common-Mode Pins
Pin Name
# of Pins
I/O
Function
RESET
BR
BG
BGH
DMS
PMS
IOMS
BMS
1
1
1
1
1
1
1
1
I
I
O
O
O
O
O
O
Processor Reset Input
Bus Request Input
Bus Grant Output
Bus Grant Hung Output
Data Memory Select Output
Program Memory Select Output
Memory Select Output
Byte Memory Select Output
CMS
RD
WR
IRQ2
PF7
IRQL1
PF6
IRQL0
PF5
IRQE
PF4
Mode D
PF3
Mode C
PF2
Mode B
PF1
Mode A
PF0
CLKIN
XTAL
CLKOUT
SPORT0
SPORT1
IRQ1–0, FI, FO
PWD
PWDACK
FL0, FL1, FL2
VDDINT
VDDEXT
GND
VDDINT
VDDEXT
1
1
1
1
1
1
1
5
5
O
O
O
I
I/O
I
I/O
I
I/O
I
I/O
I
I/O
I
I/O
I
I/O
I
I/O
I
O
O
I/O
I/O
1
1
3
2
4
10
4
7
I
O
O
I
I
I
I
I
20
9
I
I/O
Combined Memory Select Output
Memory Read Enable Output
Memory Write Enable Output
Edge- or Level-Sensitive Interrupt Request1
Programmable I/O pin
Level-Sensitive Interrupt Requests1
Programmable I/O Pin
Level-Sensitive Interrupt Requests1
Programmable I/O Pin
Edge-Sensitive Interrupt Requests1
Programmable I/O Pin
Mode Select Input—Checked Only During RESET
Programmable I/O Pin During Normal Operation
Mode Select Input—Checked Only During RESET
Programmable I/O Pin During Normal Operation
Mode Select Input—Checked Only During RESET
Programmable I/O Pin During Normal Operation
Mode Select Input—Checked Only During RESET
Programmable I/O Pin During Normal Operation
Clock Input
Quartz Crystal Output
Processor Clock Output
Serial Port I/O Pins
Serial Port I/O Pins
Edge- or Level-Sensitive Interrupts, FI, FO2
Power-Down Control Input
Power-Down Acknowledge Control Output
Output Flags
Internal VDD (1.8 V) Power (LQFP)
External VDD (1.8 V, 2.5 V, or 3.3 V) Power (LQFP)
Ground (LQFP)
Internal VDD (1.8 V) Power (Mini-BGA)
External VDD (1.8 V, 2.5 V, or 3.3 V) Power (MiniBGA)
Ground (Mini-BGA)
For Emulation Use
GND
EZ-Port
1
1
1
1
1
1
1
1Interrupt/Flag
pins retain both functions concurrently. If IMASK is set to enable the corresponding interrupts, the DSP will
vector to the appropriate interrupt vector address when the pin is asserted, either by external devices or set as a programmable
flag.
2SPORT configuration determined by the DSP System Control Register. Software configurable.
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–5–
ADSP-218xN Series
Memory Interface Pins
signals at specific pins of the DSP during either of the two
operating modes (Full Memory or Host). A signal in one
table shares a pin with a signal from the other table, with the
active signal determined by the mode that is set. For the
shared pins and their alternate signals (e.g., A4/IAD3), refer
to the package pinouts in Table 27 on page 40 and Table 28
on page 42.
ADSP-218xN series members can be used in one of two
modes: Full Memory Mode, which allows BDMA operation
with full external overlay memory and I/O capability, or
Host Mode, which allows IDMA operation with limited
external addressing capabilities.
The operating mode is determined by the state of the Mode
C pin during RESET and cannot be changed while the
processor is running. Table 3 and Table 4 list the active
Table 3. Full Memory Mode Pins (Mode C = 0)
Pin Name
# of Pins
I/O
Function
A13–0
D23–0
14
24
O
I/O
Address Output Pins for Program, Data, Byte, and I/O Spaces
Data I/O Pins for Program, Data, Byte, and I/O Spaces (8 MSBs are also used
as Byte Memory Addresses.)
Table 4. Host Mode Pins (Mode C = 1)
Pin Name
# of Pins
I/O
Function
IAD15–0
A0
D23–8
IWR
IRD
IAL
IS
IACK
16
1
16
1
1
1
1
1
I/O
O
I/O
I
I
I
I
O
IDMA Port Address/Data Bus
Address Pin for External I/O, Program, Data, or Byte Access1
Data I/O Pins for Program, Data, Byte, and I/O Spaces
IDMA Write Enable
IDMA Read Enable
IDMA Address Latch Pin
IDMA Select
IDMA Port Acknowledge Configurable in Mode D; Open Drain
1In
Host Mode, external peripheral addresses can be decoded using the A0, CMS, PMS, DMS, and IOMS signals.
Terminating Unused Pins
Table 5 shows the recommendations for terminating
unused pins.
Table 5. Unused Pin Terminations
Pin Name1
I/O
3-State
(Z)2
Reset
State
XTAL
CLKOUT
A13–1 or
IAD12–0
A0
D23–8
D7 or
IWR
D6 or
IRD
D5 or
IAL
D4 or
IS
O
O
O (Z)
I/O (Z)
O (Z)
I/O (Z)
I/O (Z)
I
I/O (Z)
I
I/O (Z)
I
I/O (Z)
I
O
O
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
I
Hi-Z
I
Hi-Z
I
Hi-Z
I
Hi-Z3 Caused By
BR, EBR
IS
BR, EBR
BR, EBR
BR, EBR
BR, EBR
BR, EBR
BR, EBR
–6–
Unused Configuration
Float
Float4
Float
Float
Float
Float
Float
High (Inactive)
Float
High (Inactive)
Float
Low (Inactive)
Float
High (Inactive)
REV. 0
ADSP-218xN Series
Table 5. Unused Pin Terminations (Continued)
Pin Name1
I/O
3-State
(Z)2
Reset
State
Hi-Z3 Caused By
Unused Configuration
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
High (Inactive)
Float
Float
Input = High (Inactive) or Program as
Output, Set to 1, Let Float5
Input = High (Inactive) or Program as
Output, Set to 1, Let Float5
Input = High (Inactive) or Program as
Output, Set to 1, Let Float5
Input = High (Inactive) or Program as
Output, Set to 1, Let Float5
High
Input = High or Low, Output = Float
High or Low
High or Low
High or Low
Float
Input = High or Low, Output = Float
High or Low
High or Low
High or Low
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
D3 or
IACK
D2–0 or
IAD15–13
PMS
DMS
BMS
IOMS
CMS
RD
WR
BR
BG
BGH
IRQ2/PF7
I/O (Z)
Hi-Z
BR, EBR
I/O (Z)
I/O (Z)
O (Z)
O (Z)
O (Z)
O (Z)
O (Z)
O (Z)
O (Z)
I
O (Z)
O
I/O (Z)
Hi-Z
Hi-Z
O
O
O
O
O
O
O
I
O
O
I
BR, EBR
IS
BR, EBR
BR, EBR
BR, EBR
BR, EBR
BR, EBR
BR, EBR
BR, EBR
IRQL1/PF6
I/O (Z)
I
IRQL0/PF5
I/O (Z)
I
IRQE/PF4
I/O (Z)
I
PWD
SCLK0
RFS0
DR0
TFS0
DT0
SCLK1
RFS1/IRQ0
DR1/FI
TFS1/IRQ1
DT1/FO
EE
EBR
EBG
ERESET
EMS
EINT
ECLK
ELIN
ELOUT
I
I/O
I/O
I
I/O
O
I/O
I/O
I
I/O
O
I
I
O
I
O
I
I
I
O
I
I
I
I
I
O
I
I
I
I
O
I
I
O
I
O
I
I
I
O
EE
1CLKIN,
RESET, and PF3–0/Mode D –A are not included in this table because these pins must be used.
bidirectional pins have three-stated outputs. When the pin is configured as an output, the output is Hi-Z (high impedance) when inactive.
3Hi-Z = High Impedance.
4If the CLKOUT pin is not used, turn it OFF, using CLKODIS in SPORT0 autobuffer control register.
5If the Interrupt/Programmable Flag pins are not used, there are two options: Option 1: When these pins are configured as INPUTS at reset and function
as interrupts and input flag pins, pull the pins High (inactive). Option 2: Program the unused pins as OUTPUTS, set them to 1 prior to enabling interrupts,
and let pins float.
2All
REV. 0
–7–
ADSP-218xN Series
Interrupts
The IFC register is a write-only register used to force and
clear interrupts. On-chip stacks preserve the processor
status and are automatically maintained during interrupt
handling. The stacks are 12 levels deep to allow interrupt,
loop, and subroutine nesting. The following instructions
allow global enable or disable servicing of the interrupts
(including power-down), regardless of the state of IMASK:
The interrupt controller allows the processor to respond to
the eleven possible interrupts and reset with minimum overhead. ADSP-218xN series members provide four dedicated
external interrupt input pins: IRQ2, IRQL0, IRQL1, and
IRQE (shared with the PF7–4 pins). In addition, SPORT1
may be reconfigured for IRQ0, IRQ1, FI and FO, for a total
of six external interrupts. The ADSP-218xN also supports
internal interrupts from the timer, the byte DMA port, the
two serial ports, software, and the power-down control circuit. The interrupt levels are internally prioritized and individually maskable (except power-down and reset). The
IRQ2, IRQ0, and IRQ1 input pins can be programmed to
be either level- or edge-sensitive. IRQL0 and IRQL1 are
level-sensitive and IRQE is edge-sensitive. The priorities
and vector addresses of all interrupts are shown in Table 6.
ENA INTS;
DIS INTS;
Disabling the interrupts does not affect serial port autobuffering or DMA. When the processor is reset, interrupt
servicing is enabled.
LOW-POWER OPERATION
ADSP-218xN series members have three low-power modes
that significantly reduce the power dissipation when the
device operates under standby conditions. These modes are:
Table 6. Interrupt Priority and Interrupt Vector
Addresses
Source Of Interrupt
Reset (or Power-Up with
PUCR = 1)
Power-Down
(Nonmaskable)
IRQ2
IRQL1
IRQL0
SPORT0 Transmit
SPORT0 Receive
IRQE
BDMA Interrupt
SPORT1 Transmit or
IRQ1
SPORT1 Receive or IRQ0
Timer
• Power-Down
• Idle
Interrupt Vector Address
(Hex)
• Slow Idle
The CLKOUT pin may also be disabled to reduce external
power dissipation.
0x0000 (Highest Priority)
0x002C
Power-Down
ADSP-218xN series members have a low-power feature that
lets the processor enter a very low-power dormant state
through hardware or software control. Following is a brief
list of power-down features. Refer to the ADSP-218x DSP
Hardware Reference, “System Interface” chapter, for detailed
information about the power-down feature.
0x0004
0x0008
0x000C
0x0010
0x0014
0x0018
0x001C
0x0020
• Quick recovery from power-down. The processor begins
executing instructions in as few as 200 CLKIN cycles.
• Support for an externally generated TTL or CMOS
processor clock. The external clock can continue running
during power-down without affecting the lowest power
rating and 200 CLKIN cycle recovery.
0x0024
0x0028 (Lowest Priority)
• Support for crystal operation includes disabling the oscillator to save power (the processor automatically waits
approximately 4096 CLKIN cycles for the crystal oscillator to start or stabilize), and letting the oscillator run to
allow 200 CLKIN cycle start-up.
Interrupt routines can either be nested with higher priority
interrupts taking precedence or processed sequentially. Interrupts can be masked or unmasked with the IMASK register. Individual interrupt requests are logically ANDed
with the bits in IMASK; the highest priority unmasked interrupt is then selected. The power-down interrupt is nonmaskable.
• Power-down is initiated by either the power-down pin
(PWD) or the software power-down force bit. Interrupt
support allows an unlimited number of instructions to be
executed before optionally powering down. The powerdown interrupt also can be used as a nonmaskable, edgesensitive interrupt.
ADSP-218xN series members mask all interrupts for one
instruction cycle following the execution of an instruction
that modifies the IMASK register. This does not affect serial
port autobuffering or DMA transfers.
• Context clear/save control allows the processor to
continue where it left off or start with a clean context when
leaving the power-down state.
The interrupt control register, ICNTL, controls interrupt
nesting and defines the IRQ0, IRQ1, and IRQ2 external
interrupts to be either edge- or level-sensitive. The IRQE
pin is an external edge-sensitive interrupt and can be forced
and cleared. The IRQL0 and IRQL1 pins are external level
sensitive interrupts.
–8–
REV. 0
ADSP-218xN Series
When the IDLE (n) instruction is used, it effectively slows
down the processor’s internal clock and thus its response
time to incoming interrupts. The one-cycle response time
of the standard idle state is increased by n, the clock divisor.
When an enabled interrupt is received, ADSP-218xN series
members remain in the idle state for up to a maximum of n
processor cycles (n = 16, 32, 64, or 128) before resuming
normal operation.
• The RESET pin also can be used to terminate powerdown.
• Power-down acknowledge pin (PWDACK) indicates
when the processor has entered power-down.
Idle
When the ADSP-218xN is in the Idle Mode, the processor
waits indefinitely in a low-power state until an interrupt
occurs. When an unmasked interrupt occurs, it is serviced;
execution then continues with the instruction following the
IDLE instruction. In Idle mode IDMA, BDMA, and autobuffer cycle steals still occur.
When the IDLE (n) instruction is used in systems that have
an externally generated serial clock (SCLK), the serial clock
rate may be faster than the processor’s reduced internal
clock rate. Under these conditions, interrupts must not be
generated at a faster rate than can be serviced, due to the
additional time the processor takes to come out of the idle
state (a maximum of n processor cycles).
Slow Idle
The IDLE instruction is enhanced on ADSP-218xN series
members to let the processor’s internal clock signal be
slowed, further reducing power consumption. The reduced
clock frequency, a programmable fraction of the normal
clock rate, is specified by a selectable divisor given in the
IDLE instruction.
SYSTEM INTERFACE
Figure 1 shows typical basic system configurations with the
ADSP-218xN series, two serial devices, a byte-wide
EPROM, and optional external program and data overlay
memories (mode-selectable). Programmable wait state generation allows the processor to connect easily to slow peripheral devices. ADSP-218xN series members also provide
four external interrupts and two serial ports or six external
interrupts and one serial port. Host Memory Mode allows
access to the full external data bus, but limits addressing to
a single address bit (A0). Through the use of external hardware, additional system peripherals can be added in this
mode to generate and latch address signals.
The format of the instruction is:
IDLE (N);
where N = 16, 32, 64, or 128. This instruction keeps the
processor fully functional, but operating at the slower clock
rate. While it is in this state, the processor’s other internal
clock signals, such as SCLK, CLKOUT, and timer clock,
are reduced by the same ratio. The default form of the instruction, when no clock divisor is given, is the standard
IDLE instruction.
FULL MEMORY MODE
HOST MEMORY MODE
ADSP-218xN
ADSP-218xN
1/2X CLOCK
OR
CRYSTAL
SERIAL
DEVICE
SERIAL
DEVICE
CLKIN
XTAL
A13–0
ADDR13–0 14
FL0–2
D23–16
24
IRQ2/PF7
IRQE/PF4 DATA23–0
IRQL0/PF5
BMS
IRQL1/PF6
WR
MODE D/PF3
RD
MODE C/PF2
MODE A/PF0
MODE B/PF1
IOMS
SPORT1
SCLK1
RFS1 OR IRQ0
TFS1 OR IRQ1
DT1 OR FO
PMS
DR1 OR FI
ert
DMSIns
CMS
SPORT0
SCLK0
BR
RFS0
BG
TFS0
BGH
DT0
PWD
DR0
PWDACK
D15–8
CLKIN
1/2X CLOCK
OR
CRYSTAL
XTAL
A0–A21
BYTE
MEMORY
DATA
IRQ2/PF7
IRQE/PF4
DATA23–8
IRQL0/PF5
IRQL1/PF6
BMS
MODE D/PF3
WR
MODE C/PF2
RD
MODE A/PF0
CS
A10–0
re
I/O SPACE
he
(PERIPHERALS)
m
DATA
2048
graLOCATIONS
CS dia
ADDR
D23–8
ce
rfa
e
t
in ADDR
m
eD23–0
t
s
DATA
sy
MODE B/PF1
SPORT1
SCLK1
RFS1 OR IRQ0
TFS1 OR IRQ1
DT1 OR FO
DR1 OR FI
A13–0
SERIAL
DEVICE
OVERLAY
MEMORY
TWO 8K
PM SEGMENTS
TWO 8K
DM SEGMENTS
SPORT0
SCLK0
RFS0
TFS0
DT0
DR0
SERIAL
DEVICE
SYSTEM
INTERFACE
OR
µCONTROLLER
16
Figure 1. Basic System Interface
REV. 0
A0
FL0–2
–9–
IDMA PORT
IRD/D6
IWR/D7
IS/D4
IAL/D5
IACK/D3
IAD15-0
IOMS
PMS
DMS
CMS
BR
BG
BGH
PWD
PWDACK
1
16
ADSP-218xN Series
Clock Signals
RESET
ADSP-218xN series members can be clocked by either a
crystal or a TTL-compatible clock signal.
The RESET signal initiates a master reset of the ADSP218xN. The RESET signal must be asserted during the
power-up sequence to assure proper initialization. RESET
during initial power-up must be held long enough to allow
the internal clock to stabilize. If RESET is activated any time
after power-up, the clock continues to run and does not
require stabilization time.
The CLKIN input cannot be halted, changed during operation, nor operated below the specified frequency during
normal operation. The only exception is while the processor
is in the power-down state. For additional information, refer
to the ADSP-218x DSP Hardware Reference, for detailed
information on this power-down feature.
If an external clock is used, it should be a TTL-compatible
signal running at half the instruction rate. The signal is
connected to the processor’s CLKIN input. When an external clock is used, the XTAL pin must be left unconnected.
ADSP-218xN series members use an input clock with a
frequency equal to half the instruction rate; a 40 MHz input
clock yields a 12.5 ns processor cycle (which is equivalent
to 80 MHz). Normally, instructions are executed in a single
processor cycle. All device timing is relative to the internal
instruction clock rate, which is indicated by the CLKOUT
signal when enabled.
The RESET input contains some hysteresis; however, if an
RC circuit is used to generate the RESET signal, the use of
an external Schmitt trigger is recommended.
Because ADSP-218xN series members include an on-chip
oscillator circuit, an external crystal may be used. The
crystal should be connected across the CLKIN and XTAL
pins, with two capacitors connected as shown in Figure 2.
Capacitor values are dependent on crystal type and should
be specified by the crystal manufacturer. A parallelresonant, fundamental frequency, microprocessor-grade
crystal should be used.
The master reset sets all internal stack pointers to the empty
stack condition, masks all interrupts, and clears the MSTAT
register. When RESET is released, if there is no pending
bus request and the chip is configured for booting, the bootloading sequence is performed. The first instruction is
fetched from on-chip program memory location 0x0000
once boot loading completes.
A clock output (CLKOUT) signal is generated by the processor at the processor’s cycle rate. This can be enabled and
disabled by the CLKODIS bit in the SPORT0 Autobuffer
Control Register.
CLKIN
XTAL
CLKOUT
DSP
The power-up sequence is defined as the total time required
for the crystal oscillator circuit to stabilize after a valid VDD
is applied to the processor, and for the internal phase-locked
loop (PLL) to lock onto the specific crystal frequency. A
minimum of 2000 CLKIN cycles ensures that the PLL has
locked, but does not include the crystal oscillator start-up
time. During this power-up sequence the RESET signal
should be held low. On any subsequent resets, the RESET
signal must meet the minimum pulse-width specification
(tRSP).
POWER SUPPLIES
ADSP-218xN series members have separate power supply
connections for the internal (VDDINT) and external (VDDEXT)
power supplies. The internal supply must meet the 1.8 V
requirement. The external supply can be connected to a
1.8 V, 2.5 V, or 3.3 V supply. All external supply pins must
be connected to the same supply. All input and I/O pins can
tolerate input voltages up to 3.6 V, regardless of the external
supply voltage. This feature provides maximum flexibility
in mixing 1.8 V, 2.5 V, or 3.3 V components.
Figure 2. External Crystal Connections
–10–
REV. 0
ADSP-218xN Series
MODES OF OPERATION
The ADSP-218xN series modes of operation appear in
Table 7.
Table 7. Modes of Operation
Mode D
Mode C
Mode B
Mode A
Booting Method
X
0
0
0
X
0
1
0
0
1
0
0
0
1
0
1
1
1
0
0
1
1
0
1
BDMA feature is used to load the first 32 program memory words
from the byte memory space. Program execution is held off until all
32 words have been loaded. Chip is configured in Full Memory
Mode.1
No automatic boot operations occur. Program execution starts at
external memory location 0. Chip is configured in Full Memory
Mode. BDMA can still be used, but the processor does not automatically use or wait for these operations.
BDMA feature is used to load the first 32 program memory words
from the byte memory space. Program execution is held off until all
32 words have been loaded. Chip is configured in Host Mode. IACK
has active pull-down. (Requires additonal hardware.)
IDMA feature is used to load any internal memory as desired.
Program execution is held off until the host writes to internal
program memory location 0. Chip is configured in Host Mode.
IACK has active pull-down.1
BDMA feature is used to load the first 32 program memory words
from the byte memory space. Program execution is held off until all
32 words have been loaded. Chip is configured in Host Mode; IACK
requires external pull-down. (Requires additonal hardware.)
IDMA feature is used to load any internal memory as desired.
Program execution is held off until the host writes to internal
program memory location 0. Chip is configured in Host Mode.
IACK requires external pull-down.1
1Considered
as standard operating settings. Using these configurations allows for easier design and better memory management.
Setting Memory Mode
Active Configuration
Memory Mode selection for the ADSP-218xN series is
made during chip reset through the use of the Mode C pin.
This pin is multiplexed with the DSP’s PF2 pin, so care must
be taken in how the mode selection is made. The two methods for selecting the value of Mode C are active and passive.
Active Configuration involves the use of a three-statable
external driver connected to the Mode C pin. A driver’s
output enable should be connected to the DSP’s RESET
signal such that it only drives the PF2 pin when RESET is
active (low). When RESET is deasserted, the driver should
be three-state, thus allowing full use of the PF2 pin as either
an input or output. To minimize power consumption during
power-down, configure the programmable flag as an output
when connected to a three-stated buffer. This ensures that
the pin will be held at a constant level, and will not oscillate
should the three-state driver’s level hover around the logic
switching point.
Passive Configuration
Passive Configuration involves the use of a pull-up or pulldown resistor connected to the Mode C pin. To minimize
power consumption, or if the PF2 pin is to be used as
an output in the DSP application, a weak pull-up or pulldown resistance, on the order of 10 k, can be used. This
value should be sufficient to pull the pin to the desired level
and still allow the pin to operate as a programmable flag
output without undue strain on the processor’s output
driver. For minimum power consumption during powerdown, reconfigure PF2 to be an input, as the pull-up or pulldown resistance will hold the pin in a known state, and will
not switch.
REV. 0
IDMA ACK Configuration
Mode D = 0 and in host mode: IACK is an active, driven
signal and cannot be “wire ORed.” Mode D = 1 and in host
mode: IACK is an open drain and requires an external
pull-down, but multiple IACK pins can be “wire ORed”
together.
–11–
ADSP-218xN Series
MEMORY ARCHITECTURE
The ADSP-218xN series provides a variety of memory and
peripheral interface options. The key functional groups are
Program Memory, Data Memory, Byte Memory, and I/O.
PROGRAM MEMORY
MODEB = 1
0X3FFF
Refer to Figure 3 through Figure 8, Table 8 on page 14, and
Table 9 on page 14 for PM and DM memory allocations in
the ADSP-218xN series.
PROGRAM MEMORY
MODEB = 0
0X3FFF
0X3FFF
PM OVERLAY 1,2
(EXTERNAL PM)
RESERVED
PM OVERLAY 0
(RESERVED)
0X2000
0X1FFF
0X2000
0X1FFF
32 MEMORY-MAPPED
CONTROL REGISTERS
0X3FE0
0X3FDF
4064 RESERVED
WORDS
0X3000
0X2FFF
INTERNAL DM
RESERVED
EXTERNAL PM
DATA MEMORY
0X2000
0X1FFF
DM OVERLAY 1,2
(EXTERNAL DM)
0X1000
0X0FFF
DM OVERLAY 0
(RESERVED)
INTERNAL PM
0X0000
0X0000
0X0000
Figure 3. ADSP-2184 Memory Architecture
PROGRAM MEMORY
MODEB = 1
0X3FFF
PROGRAM MEMORY
MODEB = 0
0X3FFF
0X3FFF
PM OVERLAY 1,2
(EXTERNAL PM)
RESERVED
DATA MEMORY
32 MEMORY-MAPPED
CONTROL REGISTERS
0X3FE0
0X3FDF
PM OVERLAY 0
(RESERVED)
0X2000
0X1FFF
0X2000
0X1FFF
EXTERNAL PM
INTERNAL DM
0X2000
0X1FFF
DM OVERLAY 1,2
(EXTERNAL DM)
INTERNAL PM
DM OVERLAY 0
(INTERNAL DM)
0X0000
0X0000
0X0000
Figure 4. ADSP-2185 Memory Architecture
PROGRAM MEMORY
MODEB = 1
0X3FFF
PROGRAM MEMORY
MODEB = 0
0X3FFF
0X3FFF
PM OVERLAY 1,2
(EXTERNAL PM)
RESERVED
DATA MEMORY
32 MEMORY-MAPPED
CONTROL REGISTERS
0X3FE0
0X3FDF
PM OVERLAY 0
(RESERVED)
0X2000
0X1FFF
0X2000
0X1FFF
EXTERNAL PM
INTERNAL DM
0X2000
0X1FFF
DM OVERLAY 1,2
(EXTERNAL DM)
INTERNAL PM
DM OVERLAY 0
(RESERVED)
0X0000
0X0000
0X0000
Figure 5. ADSP-2186 Memory Architecture
–12–
REV. 0
ADSP-218xN Series
PROGRAM MEMORY
MODEB = 1
0X3FFF
PROGRAM MEMORY
MODEB = 0
0X3FFF
0X3FFF
PM OVERLAY 1,2
(EXTERNAL PM)
RESERVED
DATA MEMORY
32 MEMORY-MAPPED
CONTROL REGISTERS
0X3FE0
0X3FDF
PM OVERLAY 0,4,5
(INTERNAL PM)
0X2000
0X1FFF
0X2000
0X1FFF
EXTERNAL PM
INTERNAL DM
0X2000
0X1FFF
DM OVERLAY 1,2
(EXTERNAL DM)
INTERNAL PM
DM OVERLAY 0,4,5
(INTERNAL DM)
0X0000
0X0000
0X0000
Figure 6. ADSP-2187 Memory Architecture
PROGRAM MEMORY
MODEB = 1
0x3FFF
PROGRAM MEMORY
MODEB = 0
0x3FFF
DATA MEMORY
0x3FFF
PM OVERLAY 1,2
(EXTERNAL PM)
RESERVED
32 MEMORY-MAPPED
CONTROL REGISTERS
0x3FE0
0x3FDF
PM OVERLAY
0,4,5,6,7
(INTERNAL PM)
0x2000
0x1FFF
0x2000
0x1FFF
EXTERNAL PM
0x2000
0x1FFF
INTERNAL PM
0x0000
0x0000
INTERNAL DM
0x0000
DM OVERLAY 1,2
(EXTERNAL DM)
DM OVERLAY
0,4,5,6,7,8
(INTERNAL DM)
Figure 7. ADSP-2188 Memory Architecture
PROGRAM MEMORY
MODEB = 1
0X3FFF
PROGRAM MEMORY
MODEB = 0
0X3FFF
DATA MEMORY
0X3FFF
PM OVERLAY 1,2
(EXTERNAL PM)
RESERVED
32 MEMORY-MAPPED
CONTROL REGISTERS
0X3FE0
0X3FDF
PM OVERLAY 0,4,5
(INTERNAL PM)
0X2000
0X1FFF
0X2000
0X1FFF
EXTERNAL PM
0X0000
INTERNAL DM
0X2000
0X1FFF
INTERNAL PM
0X0000
0X0000
Figure 8. ADSP-2189 Memory Architecture
REV. 0
–13–
DM OVERLAY 1,2
(EXTERNAL DM)
DM OVERLAY
0,4,5,6,7
(INTERNAL DM)
ADSP-218xN Series
Program Memory
Program Memory (Host Mode) allows access to all internal
memory. External overlay access is limited by a single external address line (A0). External program execution is not
available in host mode due to a restricted data bus that is
only 16 bits wide.
Program Memory (Full Memory Mode) is a 24-bit-wide
space for storing both instruction opcodes and data. The
ADSP-218xN series has up to 48K words of Program
Memory RAM on chip, and the capability of accessing up
to two 8K external memory overlay spaces, using the external data bus.
Table 8. PMOVLAY Bits
Processor
PMOVLAY
Memory
A13
A12–0
ADSP-2184N
Not Applicable
Not Applicable
Not Applicable
Internal Overlay
Not Applicable
Not Applicable
Not Applicable
Not Applicable
Not Applicable
ADSP-2187N
ADSP-2188N
ADSP-2189N
All Processors
No Internal
Overlay Region
0
No Internal
Overlay Region
0, 4, 5
0, 4, 5, 6, 7
0, 4, 5
1
Internal Overlay
Internal Overlay
Internal Overlay
External Overlay 1
Not Applicable
Not Applicable
Not Applicable
0
All Processors
2
External Overlay 2
1
Not Applicable
Not Applicable
Not Applicable
13 LSBs of Address Between 0x2000 and
0x3FFF
13 LSBs of Address Between 0x2000 and
0x3FFF
ADSP-2185N
ADSP-2186N
Data Memory
plete in one cycle. Accesses to external memory are timed
using the wait states specified by the DWAIT register and
the wait state mode bit.
Data Memory (Full Memory Mode) is a 16-bit-wide space
used for the storage of data variables and for memorymapped control registers. The ADSP-218xN series has up
to 56K words of Data Memory RAM on-chip. Part of this
space is used by 32 memory-mapped registers. Support also
exists for up to two 8K external memory overlay spaces
through the external data bus. All internal accesses com-
Data Memory (Host Mode) allows access to all internal
memory. External overlay access is limited by a single external address line (A0).
Table 9. DMOVLAY Bits
Processor
DMOVLAY
Memory
A13
A12–0
ADSP-2184N
Not Applicable
Not Applicable
Not Applicable
Internal Overlay
Not Applicable
Not Applicable
Not Applicable
Not Applicable
Not Applicable
ADSP-2187N
ADSP-2188N
ADSP-2189N
All Processors
No Internal Overlay
Region
0
No Internal Overlay
Region
0, 4, 5
0, 4, 5, 6, 7, 8
0, 4, 5, 6, 7
1
Internal Overlay
Internal Overlay
Internal Overlay
External Overlay 1
Not Applicable
Not Applicable
Not Applicable
0
All Processors
2
External Overlay 2
1
Not Applicable
Not Applicable
Not Applicable
13 LSBs of Address
Between 0x0000
and 0x1FFF
13 LSBs of Address
Between 0x0000
and 0x1FFF
ADSP-2185N
ADSP-2186N
–14–
REV. 0
ADSP-218xN Series
Memory-Mapped Registers (New to the ADSP-218xM
and N series)
WAIT STATE CONTROL
2 e1r 0
st
DM(0X3FFE)
1 eg1i 1 1
R
l
o
r
t
n
DWAIT
IOWAIT3
IOWAIT2 IOWAIT1
IOWAIT0
Co
te
a
t
S
WAIT STATE MODE SELECT
ait
0 = NORMAL MODE (PWAIT, W
DWAIT, IOWAIT0–3 = N WAIT STATES,
t
e7)r
RANGING FROM 0 TO
Ins DWAIT, IOWAIT0–3 = 2N + 1 WAIT STATES,
1 = 2N + 1 MODE (PWAIT,
ADSP-218xN series members have three memory-mapped
registers that differ from other ADSP-21xx Family DSPs.
The slight modifications to these registers (Wait State Control, Programmable Flag and Composite Select Control,
and System Control) provide the ADSP-218xN’s wait state
and BMS control features. Default bit values at reset are
shown; if no value is shown, the bit is undefined at reset.
Reserved bits are shown on a grey field. These bits should
always be written with zeros.
ADSP-218xN series members support an additional external memory space called I/O space. This space is designed
to support simple connections to peripherals (such as data
converters and external registers) or to bus interface ASIC
data registers. I/O space supports 2048 locations of 16-bit
wide data. The lower eleven bits of the external address bus
are used; the upper three bits are undefined.
Note: In Full Memory Mode, all 2048 locations of I/O space
are directly addressable. In Host Memory Mode, only
address pin A0 is available; therefore, additional logic is
required externally to achieve complete addressability of the
2048 I/O space locations.
9
8
7
6
5
4
1
1
1
1
1
1
1
1
1
1
1
1
3
RANGING FROM 0 TO 15)
Figure 9. Wait State Control Register
Composite Memory Select
I/O Space (Full Memory Mode)
Two instructions were added to the core ADSP-2100
Family instruction set to read from and write to I/O memory
space. The I/O space also has four dedicated three-bit wait
state registers, IOWAIT0–3 as shown in Figure 9, which in
combination with the wait state mode bit, specify up to 15
wait states to be automatically generated for each of four
regions. The wait states act on address ranges, as shown
in Table 10.
15 14 13 12 11 10
ADSP-218xN series members have a programmable
memory select signal that is useful for generating memory
select signals for memories mapped to more than one space.
The CMS signal is generated to have the same timing as
each of the individual memory select signals (PMS, DMS,
BMS, IOMS) but can combine their functionality. Each bit
in the CMSSEL register, when set, causes the CMS signal
to be asserted when the selected memory select is asserted.
For example, to use a 32K word memory to act as both
program and data memory, set the PMS and DMS bits in
the CMSSEL register and use the CMS pin to drive the chip
select of the memory, and use either DMS or PMS as the
additional address bit.
The CMS pin functions like the other memory select signals
with the same timing and bus request logic. A 1 in the enable
bit causes the assertion of the CMS signal at the same time
as the selected memory select signal. All enable bits default
to 1 at reset, except the BMS bit.
See Figure 10 and Figure 11 for illustration of the programmable flag and composite control register and the system
control register.
Table 10. Wait States
Address Range
Wait State Register
0x000–0x1FF
IOWAIT0 and Wait State Mode
Select Bit
IOWAIT1 and Wait State Mode
Select Bit
IOWAIT2 and Wait State Mode
Select Bit
IOWAIT3 and Wait State Mode
Select Bit
0x200–0x3FF
0x400–0x5FF
0x600–0x7FF
REV. 0
PROGRAMMABLE FLAG AND COMPOSITE
SELECT CONTROL
15 14
13 12
11 10
9
8
7
6
5
4
3
2
1
0
1
1
1
1
1
0
0
0
0
0
0
0
0
1
BM W A IT
1
0
CM SSEL
0 = D IS A B L E CMS
1 = E N A B L E CMS
DM(0X3FE6)
PFT YP E
0 = IN PU T
1 = O UTPUT
( W H E R E B IT : 1 1 - I O M , 1 0 - B M , 9 - D M , 8 - P M )
Figure 10. Programmable Flag and Composite Control
Register
–15–
ADSP-218xN Series
SYSTEM CONTROL
15 14 13 12 11 10
0
0
0
0
0
1
RESERVED
SET TO 0
BDMA CONTROL
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
1
1
RESERVED, A LWAYS
SET TO 0
SPORT0 ENABLE
0 = DISABLE
1 = ENABLE
SPORT1 ENABLE
0 = DISABLE
1 = ENABLE
DM(0X3FFF)
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
BMPAGE
PWAIT
PROGRAM MEMORY
WAIT STATES
0
BDMA
OVERLAY
BITS
(SEE TABLE 12)
DI SA BL E BMS
0 = EN AB LE BMS
1 = DISA B L E BMS
SPORT1 CONFIGURE
0 = FI, FO, IRQ0, IRQ1, SC LK
1 = SPORT1
NOTE: RESERVED B ITS ARE SHOWN O N A GRAY FIELD. THESE B ITS
SHOULD ALWAYS BE WRITTEN WITH ZEROS.
Figure 11. System Control Register
Byte Memory Select
The byte memory space is a bidirectional, 8-bit-wide,
external memory space used to store programs and data.
Byte memory is accessed using the BDMA feature. The byte
memory space consists of 256 pages, each of which is
16K 8 bits.
The byte memory space on the ADSP-218xN series supports read and write operations as well as four different data
formats. The byte memory uses data bits 15–8 for data. The
byte memory uses data bits 23–16 and address bits 13–0
to create a 22-bit address. This allows up to a 4 meg 8
(32 megabit) ROM or RAM to be used without glue logic.
All byte memory accesses are timed by the BMWAIT register and the wait state mode bit.
Byte Memory DMA (BDMA, Full Memory Mode)
The byte memory DMA controller (Figure 12) allows
loading and storing of program instructions and data using
the byte memory space. The BDMA circuit is able to access
the byte memory space while the processor is operating
normally and steals only one DSP cycle per 8-, 16-, or 24bit word transferred.
BTYPE
BDIR
0 = LOAD FROM BM
1 = STORE TO BM
BCR
0 = RUN DURING BDMA
1 = HALT DURING BDMA
Figure 12. BDMA Control Register
The BDMA circuit supports four different data formats that
are selected by the BTYPE register field. The appropriate
number of 8-bit accesses are done from the byte memory
space to build the word size selected. Table 11 shows the
data formats supported by the BDMA circuit.
Table 11. Data Formats
The ADSP-218xN’s BMS disable feature combined with
the CMS pin allows use of multiple memories in the byte
memory space. For example, an EPROM could be attached
to the BMS select, and a flash memory could be connected
to CMS. Because at reset BMS is enabled, the EPROM
would be used for booting. After booting, software could
disable BMS and set the CMS signal to respond to BMS,
enabling the flash memory.
Byte Memory
DM (0x3FE3)
BTYPE
00
01
10
11
Internal
Memory Space
Program
Memory
Data Memory
Data Memory
Data Memory
Word Size
Alignment
24
Full Word
16
8
8
Full Word
MSBs
LSBs
Unused bits in the 8-bit data memory formats are filled with
0s. The BIAD register field is used to specify the starting
address for the on-chip memory involved with the transfer.
The 14-bit BEAD register specifies the starting address for
the external byte memory space. The 8-bit BMPAGE register specifies the starting page for the external byte memory
space. The BDIR register field selects the direction of the
transfer. Finally, the 14-bit BWCOUNT register specifies
the number of DSP words to transfer and initiates the
BDMA circuit transfers.
BDMA accesses can cross page boundaries during sequential addressing. A BDMA interrupt is generated on the completion of the number of transfers specified by the
BWCOUNT register.
The BWCOUNT register is updated after each transfer so
it can be used to check the status of the transfers. When
it reaches zero, the transfers have finished and a BDMA
interrupt is generated. The BMPAGE and BEAD registers
must not be accessed by the DSP during BDMA operations.
The source or destination of a BDMA transfer will always
be on-chip program or data memory.
When the BWCOUNT register is written with a nonzero
value the BDMA circuit starts executing byte memory
accesses with wait states set by BMWAIT. These accesses
continue until the count reaches zero. When enough accesses have occurred to create a destination word, it is transferred to or from on-chip memory. The transfer takes one
–16–
REV. 0
ADSP-218xN Series
Table 12. IDMA/BDMA Overlay Bits
DSP cycle. DSP accesses to external memory have priority
over BDMA byte memory accesses.
The BDMA Context Reset bit (BCR) controls whether the
processor is held off while the BDMA accesses are occurring. Setting the BCR bit to 0 allows the processor to continue operations. Setting the BCR bit to 1 causes the
processor to stop execution while the BDMA accesses are
occurring, to clear the context of the processor, and start
execution at address 0 when the BDMA accesses have
completed.
The BDMA overlay bits specify the OVLAY memory blocks
to be accessed for internal memory. Set these bits as indicated in.
Internal Memory DMA Port (IDMA Port; Host Memory
Mode)
The IDMA Port provides an efficient means of communication between a host system and ADSP-218xN series
members. The port is used to access the on-chip program
memory and data memory of the DSP with only one DSP
cycle per word overhead. The IDMA port cannot, however,
be used to write to the DSP’s memory-mapped control registers. A typical IDMA transfer process is shown as follows:
Host starts IDMA transfer.
Host checks IACK control line to see if the DSP is
busy.
3.
Host uses IS and IAL control lines to latch either the
DMA starting address (IDMAA) or the PM/DM
OVLAY selection into the DSP’s IDMA control registers. If Bit 15 = 1, the value of bits 7–0 represent the
IDMA overlay; bits 14–8 must be set to 0. If Bit 15 = 0,
the value of Bits 13–0 represent the starting address
of internal memory to be accessed and Bit 14 reflects
PM or DM for access. Set IDDMOVLAY and
IDPMOVLAY bits in the IDMA overlay register as
indicted in Table 12.
4.
Host uses IS and IRD (or IWR) to read (or write) DSP
internal memory (PM or DM).
5.
Host checks IACK line to see if the DSP has completed
the previous IDMA operation.
6.
Host ends IDMA transfer.
IDMA/BDMA
DMOVLAY
ADSP-2184N
ADSP-2185N
ADSP-2186N
ADSP-2187N
ADSP-2188N
ADSP-2189N
0
0
0
0, 4, 5
0, 4, 5, 6, 7
0, 4, 5
0
0
0
0, 4, 5
0, 4, 5, 6, 7, 8
0, 4, 5, 6, 7
The DSP memory address is latched and then automatically
incremented after each IDMA transaction. An external
device can therefore access a block of sequentially addressed
memory by specifying only the starting address of the block.
This increases throughput as the address does not have to
be sent for each memory access.
The BMWAIT field, which has four bits on ADSP-218xN
series members, allows selection up to 15 wait states for
BDMA transfers.
2.
IDMA/BDMA
PMOVLAY
The IDMA port has a 16-bit multiplexed address and data
bus and supports 24-bit program memory. The IDMA port
is completely asynchronous and can be written while the
ADSP-218xN is operating at full speed.
Note: BDMA cannot access external overlay memory
regions 1 and 2.
1.
Processor
IDMA Port access occurs in two phases. The first is the
IDMA Address Latch cycle. When the acknowledge is asserted, a 14-bit address and 1-bit destination type can be
driven onto the bus by an external device. The address specifies an on-chip memory location, the destination type specifies whether it is a DM or PM access. The falling edge of
the IDMA address latch signal (IAL) or the missing edge of
the IDMA select signal (IS) latches this value into the
IDMAA register.
Once the address is stored, data can be read from, or written
to, the ADSP-218xN’s on-chip memory. Asserting the
select line (IS) and the appropriate read or write line (IRD
and IWR respectively) signals the ADSP-218xN that a particular transaction is required. In either case, there is a oneprocessor-cycle delay for synchronization. The memory
access consumes one additional processor cycle.
Once an access has occurred, the latched address is automatically incremented, and another access can occur.
Through the IDMAA register, the DSP can also specify the
starting address and data format for DMA operation.
Asserting the IDMA port select (IS) and address latch
enable (IAL) directs the ADSP-218xN to write the address
onto the IAD14–0 bus into the IDMA Control Register
(Figure 13). If Bit 15 is set to 0, IDMA latches the address.
If Bit 15 is set to 1, IDMA latches into the OVLAY register.
This register, also shown in Figure 13, is memory-mapped
at address DM (0x3FE0). Note that the latched address
(IDMAA) cannot be read back by the host.
When Bit 14 in 0x3FE7 is set to zero, short reads use the
timing shown in Figure 34 on page 37. When Bit 14 in
0x3FE7 is set to 1, timing in Figure 35 on page 38 applies
for short reads in short read only mode. Set IDDMOVLAY
REV. 0
–17–
ADSP-218xN Series
and IDPMOVLAY bits in the IDMA overlay register as
indicated in Table 12. Refer to the ADSP-218x DSP Hardware Reference for additional details.
Note: In full memory mode all locations of 4M-byte
memory space are directly addressable. In host memory
mode, only address pin A0 is available, requiring additional
external logic to provide address information for the byte.
IDMA Port Booting
ADSP-218xN series members can also boot programs
through its Internal DMA port. If Mode C = 1, Mode B =
0, and Mode A = 1, the ADSP-218xN boots from the IDMA
port. IDMA feature can load as much on-chip memory as
desired. Program execution is held off until the host writes
to on-chip program memory location 0.
BUS REQUEST AND BUS GRANT
ADSP-218xN series members can relinquish control of the
data and address buses to an external device. When the
external device requires access to memory, it asserts the Bus
Request (BR) signal. If the ADSP-218xN is not performing
an external memory access, it responds to the active BR
input in the following processor cycle by:
IDMA OVERLAY
15 14 13 12 11 10
0
0
0
0
0
0
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
RESERVED SET TO 0
RESERVED SET TO 0
DM (0x3FE7)
IDDMOVLAY
IDPMOVLAY
(SEE TABLE 12)
SHORT READ ONLY
0 = DISABLE
1 = ENABLE
• Three-stating the data and address buses and the PMS,
DMS, BMS, CMS, IOMS, RD, WR output drivers,
IDMA CONTROL (U = UNDEFINED AT RESET)
15 14 13 12 11 10
0
U
U
U
U
U
9
8
7
6
5
4
3
2
1
0
U
U
U
U
U
U
U
U
U
U
• Asserting the bus grant (BG) signal, and
DM (0x3FE0)
• Halting program execution.
IDMAA ADDRESS
If Go Mode is enabled, the ADSP-218xN will not halt
program execution until it encounters an instruction that
requires an external memory access.
IDMAD DESTINATION MEMORY
TYPE
0 = PM
1 = DM
NOTE: RESERVED BITS ARE SHOWN ON A GRAY FIELD. THESE
BITS SHOULD ALWAYS BE WRITTEN WITH ZEROS.
RESERVED SET TO 0
ADSP-218xN series members have two mechanisms to
allow automatic loading of the internal program memory
after reset. The method for booting is controlled by the
Mode A, B, and C configuration bits.
If an ADSP-218xN series member is performing an external
memory access when the external device asserts the BR
signal, it will not three-state the memory interfaces nor
assert the BG signal until the processor cycle after the access
completes. The instruction does not need to be completed
when the bus is granted. If a single instruction requires two
external memory accesses, the bus will be granted between
the two accesses.
When the mode pins specify BDMA booting, the ADSP218xN initiates a BDMA boot sequence when reset is
released.
When the BR signal is released, the processor releases the
BG signal, re-enables the output drivers, and continues
program execution from the point at which it stopped.
The BDMA interface is set up during reset to the following
defaults when BDMA booting is specified: the BDIR,
BMPAGE, BIAD, and BEAD registers are set to 0, the
BTYPE register is set to 0 to specify program memory 24bit words, and the BWCOUNT register is set to 32. This
causes 32 words of on-chip program memory to be loaded
from byte memory. These 32 words are used to set up the
BDMA to load in the remaining program code. The BCR
bit is also set to 1, which causes program execution to be
held off until all 32 words are loaded into on-chip program
memory. Execution then begins at address 0.
The bus request feature operates at all times, including
when the processor is booting and when RESET is active.
Figure 13. IDMA OVLAY/Control Registers
Bootstrap Loading (Booting)
The ADSP-2100 Family development software (Revision
5.02 and later) fully supports the BDMA booting feature
and can generate byte memory space-compatible boot code.
The IDLE instruction can also be used to allow the processor to hold off execution while booting continues through
the BDMA interface. For BDMA accesses while in Host
Mode, the addresses to boot memory must be constructed
externally to the ADSP-218xN. The only memory address
bit provided by the processor is A0.
The BGH pin is asserted when an ADSP-218xN series
member requires the external bus for a memory or BDMA
access, but is stopped. The other device can release the bus
by deasserting bus request. Once the bus is released, the
ADSP-218xN deasserts BG and BGH and executes the
external memory access.
FLAG I/O PINS
ADSP-218xN series members have eight general-purpose
programmable input/output flag pins. They are controlled
by two memory-mapped registers. The PFTYPE register
determines the direction, 1 = output and 0 = input. The
PFDATA register is used to read and write the values on the
pins. Data being read from a pin configured as an input is
synchronized to the ADSP-218xN’s clock. Bits that are programmed as outputs will read the value being output. The
PF pins default to input during reset.
–18–
REV. 0
ADSP-218xN Series
if the RESET pin is being used as a method of setting the
value of the mode pins, the effects of an emulator reset must
be taken into consideration.
In addition to the programmable flags, ADSP-218xN series
members have five fixed-mode flags, FI, FO, FL0, FL1, and
FL2. FL0–FL2 are dedicated output flags. FI and FO are
available as an alternate configuration of SPORT1.
One method of ensuring that the values located on the mode
pins are those desired is to construct a circuit like the one
shown in Figure 14. This circuit forces the value located on
the Mode A pin to logic high, regardless of whether it is
latched via the RESET or ERESET pin.
Note: Pins PF0, PF1, PF2, and PF3 are also used for device
configuration during reset.
INSTRUCTION SET DESCRIPTION
The ADSP-218xN series assembly language instruction set
has an algebraic syntax that was designed for ease of coding
and readability. The assembly language, which takes full
advantage of the processor’s unique architecture, offers the
following benefits:
ERESET
RESET
ADSP-218xN
• The algebraic syntax eliminates the need to remember
cryptic assembler mnemonics. For example, a typical
arithmetic add instruction, such as AR = AX0 + AY0,
resembles a simple equation.
1k
MODE A/PF0
• Every instruction assembles into a single, 24-bit word that
can execute in a single instruction cycle.
PROGRAMMABLE I/O
• The syntax is a superset ADSP-2100 Family assembly
language and is completely source and object code compatible with other family members. Programs may need
to be relocated to utilize on-chip memory and conform to
the ADSP-218xN’s interrupt vector and reset vector map.
• Sixteen condition codes are available. For conditional
jump, call, return, or arithmetic instructions, the
condition can be checked and the operation executed in
the same instruction cycle.
• Multifunction instructions allow parallel execution of an
arithmetic instruction, with up to two fetches or one write
to processor memory space, during a single instruction cycle.
The ICE-Port interface consists of the following ADSP218xN pins: EBR, EINT, EE, EBG, ECLK, ERESET,
ELIN, EMS, and ELOUT.
These ADSP-218xN pins must be connected only to the
EZ-ICE connector in the target system. These pins have no
function except during emulation, and do not require pullup or pull-down resistors. The traces for these signals
between the ADSP-218xN and the connector must be kept
as short as possible, no longer than 3 inches.
The following pins are also used by the EZ-ICE: BR, BG,
RESET, and GND.
The EZ-ICE uses the EE (emulator enable) signal to take
control of the ADSP-218xN in the target system. This
causes the processor to use its ERESET, EBR, and EBG
pins instead of the RESET, BR, and BG pins. The BG
output is three-stated. These signals do not need to be
jumper-isolated in the system.
DESIGNING AN EZ-ICE-COMPATIBLE SYSTEM
ADSP-218xN series members have on-chip emulation
support and an ICE-Port, a special set of pins that interface
to the EZ-ICE. These features allow in-circuit emulation
without replacing the target system processor by using only
a 14-pin connection from the target system to the EZ-ICE.
Target systems must have a 14-pin connector to accept the
EZ-ICE’s in-circuit probe, a 14-pin plug.
The EZ-ICE connects to the target system via a ribbon cable
and a 14-pin female plug. The female plug is plugged onto
the 14-pin connector (a pin strip header) on the target
board.
Note: The EZ-ICE uses the same VDD voltage as the VDD
voltage used for VDDEXT. Because the input pins of the
ADSP-218xN series members are tolerant to input voltages
up to 3.6 V, regardless of the value of VDDEXT, the voltage
setting for the EZ-ICE must not exceed 3.3 V.
Target Board Connector for EZ-ICE Probe
Issuing the chip reset command during emulation causes
the DSP to perform a full chip reset, including a reset of its
memory mode. Therefore, it is vital that the mode pins are
set correctly PRIOR to issuing a chip reset command from
the emulator user interface. If a passive method of maintaining mode information is being used (as discussed in Setting
Memory Mode on page 11), it does not matter that the
mode information is latched by an emulator reset. However,
REV. 0
Figure 14. Mode A Pin/EZ-ICE Circuit
The EZ-ICE connector (a standard pin strip header) is
shown in Figure 15. This connector must be added to the
target board design to use the EZ-ICE. Be sure to allow
enough room in the system to fit the EZ-ICE probe onto
the 14-pin connector.
The 14-pin, 2-row pin strip header is keyed at the Pin 7
location—Pin 7 must be removed from the header. The pins
must be 0.025 inch square and at least 0.20 inch in length.
–19–
ADSP-218xN Series
Target System Interface Signals
1
BG
GND
3
4
5
6
7
8
9
10
11
12
EBG
BR
EBR
KEY (NO PIN)
EINT
• EZ-ICE emulation introduces an 8 ns propagation
delay between the target circuitry and the DSP on the
RESET signal.
ELIN
ELOUT
ECLK
• EZ-ICE emulation introduces an 8 ns propagation
delay between the target circuitry and the DSP on the BR
signal.
EMS
EE
RESET
When the EZ-ICE board is installed, the performance on
some system signals changes. Design the system to be compatible with the following system interface signal changes
introduced by the EZ-ICE board:
2
13
14
ERESET
• EZ-ICE emulation ignores RESET and BR, when
single-stepping.
TOP VIEW
Figure 15. Target Board Connector for EZ-ICE
• EZ-ICE emulation ignores RESET and BR when in
Emulator Space (DSP halted).
Pin spacing should be 0.1 0.1 inches. The pin strip header
must have at least 0.15 inch clearance on all sides to accept
the EZ-ICE probe plug.
• EZ-ICE emulation ignores the state of target BR in certain
modes. As a result, the target system may take control of
the DSP’s external memory bus only if bus grant (BG) is
asserted by the EZ-ICE board’s DSP.
Pin strip headers are available from vendors such as 3M,
McKenzie, and Samtec.
Target Memory Interface
For the target system to be compatible with the EZ-ICE
emulator, it must comply with the memory interface guidelines listed below.
PM, DM, BM, IOM, and CM
Design the Program Memory (PM), Data Memory (DM),
Byte Memory (BM), I/O Memory (IOM), and Composite
Memory (CM) external interfaces to comply with worstcase device timing requirements and switching characteristics as specified in this data sheet. The performance of the
EZ-ICE may approach published worst-case specification
for some memory access timing requirements and switching
characteristics.
Note: If the target does not meet the worst-case chip specification for memory access parameters, the circuitry may
not be able to be emulated at the desired CLKIN frequency.
Depending on the severity of the specification violation, the
system may be difficult to manufacture, as DSP components statistically vary in switching characteristic and timing
requirements, within published limits.
Restriction: All memory strobe signals on the ADSP218xN (RD, WR, PMS, DMS, BMS, CMS, and IOMS)
used in the target system must have 10 k pull-up resistors
connected when the EZ-ICE is being used. The pull-up
resistors are necessary because there are no internal pullups to guarantee their state during prolonged three-state
conditions resulting from typical EZ-ICE debugging sessions. These resistors may be removed when the EZ-ICE is
not being used.
–20–
REV. 0
ADSP-218xN Series
SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
K Grade (Commercial)
Parameter
1
VDDINT
VDDEXT
VINPUT2
TAMB
B Grade (Industrial)
Min
Max
Min
Max
Unit
1.71
1.71
VIL = – 0.3
0
1.89
3.6
VIH = + 3.6
70
1.8
1.8
VIL = – 0.3
–40
2.0
3.6
VIH = + 3.6
+85
V
V
V
°C
1Specifications
subject to change without notice.
ADSP-218xN is 3.3 V tolerant (always accepts up to 3.6 V max VIH), but voltage compliance (on outputs, VOH) depends on the input VDDEXT,
because VOH (max) approximately equals VDDEXT (max). This 3.3 V tolerance applies to bidirectional pins (D23–D0, RFS0, RFS1, SCLK0, SCLK1,
TFS0, TFS1, A13 –A 1, PF7–PF0) and input-only pins (CLKIN, RESET, BR, DR0, DR1, PWD).
2The
ELECTRICAL CHARACTERISTICS
Parameter1
Description
Voltage2, 3
VIH
Hi-Level Input
VIL
Lo-Level Input Voltage2, 3
VOH
Hi-Level Output Voltage2, 4, 5
VOL
Lo-Level Output Voltage2, 4, 5
IIH
Hi-Level Input Current3
IIL
Lo-Level Input Current3
IOZH
IDD
Three-State Leakage
Current7
Three-State Leakage
Current7
Supply Current (Idle)9
IDD
Supply Current (Dynamic)10
IOZL
REV. 0
Test Conditions
Min
@ VDDEXT = 1.71 to 2.0 V,
VDDINT = max
@ VDDEXT = 2.1 to 3.6 V,
VDDINT = max
@ VDDEXT ⬉ 2.0 V,
VDDINT = min
@ VDDEXT ⭌ 2.0 V,
VDDINT = min
@ VDDEXT = 1.71 to 2.0 V,
IOH = – 0.5 mA
@ VDDEXT = 2.1 to 2.9 V, IOH
= – 0.5 mA
@ VDDEXT = 3.0 to 3.6 V, IOH
= – 0.5 mA
@ VDDEXT = 1.71 to 3.6 V,
IOH = – 100 µA6
@ VDDEXT = 1.71 to 3.6 V,
IOL = 2.0 mA
@ VDDINT = max,
VIN = 3.6 V
@ VDDINT = max,
VIN = 0 V
@ VDDEXT = max,
VIN = 3.6 V8
@ VDDEXT = max,
VIN = 0 V8
@ VDDINT = 1.8 V,
tCK = 12.5 ns,
TAMB = 25°C
@ VDDINT = 1.8 V,
tCK = 12.5 ns11,
TAMB = 25°C
1.25
–21–
Typ
Max
Unit
V
0.6
V
0.7
V
1.35
V
2.0
V
2.4
V
VDDEXT – 0.3
V
0.4
V
10
µA
10
µA
10
µA
10
µA
6
mA
25
mA
ADSP-218xN Series
ELECTRICAL CHARACTERISTICS
Parameter1
Description
(CONTINUED)
Test Conditions
9
IDD
Supply Current (Idle)
IDD
Supply Current (Dynamic)10
IDD
Supply Current (PowerDown)12
CI
Input Pin Capacitance3, 6
CO
Output Pin
Capacitance6, 7, 12, 13
@ VDDINT = 1.9 V,
tCK = 12.5 ns,
TAMB = 25°C
@ VDDINT = 1.9 V,
tCK = 12.5 ns11,
TAMB = 25°C
@ VDDINT = 1.8 V,
TAMB = 25°C
in Lowest Power Mode
@ VIN = 1.8 V,
fIN = 1.0 MHz,
TAMB = 25°C
@ VIN = 1.8 V,
fIN = 1.0 MHz,
TAMB = 25°C
Min
Typ
Max
Unit
6.5
mA
26
mA
100
µA
8
pF
8
pF
1Specifications
subject to change without notice.
pins: D23–0, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A13–1, PF7–0.
3Input only pins: CLKIN, RESET, BR, DR0, DR1, PWD.
4Output pins: BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, PWDACK, A0, DT0, DT1, CLKOUT, FL2 –FL0, BGH.
5Although specified for TTL outputs, all ADSP-218xN outputs are CMOS-compatible and will drive to V
DDEXT and GND, assuming no dc loads.
6Guaranteed but not tested.
7Three-statable pins: A13–A1, D23–D0, PMS, DMS, BMS, IOMS, CMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RFS1, PF7–PF0.
80 V on BR.
9Idle refers to ADSP-218xN state of operation during execution of IDLE instruction. Deasserted pins are driven to either V
DD or GND.
10I
DD measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (Types 1, 4, 5, 12, 13, 14), 30%
are Type 2 and Type 6, and 20% are idle instructions.
11V = 0 V and 3 V. For typical values for supply currents, refer to Power Dissipation section.
IN
12See ADSP-218x DSP Hardware Reference for details.
13Output pin capacitance is the capacitive load for any three-stated output pin.
2Bidirectional
ABSOLUTE MAXIMUM RATINGS
Internal Supply Voltage (VDDINT)1 . . . . . . . . –0.3 V to +2.2 V
External Supply Voltage (VDDEXT) . . . . . . . . –0.3 V to +4.0 V
Input Voltage2 . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +4.0 V
Output Voltage Swing3 . . . . . . . . . . .–0.5 V to VDDEXT +0.5 V
Operating Temperature Range . . . . . . . . . . . –40ºC to +85ºC
Storage Temperature Range . . . . . . . . . . . . –65ºC to +150ºC
Lead Temperature (5 sec) LQFP . . . . . . . . . . . . . . . –280ºC
1Stresses
greater than those listed above may cause permanent damage to the
device. These are stress ratings only. Functional operation of the device at these
or any other conditions greater than those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
2Applies to Bidirectional pins (D23–0, RFS0, RFS1, SCLK0, SCLK1, TFS0,
TFS1, A13–1, PF7–0) and Input only pins (CLKIN, RESET, BR, DR0, DR1,
PWD).
3Applies to Output pins (BG, PMS, DMS, BMS, IOMS, CMS, RD, WR,
PWDACK, A0, DT0, DT1, CLKOUT, FL2 –0, BGH).
–22–
REV. 0
ADSP-218xN Series
ESD SENSITIVITY
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V
readily accumulate on the human body and test equipment and can discharge without
detection. Although the ADSP-218xN features proprietary ESD protection circuitry,
permanent damage may occur on devices subjected to high-energy electrostatic
discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Power Dissipation
Assumptions:
To determine total power dissipation in a specific application, the following equation should be applied for each
output: C VDD2 f
• External data memory is accessed every cycle with 50%
of the address pins switching.
where: C = load capacitance, f = output switching frequency.
Example: In an application where external data memory
is used and no other outputs are active, power dissipation is
calculated as follows:
• External data memory writes occur every other cycle with
50% of the data pins switching.
• Each address and data pin has a 10 pF total load at the pin.
• Application operates at VDDEXT = 3.3 V and tCK = 30 ns.
Total Power Dissipation = PINT + (C VDDEXT2 f)
P INT = internal power dissipation from Figure 20 on
page 26.
(C VDDEXT2 f) is calculated for each output, as in the
example in Table 13.
Table 13. Example Power Dissipation Calculation
Parameters
Address
Data Output, WR
RD
CLKOUT, DMS
# of Pins
7
9
1
2
× C (pF)
2
10
10
10
10
3.3
3.32
3.32
3.32
Total power dissipation for this example is
PINT + 45.72 mW.
REV. 0
× VDDEXT2 (V)
–23–
× f (MHz)
20.0
20.0
20.0
40.0
PD (mW)
15.25
19.59
2.18
8.70
45.72
ADSP-218xN Series
Environmental Conditions
REFERENCE
SIGNAL
Table 14. Thermal Resistance
1
Rating Description
Thermal Resistance
(Case-to-Ambient)
Thermal Resistance
(Junction-to-Ambient)
Thermal Resistance
(Junction-to-Case)
tMEASURED
Symbol
θCA
LQFP
(°C/W)
48
θJA
VOH
(MEASURED)
VOL
(MEASURED)
tDECAY
OUTPUT STARTS
DRIVING
Output Disable Time
Output pins are considered to be disabled when they have
stopped driving and started a transition from the measured
output high or low voltage to a high impedance state. The
output disable time (tDIS) is the difference of tMEASURED and
tDECAY, as shown in Figure 18. The time is the interval from
when a reference signal reaches a high or low voltage level
to when the output voltages have changed by 0.5 V from the
measured output high or low voltage.
1.5V
2.0V
1.5V
0.8V
Figure 16. Voltage Reference Levels for AC
Measurements (Except Output Enable/Disable)
The decay time, tDECAY, is dependent on the capacitive load,
CL, and the current load, iL, on the output pin. It can be
approximated by the following equation:
C L × 0.5V
tDECAY = ------------------------iL
I OL
from which
TO
OUTPUT
PIN
1.0V
Figure 18. Output Enable/Disable
Test Conditions
OUTPUT
2.0V
VOL (MEASURED) + 0.5V
HIGH-IMPEDANCE STATE. TEST CONDITIONS CAUSE
THIS VOLTAGE LEVEL TO BE APPROXIMATELY 1.5V.
1Where
INPUT
VOH (MEASURED) – 0.5V
OUTPUT STOPS
DRIVING
7.4
the Ambient Temperature Rating (TAMB) is:
TAMB = TCASE – (PD × θCA)
TCASE = Case Temperature in °C
PD = Power Dissipation in W
V OH
(MEASURED)
VOL
(MEASURED)
70.7
2
tDIS
OUTPUT
63.3
50
θJC
tENA
MiniBGA
(°C/W)
1.5V
50pF
t DIS = t MEASURED – t DECAY
is calculated. If multiple pins (such as the data bus) are
disabled, the measurement value is that of the last pin to
stop driving.
Output Enable Time
IOH
Figure 17. Equivalent Loading for AC Measurements
(Including All Fixtures)
Output pins are considered to be enabled when they have
made a transition from a high-impedance state to when they
start driving. The output enable time (tENA) is the interval
from when a reference signal reaches a high or low voltage
level to when the output has reached a specified high or low
trip point, as shown in Figure 18. If multiple pins (such as
the data bus) are enabled, the measurement value is that of
the first pin to start driving.
–24–
REV. 0
ADSP-218xN Series
80
VDDEXT = 3.6V @ –40C
TIMING SPECIFICATIONS
SOURCE CURRENT – mA
60
This section contains timing information for the DSP’s
external signals.
General Notes
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of
others. While addition or subtraction would yield meaningful results for an individual device, the values given in this
data sheet reflect statistical variations and worst cases. Consequently, parameters cannot be added up meaningfully to
derive longer times.
40
VDDEXT = 2.5V @ +85C
20
VDDEXT = 1.8V @ +85C
0
VDDEXT = 3.6V @ –40C
–20
VOL
–40
VVDDEXT
1.8/2.5V@
@+85
+85
C
C
DDEXT==1.8/2.5V
VDDEXT = 3.3V @ +25 C
–60
–80
0
0.5
1.0
1.5
2.0
2.5
SOURCE VOLTAGE – V
3.0
3.5
Figure 19. Typical Output Driver Characteristics
for VDDEXT at 3.6 V, 3.3 V, 2.5 V, and 1.8 V
Timing Notes
Switching characteristics specify how the processor changes
its signals. Designers have no control over this timing—
circuitry external to the processor must be designed for
compatibility with these signal characteristics. Switching
characteristics tell what the processor will do in a given
circumstance. Switching characteristics can also be used to
ensure that any timing requirement of a device connected
to the processor (such as memory) is satisfied.
Timing requirements apply to signals that are controlled by
circuitry external to the processor, such as the data input
for a read operation. Timing requirements guarantee that
the processor operates correctly with other devices.
Frequency Dependency For Timing Specifications
tCK is defined as 0.5 tCKI. The ADSP-218xN uses an input
clock with a frequency equal to half the instruction rate. For
example, a 40 MHz input clock (which is equivalent to
25 ns) yields a 12.5 ns processor cycle (equivalent to
80 MHz). tCK values within the range of 0.5 tCKI period
should be substituted for all relevant timing parameters to
obtain the specification value.
Example: tCKH = 0.5 tCK – 2 ns = 0.5 (12.5 ns) – 2 ns= 4.25 ns
Output Drive Currents
Figure 19 shows typical I-V characteristics for the output
drivers on the ADSP-218xN series.The curves represent the
current drive capability of the output drivers as a function
of output voltage.
Figure 21 shows the typical power-down supply current.
Capacitive Loading
Figure 22 and Figure 23 on page 26 show the capacitive
loading characteristics of the ADSP-218xN.
REV. 0
VDDEXT = 3.3V @ +25C
VOH
–25–
4.0
ADSP-218xN Series
1000
60
V
= 2 .0
T
V D D IN
9V
= 1.
T
V D D IN
V
= 1 .8
T
V D D IN
1V
= 1 .7
V D D IN T
POWER (PINT) – mW
50
45
42 m W
40
38 mW
35
34 mW
30
30 mW
CURRENT (LOG SCALE) – µA
55 m W
55
50 mW
45 m W
40 mW
25
20
55
60
65
70
75
80
14.0
13 . 5 m W
13.0
V
= 2 .0
T
V D D IN
V
= 1 .9
V D D IN T
V
= 1 .8
V D D IN T
= 1.71 V
V D D IN T
POWER (PIDLE) – mW
12.0
10 . 5 m W
10.0
9.5m W
9.0
8 .5 m W
8.0
100
10
12 m W
Figure 21. Typical Power-Down Current
10 .5 m W
9m W
30
25
RISE TIME (0.4V–2.4V) – ns
6.0
55
60
65
70
75
80
85
1/tCK – M Hz
POWER, IDLE n MODES2
12.0
12.0mW
10.5mW
10.0
9.5mW
POWER (PIDLEn) – mW
T = 85 C
VDD = 0V TO 2.0V
7 .5 m W
7.0
5.0
2.0V
1.9V
1.8V
1.7V
0
25
55
85
TEMPERATURE – °C
NOTES
1. REFLECTS ADSP-218xN OPERATION IN LOWEST POWER
MODE. (SEE THE "SYSTEM INTERFACE" CHAPTER OF THE
ADSP-218x DSP HARDWARE REFERENCE FOR DETAILS.)
2. CURRENT REFLECTS DEVICE OPERATING WITH NO
INPUT LOADS.
POW ER, IDLE 1, 2, 4
15.0
=
=
=
=
0
85
1/tCK – M Hz
11.0
VDD
VDD
VDD
VDD
POW ER, INTERNAL 1, 2, 3
8.0
15
10
5
8.5mW
VDD COR E = 1.9V
VDD COR E = 1.8V
0
5.2mW
4.9mW
4.7mW
4.3mW
6.0
4.0
20
4.2mW
3.8mW
3.4mW
50
0
100
150
CL – pF
200
250
300
Figure 22. Typical Output Rise Time vs. Load Capacitance
(at Maximum Ambient Operating Temperature)
2.0
0.0
55
18
60
65
70
75
80
85
16
VALID OUTPUT DELAY OR HOLD – ns
1/tCK – M Hz
NOT ES
VALID F OR ALL TEMPERATURE GRADES.
1
POW ER R EFLEC TS D EVIC E O PERATING WITH NO OUT PUT
LOAD S.
2
TYPICAL POWER D ISSIPATION AT 1.8V O R 1.9V V DDINT AND
25°C, EXCEPT WHER E SPECIFIED.
3
4
IDD MEASUREM ENT TAKEN W ITH ALL INSTRUCTIONS
EXECU TING FROM INTERNAL MEMO RY. 50% O F THE
INSTRUCTIONS ARE MU LTIFUNCTION (TYPES 1, 4, 5, 12, 13,
14), 30% ARE TYPE 2 AND TYPE 6, AND 20% ARE IDLE
INSTRUCTIONS.
IDLE R EFERS TO STATE OF OPER ATION DURIN G EXECUTIO N
OF IDLE INSTRUCTION. DEASSERTED PINS ARE DRIVEN TO
EIT HER V DD OR G ND.
14
12
10
8
6
4
2
NOMINAL
–2
–4
–6
0
50
100
150
200
250
CL – pF
Figure 20. Power vs. Frequency
Figure 23. Typical Output Valid Delay or Hold vs. Load
Capacitance, CL (at Maximum Ambient Operating
Temperature)
–26–
REV. 0
ADSP-218xN Series
Clock Signals and Reset
Table 15. Clock Signals and Reset
Parameter
Timing Requirements:
tCKI
CLKIN Period
tCKIL
CLKIN Width Low
tCKIH
CLKIN Width High
Switching Characteristics:
tCKL
CLKOUT Width Low
CLKOUT Width High
tCKH
tCKOH
CLKIN High to CLKOUT High
Control Signals Timing Requirements:
tRSP
RESET Width Low
tMS
Mode Setup before RESET High
tMH
Mode Hold after RESET High
Min
Max
Unit
25
8
8
40
ns
ns
ns
0.5tCK – 3
0.5tCK – 3
0
5tCK1
7
5
1Applies
8
ns
ns
ns
ns
ns
ns
after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles, assuming stable CLKIN (not including
crystal oscillator start-up time).
tCKI
tCKIH
CLKIN
tCKIL
tCKOH
tCKH
CLKOUT
tCKL
MODE A D
tMS
tMH
RESET
tRSP
Figure 24. Clock Signals and Reset
REV. 0
–27–
ADSP-218xN Series
Interrupts and Flags
Table 16. Interrupts and Flags
Parameter
Min
Timing Requirements:
tIFS
IRQx, FI, or PFx Setup before CLKOUT Low1, 2, 3, 4
tIFH
IRQx, FI, or PFx Hold after CLKOUT High1, 2, 3, 4
Switching Characteristics:
tFOH
Flag Output Hold after CLKOUT Low5
tFOD
Flag Output Delay from CLKOUT Low5
Max
0.25tCK + 10
0.25tCK
Unit
ns
ns
0.5tCK – 5
0.5tCK + 4
ns
ns
1If
IRQx and FI inputs meet tIFS and tIFH setup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be
recognized on the following cycle. (Refer to “Interrupt Controller Operation” in the Program Control chapter of the ADSP-218x DSP Hardware Reference
for further information on interrupt servicing.)
2Edge-sensitive interrupts require pulsewidths greater than 10 ns; level-sensitive interrupts must be held low until serviced.
3
IRQx = IRQ0, IRQ1, IRQ2, IRQL0, IRQL1, IRQLE.
4PFx = PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7.
5Flag Outputs = PFx, FL0, FL1, FL2, FO.
tFOD
CLKOUT
tFOH
FLAG
OUTPUTS
tIFH
IRQx
FI
PFx
tIFS
Figure 25. Interrupts and Flags
–28–
REV. 0
ADSP-218xN Series
Bus Request–Bus Grant
Table 17. Bus Request–Bus Grant
Parameter
Min
Timing Requirements:
tBH
BR Hold after CLKOUT High1
tBS
BR Setup before CLKOUT Low1
Switching Characteristics:
tSD
CLKOUT High to xMS, RD, WR Disable2
tSDB
xMS, RD, WR Disable to BG Low
BG High to xMS, RD, WR Enable
tSE
tSEC
xMS, RD, WR Enable to CLKOUT High
tSDBH
xMS, RD, WR Disable to BGH Low3
tSEH
BGH High to xMS, RD, WR Enable3
Max
0.25tCK + 2
0.25tCK + 8
ns
ns
0.25tCK + 8
0
0
0.25tCK – 3
0
0
1BR
Unit
ns
ns
ns
ns
ns
ns
is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be
recognized on the following cycle. Refer to the ADSP-2100 Family User’s Manual for BR/BG cycle relationships.
2xMS = PMS, DMS, CMS, IOMS, BMS.
3BGH is asserted when the bus is granted and the processor or BDMA requires control of the bus to continue.
tBH
CLKOUT
BR
tBS
CLKOUT
PMS, DMS
BMS, RD
CMS, WR,
IOMS
BG
BGH
tSD
tSEC
tSDB
tSE
tSDBH
tSEH
Figure 26. Bus Request–Bus Grant
REV. 0
–29–
ADSP-218xN Series
Memory Read
Table 18. Memory Read
Parameter
Min
Timing Requirements:
tRDD
RD Low to Data Valid1
tAA
A13–0, xMS to Data Valid2
tRDH
Data Hold from RD High
Switching Characteristics:
tRP
RD pulsewidth
tCRD
CLKOUT High to RD Low
tASR
A13–0, xMS Setup before RD Low
tRDA
A13–0, xMS Hold after RD Deasserted
tRWR
RD High to RD or WR Low
1w
Max
Unit
0.5tCK – 5 + w
0.75tCK – 6 + w
ns
ns
ns
0
0.5tCK – 3 + w
0.25tCK – 2
0.25tCK – 3
0.25tCK – 3
0.5tCK – 3
0.25tCK + 4
ns
ns
ns
ns
ns
= wait states x tCK.
= PMS, DMS, CMS, IOMS, BMS.
2xMS
CLKOUT
A0–A13
DMS, PMS,
BMS, IOMS,
CMS
tRDA
RD
tASR
tRP
tCRD
tRWR
D0–D23
tRDD
tAA
tRDH
WR
Figure 27. Memory Read
–30–
REV. 0
ADSP-218xN Series
Memory Write
Table 19. Memory Write
1
Parameter
Min
Max
Switching Characteristics:
tDW
Data Setup before WR High1
tDH
Data Hold after WR High
tWP
WR pulsewidth
tWDE
WR Low to Data Enabled
tASW
A13–0, xMS Setup before WR Low2
tDDR
Data Disable before WR or RD Low
tCWR
CLKOUT High to WR Low
tAW
A13–0, xMS Setup before WR Deasserted
A13–0, xMS Hold after WR Deasserted
tWRA
tWWR
WR High to RD or WR Low
0.5tCK– 4 + w
0.25tCK – 1
0.5tCK – 3 + w
0
0.25tCK – 3
0.25tCK – 3
0.25tCK – 2
0.75tCK – 5 + w
0.25tCK – 1
0.5tCK – 3
w = wait states tCK.
= PMS, DMS, CMS, IOMS, BMS.
2xMS
CLKOUT
A0–A13
DMS, PMS,
BMS, CMS,
IOMS
tWRA
WR
tASW
tWWR
tWP
tAW
tDH
tCWR
D0–D23
tDW
tWDE
RD
Figure 28. Memory Write
REV. 0
–31–
tDDR
0.25tCK + 4
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ADSP-218xN Series
Serial Ports
Table 20. Serial Ports
Parameter
Min
Timing Requirements:
tSCK
SCLK Period
tSCS
DR/TFS/RFS Setup before SCLK Low
tSCH
DR/TFS/RFS Hold after SCLK Low
SCLKIN Width
tSCP
Switching Characteristics:
tCC
CLKOUT High to SCLKOUT
tSCDE
SCLK High to DT Enable
tSCDV
SCLK High to DT Valid
tRH
TFS/RFSOUT Hold after SCLK High
tRD
TFS/RFSOUT Delay from SCLK High
DT Hold after SCLK High
tSCDH
tTDE
TFS (Alt) to DT Enable
tTDV
TFS (Alt) to DT Valid
tSCDD
SCLK High to DT Disable
tRDV
RFS (Multichannel, Frame Delay Zero) to DT Valid
CLKOUT
tCC
Max
30
4
7
12
ns
ns
ns
ns
0.25tCK
0
0.25tCK + 6
12
0
12
0
0
12
12
12
t CC
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCK
SCLK
tSCP
tSCS
DR
TFSI N
RFSIN
tSCP
tSCH
tRD
tRH
RFSOUT
TFSOUT
tSCDD
tSCDV
tSCDH
tSCDE
DT
tTDE
tTDV
TFS OUT
ALTERNATE
FRAME
MODE
tRDV
RFSOUT
MULTICHANNEL
MODE,
FRAME DELAY 0
(MFD = 0)
tTDE
tTDV
TFSIN
ALTERNATE
FRAME
MODE
tRDV
RFSIN
MULTICHANNEL
MODE,
FRAME DELAY 0
(MFD = 0)
Figure 29. Serial Ports
–32–
REV. 0
ADSP-218xN Series
IDMA Address Latch
Table 21. IDMA Address Latch
Parameter
Min
Timing Requirements:
tIALP
Duration of Address Latch1, 2
tIASU
IAD15–0 Address Setup before Address Latch End2
tIAH
IAD15–0 Address Hold after Address Latch End2
tIKA
IACK Low before Start of Address Latch2, 3
tIALS
Start of Write or Read after Address Latch End2, 3
tIALD
Address Latch Start after Address Latch End1, 2
10
5
3
0
3
2
1Start
of Address Latch = IS Low and IAL High.
of Address Latch = IS High or IAL Low.
3Start of Write or Read = IS Low and IWR Low or IRD Low.
2End
IACK
tIKA
tIALD
IAL
tIALP
tIALP
IS
IAD15–0
tIASU
tIAH
tIASU
tIAH
tIALS
IRD OR
IWR
Figure 30. IDMA Address Latch
REV. 0
–33–
Max
Unit
ns
ns
ns
ns
ns
ns
ADSP-218xN Series
IDMA Write, Short Write Cycle
Table 22. IDMA Write, Short Write Cycle
Parameter
Min
Timing Requirements:
tIKW
IACK Low before Start of Write1
tIWP
Duration of Write1, 2
tIDSU
IAD15–0 Data Setup before End of Write2, 3, 4
IAD15–0 Data Hold after End of Write2, 3, 4
tIDH
Switching Characteristic:
tIKHW
Start of Write to IACK High
Max
0
10
3
2
Unit
ns
ns
ns
ns
10
ns
1Start
of Write = IS Low and IWR Low.
of Write = IS High or IWR High.
3If Write Pulse ends before IACK Low, use specifications t
IDSU, tIDH.
4If Write Pulse ends after IACK Low, use specifications t
IKSU, tIKH.
2End
tIKW
IACK
tIKHW
IS
tIWP
IWR
tIDSU
IAD15–0
tIDH
DATA
Figure 31. IDMA Write, Short Write Cycle
–34–
REV. 0
ADSP-218xN Series
IDMA Write, Long Write Cycle
Table 23. IDMA Write, Long Write Cycle
Parameter
Min
Timing Requirements:
tIKW
IACK Low before Start of Write1
tIKSU
IAD15–0 Data Setup before End of Write2, 3, 4
tIKH
IAD15–0 Data Hold after End of Write2, 3, 4
Switching Characteristics:
tIKLW
Start of Write to IACK Low4
Start of Write to IACK High
tIKHW
Max
0
0.5tCK + 5
0
ns
ns
ns
1.5tCK
10
1Start
Unit
ns
ns
of Write = IS Low and IWR Low.
Write Pulse ends before IACK Low, use specifications tIDSU, tIDH.
3If Write Pulse ends after IACK Low, use specifications t
IKSU, tIKH.
4This is the earliest time for IACK Low from Start of Write. For IDMA Write cycle relationships, please refer to the ADSP-2100 Family User’s Manual.
2If
tIKW
IACK
tIKHW
tIKLW
IS
IWR
tIKSU
tIKH
DATA
IAD15–0
Figure 32. IDMA Write, Long Write Cycle
REV. 0
–35–
ADSP-218xN Series
IDMA Read, Long Read Cycle
Table 24. IDMA Read, Long Read Cycle
Parameter
Min
Timing Requirements:
tIKR
IACK Low before Start of Read1
tIRK
End of read after IACK Low2
Switching Characteristics:
tIKHR
IACK High after Start of Read1
tIKDS
IAD15–0 Data Setup before IACK Low
tIKDH
IAD15 –0 Data Hold after End of Read2
tIKDD
IAD15–0 Data Disabled after End of Read2
tIRDE
IAD15–0 Previous Data Enabled after Start of Read
tIRDV
IAD15–0 Previous Data Valid after Start of Read
tIRDH1
IAD15–0 Previous Data Hold after Start of Read (DM/PM1)3
IAD15–0 Previous Data Hold after Start of Read (PM2)4
tIRDH2
Max
0
2
Unit
ns
ns
10
0.5tCK – 3
0
10
0
11
2tCK – 5
tCK – 5
ns
ns
ns
ns
ns
ns
ns
ns
1Start
of Read = IS Low and IRD Low.
of Read = IS High or IRD High.
3DM read or first half of PM read.
4Second half of PM read.
2End
IACK
tiKHR
tIKR
IS
tIRK
IRD
tIKDH
tIKDS
tIRDE
PREVIOUS
DATA
IAD15–0
tIRDV
READ
DATA
tiKDD
tIRDH1 OR tIRDH2
Figure 33. IDMA Read, Long Read Cycle
–36–
REV. 0
ADSP-218xN Series
IDMA Read, Short Read Cycle
Table 25. IDMA Read, Short Read Cycle
Parameter1, 2
Timing Requirements:
tIKR
IACK Low before Start of Read3
tIRP1
Duration of Read (DM/PM1)4
tIRP2
Duration of Read (PM2)5
Switching Characteristics:
tIKHR
IACK High after Start of Read3
IAD15–0 Data Hold after End of Read6
tIKDH
tIKDD
IAD15–0 Data Disabled after End of Read6
tIRDE
IAD15–0 Previous Data Enabled after Start of Read
tIRDV
IAD15–0 Previous Data Valid after Start of Read
Min
Max
Unit
0
10
10
2tCK – 5
tCK – 5
ns
ns
ns
10
0
10
0
10
1Short
ns
ns
ns
ns
ns
Read Only must be disabled in the IDMA overlay memory mapped register. This mode is disabled by clearing (=0) bit 14 of the IDMA overlay
register, and is disabled by default upon reset.
2Consider using the Short Read Only mode, instead, because Short Read mode is not applicable at high clock frequencies.
3Start of Read = IS Low and IRD Low.
4DM Read or first half of PM Read.
5Second half of PM Read.
6End of Read = IS High or IRD High.
IACK
tIKR
tIKHR
IS
tIRP
IRD
tIKDH
tIRDE
PREVIOUS
DATA
IAD15–0
tiRDV
tIKDD
Figure 34. IDMA Read, Short Read Cycle
REV. 0
–37–
ADSP-218xN Series
IDMA Read, Short Read Cycle in Short Read Only Mode
Table 26. IDMA Read, Short Read Cycle in Short Read Only Mode
Parameter1
Min
Timing Requirements:
tIKR
IACK Low before Start of Read2
tIRP
Duration of Read3
Switching Characteristics:
tIKHR
IACK High after Start of Read2
tIKDH
IAD15–0 Previous Data Hold after End of Read3
tIKDD
IAD15–0 Previous Data Disabled after End of Read3
tIRDE
IAD15–0 Previous Data Enabled after Start of Read
tIRDV
IAD15–0 Previous Data Valid after Start of Read
Max
0
10
Unit
ns
ns
10
0
10
0
10
ns
ns
ns
ns
ns
1Short
Read Only is enabled by setting Bit 14 of the IDMA overlay Register to 1 (0x3FE7). Short Read Only can be enabled by the processor core writing
to the register or by an external host writing to the register. Disabled by default.
2Start of Read = IS Low and IRD Low. Previous data remains until end of read.
3End of Read = IS High or IRD High.
IA CK
t IK R
t IK H R
IS
tIRP
IRD
tIK D H
tIR D E
PR EVIO U S
DA TA
IAD 15– 0
t IR D V
tIK D D
L EG EN D :
IM P L IE S T H A T IS A N D IR D C A N B E
H EL D IN D E F IN IT EL Y B Y H O ST
Figure 35. IDMA Read, Short Read Cycle in Short Read Only Mode
–38–
REV. 0
ADSP-218xN Series
deassertion of RESET. The multiplexed pins DT1/FO,
TFS1/IRQ1, RFS1/IRQ0, and DR1/FI, are mode
selectable by setting Bit 10 (SPORT1 configure) of the
System Control Register. If Bit 10 = 1, these pins have serial
port functionality. If Bit 10 = 0, these pins are the external
interrupt and flag pins. This bit is set to 1 by default, upon
reset.
LQFP Package Pinout
The LQFP package pinout is shown in the illustration below
and in Table 27. Pin names in bold text in the table replace
the plain-text-named functions when Mode C = 1. A + sign
separates two functions when either function can be active
for either major I/O mode. Signals enclosed in brackets [ ]
are state bits latched from the value of the pin at the
77 D17
76 D16
79 D19
78 D18
81 D20
80 GND
82 D21
83 D22
84 D23
86 FL1
85 FL2
87 FL0
89 PF2 [MODE C]
88 PF3 [MODE D]
PWD
90 VDDEXT
91
93 PF1 [MODE B]
92 GND
95 BGH
94 PF0 [MODE A]
96 PWDACK
98 A1/IAD0
97 A0
99 A2/IAD1
100 A3/IAD2
100-LEAD LQFP PIN CONFIGURATION
75 D15
A4/IAD3
1
A5/IAD4
2
GND
3
73 D13
A6/IAD5
4
72
D12
A7/IAD6
5
71
GND
A8/IAD7
6
70
D11
A9/IAD8
7
69 D10
A10/IAD9
8
68 D9
PIN 1
IDENTIFIER
74 D14
67 VDDEXT
66 GND
A11/IAD10 9
A12/IAD11 10
65 D8
A13/IAD12 11
GND 12
64
ADSP-218xN
CLKIN 13
XTAL 14
62 D5/IAL
61 D4/IS
VDDEXT 15
60 GND
VDD INT
CLKOUT 16
50
ELIN 49
EINT
ECLK 47
ELOUT 48
EE 46
EMS 45
ERESET
GND
VDDEXT
TFS0
IRQL1+PF6
RFS1/IRQ0
–39–
RESET 44
EBR
43
51
SCLK1 42
CMS 25
41
EBG
BR
39
IOMS 24
53
52
DR1/FI 40
BG
PMS 23
DT1/FO 37
TFS1/IRQ1 38
54
36
D0/IAD13
DMS 22
SCLK0 35
55
DR0 34
D1/IAD14
BMS 21
RFS0 33
56
32
D2/IAD15
RD 20
DT0 31
D3/IACK
57
IRQ2+PF7 30
58
WR 19
29
VDDINT 18
GND 28
59
IRQL0+PF5 27
GND 17
IRQE+PF4 26
REV. 0
D7/IWR
63 D6/IRD
TOP VIEW
(Not to Scale)
ADSP-218xN Series
Table 27. LQFP Package Pinout
Table 27. LQFP Package Pinout (Continued)
Pin #
Pin Name
Pin #
Pin Name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
A4/IAD3
A5/IAD4
GND
A6/IAD5
A7/IAD6
A8/IAD7
A9/IAD8
A10/IAD9
A11/IAD10
A12/IAD11
A13/IAD12
GND
CLKIN
XTAL
VDDEXT
CLKOUT
GND
VDDINT
WR
RD
BMS
DMS
PMS
IOMS
CMS
IRQE + PF4
IRQL0 + PF5
GND
IRQL1 + PF6
IRQ2 + PF7
DT0
TFS0
RFS0
DR0
SCLK0
VDDEXT
DT1/FO
TFS1/IRQ1
RFS1/IRQ0
DR1/FI
GND
SCLK1
ERESET
RESET
EMS
EE
ECLK
ELOUT
ELIN
EINT
EBR
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
BR
EBG
BG
D0/IAD13
D1/IAD14
D2/IAD15
D3/IACK
VDDINT
GND
D4/IS
D5/IAL
D6/IRD
D7/IWR
D8
GND
VDDEXT
D9
D10
D11
GND
D12
D13
D14
D15
D16
D17
D18
D19
GND
D20
D21
D22
D23
FL2
FL1
FL0
PF3 [Mode D]
PF2 [Mode C]
VDDEXT
PWD
GND
PF1 [Mode B]
PF0 [Mode A]
BGH
PWDACK
A0
A1/IAD0
A2/IAD1
A3/IAD2
–40–
REV. 0
ADSP-218xN Series
Mini-BGA Package Pinout
The Mini-BGA package pinout is shown in the illustration
below and in Table 28. Pin names in bold text in the table
replace the plain text named functions when Mode C = 1.
A + sign separates two functions when either function can
be active for either major I/O mode. Signals enclosed in
brackets [ ] are state bits latched from the value of the pin
at the deassertion of RESET. The multiplexed pins
DT1/FO, TFS1/IRQ1, RFS1/IRQ0, and DR1/FI, are mode
selectable by setting Bit 10 (SPORT1 configure) of the
System Control Register. If Bit 10 = 1, these pins have serial
port functionality. If Bit 10 = 0, these pins are the external
interrupt and flag pins. This bit is set to 1 by default upon
reset.
144-BALL MINI-BGA PACKAGE PINOUT (BOTTOM VIEW)
11
10
9
8
7
6
5
4
3
GND
GND
D22
NC
NC
NC
GND
NC
A0
GND
A1/IAD0
A2/IAD1
A
D16
D17
D18
D20
D23
V D D E XT
GND
NC
NC
GND
A3/IAD2
A4/IAD3
B
D14
NC
D15
D19
D21
V D D E XT
PWD
A7/IAD6
PWDACK
C
GND
NC
D12
D13
NC
PF2
[M ODE C]
PF1
[M ODE B]
A9/IAD8
BGH
D10
GND
GND
GND
PF3
[M ODE D]
PF0
[M ODE A]
FL 0
D9
NC
D8
D4 /I S
NC
NC
GND
NC
VD D INT
EBG
EI NT
ECLK
REV. 0
V D D E XT
FL 2
A5/IAD4
RD
NC
A8/IAD7
2
1
12
A6/IAD5
WR
NC
D
V D D E XT
E
NC
A13/IAD12
F
V D D E XT
D7 /I WR
NC
NC
FL 1
A11/IAD10
D5 /IAL
D6/IRD
NC
NC
NC
A10/IAD9
GND
NC
XT AL
G
GND
D3/IACK
D2/IAD15
TF S0
DT0
VD D I N T
GND
GND
GND
CLKIN
H
VD D I N T
D1/IAD14
BG
RF S1 /IRQ0
D0/IAD13
CL KOUT
J
BR
EBR
ERESET
SCLK1
TF S1 / IRQ 1
EL IN
RESET
GND
DR0
EM S
NC
GND
DR1/FI
EL O UT
EE
D11
SCLK0
V D D E XT
V D D E XT
NC
NC
RFS0
DMS
BMS
PM S
GND
IO M S
DT 1 / F O
GND
CMS
–41–
A12/IAD11
I RQ L 1 + PF 6
NC
VD D I NT
NC
NC
K
IRQ E + PF 4
L
IRQ 2 + PF 7 I RQ L 0 + PF 5
M
NC
ADSP-218xN Series
Table 28. Mini-BGA Package Pinout
Table 28. Mini-BGA Package Pinout
(Continued)
Ball #
Pin Name
Ball #
Pin Name
A01
A02
A03
A04
A05
A06
A07
A08
A09
A10
A11
A12
B01
B02
B03
B04
B05
B06
B07
B08
B09
B10
B11
B12
C01
C02
C03
C04
C05
C06
C07
C08
C09
C10
C11
C12
D01
D02
D03
D04
D05
D06
D07
D08
D09
D10
D11
D12
E01
E02
A2/IAD1
A1/IAD0
GND
A0
NC
GND
NC
NC
NC
D22
GND
GND
A4/IAD3
A3/IAD2
GND
NC
NC
GND
VDDEXT
D23
D20
D18
D17
D16
PWDACK
A6/IAD5
RD
A5/IAD4
A7/IAD6
PWD
VDDEXT
D21
D19
D15
NC
D14
NC
WR
NC
BGH
A9/IAD8
PF1 [MODE B]
PF2 [MODE C]
NC
D13
D12
NC
GND
VDDEXT
VDDEXT
E03
E04
E05
E06
E07
E08
E09
E10
E11
E12
F01
F02
F03
F04
F05
F06
F07
F08
F09
F10
F11
F12
G01
G02
G03
G04
G05
G06
G07
G08
G09
G10
G11
G12
H01
H02
H03
H04
H05
H06
H07
H08
H09
H10
H11
H12
J01
J02
J03
J04
J05
A8/IAD7
FL0
PF0 [MODE A]
FL2
PF3 [MODE D]
GND
GND
VDDEXT
GND
D10
A13/IAD12
NC
A12/IAD11
A11/IAD10
FL1
NC
NC
D7/IWR
D11
D8
NC
D9
XTAL
NC
GND
A10/IAD9
NC
NC
NC
D6/IRD
D5/IAL
NC
NC
D4/IS
CLKIN
GND
GND
GND
VDDINT
DT0
TFS0
D2/IAD15
D3/IACK
GND
NC
GND
CLKOUT
VDDINT
NC
VDDEXT
VDDEXT
–42–
REV. 0
ADSP-218xN Series
Table 28. Mini-BGA Package Pinout
(Continued)
Ball #
Pin Name
J06
J07
J08
J09
J10
J11
J12
K01
K02
K03
K04
K05
K06
K07
K08
K09
K10
K11
K12
L01
L02
L03
L04
L05
L06
L07
L08
L09
L10
L11
L12
M01
M02
M03
M04
M05
M06
M07
M08
M09
M10
M11
M12
SCLK0
D0/IAD13
RFS1/IRQ0
BG
D1/IAD14
VDDINT
VDDINT
NC
NC
NC
BMS
DMS
RFS0
TFS1/IRQ1
SCLK1
ERESET
EBR
BR
EBG
IRQE + PF4
NC
IRQL1 + PF6
IOMS
GND
PMS
DR0
GND
RESET
ELIN
ELOUT
EINT
IRQL0 + PF5
IRQL2 + PF7
NC
CMS
GND
DT1/FO
DR1/FI
GND
NC
EMS
EE
ECLK
REV. 0
–43–
ADSP-218xN Series
OUTLINE DIMENSIONS
Dimensions in outline dimension drawings are shown in millimeters.
144-BALL MINI-BGA
(CA-144)
A1 CO RNER INDEX
TRI ANG LE
10.10
10.00 SQ
9.90
12 11 10 9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
8.80
BSC
SQ
0.80
BSC
BALL
PITCH
BOTTOM VIEW
TOP VIEW
DETAIL A
1.40
MAX
1.00
0.85
0.43
NOTES:
0.25
1. DIMENSIONS IN MILLIMETERS .
2. ACTUAL POSITION OF THE BALL GRID IS
WITHIN 0.15 OF ITS IDEAL POSITION, RELATIVE
TO THE PACKAGE EDGES.
0.55
0.50
0.45
BALL
DIAMETER
3. ACTUAL POSITION OF EACH BALL IS WITHIN 0.08
OF ITS IDEAL POSITION, RELATIVE TO THE
BALL GRID.
4. CENTER DIMENSIONS ARE NOMINAL.
0.10
MAX
SEATING
PLANE
DETAIL A
100-LEAD METRIC THIN PLASTIC QUAD FLATPACK (LQFP)
(ST-100)
16.20
16.00 SQ
15.80
1.60 MAX
0.75
0.60 TYP
0.50
12
T YP
14.05
14.00 SQ
13.95
12.00 TYP BSC
100
1
76
75
SEATING
PLANE
TO P V IEW
(PINS DOWN)
0.08
MAX LEAD
COPLANARITY
6 ± 4
25
26
0 - 7
0.15
0.05
51
50
0.50
BSC (LEAD PITCH)
NOTES:
1. DIMENSIONS IN MILLIMETERS.
0.27
0.22 TYP (LEAD WIDTH)
0.17
2. THE ACTUAL POSITION OF EACH L EAD IS WITHIN 0.08 OF ITS
IDEAL POSITION, WHEN MEASURED IN THE LATERAL DIRECTION.
3. CENTER DIMENSIONS ARE NOMINAL.
–44–
REV. 0
ADSP-218xN Series
ORDERING GUIDE
Table 29. Ordering Guide
Part
Number
Ambient
Temperature
Range
Instruction
Rate (MHz)
Package
Description
Package
Option
ADSP-2184NKST-320
ADSP-2184NBST-320
ADSP-2185NKST-320
ADSP-2185NBST-320
ADSP-2186NKST-320
ADSP-2186NBST-320
ADSP-2187NKST-320
ADSP-2187NBST-320
ADSP-2188NKST-320
ADSP-2188NBST-320
ADSP-2189NKST-320
ADSP-2189NBST-320
ADSP-2184NKCA-320
ADSP-2184NBCA-320
ADSP-2185NKCA-320
ADSP-2185NBCA-320
ADSP-2186NKCA-320
ADSP-2186NBCA-320
ADSP-2187NKCA-320
ADSP-2187NBCA-320
ADSP-2188NKCA-320
ADSP-2188NBCA-320
ADSP-2189NKCA-320
ADSP-2189NBCA-320
0ºC to 70ºC
–40ºC to +85ºC
0ºC to 70ºC
–40ºC to +85ºC
0ºC to 70ºC
–40ºC to +85ºC
0ºC to 70ºC
–40ºC to +85ºC
0ºC to 70ºC
–40ºC to +85ºC
0ºC to 70ºC
–40ºC to +85ºC
0ºC to 70ºC
–40ºC to 85ºC
0ºC to 70ºC
–40ºC to +85ºC
0ºC to 70ºC
–40ºC to +85ºC
0ºC to 70ºC
–40ºC to +85ºC
0ºC to 70ºC
–40ºC to +85ºC
0ºC to 70ºC
–40ºC to +85ºC
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
100-Lead LQFP
100-Lead LQFP
100-Lead LQFP
100-Lead LQFP
100-Lead LQFP
100-Lead LQFP
100-Lead LQFP
100-Lead LQFP
100-Lead LQFP
100-Lead LQFP
100-Lead LQFP
100-Lead LQFP
144-Ball MBGA
144-Ball MBGA
144-Ball MBGA
144-Ball MBGA
144-Ball MBGA
144-Ball MBGA
144-Ball MBGA
144-Ball MBGA
144-Ball MBGA
144-Ball MBGA
144-Ball MBGA
144-Ball MBGA
ST-100
ST-100
ST-100
ST-100
ST-100
ST-100
ST-100
ST-100
ST-100
ST-100
ST-100
ST-100
CA-144
CA-144
CA-144
CA-144
CA-144
CA-144
CA-144
CA-144
CA-144
CA-144
CA-144
CA-144
REV. 0
–45–