PHILIPS FBL2041 3.3v btl 7-bit futurebus transceiver standard a-port Datasheet

INTEGRATED CIRCUITS
FBL2041
FBL2041I
3.3V BTL 7-bit Futurebus+ transceiver
(standard A-port)
Product specification
Supersedes data of 1998 May 11
IC23 Data Handbook
1999 Apr 27
Philips Semiconductors
Product specification
FBL2041
FBL2041I
3.3V BTL 7-bit Futurebus+ transceiver (standard A-port)
The FBL2041/FBL2041I is pin and function compatible with FB2041
but operates at a 3.3V supply voltage, greatly reducing power
consumption.
FEATURES
• 7-bit BTL transceiver
• Separate I/O on TTL A-port
• Inverting
• Three separate pairs of driver enables in a 1 bit, 3 bit, 3 bit
The B-port interfaces to “Backplane Transceiver Logic” (See the
IEEE 1194.1 BTL standard). BTL features low power consumption
by reducing voltage swing (1Vp-p, between 1V and 2V) and reduced
capacitive loading by placing an internal series diode on the drivers.
BTL also provides incident wave switching, a necessity for high
performance backplanes.
arrangement
• Drives heavily loaded backplanes with equivalent load
impedances down to 10Ω.
• High drive 100mA BTL open collector drivers on B-port
• Allows incident wave switching in heavily loaded backplane buses
• Reduced BTL voltage swing produces less noise and reduces
There are three separate pairs of driver enables in a 1 bit, 3 bit, 3 bit
arrangement. The TTL/BTL output drivers for bit 0 are enabled with
OEA1/OEB1, output drivers for bits 1–2–3 are enabled with
OEA2/OEB2 and output drivers for bits 4–5–6 are enabled with
OEA3/OEB3.
power consumption
• Built-in precision band-gap reference provides accurate receiver
The A-port operates at TTL levels with separate I/O. The 3-state
A-port drivers are enabled when OEAn goes High after an extra 6ns
delay which is built in to provide a break-before-make function.
When OEAn goes Low, A-port drivers become High impedance
without any extra delay. During power on/off cycles, the A-port
drivers are held in a High impedance state when VCC is below 1.3V.
thresholds and improved noise immunity
• Compatible with IEEE Futurebus+ or proprietary BTL backplanes
• Controlled output ramp and multiple GND pins minimize ground
bounce
• Each BTL driver has a dedicated Bus GND for a signal return
• Glitch-free power up/power down operation
• Low ICC current
• Tight output skew
• Supports live insertion
• Pins for the optional JTAG boundary scan function are provided
• High density packaging in plastic Quad Flatpack
• 5V compatible I/O on A-port
• Industrial temperature range option available as FBL2041I
The B-port has an output enable, OEB0, which affects all seven
drivers. When OEB0 is High and OEBn is Low the output driver will
be enabled. When OEB0 is Low or if OEBn is High, the B-port
drivers will be inactive and at the level of the backplane signal.
To support live insertion, OEB0 is held Low during power on/off
cycles to insure glitch free B port drivers. Proper bias for B port
drivers during live insertion is provided by the BIAS V pin when at a
3.3V level while VCC is Low. If live insertion is not a requirement, the
BIAS V pin should be tied to a VCC pin.
The LOGIC GND and BUS GND pins are isolated in the package to
minimize noise coupling between the BTL and TTL sides. These
pins should be tied to a common ground external to the package.
DESCRIPTION
Each BTL driver has an associated BUS GND pin that acts as a
signal return path and these BUS GND pins are internally isolated
from each other. In the event of a ground return fault, a “hard” signal
failure occurs instead of a pattern dependent error that may be very
infrequent and impossible to trouble-shoot.
The FBL2041/FBL2041I is a 7-bit bidirectional BTL transceiver and
is intended to provide the electrical interface to a high performance
wired-OR bus. The FBL2041 is an inverting transceiver.
The B-port drivers are Low-capacitance open collectors with
controlled ramp and are designed to sink 100mA. Precision band
gap references on the B-port insure very good noise margins by
limiting the switching threshold to a narrow region centered at 1.55V.
JTAG boundary scan functionality is provided as an option with
signals TMS, TCK, TDI and TDO. When this option is not present,
TMS and TCK are no-connects (no bond wires) and TDI and TDO
are shorted together internally.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
TYPICAL
UNIT
tPLH
tPHL
Propagation delay
AIn to Bn
4.2
3.5
ns
tPLH
tPHL
Propagation delay
Bn to AOn
4.8
4.9
ns
COB
Output capacitance (B0 - B6 only)
6
pF
IOL
Output current (B0 - B6 only)
100
mA
Standby
ICC
Supply
Su
ly Current
5.2
AIn to Bn (outputs Low or High)
3.2
Bn to AOn (outputs Low)
13.5
Bn to AOn (outputs High)
10.7
mA
ORDERING INFORMATION
PACKAGE
COMMERCIAL RANGE
VCC = 3.3V±10%; Tamb = 0 to +70°C
INDUSTRIAL RANGE
VCC = 3.3V±10%; Tamb = –40 to +85°C
DWG
No.
52-pin Plastic Quad Flatpack
FBL2041 BB
FBL2041I BB
SOT379-1
1999 Apr 27
2
853-2040 21374
Philips Semiconductors
Product specification
3.3V BTL 7-bit Futurebus+ transceiver (standard A-port)
FBL2041
FBL2041I
BUS GND
B0
TMS (option)
TCK (option)
BUS VCC
OEB0
OEB1
BIAS V
OEA1
LOGIC VCC
AI0
AO0
AO1
PIN CONFIGURATION
52 51 50 49 48 47 46 45 44 43 42 41 40
LOGIC GND
1
39
BUS GND
AI1
2
38
B1
AI2
3
37
BUS GND
AO2
4
36
B2
LOGIC GND
5
35
BUS GND
AO3
6
34
B3
LOGIC GND
7
33
BUS GND
AI3
8
32
B4
AI4
9
31
BUS GND
AO4
10
30
B5
LOGIC GND
11
29
BUS GND
AO5
12
28
B6
LOGIC GND
13
27
N/C
7-Bit Transceiver
52-lead PQFP
OEB3
OEB2
OEA3
BUS VCC
TDI (option)
OEA2
TDO (option)
LOGIC GND
AI6
LOGIC VCC
AO6
AI5
LOGIC GND
14 15 16 17 18 19 20 21 22 23 24 25 26
SG00115
PIN DESCRIPTION
SYMBOL
PIN NUMBER
TYPE
NAME AND FUNCTION
AI0 – AI6
51, 2, 3, 8, 9, 14, 18
Input
AO0 – AO6
50, 52, 4, 6, 10, 12, 16
Output
B0 – B6
40, 38, 36, 34, 32, 30, 28
I/O
OEB0
46
Input
Enables the Bn outputs when High
OEB1
45
Input
Enables the B0 output when Low
OEB2
25
Input
Enables the B1 – B3 outputs when Low
OEB3
26
Input
Enables the B4 – B6 outputs when Low
OEA1
47
Input
Enables the A0 outputs when High
OEA2
20
Input
Enables the A1 – A3 outputs when High
Data inputs (TTL)
3-State outputs (TTL)
Data inputs/Open Collector outputs, High current drive (BTL)
OEA3
24
Input
Enables the A4 – A6 outputs when High
BUS GND
41, 39, 37, 35, 33, 31, 29
GND
Bus ground (0V)
LOGIC GND
1, 5, 7, 11, 13, 15, 19
GND
Logic ground (0V)
BUS VCC
23, 43
Power
Positive supply voltage
LOGIC VCC
17, 49
Power
Positive supply voltage BAND GAP
BIAS V
48
Power
Positive supply voltage
TMS
42
Input
Test Mode Select (no-connect)
TCK
44
Input
Test Clock (no-connect)
TDI
22
Input
Test Data In (shorted to TDO)
TDO
21
Output
N/C
27
—
1999 Apr 27
Test Data Out (TDI)
Not connected
3
Philips Semiconductors
Product specification
FBL2041
FBL2041I
3.3V BTL 7-bit Futurebus+ transceiver (standard A-port)
FUNCTION TABLE
MODE
AIn to Bn
AI0 to B0
AI1 – AI3 to B1 – B3
AI4 – AI6 to B4 – B6
Disable Bn outputs
INPUTS
OUTPUTS
AIn
Bn*
OEB0
OEB1
OEB2
OEB3
OEA1
OEA2
OEA3
AOn
Bn*
L
—
H
L
L
L
L
L
L
Z
H**
H
—
H
L
L
L
L
L
L
Z
L
L
—
H
L
L
L
H
H
H
L
H**
H
—
H
L
L
L
H
H
H
H
L
L
—
H
L
X
X
L
L
L
Z
H**
H
—
H
L
X
X
L
L
L
Z
L
L
—
H
L
X
X
H
H
H
L
H**
H
—
H
L
X
X
H
H
H
H
L
L
—
H
X
L
X
L
L
L
Z
H**
H
—
H
X
L
X
L
L
L
Z
L
L
—
H
X
L
X
H
H
H
L
H**
H
—
H
X
L
X
H
H
H
H
L
L
—
H
X
X
L
L
L
L
Z
H**
H
—
H
X
X
L
L
L
L
Z
L
L
—
H
X
X
L
H
H
H
L
H**
H
—
H
X
X
L
H
H
H
H
L
X
X
L
X
X
X
X
X
X
X
H**
X
X
X
H
H
H
X
X
X
X
H**
Disable B0 outputs
X
X
H
H
X
X
X
X
X
X
H**
Disable B1 – B3 outputs
X
X
H
X
H
X
X
X
X
X
H**
Disable B4 – B6 outputs
X
X
H
X
X
H
X
X
X
X
H**
X
L
L
X
X
X
H
H
H
H
Input
X
H
L
X
X
X
H
H
H
L
Input
X
L
X
H
H
H
H
H
H
H
Input
X
H
X
H
H
H
H
H
H
L
Input
X
L
L
X
X
X
H
X
X
H
Input
X
H
L
X
X
X
H
X
X
L
Input
X
L
X
H
H
H
H
X
X
H
Input
X
H
X
H
H
H
H
X
X
L
Input
X
L
L
X
X
X
X
H
X
H
Input
X
H
L
X
X
X
X
H
X
L
Input
X
L
X
H
H
H
X
H
X
H
Input
X
H
X
H
H
H
X
H
X
L
Input
X
L
L
X
X
X
X
X
H
H
Input
X
H
L
X
X
X
X
X
H
L
Input
X
L
X
H
H
H
X
X
H
H
Input
X
H
X
H
H
H
X
X
H
L
Input
Disable AOn outputs
X
X
X
X
X
X
L
L
L
Z
X
Disable AO0 outputs
X
X
X
X
X
X
L
X
X
Z
X
Disable AO1 – AO3 outputs
X
X
X
X
X
X
X
L
X
Z
X
X
L
Z
X
Bn to AOn
B0 to AO0
B1 – B3 to AO1 – AO3
B4 – B6 to AO4 – AO6
Disable AO4 – AO6 outputs
X
X
X
X
X
X
X
NOTES:
H = High voltage level
L
= Low voltage level
X
= Don’t care
Z
= High-impedance (OFF) state
— = Input not externally driven
H** = Goes to level of pull-up voltage
B* = Precaution should be taken to ensure B inputs do not float. If they do, they are equal to Low state.
1999 Apr 27
4
Philips Semiconductors
Product specification
FBL2041
FBL2041I
3.3V BTL 7-bit Futurebus+ transceiver (standard A-port)
LOGIC DIAGRAM
OEB0
OEB1
OEA1
46
45
47
40
AI0
AO0
OEB2
OEA2
51
50
25
20
38
AI1
AO1
2
AO2
3
34
AO3
OEB3
OEA3
8
AO4
AO5
24
9
AO6
TMS
TCK
TDI
TDO
LOGIC VCC
LOGIC GND
BUS VCC
BUS GND
BIAS V
=
=
=
=
=
B4
10
14
B5
12
28
AI6
BTL
Levels
26
30
AI5
B3
6
32
AI4
B2
4
TTL
Levels
AI3
B1
52
36
AI2
B0
18
B6
16
42
44
22
21
(Future JTAG Boundary Scan option)
17, 49
1, 5, 7, 11, 13, 15, 19
23, 43
29, 31, 33, 35, 37, 39, 41
48
SG00116
1999 Apr 27
5
Philips Semiconductors
Product specification
FBL2041
FBL2041I
3.3V BTL 7-bit Futurebus+ transceiver (standard A-port)
ABSOLUTE MAXIMUM RATINGS
Operation beyond the limits set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.
SYMBOL
VCC
PARAMETER
Supply voltage
VIN
Input voltage
IIN
Input current
VOUT
Voltage applied to output in High output state
IOUT
O
Current applied to output in
Low output state/High output state
TSTG
Storage temperature
RATING
UNIT
–0.5 to +4.6
V
AI0 – AI6, OEB0, OEBn, OEAn
–0.5 to +7.0
B0 – B6
–0.5 to +3.5
VIN t 0
–50
V
–0.5 to +7.0
AO0 – AO6
64, –64
B0 – B6
200
V
mA
°C
–65 to +150
RECOMMENDED OPERATING CONDITIONS
SYMBOL
COMMERCIAL LIMITS
VCC = 3.3V±10%;
Tamb = 0 to +70°C
PARAMETER
VCC
Supply voltage
VIH
High level input voltage
High-level
VIL
Low level input voltage
Low-level
INDUSTRIAL LIMITS
VCC = 3.3V±10%;
Tamb = –40 to +85°C
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
3.0
3.3
3.6
3.0
3.3
3.6
Except B0–B6
2.0
B0 – B6
1.62
2.0
1.55
1.62
V
1.55
Except B0–B6
0.8
0.8
B0 – B6
1.47
1.47
IIK
Input clamp current
IOH
High-level output current
IOL
O
Low level output current
Low-level
COB
Output capacitance on B port
Tamb
Operating free-air temperature range
V
V
–18
–18
mA
AO0 – AO6
–32
–32
mA
AO0 – AO6
+32
+32
B0 – B6
100
100
6
0
7
+70
6
–40
mA
7
pF
+85
°C
LIVE INSERTION SPECIFICATIONS
SYMBOL
LIMITS
PARAMETER
VBIASV
Bias pin voltage
IBIASV
S
Bias pin (IBIASV
S ) input DC current
TYP
MAX
–
–
0.5
V
VCC = 0 V, Bias V = 3.6V
1.2
mA
VCC = 3.3V, Bias V = 3.6V
10
µA
2.1
V
1
µA
Voltage difference between the Bias voltage and
VCC after the PCB is plugged in.
VBn
Bus voltage during prebias
B0 – B8 = 0V, Bias V = 3.3V
ILM
Fall current during prebias
B0 – B8 = 2V, Bias V = 1.3 to 2.5V
IHM
Rise current during prebias
B0 – B8 = 1V, Bias V = 3 to 3.6V
IBnPEAK
Peak bus current during insertion
VCC = 0 to 3.3V, B0 – B8 = 0 to 2.0V,
Bias V = 2.7 to 3.6V, OEB0 = 0.8V, tr = 2ns
10
IOL
O OFF
Power up current
VCC = 0 to 3.3V, OEB0 = 0.8V
100
VCC = 0 to 1.2V, OEB0 = 0 to 5V
100
tGR
1999 Apr 27
Input glitch rejection
UNIT
MIN
VCC = 3.3V
1.62
1.0
6
µA
–1
1.35
mA
µA
ns
Philips Semiconductors
Product specification
FBL2041
FBL2041I
3.3V BTL 7-bit Futurebus+ transceiver (standard A-port)
DC ELECTRICAL CHARACTERISTICS
Over recommended operating free-air temperature range unless otherwise noted.
SYMBOL
PARAMETER
IOH
High level output current
B0 – B6
IOFF
O
Power off output current
Power-off
B0 – B6
VOH
High-level
Hi
hl
l output
t t
voltage
AO0 – AO63
TEST CONDITIONS1
Low-level output voltage
AO0 – AO63
B0 – B6
VIK
II
Input clamp voltage
Input leakage current
TYP2
MAX
100
µA
VCC = 0V, VIL = MAX, VOH = 1.9V
100
µA
VCC = 0V, VIL = MAX, VOH = 1.9V @ 85°C
300
µA
VCC –0.2
V
VCC = MIN; IOH = -8mA
2.4
V
VCC = MIN; IOH = -32mA
2.0
V
VCC = MIN; IOL = 16mA
0.4
V
VCC = MIN; IOL = 32mA
0.5
V
VCC = MIN, IOL = 4mA
VCC = MIN, IOL = 100mA
0.5
0.75
VCC = MIN, II = IIK = –18mA
1.0
–0.85
1.20
-1.2
VCC = 3.6V; VI = VCC or GND
Control/ AI0 – AI6
VCC = 0V or 3.6V; VI = 5.5V
10
AI0 – AI6
VCC = 3.6V; VI = VCC
1
Note 4
VCC = 3.6V; VI = 0V
–5
VCC = MAX, VI = 1.9V
100
VCC = MAX, VI = 3.5V, note 5
100
V
VCC = MAX; VI = 3.75V @ –40°C
100
µA
µA
mA
High-level input current
B0 – B6
IIL
Low-level input current
B0 – B6
VCC = MAX, VI = 0.75V
IOZH
Off-state output current
AO0 – AO6
VCC = MAX, VO =3V
IOZL
Off-state output current
AO0 – AO6
VCC = MAX, VO = 0.5V
ICCZ
VCC = MAX
ICCB
VCC = MAX, outputs Low or High
3.2
9.0
ICCL
VCC = MAX, outputs Low
13.5
19.5
ICCH
VCC = MAX, outputs High
10.7
16.0
Supply current (total)
V
±1.0
Control pins
IIH
ICC
UNIT
VCC = MAX, VIL = MAX, VOH = 1.9V
VCC = MIN to MAX; IOH = -100µA
VOL
LIMITS
MIN
mA
5.2
-100
µA
5
µA
-5
µA
13.5
mA
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operation conditions for the applicable type.
2. All typical values are at VCC = 3.3V, TA = 25°C.
3. Due to test equipment limitations, actual test conditions are VIH = 1.8V and VIL = 1.3V for the B side.
4. Unused pins are at VCC or GND.
5. For B port input voltage between 3 and 5 volt; IIH will be greater than 100mA but the part will continue to function normally (clamping circuit
is active).
1999 Apr 27
7
Philips Semiconductors
Product specification
FBL2041
FBL2041I
3.3V BTL 7-bit Futurebus+ transceiver (standard A-port)
AC ELECTRICAL CHARACTERISTICS
A PORT LIMITS
SYMBOL
PARAMETER
TEST
CONDITION
Tamb = +25°C,,
Vcc = 3.3V,
CL = 50pf, RL = 500Ω
FBL2041
COMMERCIAL
FBL2041I
INDUSTRIAL
Tamb = 0 to +70°C,
VCC = 3.3V±10%,
CL = 50pF, RL = 500Ω
Tamb = –40 to +85°C,
VCC = 3.3V±10%,
CL = 50pF, RL = 500Ω
UNIT
MIN
TYP
MAX
MIN
MAX
MIN
MAX
Waveform 1, 2
3.9
4.0
4.8
4.9
5.8
6.0
3.7
3.8
6.4
6.7
2.8
2.7
6.9
7.0
ns
Output enable time,
OEA to AOn
Waveform 4, 5
5.3
2.4
6.6
4.4
8.0
8.0
5.0
2.1
8.6
8.5
4.5
1.1
9.0
9.0
ns
tPHZ
tPLZ
Output disable time,
OEA to AOn
Waveform 4, 5
3.5
2.3
4.8
3.1
6.0
3.9
3.4
2.2
6.5
4.3
2.7
1.4
7.0
4.7
ns
tTLH
tTHL
Transition time, AOn Port
(10% to 90%
or 90% to 10%)
Test Circuit
and Waveforms
0.7
0.5
1.8
1.6
3.0
2.0
0.7
0.5
3.0
2.0
0.7
0.5
3.0
2.0
ns
Waveform 3
0.7
1.5
1.5
ns
TEST
CONDITION
Tamb = +25°C,
VCC = 3.3V,
CD = 30pF, RU = 9Ω
tPLH
tPHL
Propagation delay,
Bn to AOn
tPZH
tPZL
tSK(o)
Output skew between
receivers in same
package1
1.5
B PORT LIMITS
SYMBOL
PARAMETER
tPLH
tPHL
Propagation delay,
AIn to Bn
tPLH
tPHL
Tamb = 0 to +70°C,
VCC = 3.3V±10%,
CD = 30pF, RU = 9Ω
Tamb = –40 to +85°C,
VCC = 3.3V±10%,
CD = 30pF, RU = 9Ω
UNIT
Waveform 1, 2
3.3
2.7
4.2
3.5
5.2
4.5
2.9
2.5
6.0
5.0
1.8
1.7
6.7
5.6
ns
Enable/disable time,
OEB0 to Bn
Waveform 2
4.0
3.4
4.9
4.3
5.8
5.3
3.6
3.1
6.6
6.0
2.8
2.5
7.1
6.4
ns
tPLH
tPHL
Enable/disable time,
OEB1 to Bn
Waveform 1
4.2
2.9
5.1
3.8
6.1
4.7
3.9
2.6
6.9
5.5
2.9
1.9
7.3
6.0
ns
tTLH
tTHL
Transition time, Bn Port
(1.3V to 1.8V)
Test Circuit
and Waveforms
1.2
0.4
2.4
0.9
3.0
1.5
1.2
0.4
3.0
1.5
1.2
0.4
3.0
1.5
ns
1.5
ns
tSK(o)
Output skew between
drivers in same package1
Waveform 3
SYMBOL
PARAMETER
TEST
CONDITION
tPLH
tPHL
Propagation delay,
AIn to Bn
tPLH
tPHL
1.5
RU = 16.5Ω
1.5
RU = 16.5Ω
RU = 16.5Ω
UNIT
Waveform 1, 2
3.3
2.7
4.2
3.6
5.1
4.5
3.0
2.5
6.0
5.0
1.8
1.7
6.7
5.6
ns
Enable/disable time,
OEB0 to Bn
Waveform 2
4.0
3.4
4.9
4.3
5.8
5.3
3.6
3.1
6.6
6.0
2.7
2.5
7.1
6.4
ns
tPLH
tPHL
Enable/disable time,
OEB1 to Bn
Waveform 1
4.2
2.9
5.1
3.8
6.1
4.7
3.9
2.6
6.8
5.5
3.0
1.9
7.3
6.0
ns
tTLH
tTHL
Transition time, Bn Port
(1.3V to 1.8V)
Test Circuit
and Waveforms
1.2
0.4
2.4
0.9
3.0
1.5
1.2
0.4
3.0
1.5
1.2
0.4
3.0
1.5
ns
1.5
ns
tSK(o)
Output skew between
drivers in same package1
Waveform 3
1.5
1.5
NOTES:
1.  tPNactual – tPMactual for any data input to output path compared to any other data input to output path where N and M are either LH or
HL. Skew times are valid only under same test conditions (temperature, VCC, loading, etc.).
1999 Apr 27
8
Philips Semiconductors
Product specification
FBL2041
FBL2041I
3.3V BTL 7-bit Futurebus+ transceiver (standard A-port)
AC WAVEFORMS
VM = 1.55V for Bn, VM = 1.5V for all others.
AIn, Bn or Bn
OEBn
VM
VM
tPLH
OEA
tPZH
tPHL
VM
VM
VM
tPHZ
VOH -0.3V
VM
VM
AOn
AOn or Bn
OV
SG00101
SG00104
Waveform 1. Propagation Delay for Data or
Output Enable to Output
AIn, Bn
OEB0
VM
VM
tPHL
OEA
VM
AOn
SG00102
VM
VM
SG00103
Waveform 3. Output Skews
1999 Apr 27
tPLZ
VM
VOL +0.3V
Waveform 5. 3-State Output Enable Time to Low Level and
Output Disable Time from Low Level
tSK(o)
AOn, Bn
VM
SG00105
Waveform 2. Propagation Delay for Data or
Output Enable to Output
AIn, Bn
VM
tPZL
tPLH
VM
AOn, Bn
Waveform 4. 3-State Output Enable Time to High Level and
Output Disable Time from High Level
9
Philips Semiconductors
Product specification
FBL2041
FBL2041I
3.3V BTL 7-bit Futurebus+ transceiver (standard A-port)
TEST CIRCUIT AND WAVEFORMS
BIAS
V
VCC
6.0V
tW
90%
VIN
RL
VOUT
PULSE
GENERATOR
NEGATIVE
PULSE
VM
VM
10%
D.U.T.
RT
CL
10%
tTHL
(tf)
tTLH
(tr)
tTHL
POSITIVE
PULSE
VM
VM
CLOSED
tPHZ, tPZH
GND
BIAS
V
VCC
VIN
Input Pulse Definitions
2.0V (for RU = 9 Ω)
2.1V (for RU = 16.5 Ω)
VOUT
PULSE
GENERATOR
INPUT PULSE REQUIREMENTS
Family
FB+
Amplitude
Low V
Rep. Rate
A Port
3.0V
0.0V
1MHz
500ns 2.5ns
2.5ns
B Port
2.0V
1.0V
1MHz
500ns 2.5ns
2.5ns
tW
tTLH
tTHL
RU
D.U.T.
RT
LOW V
VM = 1.55V for Bn, VM = 1.5V for all others.
SWITCH
tPLZ, tPZL
10%
tW
SWITCH POSITION FOR ALL A-PORTS
(tf)
VIN
90%
10%
OPEN
(tr)
RL
Test Circuit for 3-State Outputs on A Port
tPLH, tPHL
LOW V
tTLH
90%
TEST
VIN
90%
CD
DEFINITIONS:
RL = Load Resistor; see AC CHARACTERISTICS for value.
CL = Load capacitance includes jig and probe capacitance; see AC
CHARACTERISTICS for value.
RT = Termination resistance should be equal to ZOUT of pulse generators.
CD = Load capacitance includes jig and probe capacitance; see AC
CHARACTERISTICS for value.
RU = Pull up resistor; see AC CHARACTERISTICS for value.
Test Circuit for Outputs on B Port
SG00090
1999 Apr 27
10
Philips Semiconductors
Product specification
3.3V BTL 7-bit Futurebus+ transceiver (standard A port)
QFP52: plastic quad flat package; 52 leads (lead length 1.6 mm); body 10 x 10 x 2.0 mm
1999 Apr 27
11
FBL2041
FBL2041I
SOT379-1
Philips Semiconductors
Product specification
3.3V BTL 7-bit Futurebus+ transceiver (standard A port)
FBL2041
FBL2041I
Data sheet status
Data sheet
status
Product
status
Definition [1]
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
 Copyright Philips Electronics North America Corporation 1999
All rights reserved. Printed in U.S.A.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Date of release: 11-99
Document order number:
1999 Apr 27
12
9397 750 06597