Complete Thermal System Management Controller ADM1026 FEATURES Full SMBus 1.1 support includes packet error checking (PEC) Chassis intrusion detection Interrupt output (SMBAlert) Reset input, reset outputs Thermal interrupt (THERM) output Limit comparison of all monitored values Up to 19 analog measurement channels (including internal measurements) Up to 8 fan speed measurement channels Up to 17 general-purpose logic I/O pins Remote temperature measurement with remote diode (two channels) On-chip temperature sensor Analog and PWM fan speed control outputs 2-wire serial system management bus (SMBus) 8 kB on-chip EEPROM APPLICATIONS Network servers and personal computers Telecommunications equipment Test equipment and measuring instruments ADD/ NTESTOUT SDA SCL 3.3V STBY 3.3V MAIN VCC RESET IN GPIO15 GPIO14 3.3V MAIN RESET GENERATOR GPIO13 GPIO12 SERIAL BUS INTERFACE GPIO REGISTERS GPIO11 GPIO10 RESETMAIN VCC 100kΩ GPIO9 GPIO8 VCC 3.3V STBY RESET GENERATOR RESETSTBY FAN 7/GPIO7 FAN 6/GPIO6 PWM REGISTER AND CONTROLLER FAN 5/GPIO5 FAN SPEED COUNTER FAN 3/GPIO3 FAN 2/GPIO2 VALUE AND LIMIT REGISTERS FAN 1/GPIO1 ADDRESS POINTER REGISTER FAN 0/GPIO0 VBAT +5 VIN 8k BYTES EEPROM –12 VIN +12 VIN AUTOMATIC FAN SPEED CONTROL +VCCP AIN0 (0V – +3V) AIN1 (0V – +3V) AIN2 (0V – +3V) AIN4 (0V – +3V) AIN5 (0V – +3V) LIMIT COMPARATORS INTERRUPT STATUS REGISTERS INT MASK REGISTERS CI VCC 100kΩ INT INPUT ATTENUATORS AND ANALOG MULTIPLEXER AIN3 (0V – +3V) PWM ADM1026 INTERRUPT MASKING VCC 100kΩ AIN6 (0V – +2.5V) 8-BIT ADC AIN7 (0V – +2.5V) GPIO16/THERM D2+/AIN8 (0V – +2.5V) CONFIGURATION REGISTERS D2–/AIN9 (0V – +2.5V) D1+ BAND GAP REFERENCE D1–/NTESTIN ANALOG OUTPUT REGISTER AND 8-BIT DAC BAND GAP TEMPERATURE SENSOR AGND DGND VREF (1.82V OR 2.5V) TO GPIO REGISTERS DAC 02657-A-001 FAN 4/GPIO4 Figure 1. Functional Block Diagram Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved. ADM1026 TABLE OF CONTENTS Specifications..................................................................................... 3 Measurement Inputs .................................................................. 16 Absolute Maximum Ratings............................................................ 5 Temperature Measurement System.......................................... 20 Thermal Characteristics .............................................................. 5 Analog Output ............................................................................ 22 ESD Caution.................................................................................. 5 Fan Speed Measurement ........................................................... 25 Pin Configuration and Function Descriptions............................. 6 Enabling and Clearing Interrupts ............................................ 29 Typical Performance Characteristics ............................................. 8 NAND Tree Tests........................................................................ 31 Product Description....................................................................... 10 Using the ADM1026 .................................................................. 33 Functional Description.............................................................. 10 Registers........................................................................................... 36 Internal Registers........................................................................ 11 Detailed Register Descriptions ................................................. 38 EEPROM ..................................................................................... 11 Outline Dimensions ....................................................................... 54 SMBus Protocols for RAM and EEPROM .............................. 13 Ordering Guide .......................................................................... 55 REVISION HISTORY 3/04—Data Sheet Changed from Rev. 0 to Rev. A Updated Format..................................................................Universal Change to Footnote 4, Table 1..........................................................4 Added Figure 15.................................................................................9 Changes to Table 6.......................................................................... 17 Changes to Figure 27...................................................................... 18 Change to Figure 31 ....................................................................... 19 Change to Battery Measurement Input Section ......................... 19 Changes to Table 7.......................................................................... 21 Changes to Equations in Fan Speed Measurement Section...... 26 Change to Chassis Intrusion Input Section ................................ 27 Changes to Reset Input and Outputs Section ............................. 31 Changes to Software Reset Function Section ............................. 34 Changes to Ordering Guide .......................................................... 55 5/02—Revision 0: Initial Version Rev. A | Page 2 of 56 ADM1026 SPECIFICATIONS1, 2, 3 Table 1. TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted. Parameter POWER SUPPLY Supply Voltage, 3.3 V STBY, 3.3 V MAIN Supply Current, ICC TEMPERATURE-TO-DIGITAL CONVERTER Internal Sensor Accuracy Resolution External Diode Sensor Accuracy Resolution Remote Sensor Source Current Typ Max Test Conditions/Comments Unit 3.0 3.3 2.5 5.5 4.0 Interface inactive, ADC active V mA ±3 ±1 ±3 ±1 90 5.5 ANALOG-TO-DIGITAL CONVERTER (including MUX and attenuators) Total Unadjusted Error (TUE)4 Differential Nonlinearity (DNL) Power Supply Sensitivity Conversion Time (Analog Input or Internal Temperature)5 Conversion Time (External Temperature)5 Input Resistance (+5 VIN, VCCP, AIN0 − AIN5) Input Resistance of +12 VIN pin Input Resistance of −12 VIN pin Input Resistance (AIN6 − AIN9) Input Resistance of VBAT pin4 VBAT Current Drain (when measured) VBAT Current Drain (when not measured) ANALOG OUTPUT (DAC) Output Voltage Range Total Unadjusted Error (TUE) Zero Error Differential Nonlinearity (DNL) Integral Nonlinearity Output Source Current Output Sink Current REFERENCE OUTPUT Output Voltage Output Voltage Load Regulation (ISINK = 2 mA) Load Regulation (ISOURCE = 2 mA) Short Circuit Current Output Current Source Output Current Sink FAN RPM-TO-DIGITAL CONVERTER6 Accuracy Full-Scale Count FAN0 to FAN7 Nominal Input RPM5 Internal Clock Frequency OPEN DRAIN O/Ps, PWM, GPIO0 to 16 Output High Voltage, VOH Min 0°C < TD < 100°C High level Low level ±2 ±1 80 70 8 5 80 ±0.1 11.38 34.13 100 100 10 100 80 6 12.06 36.18 120 115 12 120 100 CR2032 battery life >10 years 0–2.5 ±5 ±1 IL = 2 mA No load Monotonic by design 1.84 2.53 Bit 2 of Register 07h = 0 Bit 2 of Register 07h = 1 1 ±0.5 2 1 1.8 2.47 1.82 2.50 0.15 0.15 25 2 2 VCC = 3.3 V ±12 255 20 2.4 Rev. A | Page 3 of 56 8800 4400 2200 1100 22.5 °C °C °C °C µA µA % LSB %/V ms ms kΩ kΩ kΩ MΩ kΩ nA nA V % LSB LSB LSB mA mA V V % % mA mA mA % Divisor = 1, fan count = 153 Divisor = 2, fan count = 153 Divisor = 4, fan count = 153 Divisor = 8, fan count = 153 RPM RPM RPM RPM kHz IOUT = 3.0 mA, VCC = 3.3 V V 25 ADM1026 Parameter High Level Output Leakage Current, IOH Output Low Voltage, VOL PWM Output Frequency DIGITAL OUTPUTS (INT, RESETMAIN, RESETBY) Output Low Voltage, VOL RESET Pulse Width Min Max 1 0.4 Test Conditions/Comments VOUT = VCC IOUT = −3.0 mA, VCC = 3.3 V Unit µA V Hz 0.4 240 IOUT = −3.0 mA, VCC = 3.3 V 180 V ms 0.1 0.4 1 IOUT = –3.0 mA, VCC = 3.3 V VOUT = VCC V µA 75 140 OPEN DRAIN SERIAL DATABUS OUTPUT (SDA) Output Low Voltage, VOL High Level Output Leakage Current, IOH SERIAL BUS DIGITAL INPUTS (SCL, SDA) Input High Voltage, VIH Input Low Voltage, VIL Hysteresis DIGITAL INPUT LOGIC LEVELS (ADD, CI, FAN 0 to 7, GPIO 0 to 16)7, 8 Input High Voltage, VIH Input Low Voltage, VIL Hysteresis (Fan 0 to 7) RESETMAIN, RESETSTBY RESETMAIN Threshold RESETSBY Threshold RESETMAIN Hysteresis RESETSTBY Hysteresis DIGITAL INPUT CURRENT Input High Current, IIH Input Low Current, IIL Input Capacitance, CIN EEPROM RELIABILITY Endurance9 Data Retention10 SERIAL BUS TIMING Clock Frequency, fSCLK Glitch Immunity, tSW Bus Free Time, tBUF Start Setup Time, tSU; STA Start Hold Time, tHD; STA SCL Low Time, tLOW SCL High Time, tHIGH SCL, SDA Rise Time, tr SCL, SDA Fall Time, tf Data Setup Time, tSU; DAT Data Hold Time, tHD; DAT Typ 0.1 2.2 V V mV 0.8 500 2.4 0.8 VCC = 3.3 V VCC = 3.3 V VCC = 3.3 V V V mV 2.97 3.10 Falling voltage Falling voltage V V mV mV 1 VIN = VCC VIN = 0 µA µA pF 250 2.89 3.01 2.94 3.05 60 70 –1 20 100 10 700 kcycles Years See Figure 2 for all parameters. 400 50 4.7 4.7 4 4.7 4 1000 300 250 300 1 All voltages are measured with respect to GND, unless otherwise specified. Typicals are at TA = 25°C and represent the most likely parametric norm. Shutdown current typ is measured with VCC = 3.3 V. Timing specifications are tested at logic levels of VIL = 0.8 V for a falling edge and VIH = 2.1 V for a rising edge. 4 Total unadjusted error (TUE) includes offset, gain, and linearity errors of the ADC, multiplexer, and on-chip input attenuators. VBAT is accurate only for VBAT voltages greater than 1.5 V (see Figure 15). 5 Total analog monitoring cycle time is nominally 273 ms, made up of 18 ms × 11.38 ms measurements on analog input and internal temperature channels, and 2 ms × 34.13 ms measurements on external temperature channels. 6 The total fan count is based on two pulses per revolution of the fan tachometer output. The total fan monitoring time depends on the number of fans connected and the fan speed. See the Fan Speed Measurement section for more details. 7 ADD is a three-state input that may be pulled high, low, or left open-circuit. 8 Logic inputs accept input high voltages up to 5 V even when device is operating at supply voltages below 5 V. 9 Endurance is qualified to 100,000 cycles as per JEDEC Std. 22 method A117, and measured at −40°C, +25°C, and +85°C. Typical endurance at +25°C is 700,000 cycles. 10 Retention lifetime equivalent at junction temperature (TJ ) = 55°C as per JEDEC Std. 22 method A117. Retention lifetime based on an activation energy of 0.6 V derates with junction temperature as shown in Figure 16. 2 3 Rev. A | Page 4 of 56 kHz ns µs µs µs µs µs ns ns ns ns ADM1026 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Positive Supply Voltage (VCC) Voltage on +12 V VIN Pin Voltage on −12 V VIN Pin Voltage on Analog Pins Voltage on Open Drain Digital Pins Input Current at any Pin Package Input Current Maximum Junction Temperature (TJ MAX) Storage Temperature Range Lead Temperature, Soldering Vapor Phase (60 sec) Infrared (15 sec) ESD Rating, −12 VIN Pin ESD Rating, All Other Pins Rating 6.5 V +20 V −20 V −0.3 V to (VCC + 0.3 V) −0.3 V to +6.5 V ±5 mA ±20 mA 150°C −65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL CHARACTERISTICS • 48-Lead LQFP package • θJA = 50°C/W, θJC = 10°C/W 215°C 200°C 1000 V 2000 V tF t LOW t HD; STA tR SCL t HD; DAT t HIGH t SU; STA t SU; DAT t SU; STO SDA t BUF P S S Figure 2. Serial Bus Timing Diagram ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. A | Page 5 of 56 P 02657-A-002 t HD; STA ADM1026 GPIO9 1 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16/THERM AIN0(0V – 3V) AIN1(0V – 3V) AIN2(0V – 3V) AIN3(0V – 3V) AIN4(0V – 3V) 48 47 46 45 44 43 42 41 40 39 38 37 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 36 AIN5(0V – 3V) PIN 1 IDENTIFIER GPIO8 2 35 AIN6(0V – 2.5V) FAN0/GPIO0 3 34 AIN7(0V – 2.5V) FAN1/GPIO1 4 33 +VCCP FAN2/GPIO2 5 32 +12 VIN ADM1026 FAN3/GPIO3 6 31 –12 VIN TOP VIEW (Not to Scale) 3.3V MAIN 7 30 +5 VIN 29 VBAT DGND 8 02657-A-003 VREF 24 DAC 23 3.3V STBY 22 AGND 21 RESETMAIN 20 RESETSTBY 19 PWM 18 INT 17 25 D1–/NTESTIN CI 16 26 D1+ FAN7/GPIO7 12 ADD/NTESTOUT 15 27 D2–/AIN9(0V – 2.5V) FAN6/GPIO6 11 SCL 13 28 D2+/AIN8(0V – 2.5V) FAN5/GPIO5 10 SDA 14 FAN4/GPIO4 9 Figure 3. Pin Configuration Table 3. Pin No. 1 2 3 Mnemonic GPIO9 GPIO8 FAN0/GPIO0 Type Digital I/O1 Digital I/O1 Digital I/O 4 FAN1/GPIO1 Digital I/O 5 FAN2/GPIO2 Digital I/O 6 FAN3/GPIO3 Digital I/O 7 8 9 3.3 V MAIN DGND FAN4/GPIO4 Analog Input Ground Digital I/O 10 FAN5/GPIO5 Digital I/O 11 FAN6/GPIO6 Digital I/O 12 FAN7/GPIO7 Digital I/O 13 14 15 SCL SDA ADD/NTESTOUT Digital Input Digital I/O Digital Input 16 CI Digital Input 17 INT Digital Output Description General-purpose I/O pin that can be configured as digital inputs or outputs. General-purpose I/O pin that can be configured as digital inputs or outputs. Fan tachometer input with internal 10 kΩ pull-up resistor to 3.3 V STBY. Can be reconfigured as a general-purpose, open drain, digital I/O pin. Fan tachometer input with internal 10 kΩ pull-up resistor to 3.3 V STBY. Can be reconfigured as a general-purpose, open drain, digital I/O pin. Fan tachometer input with internal 10 kΩ pull-up resistor to 3.3 V STBY. Can be reconfigured as a general-purpose, open drain, digital I/O pin. Fan tachometer input with internal 10 kΩ pull-up resistor to 3.3 V STBY. Can be reconfigured as a general-purpose, open drain, digital I/O pin. Monitors the main 3.3 V system supply. Does not power the device. Ground pin for digital circuits. Fan tachometer input with internal 10 kΩ pull-up resistor to 3.3 V STBY. Can be reconfigured as a general-purpose, open drain, digital I/O pin. Fan tachometer input with internal 10 kΩ pull-up resistor to 3.3 V STBY. Can be reconfigured as a general-purpose, open drain, digital I/O pin. Fan tachometer input with internal 10 kΩ pull-up resistor to 3.3 V STBY. Can be reconfigured as a general-purpose, open drain, digital I/O pin. Fan tachometer input with internal 10 kΩ pull-up resistor to 3.3 V STBY. Can be reconfigured as a general-purpose, open drain, digital I/O pin. Open Drain Serial Bus Clock. Requires a 2.2 kΩ pull-up resistor. Serial Bus Data. Open drain I/O. Requires a 2.2 kΩ pull-up resistor. This is a three-state input that controls the two LSBs of the serial bus address. It also functions as the output for NAND tree testing. An active high input that captures a chassis intrusion event in Bit 6 of Status Register 4. This bit remains set until cleared, as long as battery voltage is applied to the VBAT input, even when the ADM1026 is powered off. Interrupt Request (Open Drain). The output is enabled when Bit 1 of the configuration register is set to 1. The default state is disabled. It has an on-chip 100 kΩ pull-up resistor. Rev. A | Page 6 of 56 ADM1026 Pin No. 18 Mnemonic PWM Type Digital Output 19 RESETSTBY Digital Output 20 RESETMAIN Digital I/O 21 22 23 24 25 AGND 3.3 V STBY DAC VREF D1–/NTESTIN Ground Power Supply Analog Output Analog Output Analog Input 26 27 D1+ D2–/AIN9 Analog Input Programmable 28 D2+/AIN8 Programmable 29 30 31 32 33 34 35 36 37 38 39 40 41 42 VBAT +5 VIN −12 VIN +12 VIN +VCCP AIN7 AIN6 AIN5 AIN4 AIN3 AIN2 AIN1 AIN0 GPIO16/THERM Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Digital I/O1 43 44 45 46 47 48 GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 Digital I/O1 Digital I/O1 Digital I/O1 Digital I/O1 Digital I/O1 Digital I/O1 1 Description Open drain pulse width modulated output for control of the fan speed. This pin defaults to high for the 100% duty cycle for use with NMOS drive circuitry. If a PMOS device is used to drive the fan, the PWM output may be inverted by setting Bit 1 of Test Register 1 = 1. Power-On Reset. 5 mA driver (weak 100 kΩ pull-up), active low output (100 kΩ pull-up) with a 180 ms typical pulse width. RESETSTBY is asserted whenever 3.3 V STBY is below the reset threshold. It remains asserted for approximately 180 ms after 3.3 V STBY rises above the reset threshold. Power-On Reset. 5 mA driver (weak 100 kΩ pull-up), active low output (100 kΩ pull-up) with a 180 ms typical pulse width. RESETMAIN is asserted whenever 3.3 V MAIN is below the reset threshold. It remains asserted for approximately 180 ms after 3.3 V MAIN rises above the reset threshold. If, however, 3.3 V STBY rises with or before 3.3 V MAIN, then RESETMAIN remains asserted for 180 ms after RESETSTBY is deasserted. Pin 20 also functions as an active low RESET input. Ground pin for analog circuits. Supplies 3.3 V power. Also monitors the 3.3 V standby power rail. 0 V to 2.5 V output for analog control of the fan speed. Reference Voltage Output. Can be selected as 1.8 V (default) or 2.5 V. Connected to a cathode of the first remote temperature sensing diode. If it is held high at power-on, it activates the NAND tree test mode. Connected to the anode of the first remote temperature sensing diode. Connected to the cathode of the second remote temperature sensing diode, or the analog input may be reconfigured as a 0 V− 2.5 V analog input. Connected to the anode of the second remote temperature sensing diode, or the analog input may be reconfigured as a 0 V − 2.5 V analog input. Monitors battery voltage, nominally +3 V. Monitors the +5 V supply. Monitors the −12 V supply. Monitors the +12 V supply. Monitors the processor core voltage (0 V to 3.0 V). General-purpose 0 V to 2.5 V analog inputs. General-purpose 0 V to 2.5 V analog inputs. General-purpose 0 V to 3 V analog inputs. General-purpose 0 V to 3 V analog inputs. General-purpose 0 V to 3 V analog inputs. General-purpose 0 V to 3 V analog inputs. General-purpose 0 V to 3 V analog inputs. General-purpose 0 V to 3 V analog inputs. General-purpose I/O pin that can be configured as a digital input or output. Can also be configured as a bidirectional THERM pin (100 kΩ pull-up). General-purpose I/O pin that can be configured as a digital input or output. General-purpose I/O pin that can be configured as a digital input or output. General-purpose I/O pin that can be configured as a digital input or output. General-purpose I/O pin that can be configured as a digital input or output. General-purpose I/O pin that can be configured as a digital input or output. General-purpose I/O pin that can be configured as a digital input or output. GPIO pins are open drain and require external pull-up resistors. Fan inputs have integrated 10 kΩ pull-ups, but these pins become open drain when reconfigured as GPIOs. Rev. A | Page 7 of 56 ADM1026 25 110 20 100 90 15 80 10 D+ TO GND 70 READING (°C) 5 0 –5 D+ TO VCC 60 50 40 –10 20 –20 10 –25 90 30 60 LEAKAGE RESISTANCE (MΩ) 120 0 0 14 5 12 0 10 8 250mV 6 4 100mV 02657-A-005 0 100 200 300 400 FREQUENCY (MHz) 500 600 40 50 60 70 80 PIII TEMPERATURE (°C) 90 100 110 –5 –10 –15 –25 0 10 20 30 CAPACITANCE (nF) 40 50 Figure 8. Temperature Error vs. Capacitance Between D+ and D– Figure 5. Temperature Error vs. Power Supply Noise Frequency 80 12 100mV 60mV 40mV 70 8 6 4 60 50 40 30 100mV 20 60mV 2 0 0 100 200 300 400 FREQUENCY (MHz) 500 600 02657-A-006 10 0 100 40mV 200 300 400 FREQUENCY (MHz) 500 600 02657-A-009 TEMPERATURE ERROR (°C) 10 TEMPERATURE ERROR (°C) 30 –20 2 0 20 Figure 7. Pentium® III Temperature vs. ADM1026 Reading TEMPERATURE ERROR (°C) TEMPERATURE ERROR (°C) Figure 4. Temperature Error vs. PCB Track Resistance 10 02657-A-008 0 02657-A-007 30 –15 02657-A-004 TEMPERATURE ERROR (°C) TYPICAL PERFORMANCE CHARACTERISTICS Figure 9. Temperature Error vs. Differential-Mode Noise Frequency Figure 6. Temperature Error vs. Common-Mode Noise Frequency Rev. A | Page 8 of 56 ADM1026 1.0 450 400 0.5 TEMPERATURE ERROR (°C) RESET TIMEOUT (ms) 350 300 250 200 150 100 0 –0.5 –1.0 –1.5 0 –20 20 40 60 80 TEMPERATURE (°C) 100 120 140 –2.0 0 10 Figure 10. Power-up Reset Timeout vs. Temperature 3.0 120 2.5 100 TEMPERATURE (°C) 40 50 60 70 80 TEMPERATURE (°C) 90 100 110 120 1.5 1.0 0.5 80 60 40 3.50 3.75 4.00 4.25 4.50 VCC (V) 4.75 5.00 5.25 5.50 0 2 0 4 6 8 10 12 14 TIME (s) 16 18 20 22 24 26 02657-A-014 0 3.00 3.25 02657-A-011 20 Figure 14. Response to Thermal Shock Figure 11. Supply Current vs. Supply Voltage 3.5 1.8 1.6 3.0 VBAT MEASUREMENT 1.4 1.2 1.0 0.8 0.6 2.5 2.0 1.5 1.0 0.4 0.5 0 0 10 20 30 40 50 60 70 80 TEMPERATURE (°C) 90 100 110 120 02657-A-012 0.2 0 0 1 2 VBAT VOLTAGE 3 Figure 15. VBAT Measurement vs. Voltage Figure 12. Local Sensor Temperature Error Rev. A | Page 9 of 56 4 02657-A-015 IDD (mA) 30 Figure 13. Remote Sensor Temperature Error 2.0 TEMPERATURE ERROR (°C) 20 02657-A-013 0 –40 02657-A-010 50 ADM1026 PRODUCT DESCRIPTION The ADM1026 is a complete system hardware monitor for microprocessor-based systems, providing measurement and limit comparison of various system parameters. The ADM1026 has up to 19 analog measurement channels. Fifteen analog voltage inputs are provided, five of which are dedicated to monitoring +3.3 V, +5 V, and ±12 V power supplies, and the processor core voltage. The ADM1026 can monitor two other power supply voltages by measuring its own VCC and the main system supply. One input (two pins) is dedicated to a remote temperature-sensing diode. Two additional pins can be configured as general-purpose analog inputs to measure 0 V to 2.5 V, or as a second temperature sensing input. The eight remaining inputs are general-purpose analog inputs with a range of 0 V to 2.5 V or 0 V to 3 V. The ADM1026 also has an on-chip temperature sensor. The ADM1026 has eight pins that can be configured for fan speed measurement or as general-purpose logic I/O pins. Another eight pins are dedicated to general-purpose logic I/O. An additional pin can be configured as a general-purpose I/O or as the bidirectional THERM pin. Measured values can be read out via a 2-wire serial system management bus, and values for limit comparisons can be programmed over the same serial bus. The high speed, successive approximation ADC allows frequent sampling of all analog channels to ensure a fast interrupt response to any outof-limit measurement. FUNCTIONAL DESCRIPTION The ADM1026 is a complete system hardware monitor for microprocessor-based systems. The device communicates with the system via a serial system management bus. The serial bus controller has a hardwired address line for device selection (ADD, Pin 15), a serial data line for reading and writing addresses and data (SDA, Pin 14), and an input line for the serial clock (SCL, Pin 13). All control and programming functions of the ADM1026 are performed over the serial bus. Pins 29 to 33 are dedicated analog inputs with on-chip attenuators configured to monitor VBAT, +5 V, −12 V, +12 V, and the processor core voltage VCCP, respectively. Pins 34 to 41 are general-purpose analog inputs with a range of 0 V to 2.5 V or 0 V to 3 V. These are mainly intended for monitoring SCSI termination voltages, but may be used for other purposes. The ADC also accepts input from an on-chip band gap temperature sensor that monitors system ambient temperature. In addition, the ADM1026 monitors the supply from which it is powered, 3.3 V STBY, so there is no need for a separate pin to monitor the power supply voltage. The ADM1026 has eight pins that are general-purpose logic I/O pins (Pins 1, 2, and 43 to 48), a pin that can be configured as GPIO or as a bidirectional thermal interrupt (THERM) pin (Pin 42), and eight pins that can be configured for fan speed measurement or as general-purpose logic pins (Pins 3 to 6 and Pins 9 to 12). Sequential Measurement When the ADM1026 monitoring sequence is started, it cycles sequentially through the measurement of analog inputs and the temperature sensor, while at the same time the fan speed inputs are independently monitored. Measured values from these inputs are stored in value registers. These can be read over the serial bus, or can be compared with programmed limits stored in the limit registers. The results of out-of-limit comparisons are stored in the interrupt status registers. An out-of-limit event generates an interrupt on the INT line (Pin 17). Any or all of the interrupt status bits can be masked by appropriate programming of the interrupt mask registers. Chassis Intrusion A chassis intrusion input (Pin 16) is provided to detect unauthorized tampering with the equipment. This event is latched in a battery-backed register bit. Measurement Inputs Resets Programmability of the analog and digital measurement inputs makes the ADM1026 extremely flexible and versatile. The device has an 8-bit A/D converter, and 17 analog measurement input pins that can be configured in different ways. The ADM1026 has two power-on reset outputs, RESETMAIN and RESETSTBY, that are asserted when 3.3 V MAIN or 3.3 V STBY fall below the reset threshold. These give a 180 ms reset pulse at power-up. RESETMAIN also functions as an active-low RESET input. Pins 25 and 26 are dedicated temperature inputs and may be connected to the cathode and anode of a remote temperaturesensing diode. Pins 27 and 28 may be configured as temperature inputs and connected to a second temperature-sensing diode, or may be reconfigured as analog inputs with a range of 0 V to 2.5 V. Rev. A | Page 10 of 56 ADM1026 • Either or both of these outputs may be used to implement a temperature-controlled fan by controlling the speed of a fan using the temperature measured by the on-chip temperature sensor or remote temperature sensors. INTERNAL REGISTERS Table 4 describes the principal registers of the ADM1026. For more detailed information, see Table 11 to Table 124. Table 4. Principal Registers Type Address Pointer Configuration Registers Fan Divisor Registers DAC/PWM Control Registers GPIO Configuration Registers Value and Limit Registers Status Registers Mask Registers Description Contains the address that selects one of the other internal registers. When writing to the ADM1026, the first byte of data is always a register address, and is written to the address pointer register. Provide control and configuration for various operating parameters. Contain counter prescaler values for fan speed measurement. Contain speed values for PWM and DAC fan drive outputs. Configure the GPIO pins as input or output and for signal polarity. Store the results of analog voltage inputs, temperature, and fan speed measurements, along with their limit values. Store events from the various interrupt sources. Allow masking of individual interrupt sources. EEPROM The ADM1026 has 8 kB of nonvolatile, electrically erasable, programmable read-only memory (EEPROM) from register Addresses 8000h to 9FFFh. This may be used for permanent storage of data that is not lost when the ADM1026 is powered down, unlike the data in the volatile registers. Although referred to as read-only memory, the EEPROM can be written to (as well as read from) via the serial bus in exactly the same way as the other registers. The main differences between the EEPROM and other registers are • • Writing to the EEPROM should be restricted because its typical cycle life is 100,000 write operations, due to the usual EEPROM wear-out mechanisms. The EEPROM in the ADM1026 has been qualified for two key EEPROM memory characteristics: memory cycling endurance and memory data retention. Endurance qualifies the ability of the EEPROM to be cycled through many program, read, and erase cycles. In real terms, a single endurance cycle is composed of four independent, sequential events, as follows: 1. 2. 3. 4. Initial page erase sequence Read/verify sequence Program sequence Second read/verify sequence In reliability qualification, every byte is cycled from 00h to FFh until a first fail is recorded, signifying the endurance limit of the EEPROM memory. Retention quantifies the ability of the memory to retain its programmed data over time. The EEPROM in the ADM1026 has been qualified in accordance with the formal JEDEC Retention Lifetime Specification (A117) at a specific junction temperature (TJ = 55°C) to guarantee a minimum of 10 years retention time. As part of this qualification procedure, the EEPROM memory is cycled to its specified endurance limit described above before data retention is characterized. This means that the EEPROM memory is guaranteed to retain its data for its full specified retention lifetime every time the EEPROM is reprogrammed. Note that retention lifetime based on an activation energy of 0.6 V derates with TJ, as shown in Figure 16. 300 250 An EEPROM location must be blank before it can be written to. If it contains data, it must first be erased. Writing to EEPROM is slower than writing to RAM. Rev. A | Page 11 of 56 200 150 100 50 0 40 50 60 70 80 90 100 JUNCTION TEMPERATURE (°C) 110 Figure 16. Typical EEPROM Memory Retention 120 02657-A-016 The ADM1026 has two outputs intended to control fan speed, though they can also be used for other purposes. Pin 18 is an open drain, pulse width modulated (PWM) output with a programmable duty cycle and an output frequency of 75 Hz. Pin 23 is connected to the output of an on-chip, 8-bit, digital-toanalog converter with an output range of 0 V to 2.5 V. RETENTION (Years) Fan Speed Control Outputs ADM1026 Serial Bus Interface The peripheral whose address corresponds to the transmitted address responds by pulling the data line low during the low period before the ninth clock pulse, known as the acknowledge bit, and holding it low during the high period of this clock pulse. All other devices on the bus remain idle while the selected device waits for data to be read from or written to it. If the R/W bit is 0, the master writes to the slave device. If the R/W bit is 1, the master reads from the slave device. Control of the ADM1026 is carried out via the serial system management bus (SMBus). The ADM1026 is connected to this bus as a slave device, under the control of a master device. The ADM1026 has a 7-bit serial bus slave address. When the device is powered on, it does so with a default serial bus address. The 5 MSBs of the address are set to 01011, and the 2 LSBs are determined by the logical states of Pin 15 ADD/NTESTOUT. This pin is a three-state input that can be grounded, connected to VCC, or left open-circuit to give three different addresses. 2. Table 5. Address Pin Truth Table ADD Pin GND No Connect VCC A1 0 1 0 A0 0 0 1 If ADD is left open-circuit, the default address is 0101110 (5Ch). ADD is sampled only at power-up on the first valid SMBus transaction, so any changes made while the power is on (and the address is locked) have no effect. If the operation is a write operation, the first data byte after the slave address is a command byte. This tells the slave device what to expect next. It may be an instruction telling the slave device to expect a block write, or it may simply be a register address that tells the slave where subsequent data is to be written. The facility to make hardwired changes to device addresses allows the user to avoid conflicts with other devices sharing the same serial bus, for example if more than one ADM1026 is used in a system. Because data can flow in only one direction as defined by the R/W bit, it is not possible to send a command to a slave device during a read operation. Before doing a read operation, it may first be necessary to do a write operation to tell the slave what type of read operation to expect and/or the address from which data is to be read. General SMBus Timing Figure 17 and Figure 18 show timing diagrams for general read and write operations using the SMBus. The SMBus specification defines specific conditions for different types of read and write operations, which are discussed later in this section. The general SMBus protocol1 operates as follows: 1. The master initiates data transfer by establishing a start condition, defined as a high-to-low transition on the serial data line (SDA) while the serial clock line SCL remains high. This indicates that a data stream follows. All slave peripherals connected to the serial bus respond to the start condition and shift in the next 8 bits, consisting of a 7-bit slave address (MSB first) and an R/W bit, which determine the direction of the data transfer, that is, whether data is written to or read from the slave device (0 = write, 1 = read). Data is sent over the serial bus in sequences of nine clock pulses, 8 bits of data followed by an acknowledge bit from the slave device. Data transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, because a low-to-high transition when the clock is high may be interpreted as a stop signal. 3. 1 When all data bytes have been read or written, stop conditions are established. In write mode, the master pulls the data line high during the 10th clock pulse to assert a stop condition. In read mode, the master device releases the SDA line during the low period before the ninth clock pulse, but the slave device does not pull it low (called No Acknowledge). The master takes the data line low during the low period before the 10th clock pulse, then high during the 10th clock pulse to assert a stop condition. If it is required to perform several read or write operations in succession, the master can send a repeat start condition instead of a stop condition to begin a new operation. Rev. A | Page 12 of 56 ADM1026 1 9 1 9 SCL 0 SDA 1 0 1 1 A1 A0 START BY MASTER D7 R/W D6 D5 D4 D3 D2 D1 D0 ACK. BY SLAVE ACK. BY SLAVE FRAME 1 SLAVE ADDRESS FRAME 2 COMMAND CODE 1 9 1 9 SCL (CONTINUED) SDA (CONTINUED) D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 ACK. BY SLAVE STOP BY MASTER 02657-A-017 ACK. BY SLAVE FRAME N DATA BYTE FRAME 3 DATA BYTE Figure 17. General SMBus Write Timing Diagram 1 9 1 9 SCL SDA 0 1 0 1 1 A1 A0 D7 R/W D6 D5 D4 D3 D2 D1 D0 ACK. BY SLAVE START BY MASTER ACK. BY MASTER FRAME 1 SLAVE ADDRESS FRAME 2 DATA BYTE 1 9 1 9 SCL (CONTINUED) D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 ACK. BY MASTER D1 D0 NO ACK. FRAME N DATA BYTE FRAME 3 DATA BYTE STOP BY MASTER 02657-A-018 SDA (CONTINUED) Figure 18. General SMBus Read Timing Diagram SMBus PROTOCOLS FOR RAM AND EEPROM The ADM1026 contains volatile registers (RAM) and nonvolatile EEPROM. RAM occupies Addresses 00h to 6Fh, while EEPROM occupies Addresses 8000h to 9FFFh. Data can be written to and read from both RAM and EEPROM as single data bytes and as block (sequential) read or write operations of 32 data bytes, the maximum block size allowed by the SMBus specification. Data can only be written to unprogrammed EEPROM locations. To write new data to a programmed location, it is first necessary to erase it. EEPROM erasure cannot be done at the byte level; the EEPROM is arranged as 128 pages of 64 bytes, and an entire page must be erased. Note that of these 128 pages, only 124 pages are available to the user. The last four pages are reserved for manufacturing purposes and cannot be erased/rewritten. The EEPROM has three RAM registers associated with it, EEPROM Registers 1, 2, and 3 at Addresses 06h, 0Ch, and 13h. EEPROM Registers 1 and 2 are for factory use only. EEPROM Register 3 sets up the EEPROM operating mode. Setting Bit 0 of EEPROM Register 3 puts the EEPROM into read mode. Setting Bit 1 puts it into programming mode. Setting Bit 2 puts it into erase mode. Only one of these bits must be set before the EEPROM may be accessed. Setting no bits or more than one of them causes the device to respond with No Acknowledge if an EEPROM read, program, or erase operation is attempted. It is important to distinguish between SMBus write operations, such as sending an address or command, and EEPROM programming operations. It is possible to write an EEPROM address over the SMBus, whatever the state of EEPROM Register 3. However, EEPROM Register 3 must be correctly set before a subsequent EEPROM operation can be performed. For example, when reading from the EEPROM, Bit 0 of EEPROM Register 3 can be set, even though SMBus write operations are required to set up the EEPROM address for reading. Rev. A | Page 13 of 56 ADM1026 EEPROM Register 3 Bit 7 is used for clock extend. Programming an EEPROM byte takes approximately 250 µs, which would limit the SMBus clock for repeated or block write operations. Because EEPROM block read/write access is slow, it is recommended that this clock extend bit typically be set to 1. This allows the ADM1026 to pull SCL low and extend the clock pulse when it cannot accept any more data. ADM1026 SMBus Operations The SMBus specification defines several protocols for different types of read and write operations. The ones used in the ADM1026 are discussed below. The following abbreviations are used in the diagrams: Start Write Stop Acknowledge Read No Acknowledge 1. 2. The master device asserts a start condition on the SDA. The master sends the 7-bit slave address followed by the write bit (low). 3. The addressed slave device asserts an ACK on the SDA. 4. The master sends a command code. 5. The slave asserts an ACK on the SDA. 6. The master sends a data byte. 7. The slave asserts an ACK on the SDA. 8. The master sends a data byte (or may assert stop here.) 9. The slave asserts an ACK on the SDA. 10. The master asserts a stop condition on the SDA to end the transaction. In the ADM1026, the write byte/word protocol is used for four purposes. The ADM1026 knows how to respond by the value of the command byte and EEPROM Register 3. The first purpose is to write a single byte of data to RAM. In this case, the command byte is the RAM address from 00h to 6Fh and the (only) data byte is the actual data. This is illustrated in Figure 20. 1 2 The master device asserts a start condition on the SDA. The master sends the 7-bit slave address followed by the write bit (low). The addressed slave device asserts an ACK on the SDA. The master sends a command code. The slave asserts ACK on the SDA. The master asserts a stop condition on the SDA and the transaction ends. In the ADM1026, the send byte protocol is used to write a register address to RAM for a subsequent single-byte read from the same address or block read or write starting at that address. This is illustrated in Figure 19. 2 3 SLAVE W A S ADDRESS 4 5 6 RAM ADDRESS A P (00h TO 6Fh) 02657-A-019 1 5 6 7 8 Figure 20. Single Byte Write to RAM Send Byte In this operation, the master device sends a single command byte to a slave device, as follows: 3. 4. 5. 6. 4 RAM SLAVE W A ADDRESS A DATA A P S ADDRESS (00h TO 6Fh) ADM1026 Write Operations 1. 2. 3 Figure 19. Setting a RAM Address for Subsequent Read If it is required to read data from the RAM immediately after setting up the address, the master can assert a repeat start condition immediately after the final ACK and carry out a single byte read, block read, or block write operation without asserting an intermediate stop condition. The protocol is also used to set up a 2-byte EEPROM address for a subsequent read or block read. In this case, the command byte is the high byte of the EEPROM address from 80h to 9Fh. The (only) data byte is the low byte of the EEPROM address. This is illustrated in Figure 21. 1 2 3 4 5 6 7 8 EEPROM EEPROM ADDRESS SLAVE W A S A ADDRESS A P HIGH BYTE ADDRESS LOW BYTE (80h TO 9Fh) (00h TO FFh) 02657-A-021 S W P A R A Write Byte/Word In this operation, the master device sends a command byte and one or two data bytes to the slave device as follows: 02657-A-020 Bit 3 of EEPROM Register 3 is used for EEPROM write protection. Setting this bit prevents accidental programming or erasure of the EEPROM. If an EEPROM write or erase operation is attempted when this bit is set, the ADM1026 responds with No Acknowledge. This bit is write-once and can only be cleared by a power-on reset. Figure 21. Setting an EEPROM Address If it is required to read data from the EEPROM immediately after setting up the address, the master can assert a repeat start condition immediately after the final ACK and carry out a single-byte read or block read operation without asserting an intermediate stop condition. In this case, Bit 0 of EEPROM Register 3 should be set. The third use is to erase a page of EEPROM memory. EEPROM memory can be written to only if it is previously erased. Before writing to one or more EEPROM memory locations that are already programmed, the page or pages containing those locations must first be erased. EEPROM memory is erased by writing an EEPROM page address plus an arbitrary byte of data with Bit 2 of EEPROM Register 3 set to 1. Rev. A | Page 14 of 56 ADM1026 Because the EEPROM consists of 128 pages of 64 bytes, the EEPROM page address consists of the EEPROM address high byte (from 80h to 9Fh) and the two MSBs of the low byte. The lower six bits of the EEPROM address (low byte only) specify addresses within a page and are ignored during an erase operation. 3 4 5 6 7 9 10 8 02657-A-022 EEPROM EEPROM ADDRESS ADDRESS SLAVE ARBITRARY A W A S A A Y HIGH BYTE LOW BYTE ADDRESS DATA (80h TO 9Fh) (00h TO FFh) S COMMAND SLAVE DATA W A A0h BLOCK A BYTE A DATA 1 A DATA 2 A A PEC A ADDRESS 32 COUNT WRITE Figure 22. EEPROM Page Erasure Figure 24. Block Write to EEPROM or RAM Page erasure takes approximately 20 ms. If the EEPROM is accessed before erasure is complete, the ADM1026 responds with No Acknowledge. When performing a block write to EEPROM, Bit 1 of EEPROM Register 3 must be set. Last, this protocol is used to write a single byte of data to EEPROM. In this case, the command byte is the high byte of the EEPROM address from 80h to 9Fh. The first data byte is the low byte of the EEPROM address, and the second data byte is the actual data. Bit 1 of EEPROM Register 3 must be set. This is illustrated in Figure 23. 2 3 4 5 6 7 8 EEPROM EEPROM ADDRESS ADDRESS SLAVE A W A S A DATA LOW BYTE HIGH BYTE ADDRESS (00h TO FFh) (80h TO 9Fh) 9 10 A Y 02657-A-023 1 Figure 23. Single-Byte Write to EEPROM Block Write In this operation, the master device writes a block of data to a slave device. The start address for a block write must have been set previously. In the case of the ADM1026, this is done by a Send Byte operation to set a RAM address or by a write byte/word operation to set an EEPROM address. 1. 2. 3. 4. 5. 6. 7. 8. P 02857-A-024 2 The master device asserts a start condition on the SDA. The master sends the 7-bit slave address followed by the write bit (low). The addressed slave device asserts an ACK on the SDA. The master sends a command code that tells the slave device to expect a block write. The ADM1026 command code for a block write is A0h (10100000). The slave asserts an ACK on the SDA. The master sends a data byte (20h) that tells the slave device that 32 data bytes are being sent to it. The master should always send 32 data bytes to the ADM1026. The slave asserts an ACK on the SDA. The master sends 32 data bytes. Unlike some EEPROM devices that limit block writes to within a page boundary, there is no limitation on the start address when performing a block write to EEPROM, except: • There must be at least 32 locations from the start address to the highest EEPROM address (9FFF) to avoid writing to invalid addresses. • If the addresses cross a page boundary, both pages must be erased before programming. ADM1026 Read Operations The ADM1026 uses the SMBus read protocols described here. Receive Byte In this operation, the master device receives a single byte from a slave device as follows: 1. 2. 3. 4. 5. 6. The master device asserts a start condition on the SDA. The master sends the 7-bit slave address followed by the read bit (high). The addressed slave device asserts an ACK on the SDA. The master receives a data byte. The master asserts a NO ACK on the SDA. The master asserts a stop condition on the SDA to end the transaction. In the ADM1026, the receive byte protocol is used to read a single byte of data from a RAM or EEPROM location whose address has previously been set by a send byte or write byte/word operation. Figure 25 shows this. When reading from EEPROM, Bit 0 of EEPROM Register 3 must be set. 1 S 2 3 4 SLAVE R A DATA ADDRESS 5 6 A P 02657-A-025 1 9. The slave asserts an ACK on the SDA after each data byte. 10. The master sends a packet error checking (PEC ) byte. 11. The ADM1026 checks the PEC byte and issues an ACK if correct. If incorrect (NACK), the master resends the data bytes. 12. The master asserts a stop condition on the SDA to end the transaction. Figure 25. Single-Byte Read from EEPROM or RAM Rev. A | Page 15 of 56 ADM1026 Block Read In this operation, the master device reads a block of data from a slave device. The start address for a block read must have been set previously. In the case of the ADM1026 this is done by a send byte operation to set a RAM address, or by a write byte/word operation to set an EEPROM address. The block read operation consists of a send byte operation that sends a block read command to the slave, immediately followed by a repeated start and a read operation that reads out multiple data bytes as follows: When block reading from EEPROM, Bit 0 of EEPROM Register 3 must be set. 1. 2. MEASUREMENT INPUTS 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. S A COMMAND SLAVE W A A1h BLOCK A ADDRESS READ BYTE COUNT A DATA 1 A DATA 32 SLAVE ADDRESS S A PEC A R P 02657-A-026 3. 4. The master device asserts a start condition on the SDA. The master sends the 7-bit slave address followed by the write bit (low). The addressed slave device asserts an ACK on the SDA. The master sends a command code that tells the slave device to expect a block read. The ADM1026 command code for a block read is A1h (10100001). The slave asserts an ACK on the SDA. The master asserts a repeat start condition on the SDA. The master sends the 7-bit slave address followed by the read bit (high). The slave asserts an ACK on the SDA. The ADM1026 sends a byte count data byte that tells the master how many data bytes to expect. The ADM1026 always returns 32 data bytes (20h), the maximum allowed by the SMBus 1.1 specification. The master asserts an ACK on the SDA. The master receives 32 data bytes. The master asserts an ACK on the SDA after each data byte. The ADM1026 issues a PEC byte to the master. The master should check the PEC byte and issue another block read if the PEC byte is incorrect. A NACK is generated after the PEC byte to signal the end of the read. The master asserts a stop condition on the SDA to end the transaction. Note that although the ADM1026 supports packet error checking (PEC), its use is optional. The PEC byte is calculated using CRC-8. The frame check sequence (FCS) conforms to CRC-8 by the polynomial: C(x) = x8 + x2 + x1 + 1 Consult the SMBus 1.1 Specification for more information. The ADM1026 has 17 external analog measurement pins that can be configured to perform various functions. It also measures two supply voltages, 3.3 V MAIN and 3.3 V STBY, and the internal chip temperature. Pins 25 and 26 are dedicated to remote temperature measurement, while Pins 27 and 28 can be configured as analog inputs with a range of 0 V to 2.5 V, or as inputs for a second remote temperature sensor. Pins 29 to 33 are dedicated to measuring VBAT, +5 V, −12 V, +12 V supplies, and the processor core voltage VCCP. The remaining analog inputs, Pins 34 to 41, are general-purpose analog inputs with a range of 0 V to 2.5 V (Pins 34 and 35) or 0 V to 3 V (Pins 36 to 41). A-to-D Converter (ADC) These inputs are multiplexed into the on-chip, successive approximation, analog-to-digital converter. The ADC has a resolution of 8 bits. The basic input range is 0 V to 2.5 V, which is the input range of AIN6 to AIN9, but five of the inputs have built-in attenuators to allow measurement of VBAT, +5 V, −12 V, +12 V, and the processor core voltage VCCP, without any external components. To allow the tolerance of these supply voltages, the ADC produces an output of 3/4 full scale (decimal 192) for the nominal input voltage, and so has adequate headroom to cope with over voltages. Table 6 shows the input ranges of the analog inputs and output codes of the ADC. When the ADC is running, it samples and converts an analog or local temperature input every 711 µs (typical value). Each input is measured 16 times and the measurements are averaged to reduce noise, so the total conversion time for each input is 11.38 ms. Figure 26. Block Read from EEPROM or RAM Measurements on the remote temperature (D1 and D2) inputs take 2.13 ms. These are also measured 16 times and are averaged, so the total conversion time for a remote temperature input is 34.13 ms. Rev. A | Page 16 of 56 ADM1026 Table 6. A-to-D Output Code vs. VIN +12 VIN < 0.0625 0.062-0.125 0.125-0.187 0.188-0.250 0.250-0.313 0.313-0.375 0.375-0.438 0.438-0.500 0.500-0.563 +5 VIN < 0.026 0.026-0.052 0.052-0.078 0.078-0.104 0.104-0.130 0.130-0.156 0.156-0.182 0.182-0.208 0.208-0.234 Input Voltage 3.3 V MAIN 3.3 V STBY VBAT1 < 0.0172 NA 0.017-0.034 NA 0.034-0.052 NA 0.052-0.069 NA 0.069-0.086 NA 0.086-0.103 NA 0.103-0.120 NA 0.120-0.138 NA 0.138-0.155 NA A-to-D Output VCCP < 0.012 0.012-0.023 0.023-0.035 0.035-0.047 0.047-0.058 0.058-0.070 0.070-0.082 0.082-0.094 0.094-0.105 AIN (0–5) < 0.012 0.012-0.023 0.023-0.035 0.035-0.047 0.047-0.058 0.058-0.070 0.070-0.082 0.082-0.094 0.094-0.105 AIN (6–9) < 0.010 0.010-0.019 0.019-0.029 0.029-0.039 0.039-0.049 0.049-0.058 0.058-0.068 0.068-0.078 0.078-0.087 Decimal 0 1 2 3 4 5 6 7 8 Binary 00000000 00000001 00000010 00000011 00000100 00000101 00000110 00000111 00001000 1.667-1.693 1.110-1.127 NA 0.750-0.780 0.750-0.780 0.625-0.635 64 (1⁄4 scale) 01000000 4.000-4.063 –12 VIN < -15.928 −15.928-15.855 −15.855-15.783 −15.783-15.711 −15.711-15.639 −15.639-15.566 −15.566-15.494 −15.494-15.422 −15.422-15.349 • • • −11.375-11.303 8.000-8.063 • • • −6.750−6.678 3.333-3.359 2.000-2.016 2.000-2.016 1.500-1.512 1.500-1.512 1.250-1.260 128 (1⁄2 scale) 12.000-12.063 • • • −2.125-2.053 5-5.026 3.330-3.347 3.000-3.016 2.250-2.262 2.250-2.262 1.875-1.885 192 (3⁄4 scale) 11000000 15.313-15.375 15.375-15.437 15.437-15.500 15.500-15.563 15.562-15.625 15.625-15.688 15.688-15.750 15.750-15.812 15.812-15.875 15.875-15.938 >15.938 • • • 1.705-1.777 1.777-1.850 1.850-1.922 1.922-1.994 1.994-2.066 2.066-2.139 2.139-2.211 2.211-2.283 2.283-2.355 2.355-2.428 >2.428 6.38-6.406 6.406-6.432 6.432-6.458 6.458-6.484 6.484-6.51 6.51-6.536 6.536-6.563 6.563-6.589 6.589-6.615 6.615-6.641 >6.634 4.249-4.267 4.267-4.284 4.284-4.301 4.301-4.319 4.319-4.336 4.336-4.353 4.353-4.371 4.371-4.388 4.388-4.405 4.405-4.423 >4.423 3.828-3.844 3.844-3.860 3.860-3.875 3.875-3.890 3.890-3.906 3.906-3.921 3.921-3.937 3.937-3.953 3.953-3.969 3.969-3.984 >3.984 2.871-2.883 2.883-2.895 2.895-2.906 2.906-2.918 2.918-2.930 2.930-2.941 2.941-2.953 2.953-2.965 2.965-2.977 2.977-2.988 >2.988 2.871-2.883 2.883-2.895 2.895-2.906 2.906-2.918 2.918-2.930 2.930-2.941 2.941-2.953 2.953-2.965 2.965-2.977 2.977-2.988 >2.988 2.392-2.402 2.402-2.412 2.412-2.422 2.422-2.431 2.431-2.441 2.441-2.451 2.451-2.460 2.460-2.470 2.470-2.480 2.480-2.490 >2.490 245 246 247 248 249 250 251 252 253 254 255 11110101 11110110 11110111 11111000 11111001 11111010 11111011 11111100 11111101 11111110 11111111 1 VBAT is not accurate for voltages under 1.5 V (see Figure 15). Rev. A | Page 17 of 56 10000000 ADM1026 Voltage Measurement Inputs The internal structure for all the analog inputs is shown in Figure 27. Each input circuit consists of an input protection diode, an attenuator, plus a capacitor to form a first-order lowpass filter that gives each voltage measurement input immunity to high frequency noise. The −12 V input also has a resistor connected to the on-chip reference to offset the negative voltage range so that it is always positive and can be handled by the ADC. This allows most popular power supply voltages to be monitored directly by the ADM1026 without requiring any additional resistor scaling. However, when scaling AIN0 to AIN5, it should be noted that these inputs already have an on-chip attenuator, because their primary function is to monitor SCSI termination voltages. This attenuator loads any external attenuator. The input resistance of the on-chip attenuator can be between 100 kΩ and 200 kΩ. For this tolerance not to affect the accuracy, the output resistance of the external attenuator should be very much lower than this, that is, 1 kΩ in order to add not more than 1% to the total unadjusted error (TUE). Alternatively, the input can be buffered using an op amp. AIN0 – AIN5 (0V – 3V) 109.4kΩ 4.6pF ) ( ) R1 V fs − 2.5 (for AIN6 to AIN9 ) = R2 2.5 52.5kΩ AIN6 – AIN9 (0V – 2.5V) ( R1 V fs − 3.0 (for AIN0 to AIN5 ) = R2 3.0 21.9kΩ Negative and bipolar input ranges can be accommodated by using a positive reference voltage to offset the input voltage range so that it is always positive. To monitor a negative input voltage, an attenuator can be used as shown in Figure 29. 4.6pF 113.5kΩ +12V 9.3pF 21kΩ R2 VREF 17.5kΩ MUX VIN –12V R1 AIN(0–9) 02657-A-029 114.3kΩ 9.3pF 83.5kΩ +5V Figure 29. Scaling and Offsetting AIN0 − AIN9 for Negative Inputs 50kΩ 4.6pF This offsets the negative voltage so that the ADC always sees a positive voltage. R1 and R2 are chosen so that the ADC input voltage is zero when the negative input voltage is at its maximum (most negative) value, that is: 49.5kΩ VBAT 82.7kΩ 4.5pF R1 V fs − = R2 VOS * SEE TEXT 21.9k 109.4kΩ This is a simple and low cost solution, but note the following: 18.5pF 02657-A-027 +VCCP • Figure 27. Voltage Measurement Inputs Setting Other Input Ranges AIN0 to AIN9 can easily be scaled to voltages other than 2.5 V or 3 V. If the input voltage range is zero to some positive voltage, all that is required is an input attenuator, as shown in Figure 28. • R1 AIN(0–9) R2 Figure 28. Scaling AIN0 − AIN9 02657-A-028 VIN Because the input signal is offset but not inverted, the input range is transposed. An increase in the magnitude of the negative voltage (going more negative) causes the input voltage to fall and give a lower output code from the ADC. Conversely, a decrease in the magnitude of the negative voltage causes the ADC code to increase. The maximum negative voltage corresponds to zero output from the ADC. This means that the upper and lower limits are transposed. For the ADC output to be full scale when the negative voltage is zero, VOS must be greater than the full-scale voltage of the ADC, because VOS is attenuated by R1 and R2. If VOS is equal to or less than the full-scale voltage of the ADC, the input range is bipolar but not necessarily symmetrical. This is a problem only if the ADC output must be full scale when the negative voltage is zero. Rev. A | Page 18 of 56 ADM1026 Symmetrical bipolar input ranges can be accommodated easily by making VOS equal to the full-scale voltage of the analog input, and by adding a third resistor to set the positive full scale. For example, when VBAT = 3 V, I= +VOS R1 100 k Ω × 711 µs 273 ms = 78 nA where TPULSE = VBAT measurement time (711 µs typical), TPERIOD = time to measure all analog inputs (273 ms typical), and VBAT input battery protection. R2 VIN 3V AIN(0–9) 02657-A-030 VBAT Input Battery Protection R3 Figure 30. Scaling and Offsetting AIN0 − AIN9 for Bipolar Inputs R1 V fs − = R2 VOS Note that R3 has no effect as the input voltage at the device pin is zero when VIN = negative full scale. ( ) R1 V fs − 3.0 (for AIN0 to AIN5 ) = R3 3.0 R1 (V = R3 fs − 2.5 2. 5 ) (for A In addition to minimizing battery current drain, the VBAT measurement circuitry was specifically designed with battery protection in mind. Internal circuitry prevents the battery from being back-biased by the ADM1026 supply or through any other path under normal operating conditions. In the unlikely event of a catastrophic ADM1026 failure, the ADM1026 includes a second level of battery protection including a series 3 kΩ resistor to limit current to the battery, as recommended by UL. Thus, it is not necessary to add a series resistor between the battery and the VBAT input; the battery can be connected directly to the VBAT input to improve voltage measurement accuracy. VBAT IN6 to AIN9 ) 49.5kΩ Also, note that R2 has no effect as the input voltage at the device pin is equal to VOS when VIN = positive full scale. 3kΩ DIGITAL CONTROL ADC 82.7kΩ 02657-A-031 4.5pF 3kΩ Battery Measurement Input (VBAT) The VBAT input allows the condition of a CMOS backup battery to be monitored. This is typically a lithium coin cell such as a CR2032. The VBAT input is accurate only for voltages greater than 1.5 V (see Figure 15). Typically, the battery in a system is required to keep some device powered on when the system is in a powered-off state. The VBAT measurement input is specially designed to minimize battery drain. To reduce current drain from the battery, the lower resistor of the VBAT attenuator is not connected, except whenever a VBAT measurement is being made. The total current drain on the VBAT pin is 80 nA typical (for a maximum VBAT voltage = 4 V), so a CR2032 CMOS battery functions in a system in excess of the expected 10 years. Note that when a VBAT measurement is not being made, the current drain is reduced to 6 nA typical. Under normal voltage measurement operating conditions, all measurements are made in a round-robin format, and each reading is actually the result of 16 digitally averaged measurements. However, averaging is not carried out on the VBAT measurement to reduce measurement time and therefore reduce the current drain from the battery. Figure 31. Equivalent VBAT Input Protection Circuit Reference Output (VREF) The ADM1026 offers an on-chip reference voltage (Pin 24) that can be used to provide a 1.82 V or 2.5 V reference voltage output. This output is buffered and specified to sink or source a load current of 2 mA. The reference voltage outputs 1.82 V if Bit 2 of Configuration Register 3 (Address 07h) is 0; it outputs 2.5 V when this bit is set to 1. This voltage reference output can be used to provide a stable reference voltage to external circuitry such as LDOs. The load regulation of the VREF output is typically 0.15% for a sink current of 2 mA and 0.15% for 2 mA source current. There may be some ripple present on the VREF output that requires filtering (±4 m VMAX). Figure 32 shows the recommended circuitry for the VREF output for loads less than 2 mA. For loads in excess of 2 mA, external circuitry, such as that shown in Figure 33, can be used to buffer the VREF output. The VBAT current drain when a measurement is being made is calculated by ADM1026 24 10kΩ VREF VREF 0.1µF 02657-A-033 V T I = BAT × PULSE 100 k Ω TPERIOD Figure 32. VREF Interface Circuit for VREF Loads < 2 mA Rev. A | Page 19 of 56 ADM1026 If the VREF output is not being used, it should be left unconnected. Do not connect VREF to GND using a capacitor. The internal output buffer on the voltage reference is capacitively loaded, which can cause the voltage reference to oscillate. This affects temperature readings reported back by the ADM1026. The recommended interface circuit for the VREF output is shown in Figure 33. +12V ADM1026 VREF 24 The forward voltage of a diode or diode-connected transistor, operated at a constant current, exhibits a negative temperature coefficient of about −2 mV/°C. Unfortunately, the absolute value of Vbe varies from device to device, and individual calibration is required to null this out, so the technique is unsuitable for mass production. The technique used in the ADM1026 is to measure the change in Vbe when the device is operated at two different currents, given by ΔVbe = 10kΩ NDT3055 0.1µF 50Ω 0.1µF 10µF 02657-A-034 VREF Figure 33. VREF Interface Circuit for VREF Loads > 2 mA TEMPERATURE MEASUREMENT SYSTEM Local Temperature Measurement The ADM1026 contains an on-chip band gap temperature sensor whose output is digitized by the on-chip ADC. The temperature data is stored in the local temperature value register (Address 1Fh). As both positive and negative temperatures can be measured, the temperature data is stored in twos complement format, as shown in Table 7. Theoretically, the temperature sensor and ADC can measure temperatures from −128°C to +127°C with a resolution of 1°C. Temperatures below TMIN and above TMAX are outside the operating temperature range of the device, however, so local temperature measurements outside this range are not possible. Temperature measurement from −128°C to +127°C is possible using a remote sensor. Remote Temperature Measurement The ADM1026 can measure the temperature of two remote diode sensors, or diode-connected transistors, connected to Pins 25 and 26, or 27 and 28. Pins 25 and 26 are a dedicated temperature input channel. Pins 27 and 28 can be configured to measure a diode sensor by clearing Bit 3 of Configuration Register 1 (Address 00h) to 0. If this bit is 1, then Pins 27 and 28 are AIN8 and AIN9. K ×T q × log n(N ) where K is Boltzmann’s constant, q is the charge on the carrier, T is the absolute temperature in Kelvins, and N is the ratio of the two currents. Figure 34 shows the input signal conditioning used to measure the output of a remote temperature sensor. This figure shows the external sensor as a substrate transistor provided for temperature monitoring on some microprocessors, but it could equally well be a discrete transistor such as a 2N3904. If a discrete transistor is used, the collector is not grounded and should be linked to the base. If a PNP transistor is used, the base is connected to the D− input and the emitter to the D+ input. If an NPN transistor is used, the emitter is connected to the D− input and the base to the D+ input. To prevent ground noise from interfering with the measurement, the more negative terminal of the sensor is not referenced to ground but is biased above ground by an internal diode at the D− input. To measure ΔVbe, the sensor is switched between operating currents of I and N × I. The resulting waveform is passed through a 65 kHz low-pass filter to remove noise, and to a chopper-stabilized amplifier that performs the functions of amplification and rectification of the waveform to produce a DC voltage proportional to ΔVbe. This voltage is measured by the ADC to give a temperature output in 8-bit, twos complement format. To further reduce the effects of noise, digital filtering is performed by averaging the results of 16 measurement cycles. A remote temperature measurement takes nominally 2.14 ms. Rev. A | Page 20 of 56 ADM1026 VDD N×I IBIAS D+ VOUT+ TO ADC C1* REMOTE SENSING TRANSISTOR D– BIAS DIODE VOUT– LOW-PASS FILTER fC = 65kHz * CAPACITOR C1 IS OPTIONAL. IT IS ONLY NECESSARY IN NOISY ENVIRONMENTS. C1 = 2.2nF TYPICAL, 3nF MAX. 02657-A-032 I Figure 34. Signal Conditioning for Remote Diode Temperature Sensors The results of external temperature measurements are stored in 8-bit, twos complement format, as illustrated in Table 7. 10MIL Table 7. Temperature Data Format Digital Output 1000 0000 1000 0011 1001 1100 1011 0101 1100 1110 1110 0111 11110110 0000 0000 0000 1010 0001 1001 0011 0010 0100 1011 0110 0100 0111 1101 0111 1111 10MIL 10MIL D– 10MIL GND 10MIL Figure 35. Arrangement of Signal Tracks Layout Considerations Digital boards can be electrically noisy environments. Take these precautions to protect the analog inputs from noise, particularly when measuring the very small voltages from a remote diode sensor. • Try to minimize the number of copper/solder joints, which can cause thermocouple effects. Where copper/solder joints are used, make sure that they are in both the D+ and D− paths and are at the same temperature. • Thermocouple effects should not be a major problem because 1°C corresponds to about 240 µV, and thermocouple voltages are about 3 µV/°C of temperature difference. Unless there are two thermocouples with a big temperature differential between them, thermocouple voltages should be much less than 200 mV. • • Place a 0.1 µF bypass capacitor close to the ADM1026. If the distance to the remote sensor is more than eight inches, the use of twisted-pair cable is recommended. This works from about 6 to 12 feet. For very long distances (up to 100 feet), use shielded twisted pair such as Belden #8451 microphone cable. Connect the twisted pair to D+ and D− and the shield to GND close to the ADM1026. Leave the remote end of the shield unconnected to avoid ground loops. • • Place the ADM1026 as close as possible to the remote sensing diode. Provided that the worst noise sources such as clock generators, data/address buses, and CRTs are avoided, this distance can be 4 to 8 inches. • Route the D+ and D− tracks close together, in parallel, with grounded guard tracks on each side. Provide a ground plane under the tracks if possible. Use wide tracks to minimize inductance and reduce noise pickup. A 10 mil track minimum width and spacing is recommended. • 10MIL D+ Hex 80 83 9C B5 CE E7 F6 00 0A 19 32 4B 64 7D 7F 02657-A-035 Temperature −128°C −125°C −100°C −75°C −50°C −25°C −10°C 0°C 10°C 25°C 50°C 75°C 100°C 125°C 127°C 10MIL GND Because the measurement technique uses switched current sources, excessive cable and/or filter capacitance can affect the measurement. When using long cables, the filter capacitor may be reduced or removed. Cable resistance can also introduce errors. A 1 Ω series resistance introduces about 0.5°C error. Rev. A | Page 21 of 56 ADM1026 Limit Values Limit values for analog measurements are stored in the appropri ate limit registers. In the case of voltage measurements, high and low limits can be stored so that an interrupt request is generated if the measured value goes above or below acceptable values. In the case of temperature, a hot temperature or high limit can be programmed, and a hot temperature hysteresis or low limit can be programmed, which is usually some degrees lower. This can be useful because it allows the system to be shut down when the hot limit is exceeded, and restarted automatically when it has cooled down to a safe temperature. Analog Monitoring Cycle Time The analog monitoring cycle begins when a 1 is written to the start bit (Bit 0), and a 0 to the INT_Clear bit (Bit 2) of the configuration register. INT_Enable (Bit 1) should be set to 1 to enable the INToutput. The ADC measures each analog input in turn, starting with Remote Temperature Channel 1 and ending with local temperature. As each measurement is completed, the result is automatically stored in the appropriate value register. This round-robin monitoring cycle continues until it is disabled by writing a 0 to Bit 0 of the configuration register. Because the ADC is typically left to free-run in this way, the most recently measured value of any input can be read out at any time. For applications where the monitoring cycle time is important, it can easily be calculated. The total number of channels measured is • • • • • • Five dedicated supply voltage inputs Ten general-purpose analog inputs 3.3 V MAIN 3.3 V STBY Local temperature Two remote temperature The ADC uses the internal 22.5 kHz clock, which has a tolerance of ±6%, so the worst-case monitoring cycle time is 290 ms. The fan speed measurement uses a completely separate monitoring loop, as described later. Input Safety Scaling of the analog inputs is performed on-chip, so external attenuators are typically not required. However, because the power supply voltages appear directly at the pins, it is advisable to add small external resistors (that is, 500 Ω) in series with the supply traces to the chip to prevent damaging the traces or power supplies should an accidental short such as a probe connect two power supplies together. Because the resistors form part of the input attenuators, they affect the accuracy of the analog measurement if their value is too high. The worst such accident would be connecting −12 V to +12 V where there is a total of 24 V difference. With the series resistors, this would draw a maximum current of approximately 24 mA. ANALOG OUTPUT The ADM1026 has a single analog output from an unsigned 8-bit DAC that produces 0 V to 2.5 V (independent of the reference voltage setting). The input data for this DAC is contained in the DAC control register (Address 04h). The DAC control register defaults to FFh during a power-on reset, which produces maximum fan speed. The analog output may be amplified and buffered with external circuitry such as an op amp and a transistor to provide fan speed control. During automatic fan speed control, described later, the four MSBs of this register set the minimum fan speed. Suitable fan drive circuits are shown in Figure 36 through Figure 40. When using any of these circuits, note the following: Pins 28 and 27 are measured both as analog inputs AIN8/AIN9 and as remote temperature input D2+/D2−, irrespective of which configuration is selected for these pins. If Pins 28 and 27 are configured as AIN8/AIN9, the measurements for these channels are stored in Registers 27h and 29h, and the invalid temperature measurement is discarded. On the other hand, if Pins 28 and 27 are configured as D2+/D2−, the temperature measurement is stored in Register 29h, and there is no valid result in Register 27h. • • • • As mentioned previously, the ADC performs a conversion every 711 µs on the analog and local temperature inputs and every 2.13 ms on the remote temperature inputs. Each input is measured 16 times and averaged to reduce noise. The total monitoring cycle time for voltage and temperature inputs is therefore nominally • (18 × 16 × 0.711) + (2 × 16 × 2.13) = 273 ms Rev. A | Page 22 of 56 All of these circuits provide an output range from 0 V to almost +12 V, apart from Figure 36, which loses the baseemitter voltage drop of Q1 due to the emitter-follower configuration. To amplify the 2.5 V range of the analog output up to 12 V, the gain of these circuits needs to be about 4.8. Take care when choosing the op amp to ensure that its input common-mode range and output voltage swing are suitable. The op amp may be powered from the +12 V rail alone or from ±12 V. If it is powered from +12 V, the input common-mode range should include ground to accommodate the minimum output voltage of the DAC, and the output voltage should swing below 0.6 V to ensure that the transistor can be turned fully off. If the op amp is powered from −12 V, precautions such as a clamp diode to ground may be needed to prevent the base-emitter junction of the output transistor being reverse-biased in the unlikely event that the output of the op amp should swing negative for any reason. ADM1026 12V R2 100kΩ R2 100kΩ Q3 IRF9620 R3 39kΩ Q1/Q2 MBT3904 DUAL DAC R4 10kΩ 02657-A-039 12V 1/4 LM324 DAC Figure 39. Discrete Fan Drive Circuit with P-Channel MOSFET, Single Supply Q1 2N2219A +12V R2 100kΩ R2 36kΩ Q3 IRF9620 02657-A-036 R1 10kΩ R3 39kΩ Figure 36. Fan Drive Circuit with Op Amp and Emitter-Follower Q1/Q2 MBT3904 DUAL DAC R4 10kΩ 12V 1/4 LM324 R4 1kΩ DAC R3 1kΩ –12V Q1 BD136 2SA968 Figure 40. Discrete Fan Drive Circuit with P-Channel MOSFET, Dual Supply PWM Output R2 39kΩ R1 10kΩ Figure 37. Fan Drive Circuit with Op Amp and PNP Transistor 12V 1/4 LM324 Fan speed may also be controlled using pulse width modulation (PWM). The PWM output (Pin 18) produces a pulsed output with a frequency of approximately 75 Hz and a duty cycle defined by the contents of the PWM control register (Address 05h). During automatic fan speed control, described below, the four MSBs of this register set the minimum fan speed. The open drain PWM output must be amplified and buffered to drive the fans. The PWM output is intended to be used with an NMOS driver, but may be inverted by setting Bit 1 of Test Register 1 (Address 14h) if using PMOS drivers. Figure 41 shows how a fan may be driven under PWM control using an N-channel MOSFET. R3 100kΩ DAC 02657-A-040 R1 4.7kΩ 02657-A-037 +V Q1 IRF9620 3.3V 5V OR 12V FAN R2 39kΩ 10kΩ TYP R1 10kΩ PWM Q1 NDT3055L 02657-A-041 • In all these circuits, the output transistor must have an ICMAX greater than the maximum fan current, and be capable of dissipating power due to the voltage dropped across it when the fan is not operating at full speed. If the fan motor produces a large back EMF when switched off, it may be necessary to add clamp diodes to protect the output transistors in the event that the output goes from full scale to zero very quickly. 02657-A-038 • Figure 41. PWM Fan Drive Circuit Using an N-Channel MOSFET Figure 38. Fan Drive Circuit with Op Amp and P-Channel MOSFET Rev. A | Page 23 of 56 ADM1026 The ADM1026 offers a simple method of controlling fan speed according to temperature without intervention from the host processor. Monitoring must be enabled by setting Bit 0 of Configuration Register 1 (Address 00h), to enable automatic fan speed control. Automatic fan speed control can be applied to the DAC output, the PWM output, or both, by setting Bit 5 and/or Bit 6 of Configuration Register 1. The TMIN registers (Addresses 10h to 12h) contain minimum temperature values for the three temperature channels (on-chip sensor and two remote diodes). This is the temperature at which a fan starts to operate when the temperature sensed by the controlling sensor exceeds TMIN. TMIN can be the same or different for all three channels. TMIN is set by writing a twos complement temperature value to the TMIN registers. If any sensor channel is not required for automatic fan speed control, TMIN for that channel should be set to 127°C (01111111). In automatic fan speed control mode, (as shown Figure 42 and Figure 43) the four MSBs of the DAC control register (Address 04h) and PWM control register (Address 05h) set the minimum values for the DAC and PWM outputs. Note that, if both DAC control and PWM control are enabled (Bits 5 and 6 of Configuration Register 1 = 1), the four MSBs of the DAC control register (Address 04h) define the minimum fan speed values for both the DAC and PWM outputs. The value in the PWM control register (Address 05h) has no effect. output jumps to full scale. To ensure that the maximum cooling capacity is always available, the fan drive is always set by the sensor channel demanding the highest fan speed. If the temperature falls, the fan does not turn off until the temperature measured by all three temperature sensors has fallen to their corresponding TMIN − 4°C. This prevents the fan from cycling on and off continuously when the temperature is close to TMIN. Whenever a fan starts or stops during automatic fan speed control, a one-off interrupt is generated at the INT output. This is described in more detail in the section on the ADM1026 Interrupt Structure. SPIN UP FOR 2 SECONDS 100% PWM OUTPUT MIN TMIN – 4°C Minimum DAC Code DACMIN = 16 × D Figure 42. Automatic PWM Fan Control Transfer Function Code 256 SPIN UP FOR 2 SECONDS 255 Minimum PWM Duty Cycle PWMMIN = 6.67 × D 240 where D is the decimal equivalent of Bits 7 to 4 of the register. DAC OUTPUT When the temperature measured by any of the sensors exceeds the corresponding TMIN, the fan is spun up for 2 seconds with the fan drive set to maximum (full scale from the DAC or 100% PWM duty cycle). The fan speed is then set to the minimum as previously defined. As the temperature increases, the fan drive increases until the temperature reaches TMIN + 20°C. MIN The fan drive at any temperature up to 20°C above TMIN is given by PWM = PWM MIN + (100 − PWM MIN ) × TMIN – 4°C TMIN TMIN + 20°C TEMPERATURE TACTUAL − TMIN 20 or DAC = DAC MIN TMIN + 20°C T − TMIN + (240 − DAC MIN ) × ACTUAL 20 For simplicity of the automatic fan speed algorithm, the DAC code increases linearly up to 240, not its full scale of 255. However, when the temperature exceeds TMIN +20°C, the DAC 02657-A-043 DAC Output Voltage = 2.5 × TMIN TEMPERATURE 02657-A-042 Automatic Fan Speed Control Figure 43. Automatic DAC Fan Control Transfer Function Fan Inputs Pins 3 to 6 and 9 to 12 may be configured as fan speed measuring inputs by clearing the corresponding bit(s) of Configuration Register 2 (Address 01h), or as general-purpose logic inputs/outputs by setting bits in this register. The poweron default value for this register is 00h, which means all the inputs are set for fan speed measurement. Rev. A | Page 24 of 56 ADM1026 If the fan tach output is open-drain or has a resistive pull-up to VCC, then it can be connected directly to the fan input, as shown in Figure 44. TACH OUTPUT FAN(0–7) PULL-UP TYP <1 kΩ OR TOTEM POLE 12V VCC <1 kΩ R1* FAN SPEED COUNTER VCC ZD1* ZENER FAN SPEED COUNTER * CHOOSE ZD1 VOLTAGE APPROXIMATELY 0.8 × VCC 02657-A-045 TACH OUTPUT FAN(0–7) Figure 47. Fan with Strong Tach Pull-Up to >VCC or Totem Pole Output, Attenuated with R1/R2 FAN SPEED MEASUREMENT The fan counter does not count the fan tach output pulses directly because the fan speed may be less than 1000 RPM and it would take several seconds to accumulate a reasonably large and accurate count. Instead, the period of the fan revolution is measured by gating an on-chip 22.5 kHz oscillator into the input of an 8-bit counter for two periods of the fan tach output, as shown in Figure 48, so the accumulated count is actually proportional to the fan tach period and inversely proportional to the fan speed. 22.5kHz CLOCK Figure 45. Fan with Tach Pull-Up to Voltage > VCC (e.g. 12 V), Clamped with Zener Diode If the fan has a strong pull-up (less than 1 kΩ) to +12 V, or a totem pole output, a series resistor can be added to limit the Zener current, as shown in Figure 46. Alternatively, a resistive attenuator may be used, as shown in Figure 47. CONFIGURATION REG. 1 BIT 0 1 2 3 4 FAN0 INPUT 1 2 3 4 FAN1 INPUT R1 and R2 should be chosen such that 2V < VPULLUP × FAN SPEED COUNTER * SEE TEXT If the fan output has a resistive pull-up to +12 V (or other voltage greater than 3.3 V STBY), the fan output can be clamped with a Zener diode, as shown in Figure 45. The Zener voltage should be chosen so that it is greater than VIH but less than 3.3 V STBY, allowing for the voltage tolerance of the Zener. PULL-UP 4.7kΩ TYP FAN(0–7) TACH OUTPUT Figure 44. Fan with Tach Pull-Up to +VCC 12V FAN SPEED COUNTER Figure 46. Fan with Strong Tach Pull-Up to > VCC or Totem Pole Output, Clamped with Zener and Resistor 02657-A-044 TACH OUTPUT ZD1* ZENER START OF MONITORING CYCLE R2 < 3.3 V STBY (R PULLUP + R1 + R2) FAN0 MEASUREMENT PERIOD FAN1 MEASUREMENT PERIOD 02657-A-048 FAN(0–7) R1 10kΩ * CHOOSE ZD1 VOLTAGE APPROXIMATELY 0.8 × VCC VCC PULL-UP 4.7kΩ TYP VCC 02657-A-047 12V 12V 02657-A-046 Signal conditioning in the ADM1026 accommodates the slow rise and fall times typical of fan tachometer outputs. The fan tach inputs have internal 10 kΩ pull-up resistors to 3.3 V STBY. In the event that these inputs are supplied from fan outputs that exceed the supply, either resistive attenuation of the fan signal or diode clamping must be included to keep inputs within an acceptable range. Figure 44 through Figure 47 show circuits for common fan tach outputs. Figure 48. Fan Speed Measurement The monitoring cycle begins when a 1 is written to the monitor bit (Bit 0 of Configuration Register 1). The INT_Enable (Bit 1) should be set to 1 to enable the INT output. Rev. A | Page 25 of 56 ADM1026 The fan speed counter starts counting as soon as the fan channel has been switched to. If the fan tach count reaches 0xFF, the fan has failed or is not connected. If a fan is connected and running, the counter is reset on the second tach rising edge, and oscillator pulses are actually counted from the second rising tach edge to the fourth rising edge. The measurement then switches to the next fan channel. Here again, the counter begins counting and is reset on the second tach rising edge, and oscillator pulses are counted from the second rising edge to the fourth rising edge. This is repeated for the other six fan channels. Note that fan speed measurement does not occur until 1.8 seconds after the monitor bit has been set. This is to allow the fans adequate time to spin up. Otherwise, the ADM1026 could generate false fan failure interrupts. During the 1.8 second fan spin-up time, all fan tach registers read 0x00. To accommodate fans of different speed and/or different numbers of output pulses per revolution, a prescaler (divisor) of 1, 2, 4, or 8 may be added before the counter. Divisor values for Fans 0 to 3 are contained in the Fan 0–3 divisor register (Address 02h) and those for Fans 4 to 7 in the Fan 4–7 divisor register (Address 03h). The default value is 2, which gives a count of 153 for a fan running at 4400 RPM producing two output pulses per revolution. The count is calculated by the equation: Count = Limit Values Fans generally do not over-speed if run from the correct voltage, so the failure condition of interest is under speed due to electrical or mechanical failure. For this reason, only low speed limits are programmed into the limit registers for the fans. It should be noted that because fan period rather than speed is being measured, a fan failure interrupt occurs when the measurement exceeds the limit value. Fan Monitoring Cycle Time The fan speeds are measured in sequence from 0 to 7. The monitoring cycle time depends on the fan speed, the number of tach output pulses per revolution, and the number of fans being monitored. If a fan is stopped or running so slowly that the fan speed counter reaches 255 before the second tach pulse after initialization, or before the fourth tach pulse during measurement, the measurement is terminated. This also occurs if an input is configured as GPIO instead of fan. Any channels connected in this manner time out after 255 clock pulses. The worst-case measurement time for a fan-configured channel occurs when the counter reaches 254 from start to the second tach pulse and reaches 255 after the second tach pulse. Taking into account the tolerance of the oscillator frequency, the worstcase measurement time is 509 × D × 0.05 ms 22.5 × 10 3 × 60 RPM × Divisor For constant-speed fans, fan failure is typically considered to have occurred when the speed drops below 70% of nominal, corresponding to a count of 219. Full scale (255) is reached if the fan speed fell to 60% of its nominal value. For temperaturecontrolled, variable-speed fans, the situation is different. Table 8 shows the relationship between fan speed and time per revolution at 60%, 70%, and 100% of nominal RPM for fan speeds of 1100, 2200, 4400, and 8800 RPM, and the divisor that would be used for each of these fans, based on two tach pulses per revolution. where: 509 is the total number of clock pulses. D is the divisor: 1, 2, 4, or 8. 0.05 ms is the worst-case oscillator period in ms. The worst-case fan monitoring cycle time is the sum of the worst-case measurement time for each fan. Although the fan monitoring cycle and the analog input monitoring cycle are started together, they are not synchronized in any other way. Table 8. Fan Speeds and Divisors Divisor RPM ÷1 ÷2 ÷4 ÷8 Nominal Rev 8800 4400 2200 1100 RPM (ms) 6.82 13.64 27.27 54.54 70% RPM 6160 3080 1540 770 Rev. A | Page 26 of 56 Time Per Rev 70% (ms) 9.74 19.48 38.96 77.92 60% RPM 5280 2640 1320 660 Rev 60% (ms) 11.36 22.73 45.45 90.9 ADM1026 Chassis Intrusion Input General-Purpose I/O Pins (Open Drain) The chassis intrusion input is an active high input intended for detection and signaling of unauthorized tampering with the system. When this input goes high, the event is latched in Bit 6 of Status Register 4, and an interrupt is generated. The bit remains set until cleared by writing a 1 to CI clear, Bit 1 of Configuration Register 3 (05h), as long as battery voltage is connected to the VBAT input. The CI clear bit itself is cleared by writing a 0 to it. The ADM1026 has eight pins that are dedicated to generalpurpose logic input/output (Pins 1, 2, and 43 to 48), eight pins that can be configured as general-purpose logic pins or fan speed inputs (Pins 3 to 6, and 9 to 12), and one pin that can be configured as GPIO16 or the bidirectional THERM pin (Pin 42). The GPIO/FAN pins are configured as generalpurpose logic pins by setting Bits 0 to 7 of Configuration Register 2 (Address 01h). Pin 42 is configured as GPIO16 by setting Bit 0 of Configuration Register 3, or as the THERM function by clearing this bit. The CI input detects chassis intrusion events even when the ADM1026 is powered off (provided battery voltage is applied to VBAT) but does not immediately generate an interrupt. Once a chassis intrusion event is detected and latched, an interrupt is generated when the system is powered on. The actual detection of chassis intrusion is performed by an external circuit that detects, for example, when the cover has been removed. A wide variety of techniques may be used for the detection, for example: • • • • A microswitch that opens or closes when the cover is removed. A reed switch operated by magnet fixed to the cover. A hall-effect switch operated by magnet fixed to the cover. A phototransistor that detects light when the cover is removed. The chassis intrusion input can also be used for other types of alarm input. Figure 49 shows a temperature alarm circuit using an AD22105 temperature switch sensor. This produces a lowgoing output when the preset temperature is exceeded, so the output is inverted by Q1 to make it compatible with the CI input. Q1 can be almost any small-signal NPN transistor, or a TTL or CMOS inverter gate may be used if one is available. See the AD22105 data sheet on the Analog Devices, Inc. website (www.analog.com) for information on selecting RSET. VCC 6 7 AD22105 TEMPERATURE SENSOR 1 3 2 CI 18 Q1 02657-A-049 RSET R1 10kΩ Figure 49. Using the CI Input with a Temperature Sensor Each GPIO pin has four data bits associated with it, two bits in one of the GPIO configuration registers (Addresses 08h to 0Bh), one in the GPIO status registers (Addresses 24h and 25h), and one in the GPIO mask registers (Addresses 1Ch and 1Dh) Setting a direction bit = 1 in one of the GPIO configuration registers makes the corresponding GPIO pin an output. Clearing the direction bit to 0 makes it an input. Setting a polarity bit = 1 in one of the GPIO configuration registers makes the corresponding GPIO pin active high. Clearing the polarity bit to 0 makes it active low. When a GPIO pin is configured as an input, the corresponding bit in one of the GPIO status registers is read-only, and is set when the input is asserted (“asserted” may be high or low depending on the setting of the polarity bit). When a GPIO pin is configured as an output, the corresponding bit in one of the GPIO status registers becomes read/write. Setting this bit then asserts the GPIO output. (Here again, “asserted” may be high or low depending on the setting of the polarity bit.) The effect of a GPIO status register bit on the INT output can be masked out by setting the corresponding bit in one of the GPIO mask registers. When the pin is configured as an output, this bit is automatically masked to prevent the data written to the status bit from causing an interrupt, with the exception of GPIO16, which must be masked manually by setting Bit 7 of Mask Register 4 (Reg 1Bh). When configured as inputs, the GPIO pins may be connected to external interrupt sources such as temperature sensors with digital output. Another application of the GPIO pins would be to monitor a processor’s voltage ID code (VID code). Rev. A | Page 27 of 56 ADM1026 ADM1026 Interrupt Structure Interrupt Mask Registers 1, 2, and 4 have bits corresponding to each of the interrupt status register bits. Setting an interrupt mask bit high conceals an asserted status bit from display on Interrupt Pin 17. Setting an interrupt mask bit low allows the corresponding status bit to be asserted and displayed on Pin 17. After mask gating, the status bits are all OR’ed together to produce the analog and fan interrupt that is used to set a latch. The output of this latch is OR’ed with other interrupt sources to produce the INT output. This pulls low if any unmasked status bit goes high, that is, when any measured value goes out of limit. The Interrupt Structure of the ADM1026 is shown in Figure 53. Interrupts can come from a number of sources, which are combined to form a common INT output. When INT is asserted, this output pulls low. The INT pin has an internal, 100 kΩ pull-up resistor. Analog/Temperature Inputs As each analog measurement value is obtained and stored in the appropriate value register, the value and the limits from the corresponding limit registers are fed to the high and low limit comparators. The device performs greater than comparisons to the high limits. An out-of-limit is also generated if a result is less than or equal to a low limit. The result of each comparison (1 = out of limit, 0 = in limit) is routed to the corresponding bit input of Interrupt Status Register 1, 2, or 4 via a data demultiplexer, and used to set that bit high or low as appropriate. Status bits are self-clearing. If a bit in a status register is set due to an out-of-limit measurement, it continues to cause INT to be asserted as long as it remains set, as described later. However, if a subsequent measurement is in limit, it is reset and does not cause INT to be reasserted. Status bits are unaffected by clearing the interrupt. LOCAL TEMPERATURE MEASUREMENT INT CLEARED START OF ANALOG MONITORING CYCLE OUT-OF-LIMIT MEASUREMENT LOCAL TEMPERATURE MEASUREMENT INT START OF ANALOG MONITORING CYCLE INT RE-ASSERTED FULL MONITORING CYCLE = 273ms 02657-A-051 START OF ANALOG OUT-OF-LIMIT MONITORING MEASUREMENT CYCLE When an INT output caused by an out-of-limit analog/ temperature measurement is cleared by one of the methods described later, the latch is reset. It is not set again, and INT is not reasserted until after two local temperature measure-ments have been taken, even if the status bit remains set or a new analog/temperature event occurs, as shown in Figure 50. This delay corresponds to almost two monitoring cycles, and is about 530 ms. However, interrupts from other sources such as a fan or GPIO can still occur. This is illustrated in Figure 51. Figure 50. Delay After Clearing INT Before Reassertion START OF ANALOG OUT-OF-LIMIT MONITORING CYCLE MEASUREMENT INT CLEARED LOCAL TEMPEREATURE START OF ANALOG MEASUREMENT MONITORING CYCLE INT CLEARED LOCAL TEMPERATURE MEASUREMENT START OF ANALOG MONITORING CYCLE GPIO DE-ASSERTED INT NEW INT FROM FAN NEW INT FROM GPIO Figure 51. Other Interrupt Sources Can Reassert INT Immediately Rev. A | Page 28 of 56 02657-A-052 INT RE-ASSERTED ADM1026 Status Register 4 also stores inputs from two other interrupt sources that operate in a different way from the other status bits. If automatic fan speed control (AFC) is enabled, Bit 4 of Status Register 4 is set whenever a fan starts or stops. This bit causes a one-off INT output as shown in Figure 52. It is cleared during the next monitoring cycle and if INT has been cleared, it does not cause INT to be reasserted. The GPIO and CI status bits, after mask gating, are OR’ed together and OR’ed with other interrupt sources to produce the INT output. GPIO and CI interrupts are not latched and cannot be cleared by normal interrupt clearing. They can only be cleared by masking the status bits or by removing the source of the interrupt. ENABLING AND CLEARING INTERRUPTS The INT output is enabled when Bit 1 of Configuration Register 1 (INT_Enable) is high, and Bit 2 (INT_Clear) is low. INT may be cleared if FAN ON FAN OFF INT CLEARED BY STATUS REGULAR 1 READ, BIT 2 OF CONFIGURATION REGULAR 1 SET, OR ARA 02657-A-053 INT • Figure 52. Assertion of INT Due to AFC Event In a similar way, a change of state at the THERM output (described in more detail later), sets Bit 3 of Status Register 4 and causes a one-off INT output. A change of state at the THERM output also causes Bit 0 of Status Register 1, Bit 1 of Status Register 1, or Bit 0 of Status Register 4 to be set, depending on which temperature channel caused the THERM event. This bit is reset during the next monitoring cycle, provided the temperature channel is within the normal high and low limits. Fan Inputs Fan inputs generate interrupts in a similar way to analog/ temperature inputs, but as the analog/ temperature inputs and fan inputs have different monitoring cycles, they have separate interrupt circuits. As the speed of each fan is measured, the output of the fan speed counter is stored in a value register. The result is compared to the fan speed limit and is used to set or clear a bit in Status Register 3. In this case, the fan is monitored only for under-speed (fan counter > fan speed limit). Mask Register 3 is used to mask fan interrupts. After mask gating, the fan status bits are OR’ed together and used to set a latch, whose output is OR’ed with other interrupt sources to produce the INT output. Like the analog/temp interrupt, an INT output caused by an out-of-limit fan speed measurement, once cleared, is not reasserted until the end of the next monitoring cycle, although other interrupt sources may cause INT to be asserted. GPIO and CI Pins. When GPIO pins are configured as inputs, asserting a GPIO input (high or low, depending on polarity) sets the corresponding GPIO status bit in Status Registers 5 and 6, or Bit 7 of Status Register 4 (GPIO16). A chassis intrusion event sets Bit 6 of Status Register 4. • • Status Register 1 is read. Ideally, if polling the status registers trying to identify interrupt sources, Status Register 1 should be polled last, because a read of Status Register 1 clears all the other interrupt status registers. The ADM1026 receives the alert response address (ARA) (0001 100) over the SMBus. Bit 2 of Configuration Register 1 is set. Bidirectional THERM Pin The ADM1026 has a second interrupt pin (GPIO16/THERM Pin 42) that responds only to critical thermal events. The THERM pin goes low whenever a THERM limit is exceeded. This function is useful for CPU throttling or system shutdown. In addition, whenever THERM is activated, the PWM and DAC outputs go full scale to provide fail-safe system cooling. This output is enabled by setting Bit 4 of Configuration Register 1 (Register 00h). Whenever a THERM limit is exceeded, Bit 3 of Status Register 4 (Reg 23h) is set, even if the THERM function is disabled (Bit 4 of Configuration Register 1 = 0). In this case, the THERM status bit is set, but the PWM and DAC outputs are not forced to full scale. Three thermal limit registers are provided for the three temperature sensors at Addresses 0Dh to 0Fh. These registers are dedicated to the THERM function and none of the other limit registers have any effect on the THERM output. If any of the temperature measurements exceed the corresponding limit, THERM is asserted (low) and the DAC and PWM outputs go to maximum to drive any cooling fans to full speed. To avoid cooling fans cycling on and off continually when the temperature is close to the limit, a fixed hysteresis of 5°C is provided. THERM is only deasserted when the measured temperature of all three sensors is 5°C below the limit. Whenever the THERM output changes, INT is asserted, as shown in Figure 54. However, this is edge-triggered, so if INT is subsequently cleared by one of the methods previously described, it is not reasserted, even if THERM remains asserted. THERM causes INT to be reasserted only when it changes state. Rev. A | Page 29 of 56 ADM1026 MASK DATA FROM SMBus (SAME BIT NAMES AND ORDER AS STATUS BITS) VALUE LOW LIMIT 1 = OUT OF LIMIT AIN0 AIN1 AIN2 DATA DEMULTIPLEXER HIGH LIMIT HIGH AND LOW LIMIT COMPARATORS FROM ANALOG/TEMP VALUE AND LIMIT REGISTERS AIN3 AIN4 AIN5 AIN6 AIN7 MASK DATA FROM SMBus (SAME BIT NAMES AND ORDER AS STATUS BITS) MASK GATING × 8 STATUS REGISTER 1 0 1 2 3 4 5 6 7 STATUS BIT MASK BIT MASK REGISTER 1 0 1 2 3 4 5 6 7 MASK GATING × 8 STATUS REGISTER 2 EXT1 TEMP EXT 2 TEMP 3.3V STBY 3.3V MAIN +5V VCCP +12V –12V STATUS BIT IN OUT LATCH MASK BIT RESET MASK REGISTER 2 INT TEMP THERM AFC RESERVED CI GPIO16 HIGH LIMIT 1 = OUT OF LIMIT MASK DATA FROM SMBus (SAME BIT NAMES AND ORDER AS STATUS BITS) MASK GATING × 8 STATUS BIT MASK BIT MASK REGISTER 4 0 1 2 3 4 5 6 7 CI GPIO16 MASK GATING × 8 STATUS BIT IN OUT MASK BIT RESET MASK REGISTER 3 INT ENABLE MASK GATING × 8 GPIO0 TO GPIO7 STATUS REGISTER 5 MASKING DATA FROM SMBus MASK REGISTER 5 GPIO8 TO GPIO15 STATUS REGISTER 6 MASKING DATA FROM SMBus MASK REGISTER 6 INT LATCH INT CLEAR STATUS BIT MASK BIT MASK GATING × 8 STATUS BIT MASK BIT Figure 53. Interrupt Structure Rev. A | Page 30 of 56 02657-A-050 FROM FAN SPEED VALUE AND LIMIT REGISTERS FAN0 FAN1 FAN2 FAN3 FAN4 FAN5 FAN6 FAN7 DATA DEMULTIPLEXER VALUE HIGH LIMIT COMPARATOR MASK DATA FROM SMBus (SAME BIT NAMES AND ORDER AS STATUS BITS) 0 1 2 3 4 5 6 7 STATUS REGISTER 4 AIN8 STATUS REGISTER 3 VBAT ADM1026 3.3VSTBY Note that the THERM pin is bidirectional, so THERM may be pulled low externally as an input. This causes the PWM and DAC outputs to go to full scale until THERM is returned high again. To disable THERM as an input, set Bit 0 of Configuration Register 3 (Reg. 07h). This configures Pin 42 as GPIO16 and prevents a low on Pin 42 from driving the fans at full speed. 3.3VMAIN ~1V ~1V RESETSTBY TEMPERATURE 180ms 02657-A-055 RESETMAIN THERM LIMIT 180ms POWER-ON RESET THERM LIMIT – 5°C Figure 55. Operation of Offset Outputs NAND TREE TESTS THERM Figure 54. Assertion of INT Due to THERM Event Reset Input and Outputs The ADM1026 has two active low, power-on reset outputs, RESETMAIN and RESETSTBY. These operate as follows. A NAND tree is provided in the ADM1026 for automated test equipment (ATE) board-level connectivity testing. This allows the functionality of all digital inputs to be tested in a simple manner and any pins that are nonfunctional or shorted together to be identified. The structure of the NAND tree is shown in Figure 56. The device is placed into NAND tree test mode by powering up with Pin 25 held high. This pin is sampled automatically after power-up, and if it is connected high, then the NAND test mode is invoked. GPIO8 RESETSTBY monitors 3.3 V STBY. At power-up, RESETSTBY is asserted (pulled low) until 180 ms after 3.3 V STBY rises above the reset threshold. FAN0 FAN1 RESETMAIN monitors 3.3 V MAIN. This means that at powerup, RESETMAIN is asserted (pulled low) until 180 ms after 3.3 V MAIN rises above the reset threshold. FAN2 INT CI If 3.3 V MAIN rises with or before DVCC, RESETMAIN remains asserted until 180 ms after RESETSTBY is negated. RESETMAIN can also function as a RESET input. Pulling this pin low resets the registers, which are initialized to their default values by a software reset. (See the Software Reset Function section for register details). Note that the 3.3 V STBY pin supplies power to the ADM1026. In applications that do not require monitoring of a 3.3 V STBY and 3.3 V MAIN supply, these two pins should be connected together (3.3 V MAIN should not be left floating). FAN4 SDA SCL FAN7 FAN5 FAN6 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 NTESTOUT Figure 56. NAND Tree The NAND tree test may be carried out in one of two ways. 1. Start with all inputs low and take them high in turn, starting with the input nearest to NTEST_OUT (GPIO16/THERM) and working back up the tree to the input furthest from NTESTOUT (INT). This should give the characteristic output pattern shown in Figure 57, with NTESTOUT toggling each time an input is taken high. 2. Start with all inputs high and take them low in turn, starting with the input furthest from NTEST_OUT (INT) and working down the tree to the input nearest to NTEST_OUT (GPIO16/ THERM). This should give a similar output pattern to Figure 58. To ensure that the 3.3 V STBY pin does not become backdriven, the 3.3 V STBY supply should power on before all other voltages in the system. See Table 3 for more information about pin configuration. FAN3 GPIO9 02657-A-056 INT CLEARED BY STATUS REG 1 READ, BIT 2 OF CONFIG. REG. 1 SET, OR ARA 02657-A-054 INT Rev. A | Page 31 of 56 ADM1026 Notes • • • INT CI For a NAND tree test to work, all outputs (INT, RSTMAIN, RSTSTBY, and PWM) must remain high during the test. SDA SCL When generating test waveforms, allow for a typical propagation delay of 500 ns through the NAND tree. FAN7 FAN6 If any of the inputs shown in Figure 56 are unused, they should not be connected direct to ground, but via a resistor such as 10 kΩ. This allows the automatic test equipment (ATE) to drive every input high so that the NAND tree test can be properly carried out. FAN5 FAN4 FAN3 FAN2 FAN1 GPIO16 FAN0 GPIO15 GPIO8 GPIO14 GPIO9 GPIO13 GPIO10 GPIO12 GPIO11 GPIO11 GPIO12 GPIO10 GPIO13 GPIO9 GPIO14 GPIO8 GPIO15 02657-A-058 FAN0 GPIO16 FAN1 NTESTOUT FAN2 Figure 58. NAND Tree Test Taking Inputs Low in Turn FAN3 FAN4 GPIO16 FAN5 GPIO15 FAN6 GPIO14 FAN7 GPIO13 SCL GPIO12 SDA GPIO11 CI GPIO10 INT GPIO9 GPIO8 02657-A-057 Figure 57. NAND Tree Test Taking Inputs High in Turn FAN0 02657-A-059 NTESTOUT FAN1 NTESTOUT In the event of an input being nonfunctional (stuck high or low) or two inputs shorted together, the output pattern is different. Some examples are given in Figure 59 through Figure 61. Figure 59 shows the effect of one input being stuck low. The output pattern is normal until the stuck input is reached. Because that input is permanently low, neither it nor any inputs further up the tree can have any effect on the output. Rev. A | Page 32 of 56 Figure 59. NAND Tree Test with GPIO11 Stuck Low ADM1026 Figure 60 shows the effect of one input being stuck high. Taking GPIO12 high should take the output high. However, the next input up the tree, GPIO11, is already high, so the output immediately goes low again, causing a missing pulse in the output pattern. GPIO16 GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8 02657-A-060 FAN0 FAN1 NTESTOUT Figure 60. NAND Tree Test with One Input Stuck High A similar effect occurs if two adjacent inputs are shorted together. The example in Figure 61 assumes that the current sink capability of the circuit driving the inputs is considerably higher than the source capability, so the inputs are low if either is low, but high only if both are high. When GPIO12 goes high the output should go high. But because GPIO12 and GPIO11 are shorted, they both go high together, causing a missing pulse in the output pattern. The ADM1026 can also be initialized at any time by writing a 1 to Bit 7 of Configuration Register 1, which sets some registers to their default power-on conditions. This bit should be cleared by writing a 0 to it. After power-on, the ADM1026 must be configured to the user’s specific requirements. This consists of • Writing values to the limit registers. • Configuring Pins 3 to 6, and 9 to 12 as fan inputs or GPIO, using Configuration Register 2 (Address 01h). • Setting the fan divisors using the fan divisor registers (Addresses 02h and 03h). • Configuring the GPIO pins for input/output polarity, using GPIO Configuration Registers 1 to 4 (Addresses 08h to 0Bh) and Bits 6 and 7 of Configuration Register 3. • Setting mask bits in Mask Registers 1 to 6 (Addresses 18h to 1Dh) for any inputs that are to be masked out. • Setting up Configuration Registers 1 and 3, as described in Table 9 and Table 10. Table 9. Configuration Register 1 Bit 0 1 GPIO16 GPIO15 2 GPIO14 GPIO13 3 GPIO12 GPIO11 4 5 GPIO10 GPIO9 GPIO8 6 02657-A-061 FAN0 FAN1 NTESTOUT 7 Description Controls the monitoring loop of the ADM1026. Setting Bit 0 low stops the monitoring loop and puts the ADM1026 into low power mode and reduces power consumption. Serial bus communication is still possible with any register in the ADM1026 while in low power mode. Setting bit 0 high starts the monitoring loop. Enables or disables the INT interrupt output. Setting Bit 1 high enables the INT output, setting Bit 1 low disables the output. Used to clear the INT interrupt output when set high. GPIO pins and interrupt status register contents are not affected. Configures Pins 27 and 28 as the second external temperature channel when 0, and as AIN8 and AIN9 when set to 1. Enables the THERM output when set to 1. Enables automatic fan speed control on the DAC output when set to 1. Enables automatic fan speed control on the PWM output when set to 1. Performs a soft reset when set to 1. Table 10. Configuration Register 3 Figure 61. NAND Tree Test with Two Inputs Shorted Bit 0 USING THE ADM1026 When power is first applied, the ADM1026 performs a poweron reset on all its registers (not EEPROM), which sets them to default conditions as shown in Table 12. In particular, note that all GPIO pins are configured as inputs to avoid possible conflicts with circuits trying to drive these pins. 1 2 3–5 6, 7 Rev. A | Page 33 of 56 Description Configures Pin 42 as GPIO when set to 1 or as THERM when cleared to 0. Clears the CI latch when set to 1. Thereafter, a 0 must be written to allow subsequent CI detection. Selects VREF as 2.5 V when set to 1 or as 1.82 V when cleared to 0. Unused. Set up GPIO16 for direction and polarity. ADM1026 Starting Conversion The monitoring function (analog inputs, temperature, and fan speeds) in the ADM1026 is started by writing to Configuration Register 1 and setting Start (Bit 0) high. The INT _Enable (Bit 1) should be set to 1, and INT Clear (Bit 2) set to 0 to enable interrupts. The THERM enable bit (Bit 4) should be set to 1 to enable temperature interrupts at the THERM pin. Apart from initially starting together, the analog measurements and fan speed measurements proceed independently, and are not synchronized in any way. Reduced Power Mode The ADM1026 can be placed in a low power mode by setting Bit 0 of the configuration register to 0. This disables the internal ADC. Note that the limit registers (0Dh to 12h, 40h to 6Dh) are not reset by the software reset function. This can be useful if one needs to reset the part but does not want to reprogram all parameters again. Note that a power-on reset initializes all registers on the ADM1026, including the limit registers. Application Schematic Figure 62 shows how the ADM1026 could be used in an application that requires system management of a PC or server. Several GPIOs are used to read the VID codes of the CPU. Up to two CPU temperature measurements can be read back. All power supply voltages are monitored in the system. Up to eight fan speeds can be measured, irrespective of whether they are controlled by the ADM1026 or hardwired to a system supply. The VREF output includes the recommended filtering circuitry. Software Reset Function As previously mentioned, the ADM1026 can be reset in software by setting Bit 7 of Configuration Register 1 (Reg. 00h) to 1. Configuration Register 1, 00h, should then be manually cleared. Note that the software reset differs from a power-on reset in that only some of the ADM1026 registers are reinitialized to their power-on default values. The registers that are initialized to their default values by the software reset are • • • • Configuration Registers (Registers 01h to 0Bh) Mask Registers 1 to 6, internal temperature offset, and Status Registers 4, 5, and 6 (Registers 18h to 25h) All value registers (Registers 1Fh, 20h to 3Fh) External 1 and External 2 Offset Registers (6Eh, 6Fh) Rev. A | Page 34 of 56 Figure 62. ADM1026 Schematic Rev. A | Page 35 of 56 02657-A-062 FAN 3 Q1 SDATA SCLOCK R2 2kΩ 46 GPIO12 2 R1 2kΩ DAC 23 3.3V STBY 22 AGND 21 1 D1– 25 D1+ 26 D2–/A IN9 27 D2+/A IN8 28 +VBAT 29 –12V IN 31 +5 VIN 30 AIN7 34 +VCCP 33 +12 VIN 32 AIN5 36 AIN6 35 R3 470kΩ R6 10kΩ CPU1_THERMDC CPU1_THERMDA CPU2_THERMDC CPU2_THERMDA +5 VIN –12 VIN CPU1_VCCP +12 VIN CPU2_VCCP SYS_THERM 4 X5 3.3V STDY 12 FAN7/GPIO7 11 FAN6/GPIO6 10 FAN5/GPIO5 9 FAN4/GPIO4 45 GPIO13 +12V 3 3 FAN 2 1 2 X4 38 A IN3 39 A IN2 1 8 DGND 44 GPIO14 U1 ADM1026_SKT 42 THERM 43 GPIO15 7 3.3VMAIN 6 FAN3/GPIO3 5 FAN2/GPIO2 4 FAN1/GPIO1 3 FAN0/GPIO0 48 GPIO10 +12V 3 3 1 GPIO9 2 GPIO8 47 GPIO11 +12V 2 FAN +12V 1 2 X2 40 A IN1 41 A IN0 FAN FAN +12V 1 37 A IN4 X3 X1 CPU1_VID4 CPU1_VID3 CPU1_VID2 CPU1_VID1 CPU1_VID0 R5 10kΩ C1 0.1µF R4 10kΩ VCC + B1 POWER_GOOD SMB_ALERT CPURESET 0–2.5V_OUT VREF_OUT ADM1026 S1 1 VREF 24 RESETMAIN 20 3.3V_STBY RESETSTBY 19 PWM 18 INT 17 ADD 15 CI 16 SDA 14 SCL 13 ADM1026 REGISTERS Table 11. Address Pointer Register Bit 7–0 Name Address Pointer R/W Write Description Address of ADM1026 registers. See the following tables for details. Table 12. List of Registers Hex Address 00 01 02 03 04 Name Configuration 1 Configuration 2 Fan 0–3 Divisor Fan 4–7 Divisor DAC Control Power-On Value 00h 00h 55h 55h FFh 05 PWM Control FFh 06 07 08 09 0A EEPROM Register Configuration Register GPIO Config 1 GPIO Config 2 GPIO Config 3 100h 300h 00h 00h 00h 0B GPIO Config 4 00h 0C 0D EEPROM Register 2 Int Temp THERM Limit 00h 37h (55°C) 0E TDM1 THERM Limit 50h (80°C) 0F TDM2 THERM Limit 50h (80°C) 10 Int Temp TMIN 28h (40°C) 11 TDM1 TMIN 40h (64°C) 12 TDM2 TMIN 40h (64°C) 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 EEPROM Register 3 Test Register 1 Test Register 2 Manufacturer’s ID Revision Mask Register 1 Mask Register 2 Mask Register 3 Mask Register 4 Mask Register 5 Mask Register 6 Int Temp Offset Int Temp Value Status Register 1 Status Register 2 Status Register 3 Status Register 4 00h 00h 00h 41h 4xh 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h Description Configures various operating parameters Configures Pins 3–6 and 9–12 as fan inputs or GPIO Sets oscillator frequency for Fan 0–3 speed measurement Sets oscillator frequency for Fan 4–7 speed measurement Contains value for fan speed DAC (analog fan speed control) or minimum value for automatic fan speed control Contains value for PWM fan speed control or minimum value for automatic fan speed control For factory use only Configuration register for THERM, VREF and GPIO16 Configures GPIO0 to GPIO3 as input or output and as active high or active low Configures GPIO4 to GPIO7 as input or output and as active high or active low Configures GPIO8 to GPIO11 as input or output and as active high or active low Configures GPIO12 to GPIO15 as input or output and as active high or active low For factory use only High limit for THERM interrupt output based on internal temperature measurement High limit for THERM interrupt output based on Remote Channel 1 (D1) temperature measurement High limit for THERM interrupt output based on Remote Channel 2 (D2) temperature measurement TMIN value for automatic fan speed control based on internal temperature measurement TMIN value for automatic fan speed control based on Remote Channel 1 (D1) temperature measurement TMIN value for automatic fan speed control based on Remote Channel 2 (D2) temperature measurement Configures EEPROM for read/write/erase, etc. Manufacturer’s test register For manufacturer’s use only Contains manufacturer’s ID code Contains code for major and minor revisions Interrupt mask register for temperature and supply voltage faults Interrupt mask register for analog input faults Interrupt mask register for fan faults Interrupt mask register for local temp, VBAT, AIN8, THERM, AFC, CI and GPIO16 Interrupt mask register for GPIO0 to GPIO7 Interrupt mask register for GPIO8 to GPIO15 Offset register for internal temperature measurement Measured temperature from on–chip sensor Interrupt status register for external temp and supply voltage faults Interrupt status register for analog input faults Interrupt status register for fan faults Interrupt status register for local temp, VBAT, AIN8, THERM, AFC, CI, and GPIO16 Rev. A | Page 36 of 56 ADM1026 Hex Address 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 Name Status Register 5 Status Register 6 VBAT Value AIN8 Value TDM1 Value TDM2/AIN9 Value 3.3 V STBY Value 3.3 V MAIN Value +5 V Value VCCP Value +12 V Value −12 V Value AIN0 Value AIN1 Value AIN2 Value AIN3 Value AIN4 Value AIN5 Value AIN6 Value AIN7 Value FAN0 Value FAN1 Value FAN2 Value FAN3 Value FAN4 Value FAN5 Value FAN6 Value FAN7 Value TDM1 High Limit TDM2/AIN9 High Limit 3.3 V STBY High Limit 3.3 V MAIN High Limit +5 V High Limit VCCP High Limit +12 V High Limit −12 V High Limit TDM1 Low Limit TDM2/AIN9 Low Limit 3.3 V STBY Low Limit 3.3 V MAIN Low Limit +5 V Low Limit VCCP Low Limit +12 V Low Limit −12 V Low Limit AIN0 High Limit AIN1 High Limit AIN2 High Limit AIN3 High Limit AIN4 High Limit AIN5 High Limit AIN6 High Limit AIN7 High Limit Power-On Value 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 64h (100°C) 64h (100°C) FFh FFh FFh FFh FFh FFh 80h 80h 00h 00h 00h 00h 00h 00h FFh FFh FFh FFh FFh FFh FFh FFh Description Interrupt status register for GPIO0 to GPIO7 Interrupt status register for GPIO8 to GPIO15 Measured value of VBAT Measured value of AIN8 Measured value of remote temperature channel 1 (D1) Measured value of remote temperature channel 2 (D2) or AIN9 Measured value of 3.3 V STBY Measured value of 3.3 V MAIN Measured value of +5 V supply Measured value of processor core voltage Measured value of +12 V supply Measured value of −12 V supply Measured value of AIN0 Measured value of AIN1 Measured value of AIN2 Measured value of AIN3 Measured value of AIN4 Measured value of AIN5 Measured value of AIN6 Measured value of AIN7 Measured speed of Fan 0 Measured speed of Fan 1 Measured speed of Fan 2 Measured speed of Fan 3 Measured speed of Fan 4 Measured speed of Fan 5 Measured speed of Fan 6 Measured speed of Fan 7 High limit for Remote Temperature Channel 1 (D1) measurement High limit for Remote Temperature Channel 2 (D2) or AIN9 measurement High limit for 3.3 V STBY measurement High limit for 3.3 V MAIN measurement High limit for +5 V supply measurement High limit for processor core voltage measurement High limit for +12 V supply measurement High limit for −12 V supply measurement Low limit for Remote Temperature Channel 1 (D1) measurement Low limit for Remote Temperature Channel 2 (D2) or AIN9 measurement Low limit for 3.3 V STBY measurement Low limit for 3.3 V MAIN measurement Low limit for +5 V supply Low limit for processor core voltage measurement Low limit for +12 V supply measurement Low limit for −12 V supply measurement High limit for AIN0 measurement High limit for AIN1 measurement High limit for AIN2 measurement High limit for AIN3 measurement High limit for AIN4 measurement High limit for AIN5 measurement High limit for AIN6 measurement High limit for AIN7 measurement Rev. A | Page 37 of 56 ADM1026 Hex Address 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F Name AIN0 Low Limit AIN1 Low Limit AIN2 Low Limit AIN3 Low Limit AIN4 Low Limit AIN5 Low Limit AIN6 Low Limit AIN7 Low Limit FAN0 High Limit FAN1 High Limit FAN2 High Limit FAN3 High Limit FAN4 High Limit FAN5 High Limit FAN6 High Limit FAN7 High Limit Int. Temp. High Limit Int. Temp. Low Limit VBAT High Limit VBAT Low Limit AIN8 High Limit AIN8 Low Limit Ext1 Temp Offset Ext2 Temp Offset Power-On Value 00h 00h 00h 00h 00h 00h 00h 00h FFh FFh FFh FFh FFh FFh FFh FFh 50h (80°C) 80h FFh 00h FFh 00h 00h 00h Description Low limit for AIN0 measurement Low limit for AIN1 measurement Low limit for AIN2 measurement Low limit for AIN3 measurement Low limit for AIN4 measurement Low limit for AIN5 measurement Low limit for AIN6 measurement Low limit for AIN7 measurement High limit for Fan 0 speed measurement (no low limit) High limit for Fan 1 speed measurement (no low limit) High limit for Fan 2 speed measurement (no low limit) High limit for Fan 3 speed measurement (no low limit) High limit for Fan 4 speed measurement (no low limit) High limit for Fan 5 speed measurement (no low limit) High limit for Fan 6 speed measurement (no low limit) High limit for Fan 7 speed measurement (no low limit) High limit for local temperature measurement Low limit for local temperature measurement High limit for VBAT measurement Low limit for VBAT measurement High limit for AIN8 measurement Low limit for AIN8 measurement Offset register for Remote Temperature Channel 1 Offset register for Remote Temperature Channel 2 DETAILED REGISTER DESCRIPTIONS Table 13. Register 00h, Configuration Register 1 (Power-On Default 00h) Bit Name R/W Description 0 Monitor = 0 R/W 1 2 Int Enable = 0 Int Clear = 0 R/W R/W 3 Enable Voltage/Ext2 = 0 R/W 4 Enable THERM = 0 R/W 5 Enable DAC AFC = 0 R/W 6 Enable PWM AFC = 0 R/W 7 Software Reset = 0 R/W When this bit is set the ADM1026 monitors all voltage, temperature and fan channels in a round robin manner. When this bit is set, the INT output pin is enabled. Setting this bit clears an interrupt from the voltage, temperature or fan speed channels. Because GPIO interrupts are level triggered, this bit has no effect on interrupts originating from GPIO channels. This bit is cleared by writing a 0 to it. If in monitoring mode voltages, temperatures and fan speeds continue to be monitored after writing to this bit to clear an interrupt, so an interrupt may be set again on the next monitoring cycle. When this bit is 1, the ADM1026 monitors voltage (AIN8 and AIN9) on Pins 28 and 27, respectively. When this bit is 0, the ADM1026 monitors a second thermal diode temperature channel, D2, on these pins. If the second thermal diode channel is not being used, it is recommended that the bit be set to 1. When this bit is 1, the THERM pin (Pin 42) is asserted (go low) if any of the THERM limits are exceeded. If THERM is pulled low as an input, the DAC and PWM outputs are forced to full scale until THERM is taken high. When this bit is 1, the DAC output is enabled for automatic fan speed control (AFC) based on temperature. When this bit is 0, the DAC Output reflects the value in Reg 04h, the DAC Control Register. When this bit is 1, the PWM output is enabled for automatic fan speed control (AFC) based on temperature. When this bit is 0, the PWM Output reflects the value in Reg 05h, the PWM Control Register. Writing a 1 to this bit restores all registers to the power-on defaults. This bit is cleared by writing a 0 to it. For more info, see the Software Reset Function section. Rev. A | Page 38 of 56 ADM1026 Table 14. Register 01h, Configuration Register 2 (Power-On Default 00h) Bit Name R/W Description 0 Enable GPIO0/Fan0 = 0 R/W 1 Enable GPIO1/Fan1 = 0 R/W 2 Enable GPIO2/Fan2 = 0 R/W 3 Enable GPIO3/Fan3 = 0 R/W 4 Enable GPIO4/Fan4 = 0 R/W 5 Enable GPIO5/Fan5 = 0 R/W 6 Enable GPIO6/Fan6 = 0 R/W 7 Enable GPIO7/Fan7 = 0 R/W When this bit is 1, Pin 3 is enabled as a general-purpose I/O pin (GPIO0), otherwise it is a fan tach measurement input (Fan 0). When this bit is 1, Pin 4 is enabled as a general-purpose I/O pin (GPIO1), otherwise it is a fan tach measurement input (Fan 1). When this bit is 1, Pin 5 is enabled as a general-purpose I/O pin (GPIO2), otherwise it is a fan tach measurement input (Fan 2). When this bit is 1, Pin 6 is enabled as a general-purpose I/O pin (GPIO3), otherwise it is a fan tach measurement input (Fan 3). When this bit is 1, Pin 9 is enabled as a general-purpose I/O pin (GPIO4), otherwise it is a fan tach measurement input (Fan 4). When this bit is 1, Pin 10 is enabled as a general-purpose I/O pin (GPIO5), otherwise it is a fan tach measurement input (Fan 5). When this bit is 1, Pin 11 is enabled as a general-purpose I/O pin (GPIO6), otherwise it is a fan tach measurement input (Fan 6). When this bit is 1, Pin 12 is enabled as a general-purpose I/O pin (GPIO7), otherwise it is a fan tach measurement input (Fan 7). Table 15. Register 02h, Fans 0 to 3 Fan Divisor Register (Power-On Default 55h) Bit Name R/W Description 1–0 Fan 0 Divisor R/W 3–2 5–4 7–6 Fan 1 Divisor Fan 2 Divisor Fan 3 Divisor R/W R/W R/W Sets the oscillator prescaler division ratio for Fan 0 speed measurement. The division ratios, oscillator frequencies, and typical fan speeds (based on 2 tach pulses per revolution) are as follows: Oscillator Code Divide By Frequency (kHz) Fan Speed (RPM) 00 1 22.5 8800, nominal, for count of 153 01 2 11.25 4400, nominal, for count of 153 10 4 5.62 2200, nominal, for count of 153 11 8 2.81 1100, nominal, for count of 153 Same as Fan 0 Same as Fan 0 Same as Fan 0 Table 16. Register 03h, Fans 4 to 7 Fan Divisor Register (Power-On Default 55h) Bit Name R/W Description 1–0 Fan 4 Divisor R/W 3-2 5-4 7-6 Fan 5 Divisor Fan 6 Divisor Fan 7 Divisor R/W R/W R/W Sets the oscillator prescaler division ratio for Fan 4 speed measurement. The division ratios, oscillator frequencies, and typical fan speeds (based on 2 tach pulses per revolution) are as follows: Oscillator Code Divide By Frequency (kHz) Fan Speed (RPM) 00 1 22.5 8800, nominal, for count of 153 01 2 11.25 4400, nominal, for count of 153 10 4 5.62 2200, nominal, for count of 153 11 8 2.81 1100, nominal, for count of 153 Same as Fan 4 Same as Fan 4 Same as Fan 4 Table 17. Register 04h, DAC Control Register (Power-On Default FFh) Bit Name R/W Description 7–0 DAC Control R/W This register contains the value to which the fan speed DAC is programmed in normal mode, or the 4 MSBs contain the minimum fan speed in auto fan speed control mode. Rev. A | Page 39 of 56 ADM1026 Table 18. Register 05h, PWM Control Register (Power-On Default FFh) Bit Name R/W Description 7–4 PWM Control R/W 3–0 Unused R This register contains the value to which the PWM fan speed is programmed in normal mode, or the 4 MSBs contain the minimum fan speed in auto fan speed control mode. 0000 = 0% Duty Cycle 0001 = 7% Duty Cycle 0101 = 33% Duty Cycle 0110 = 40% Duty Cycle 0111 = 47% Duty Cycle 1110 = 93% Duty Cycle 1111 = 100% Duty Cycle Undefined Table 19. Register 06h, EEPROM Register 1 (Power-On Default 00h) Bit Name R/W Description 7–0 Factory Use R/W For factory use only. Do not write to this register. Table 20. Register 07h, Configuration Register 3 (Power-On Default 00h) Bit Name R/W Description 0 Enable GPIO16/ THERM = 0 R/W When this bit is 1, Pin 42 is enabled as a general-purpose I/O pin (GPIO16); otherwise it is the THERM output. 1 2 5–3 6 7 CI Clear = 0 VREF Select = 0 Unused GPIO16 Direction GPIO16 Polarity R/W R/W R R/W R/W Writing a 1 to this bit clears the CI latch. This bit is cleared by writing a 0 to it. When this bit is 0, VREF (Pin 24) outputs 1.82 V, otherwise, it outputs 2.5 V. Undefined, reads back 0. When this bit is 0, GPIO16 is configured as an input; otherwise, it is an output. When this bit is 0, GPIO16 is active low; otherwise, it is active high. Table 21. Register 08h, GPIO Configuration Register 1 (Power-On Default 00h) Bit Name R/W Description 0 1 2 3 4 5 6 7 GPIO0 Direction GPIO0 Polarity GPIO1 Direction GPIO1 Polarity GPIO2 Direction GPIO2 Polarity GPIO3 Direction GPIO3 Polarity R/W R/W R/W R/W R/W R/W R/W R/W When this bit is 0, GPIO0 is configured as an input; otherwise, it is an output. When this bit is 0, GPIO0 is active low; otherwise it is active high. When this bit is 0, GPIO1 is configured as an input; otherwise, it is an output. When this bit is 0, GPIO1 is active low; otherwise it is active high. When this bit is 0, GPIO2 is configured as an input; otherwise, it is an output. When this bit is 0, GPIO2 is active low; otherwise, it is active high. When this bit is 0, GPIO3 is configured as an input; otherwise, it is an output. When this bit is 0, GPIO3 is active low; otherwise, it is active high. Table 22. Register 09h, GPIO Configuration Register 2 (Power-On Default 00h) Bit Name R/W Description 0 1 2 3 4 5 6 7 GPIO4 Direction GPIO4 Polarity GPIO5 Direction GPIO5 Polarity GPIO6 Direction GPIO6 Polarity GPIO7 Direction GPIO7 Polarity R/W R/W R/W R/W R/W R/W R/W R/W When this bit is 0, GPIO4 is configured as an input; otherwise, it is an output. When this bit is 0, GPIO4 is active low; otherwise, it is active high. When this bit is 0, GPIO5 is configured as an input; otherwise, it is an output. When this bit is 0, GPIO5 is active low; otherwise, it is active high. When this bit is 0, GPIO6 is configured as an input; otherwise, it is an output. When this bit is 0, GPIO6 is active low; otherwise, it is active high. When this bit is 0, GPIO7 is configured as an input; otherwise, it is an output. When this bit is 0, GPIO7 is active low; otherwise, it is active high. Rev. A | Page 40 of 56 ADM1026 Table 23. Register 0Ah, GPIO Configuration Register 3 (Power-On Default 00h) Bit Name R/W Description 0 1 2 3 4 5 6 7 GPIO8 Direction GPIO8 Polarity GPIO9 Direction GPIO9 Polarity GPIO10 Direction GPIO10 Polarity GPIO11 Direction GPIO11 Polarity R/W R/W R/W R/W R/W R/W R/W R/W When this bit is 0, GPIO8 is configured as an input; otherwise, it is an output. When this bit is 0, GPIO8 is active low; otherwise, it is active high. When this bit is 0, GPIO9 is configured as an input; otherwise, it is an output. When this bit is 0, GPIO9 is active low; otherwise, it is active high. When this bit is 0, GPIO10 is configured as an input; otherwise, it is an output. When this bit is 0, GPIO10 is active low; otherwise, it is active high. When this bit is 0, GPIO11 is configured as an input; otherwise, it is an output. When this bit is 0, GPIO11 is active low; otherwise, it is active high. Table 24. Register 0Bh, GPIO Configuration Register 4 (Power-On Default 00h) Bit Name R/W Description 0 1 2 3 4 5 6 7 GPIO12 Direction GPIO12 Polarity GPIO13 Direction GPIO13 Polarity GPIO14 Direction GPIO14 Polarity GPIO15 Direction GPIO15 Polarity R/W R/W R/W R/W R/W R/W R/W R/W When this bit is 0, GPIO12 is configured as an input; otherwise, it is an output. When this bit is 0, GPIO12 is active low; otherwise, it is active high. When this bit is 0, GPIO13 is configured as an input; otherwise, it is an output. When this bit is 0, GPIO13 is active low; otherwise, it is active high. When this bit is 0, GPIO14 is configured as an input; otherwise, it is an output. When this bit is 0, GPIO14 is active low; otherwise, it is active high. When this bit is 0, GPIO15 is configured as an input; otherwise, it is an output. When this bit is 0, GPIO15 is active low; otherwise, it is active high. Table 25. Register 0ch, EEPROM Register 2 (Power-On Default 00h) Bit Name R/W Description 7–0 Factory Use R For factory use only. Do not write to this register. Table 26. Register 0Dh, Internal Temperature THERM Limit (Power-On Default, 37h 55°C) Bit Name R/W Description 7–0 Int Temp THERM Limit R/W This register contains the THERM limit for the internal temperature channel. Exceeding this limit causes the THERM output pin to be asserted. Table 27. Register 0Eh, TDM1 THERM Limit (Power-On Default 50h, 80°C) Bit Name R/W Description 7–0 TDM1 THERM Limit R/W This register contains the THERM limit for the TDM1 temperature channel. Exceeding this limit causes the THERM output pin to be asserted. Table 28. Register 0Fh, TDM2 THERM Limit (Power-On Default 50h, 80°C) Bit Name R/W Description 7–0 TDM2 THERM Limit R/W This register contains the THERM limit for the TDM2 temperature channel. Exceeding this limit causes the THERM output pin to be asserted. Table 29. Register 10h, Internal Temperature TMIN (Power-On Default 28h, 40°C) Bit Name R/W Description 7–0 Internal Temp TMIN R/W This register contains the TMIN value for automatic fan speed control based on the internal temperature channel. Table 30. Register 11h, TDM1 Temperature TMIN (Power-On Default 40h, 64°C) Bit Name R/W Description 7–0 TDM1 Temp TMIN R/W This register contains the TMIN value for automatic fan speed control based on the TDM1 temperature channel. Rev. A | Page 41 of 56 ADM1026 Table 31. Register 12h, TDM2 Temperature TMIN (Power-On Default 40h, 64°C) Bit Name R/W Description 7–0 TDM2 Temp TMIN R/W This register contains the TMIN value for automatic fan speed control based on the TDM2 temperature channel. Table 32. Register 13h, EEPROM Register 3 (Power-On Default 00h) Bit 0 1 2 3 Name Read Write Erase Write Protect 4 5 6 Test Mode Bit 0 Test Mode Bit 1 Test Mode Bit 2 Clock Extend R/W Description Setting this bit puts the EEPROM into read mode. Setting this bit puts the EEPROM in write (program) mode. Setting this bit puts the EEPROM into erase mode. R/W R/W R/W R/W Once R/W R/W R/W R/W Setting this bit protects the EEPROM against accidental writing or erasure. This bit is write-once and can only be cleared by a power-on reset. Test mode bits. For factory use only Test mode bits. For factory use only. Test mode bits. For factory use only Setting this bit enables SMBus clock extension. The ADM1026 can pull SCL low to extend the clock pulse if it cannot accept any more data. It is recommended to set this bit to 1 to extend the clock pulse during repeated EEPROM write or block write operations. 7 Table 33. Register 14h, Manufacturer’s Test Register 1 (Power-On Default 00h) Bit Name R/W Description 7–0 Manufacturer’s Test 1 R/W This register is used by the manufacturer for test purposes. It should not be read from or written to in normal operation. Table 34. Register 15h, Manufacturer’s Test Register 2 (Power-On Default 00h) Bit Name R/W Description 7–0 Manufacturer’s Test 2 R/W This register is used by the manufacturer for test purposes. It should not be read from or written to in normal operation. Table 35. Register 16h, Manufacturer’s ID (Power-On Default 41h) Bit Name R/W Description 7–0 Manufacturer’s ID Code R This register contains the manufacturer’s ID code. Table 36. Register 17h, Revision Register (Power-On Default 4xh) Bit Name R/W Description 3–0 Minor Revision Code R 7–4 Major Revision Code R This nibble contains the manufacturer’s code for minor revisions to the device. Rev 1 = 0h, Rev 2 = 1h, and so on. This nibble denotes the generation of the device. For the ADM1026, this nibble reads 4h. Table 37. Register 18h, Mask Register 1 (Power-On Default 00h) Bit Name R/W Description 0 1 2 3 4 5 6 7 Ext1 Temp Mask = 0 Ext2 Temp 3.3 V STBY Mask = 0 3.3 V MAIN Mask = 0 +5 V Mask = 0 VCCP Mask = 0 +12 V Mask = 0 −12 V Mask = 0 R/W R/W R/W R/W R/W R/W R/W R/W When this bit is set, interrupts generated on the Ext1 temperature channel are masked out. When this bit is set, interrupts generated on the Ext2/AIN9 channel are masked out. When this bit is set, interrupts generated on the 3.3 V STBY voltage channel are masked out. When this bit is set, interrupts generated on the 3.3 V MAIN voltage channel are masked out. When this bit is set, interrupts generated on the +5 V voltage channel are masked out. When this bit is set, interrupts generated on the VCCP voltage channel are masked out. When this bit is set, interrupts generated on the +12 V voltage channel are masked out. When this bit is set, interrupts generated on the −12 V voltage channel are masked out. Rev. A | Page 42 of 56 ADM1026 Table 38. Register 19h, Mask Register 2 (Power-On Default 00h) Bit Name R/W Description 0 1 2 3 4 5 6 7 AIN0 Mask = 0 AIN1 Mask = 0 AIN2 Mask = 0 AIN3 Mask = 0 AIN4 Mask = 0 AIN5 Mask = 0 AIN6 Mask = 0 AIN7 Mask = 0 R/W R/W R/W R/W R/W R/W R/W R/W When this bit is set, interrupts generated on the AIN0 voltage channel are masked out. When this bit is set, interrupts generated on the AIN1 voltage channel are masked out. When this bit is set, interrupts generated on the AIN2 voltage channel are masked out. When this bit is set, interrupts generated on the AIN3 voltage channel are masked out. When this bit is set, interrupts generated on the AIN4 voltage channel are masked out. When this bit is set, interrupts generated on the AIN5 voltage channel are masked out. When this bit is set, interrupts generated on the AIN6 voltage channel are masked out. When this bit is set, interrupts generated on the AIN7 voltage channel are masked out. Table 39. Register 1Ah, Mask Register 3 (Power-On Default 00h) Bit Name R/W Description 0 1 2 3 4 5 6 7 FAN0 Mask = 0 FAN1 Mask = 0 FAN2 Mask = 0 FAN3 Mask = 0 FAN4 Mask = 0 FAN5 Mask = 0 FAN6 Mask = 0 FAN7 Mask = 0 R/W R/W R/W R/W R/W R/W R/W R/W When this bit is set, interrupts generated on the FAN0 tach channel are masked out. When this bit is set, interrupts generated on the FAN1 tach channel are masked out. When this bit is set, interrupts generated on the FAN2 tach channel are masked out. When this bit is set, interrupts generated on the FAN3 tach channel are masked out. When this bit is set, interrupts generated on the FAN4 tach channel are masked out. When this bit is set, interrupts generated on the FAN5 tach channel are masked out. When this bit is set, interrupts generated on the FAN6 tach channel are masked out. When this bit is set, interrupts generated on the FAN7 tach channel are masked out. Table 40. Register 1Bh, Mask Register 4 (Power-On Default 00h) Bit Name R/W Description 0 1 2 3 4 5 6 7 Int Temp Mask = 0 VBAT Mask = 0 AIN8 Mask = 0 THERM Mask = 0 AFC Mask = 0 Unused CI Mask = 0 GPIO16 Mask = 0 R/W R/W R/W R/W R/W R/W R/W R/W When this bit is set, interrupts generated on the internal temperature channel are masked out. When this bit is set, interrupts generated on the VBAT voltage channel are masked out. When this bit is set, interrupts generated on the AIN8 voltage channel are masked out. When this bit is set, interrupts generated from THERM events are masked out. When this bit is set, interrupts generated from automatic fan control events are masked out. Unused. Reads back 0. When this bit is set, interrupts generated by the chassis intrusion input are masked out. When this bit is set, interrupts generated on the GPIO16 channel are masked out. Table 41. Register 1Ch, Mask Register 5 (Power-On Default 00h) Bit Name R/W Description 0 1 2 3 4 5 6 7 GPIO0 Mask = 0 GPIO1 Mask = 0 GPIO2 Mask = 0 GPIO3 Mask = 0 GPIO4 Mask = 0 GPIO5 Mask = 0 GPIO6 Mask = 0 GPIO7 Mask = 0 R/W R/W R/W R/W R/W R/W R/W R/W When this bit is set, interrupts generated on the GPIO0 channel are masked out. When this bit is set, interrupts generated on the GPIO1 channel are masked out. When this bit is set, interrupts generated on the GPIO2 channel are masked out. When this bit is set, interrupts generated on the GPIO3 channel are masked out. When this bit is set, interrupts generated on the GPIO4 channel are masked out. When this bit is set, interrupts generated on the GPIO5 channel are masked out. When this bit is set, interrupts generated on the GPIO6 channel are masked out. When this bit is set, interrupts generated on the GPIO7 channel are masked out. Rev. A | Page 43 of 56 ADM1026 Table 42. Register 1Dh, Mask Register 6 (Power-On Default 00h) Bit Name R/W Description 0 1 2 3 4 5 6 7 GPIO8 Mask = 0 GPIO9 Mask = 0 GPIO10 Mask = 0 GPIO11Mask = 0 GPIO12 Mask = 0 GPIO13 Mask = 0 GPIO14 Mask = 0 GPIO15 Mask = 0 R/W R/W R/W R/W R/W R/W R/W R/W When this bit is set, interrupts generated on the GPIO8 channel are masked out. When this bit is set, interrupts generated on the GPIO9 channel are masked out. When this bit is set, interrupts generated on the GPIO10 channel are masked out. When this bit is set, interrupts generated on the GPIO11 channel are masked out. When this bit is set, interrupts generated on the GPIO12 channel are masked out. When this bit is set, interrupts generated on the GPIO13 channel are masked out. When this bit is set, interrupts generated on the GPIO14 channel are masked out. When this bit is set, interrupts generated on the GPIO15 channel are masked out. Table 43. Register 1Eh, INT Temp Offset (Power-On Default 00h) Bit Name R/W Description 7–0 Int Temp Offset R/W This register contains the offset value for the internal temperature channel, a twos complement result before it is stored or compared to limits. In this way, a sort of one-point calibration can be done whereby the whole transfer function of the channel can be moved up or down. From a software point of view, this may be a very simple method to vary the characteristics of the measurement channel if the thermal characteristics change for any reason (for instance from one chassis to another), if the measurement point is moved, if a plug-in card is inserted or removed, and so on. Table 44. Register 1Fh, INT Temp Measured Value (Power-On Default 00h) Bit Name R/W Description 7–0 Int Temp Value R This register contains the measured value of the internal temperature channel. Table 45. Register 20h, Status Register 1 (Power-On Default 00h) Bit Name R/W Description 0 Ext1 Temp Status = 0 R 1 Ext2 Temp Status = 0 R 2 3.3 V STBY Status = 0 R 3 3.3 V MAIN Status = 0 R 4 +5 V Status = 0 R 5 VCCP Status = 0 R 6 +12 V Status = 0 R 7 −12 V Status = 0 R 1, if Ext1 value is above the high limit or below the low limit on the previous conversion cycle; 0 otherwise. This bit is set (once only) if a THERM mode is engaged as a result of Ext1 temp readings exceeding the Ext1 THERM limit. This bit is also set (once only) if THERM mode is disengaged as a result of Ext1 temperature readings going 5°C below Ext1 THERM limit. 1, if Ext 2 value (or AIN9 if in voltage measurement mode) is above the /AIN9 status = 0 high limit or below the low limit on the previous conversion cycle; 0 otherwise. This bit is set (once only) if a THERM mode is engaged as a result of Ext2 temperature readings exceeding the Ext2 THERM limit. This bit is also set (once only) if THERM mode is disengaged as a result of Ext2 temperature readings going 5°C below Ext2 THERM limit. 1, if 3.3 V STBY value is above the high limit or below the low limit on the previous conversion cycle; 0 otherwise. 1, if 3.3 V MAIN value is above the high limit or below the low limit on the previous conversion cycle; 0 otherwise. 1, if +5 V value is above the high limit or below the low limit on the previous conversion cycle; 0 otherwise. 1, if VCCP value is above the high limit or below the low limit on the previous conversion cycle; 0 otherwise. 1, if +12 V value is above the high limit or below the low limit on the previous conversion cycle; 0 otherwise. 1, if −12 V value is above the high limit or below the low limit on the previous conversion cycle; 0 otherwise. Rev. A | Page 44 of 56 ADM1026 Table 46. Register 21h, Status Register 2 (Power-On Default 00h) Bit Name R/W 0 AIN0 Status = 0 R 1 AIN1 Status = 0 R 2 AIN2 Status = 0 R 3 AIN3 Status = 0 R 4 AIN4 Status = 0 R 5 AIN5 Status = 0 R 6 AIN6 Status = 0 R 7 AIN7 Status = 0 R Description 1, if AIN0 to AIN7 value is above the high limit or below the low limit on the previous conversion cycle;0 otherwise. 1, if AIN0 to AIN7 value is above the high limit or below the low limit on the previous conversion cycle;0 otherwise. 1, if AIN0 to AIN7 value is above the high limit or below the low limit on the previous conversion cycle;0 otherwise. 1, if AIN0 to AIN7 value is above the high limit or below the low limit on the previous conversion cycle;0 otherwise. 1, if AIN0 to AIN7 value is above the high limit or below the low limit on the previous conversion cycle;0 otherwise. 1, if AIN0 to AIN7 value is above the high limit or below the low limit on the previous conversion cycle;0 otherwise. 1, if AIN0 to AIN7 value is above the high limit or below the low limit on the previous conversion cycle;0 otherwise. 1, if AIN0 to AIN7 value is above the high limit or below the low limit on the previous conversion cycle;0 otherwise. Table 47. Register 22h, Status Register 3 (Power-On Default 00h) Bit 0 1 2 3 4 5 6 7 Name FAN0 Status 1 = 0 FAN1 Status 1 = 0 FAN2 Status 1 = 0 FAN3 Status 1 = 0 FAN4 Status 1 = 0 FAN5 Status 1 = 0 FAN6 Status 1 = 0 FAN7 Status 1 = 0 R/W R R R R R R R R Description 1, if FAN0 to FAN7 value is above the high limit on the previous conversion cycle; 0 otherwise. 1, if FAN0 to FAN7 value is above the high limit on the previous conversion cycle; 0 otherwise. 1, if FAN0 to FAN7 value is above the high limit on the previous conversion cycle; 0 otherwise. 1, if FAN0 to FAN7 value is above the high limit on the previous conversion cycle; 0 otherwise. 1, if FAN0 to FAN7 value is above the high limit on the previous conversion cycle; 0 otherwise. 1, if FAN0 to FAN7 value is above the high limit on the previous conversion cycle; 0 otherwise. 1, if FAN0 to FAN7 value is above the high limit on the previous conversion cycle; 0 otherwise. 1, if FAN0 to FAN7 value is above the high limit on the previous conversion cycle; 0 otherwise. Table 48. Register 23h, Status Register 4 (Power-On Default 00h) Bit Name R/W Description 0 Int Temp Status = 0 R 1 VBAT Status = 0 R 2 AIN8 Status = 0 R 3 THERM Status = 0 R 4 AFC Status = 0 R 5 6 7 Unused CI Status = 0 GPIO16 Status = 0 R R R 1, if Int value is above the high limit or below the low limit on the previous conversion cycle, 0 otherwise. This bit is set (once only) if a THERM mode is engaged as a result of int temperature readings exceeding the Int THERM limit. This bit is also set (once only) if THERM mode is disengaged as a result of internal temperature readings going 5°C below Int THERM limit. 1, if VBAT value is above the high limit or below the low limit on the previous conversion cycle, 0 otherwise. 1, if AIN8 value is above the high limit or below the low limit on the previous conversion cycle, 0 otherwise. This bit is set (once only) if a THERM mode is engaged as a result of temperature readings exceeding the THERM limits on any channel. This bit is also set (once only) if THERM mode is disengaged as a result of temperature readings going 5°C below THERM limits on any channel. This bit is set (once only) if the fan turns on when in automatic fan speed control (AFC) mode as a result of a temperature reading exceeding TMIN on any channel. This bit is also set (once only) if the fan turns off when in automatic fan speed control mode. Unused. Reads back 0. This bit latches a chassis intrusion event. When GPIO16 is configured as an input, this bit is set when GPIO16 is asserted. (Asserted may be active high or active low depending on the setting in GPIO configuration register.) When GPIO16 is configured as an output, setting this bit asserts GPIO16. (Asserted may be active high or active low depending on setting in GPIO configuration register.) R/W Rev. A | Page 45 of 56 ADM1026 Table 49. Register 24h, Status Register 5 (Power-On Default 00h) Bit Name R/W1 Description 0 GPIO0 Status = 0 R When GPIO0 is configured as an input, this bit is set when GPIO0 is asserted. (Asserted may be active high or active low depending on setting of Bit 1 in GPIO Configuration Register 1.) When GPIO0 is configured as an output, setting this bit asserts GPIO0. (Asserted may be active high or active low depending on setting of Bit 1 in GPIO Configuration Register 1.) When GPIO1 is configured as an input, this bit is set when GPIO1 is asserted. (Asserted may be active high or active low depending on setting of Bit 3 in GPIO Configuration Register 1.) When GPIO1 is configured as an output, setting this bit asserts GPIO1. (Asserted may be active high or active low depending on setting of Bit 3 in GPIO Configuration Register 1.) When GPIO2 is configured as an input, this bit is set when GPIO2 is asserted. (Asserted may be active high or active low depending on setting of Bit 5 in GPIO Configuration Register 1.) When GPIO2 is configured as an output, setting this bit asserts GPIO2. (Asserted may be active high or active low depending on setting of Bit 5 in GPIO Configuration Register 1.) When GPIO3 is configured as an input, this bit is set when GPIO3 is asserted. (Asserted may be active high or active low depending on setting of Bit 7 in GPIO Configuration Register 1.) When GPIO3 is configured as an output, setting this bit asserts GPIO3. (Asserted may be active high or active low depending on setting of Bit 7 in GPIO Configuration Register 1.) When GPIO4 is configured as an input, this bit is set when GPIO4 is asserted. (Asserted may be active high or active low depending on setting of Bit 1 in GPIO Configuration Register 2.) When GPIO4 is configured as an output, setting this bit asserts GPIO4. (Asserted may be active high or active low depending on setting of Bit 1 in GPIO Configuration Register 2.) When GPIO5 is configured as an input, this bit is set when GPIO5 is asserted. (Asserted may be active high or active low depending on setting of Bit 3 in GPIO Configuration Register 2.) When GPIO5 is configured as an output, setting this bit asserts GPIO5. (Asserted may be active high or active low depending on setting of Bit 3 in GPIO Configuration Register 2.) When GPIO6 is configured as an input, this bit is set when GPIO6 is asserted. (Asserted may be active high or active low depending on setting of Bit 5 in GPIO Configuration Register 2.) When GPIO6 is configured as an output, setting this bit asserts GPIO6. (Asserted may be active high or active low depending on setting of Bit 5 in GPIO Configuration Register 2.) When GPIO7 is configured as an input, this bit is set when GPIO7 is asserted. (Asserted may be active high or active low depending on setting of Bit 7 in GPIO Configuration Register 2.) When GPIO7 is configured as an output, setting this bit asserts GPIO7. (Asserted may be active high or active low depending on setting of Bit 7 in GPIO Configuration Register 2.) R/W 1 GPIO1 Status = 0 R R/W 2 GPIO2 Status = 0 R R/W 3 GPIO3 Status = 0 R R/W 4 GPIO4 Status = 0 R R/W 5 GPIO5 Status = 0 R R/W 6 GPIO6 Status = 0 R R/W 7 GPIO7 Status = 0 R R/W 1 GPIO status bits can be written only when a GPIO pin is configured as output. Read-only otherwise. Rev. A | Page 46 of 56 ADM1026 Table 50. Register 25h, Status Register 6 (Power-On Default 00h) Bit Name R/W1 0 GPIO8 Status = 0 R R/W 1 GPIO9 Status = 0 R R/W 2 GPIO10 Status = 0 R R/W 3 GPIO11 Status = 0 R R/W 4 GPIO12 Status = 0 R R/W 5 GPIO13 Status = 0 R R/W 6 GPIO14 Status = 0 R R/W 7 GPIO15 Status = 0 R R/W 1 Description When GPIO8 is configured as an input, this bit is set when GPIO8 is asserted. (Asserted may be active high or active low depending on setting of Bit 1 in GPIO Configuration Register 3.) When GPIO8 is configured as an output, setting this bit asserts GPIO8. (Asserted may be active high or active low depending on setting of Bit 1 in GPIO Configuration Register 3.) When GPIO9 is configured as an input, this bit is set when GPIO9 is asserted. (Asserted may be active high or active low depending on setting of Bit 3 in GPIO Configuration Register 3.) When GPIO9 is configured as an output, setting this bit asserts GPIO9. (Asserted may be active high or active low depending on setting of Bit 3 in GPIO Configuration Register 3.) When GPIO10 is configured as an input, this bit is set when GPIO10 is asserted. (Asserted may be active high or active low depending on setting of Bit 5 in GPIO Configuration Register 3.) When GPIO10 is configured as an output, setting this bit asserts GPIO10. (Asserted may be active high or active low depending on setting of Bit 5 in GPIO Configuration Register 3.) When GPIO11 is configured as an input, this bit is set when GPIO11 is asserted. (Asserted may be active high or active low depending on setting of Bit 7 in GPIO Configuration Register 3.) When GPIO11 is configured as an output, setting this bit asserts GPIO11. (Asserted may be active high or active low depending on setting of Bit 7 in GPIO Configuration Register 3.) When GPIO12 is configured as an input, this bit is set when GPIO12 is asserted. (Asserted may be active high or active low depending on setting of Bit 1 in GPIO Configuration Register 4.) When GPIO12 is configured as an output, setting this bit asserts GPIO12. (Asserted may be active high or active low depending on setting of Bit 1 in GPIO Configuration Register 4.) When GPIO13 is configured as an input , this bit is set when GPIO13 is asserted. (Asserted may be active high or active low depending on setting of Bit 3 in GPIO Configuration Register 4.) When GPIO13 is configured as an output, setting this bit asserts GPIO13. (Asserted may be active high or active low depending on setting of Bit 3 in GPIO Configuration Register 4.) When GPIO14 is configured as an input , this bit is set when GPIO14 is asserted. (Asserted may be active high or active low depending on setting of Bit 5 in GPIO Configuration Register 4.) When GPIO14 is configured as an output, setting this bit asserts GPIO14. (Asserted may be active high or active low depending on setting of Bit 5 in GPIO Configuration Register 4.) When GPIO15 is configured as an input, this bit is set when GPIO15 is asserted. (Asserted may be active high or active low depending on setting of Bit 7 in GPIO Configuration Register 4.) When GPIO15 is configured as an output, setting this bit asserts GPIO15. (Asserted may be active high or active low depending on setting of Bit 7 in GPIO Configuration Register 4.) GPIO status bits can be written only when a GPIO pin is configured as output. Read-only otherwise. Table 51. Register 26h, VBAT Measured Value (Power-On Default 00h) Bit Name R/W Description 7–0 VBAT Value R This register contains the measured value of the VBAT analog input channel. Table 52. Register 27h, AIN8 Measured Value (Power-On Default 00h) Bit Name R/W Description 7–0 AIN8 Value R This register contains the measured value of the AIN8 analog input channel. Table 53. Register 28h, EXT1 Measured Value (Power-On Default 00h) Bit Name R/W Description 7–0 Ext1 Value R This register contains the measured value of the Ext1 Temp channel. Table 54. Register 29h, EXT2/AIN9 Measured Value (Power-On Default 00h) Bit Name R/W Description 7–0 Ext2 Temp/ AIN9 Low Limit R This register contains the measured value of the Ext2 Temp/AIN9 channel depending on which bit is configured. Rev. A | Page 47 of 56 ADM1026 Table 55. Register 2Ah, 3.3 V STBY Measured Value (Power-On Default 00h) Bit Name R/W Description 7–0 3.3 V STBY Value R This register contains the measured value of the 3.3 V STBY voltage. Table 56. Register 2Bh, 3.3 V MAIN Measured Value (Power-On Default 00h) Bit Name R/W Description 7–0 3.3 V MAIN Value R This register contains the measured value of the 3.3 V MAIN voltage. Table 57. Register 2Ch, +5 V Measured Value (Power-On Default 00h) Bit Name R/W Description 7–0 +5 V Value R This register contains the measured value of the +5 V analog input channel. Table 58. Register 2Dh, VCCP Measured Value (Power-On Default 00h) Bit Name R/W Description 7–0 VCCP Value R This register contains the measured value of the VCCP analog input channel. Table 59. Register 2Eh, +12V Measured Value (Power-On Default 00h) Bit Name R/W Description 7–0 +12 V Value R This register contains the measured value of the +12 V analog input channel. Table 60. Register 2Fh, –12V Measured Value (Power-On Default 00h) Bit Name R/W Description 7–0 –12 V Value R This register contains the measured value of the −12 V analog input channel. Table 61. Register 30h, AIN0 Measured Value (Power-On Default 00h) Bit Name R/W Description 7–0 AIN0 Value R This register contains the measured value of the AIN0 analog input channel. Table 62. Register 31h, AIN1 Measured Value (Power-On Default 00h) Bit Name R/W Description 7–0 AIN1 Value R This register contains the measured value of the AIN1 analog input channel. Table 63. Register 32h, AIN2 Measured Value (Power-On Default 00h) Bit Name R/W Description 7–0 AIN2 Value R This register contains the measured value of the AIN2 analog input channel. Table 64. Register 33h, AIN3 Measured Value (Power-On Default 00h) Bit Name R/W Description 7–0 AIN3 Value R This register contains the measured value of the AIN3 analog input channel. Table 65. Register 34h, AIN4 Measured Value (Power-On Default 00h) Bit Name R/W Description 7–0 AIN4 Value R This register contains the measured value of the AIN4 analog input channel. Table 66. Register 35h, AIN5 Measured Value (Power-On Default 00h) Bit Name R/W Description 7–0 AIN5 Value R This register contains the measured value of the AIN5 analog input channel. Table 67. Register 36h, AIN6 Measured Value (Power-On Default 00h) Bit Name R/W Description 7–0 AIN6 Value R This register contains the measured value of the AIN6 analog input channel. Table 68. Register 37h, AIN7 Measured Value (Power-On Default 00h) Bit Name R/W Description 7–0 AIN7 Value R This register contains the measured value of the AIN7 analog input channel. Rev. A | Page 48 of 56 ADM1026 Table 69. Register 38h, FAN0 Measured Value (Power-On Default 00h) Bit Name R/W Description 7–0 FAN0 Value R This register contains the measured value of the FAN0 tach input channel. Table 70. Register 39h, FAN1 Measured Value (Power-On Default 00h) Bit Name R/W Description 7–0 FAN1 Value R This register contains the measured value of the FAN1 tach input channel. Table 71. Register 3Ah, FAN2 Measured Value (Power-On Default 00h) Bit Name R/W Description 7–0 FAN2 Value R This register contains the measured value of the FAN2 tach input channel. Table 72. Register 3Bh, FAN3 Measured Value (Power-On Default 00h) Bit Name R/W Description 7–0 FAN3 Value R This register contains the measured value of the FAN3 tach input channel. Table 73. Register 3Ch, FAN4 Measured Value (Power-On Default 00h) Bit Name R/W Description 7–0 FAN4 Value R This register contains the measured value of the FAN4 tach input channel. Table 74. Register 3Dh, FAN5 Measured Value (Power-On Default 00h) Bit Name R/W Description 7–0 FAN5 Value R This register contains the measured value of the FAN5 tach input channel. Table 75. Register 3Eh, FAN6 Measured Value (Power-On Default 00h) Bit Name R/W Description 7–0 FAN6 Value R This register contains the measured value of the FAN6 tach input channel. Table 76. Register 3Fh, FAN7 Measured Value (Power-On Default 00h) Bit Name R/W Description 7–0 FAN7 Value R This register contains the measured value of the FAN7 tach input channel. Table 77. Register 40h, Ext1 High Limit (Power-On Default 64h/100°C) Bit Name R/W Description 7–0 Ext1 High Limit R/W This register contains the high limit of the Ext1 Temp channel. Table 78. Register 41h, Ext2/AIN9 High Limit (Power-On Default 64h/100°C) Bit Name R/W Description 7–0 Ext2 Temp/ AIN9 High Limit R/W This register contains the high limit of the Ext2 Temp/AIN9 channel depending on which one is configured. Table 79. Register 42h, 3.3 V STBY High Limit (Power-On Default FFh) Bit Name R/W Description 7–0 3.3 V STBY High Limit R/W This register contains the high limit of the 3.3 V STBY analog input channel. Table 80. Register 43h, 3.3 V MAIN High Limit (Power-On Default FFh) Bit Name R/W Description 7–0 3.3 V MAIN High Limit R/W This register contains the high limit of the 3.3 V MAIN analog input channel. Table 81. Register 44h, +5 V High Limit (Power-On Default FFh) Bit Name R/W Description 7–0 +5 V High Limit R/W This register contains the high limit of the +5 V analog input channel. Table 82. Register 45h, VCCP High Limit (Power-On Default FFh) Bit Name R/W Description 7–0 VCCP High Limit R/W This register contains the high limit of the VCCP analog input channel. Rev. A | Page 49 of 56 ADM1026 Table 83. Register 46h, +12 V High Limit (Power-On Default FFh) Bit Name R/W Description 7–0 +12 V High Limit R/W This register contains the high limit of the +12 V analog input channel. Table 84. Register 47h, −12 V High Limit (Power-On Default FFh) Bit Name R/W Description 7–0 −12V High Limit R/W This register contains the high limit of the −12 V analog input channel. Table 85. Register 48h, Ext1 Low Limit (Power-On Default 80h) Bit Name R/W Description 7–0 Ext1 Low Limit R/W This register contains the low limit of the Ext1 Temp channel. Table 86. Register 49h, Ext2 / AIN9 Low Limit (Power-On-Default 80h) Bit Name R/W Description 7–0 Ext2 Temp /AIN9 Low Limit R/W This register contains the low limit of the Ext2 Temp/AIN9 channel depending on which bit is configured. Table 87. Register 4Ah, 3.3 V STBY Low Limit (Power-On Default 00h) Bit Name R/W Description 7–0 3.3 V STBY Low Limit R/W This register contains the low limit of the 3.3 V STBY analog input channel. Table 88. Register 4Bh, 3.3 V MAIN Low Limit (Power-On Default 00h) Bit Name R/W Description 7–0 3.3 V MAIN Low Limit R/W This register contains the low limit of the 3.3 V MAIN analog input channel. Table 89. Register 4Ch, +5V Low Limit (Power-On Default 00h) Bit Name R/W Description 7–0 0+5 V Low Limit R/W This register contains the low limit of the +5 V analog input channel. Table 90. Register 4Dh, VCCP Low Limit (Power-On Default 00h) Bit Name R/W Description 7–0 VCCP Low Limit R/W This register contains the low limit of the VCCP analog input channel. Table 91. Register 4Eh, +12V Low Limit (Power-On Default 00h) Bit Name R/W Description 7–0 +12 V Low Limit R/W This register contains the low limit of the +12 V analog input channel. Table 92. Register 4Fh, –12V Low Limit (Power-On Default 00h) Bit Name R/W Description 7–0 −12 V Low Limit R/W This register contains the low limit of the −12 V analog input channel. Table 93. Register 50h, AIN0 High Limit (Power-On Default FFh) Bit Name R/W Description 7–0 AIN0 High Limit R/W This register contains the high limit of the AIN0 analog input channel. Table 94. Register 51h, AIN1 High Limit (Power-On Default FFh) Bit Name R/W Description 7–0 AIN1 High Limit R/W This register contains the high limit of the AIN1 analog input channel. Table 95. Register 52h, AIN2 High Limit (Power-On Default FFh) Bit Name R/W Description 7–0 AIN2 High Limit R/W This register contains the high limit of the AIN2 analog input channel. Table 96. Register 53h, AIN3 High Limit (Power-On Default FFh) Bit Name R/W Description 7–0 AIN3 High Limit R/W This register contains the high limit of the AIN3 analog input channel. Rev. A | Page 50 of 56 ADM1026 Table 97. Register 54h, AIN4 High Limit (Power-On Default FFh) Bit Name R/W Description 7–0 AIN4 High Limit R/W This register contains the high limit of the AIN4 analog input channel. Table 98. Register 55h, AIN5 High Limit (Power-On Default FFh) Bit Name R/W Description 7–0 AIN5 High Limit R/W This register contains the high limit of the AIN5 analog input channel. Table 99. Register 56h, AIN6 High Limit (Power-On Default FFh) Bit Name R/W Description 7–0 AIN6 High Limit R/W This register contains the high limit of the AIN6 analog input channel. Table 100. Register 57h, AIN7 High Limit (Power-On Default FFh) Bit Name R/W Description 7–0 AIN7 High Limit R/W This register contains the high limit of the AIN7 analog input channel. Table 101. Register 58h, AIN0 Low Limit (Power-On Default 00h) Bit Name R/W Description 7–0 AIN0 Low Limit R/W This register contains the low limit of the AIN0 analog input channel. Table 102. Register 59h, AIN1 Low Limit (Power-On Default 00h) Bit Name R/W Description 7–0 AIN1 Low Limit R/W This register contains the low limit of the AIN1 analog input channel. Table 103. Register 5Ah, AIN2 Low Limit (Power-On Default 00h) Bit Name R/W Description 7–0 AIN2 Low Limit R/W This register contains the low limit of the AIN2 analog input channel. Table 104. Register 5Bh, AIN3 Low Limit (Power-On Default 00h) Bit Name R/W Description 7–0 AIN3 Low Limit R/W This register contains the low limit of the AIN3 analog input channel. Table 105. Register 5Ch, AIN4 Low Limit (Power-On Default 00h) Bit Name R/W Description 7–0 AIN4 Low Limit R/W This register contains the low limit of the AIN4 analog input channel. Table 106. Register 5Dh, AIN5 Low Limit (Power-On Default 00h) Bit Name R/W Description 7–0 AIN5 Low Limit R/W This register contains the low limit of the AIN5 analog input channel. Table 107. Register 5Eh, AIN6 Low Limit (Power-On Default 00h) Bit Name R/W Description 7–0 AIN6 Low Limit R/W This register contains the low limit of the AIN6 analog input channel. Table 108. Register 5Fh, AIN7 Low Limit (Power-On Default 00h) Bit Name R/W Description 7–0 AIN7 Low Limit R/W This register contains the low limit of the AIN7 analog input channel. Table 109. Register 60h, FAN0 High Limit (Power-On Default FFh) Bit Name R/W Description 7–0 FAN0 High Limit R/W This register contains the high limit of the FAN0 tach channel. Table 110. Register 61h, FAN1 High Limit (Power-On Default FFh) Bit Name R/W Description 7–0 FAN1 High Limit R/W This register contains the high limit of the FAN1 tach channel. Rev. A | Page 51 of 56 ADM1026 Table 111. Register 62h, FAN2 High Limit (Power-On Default FFh) Bit Name R/W Description 7–0 FAN2 High Limit R/W This register contains the high limit of the FAN2 tach channel. Table 112. Register 63h, FAN3 High Limit (Power-On Default FFh) Bit Name R/W Description 7–0 FAN3 High Limit R/W This register contains the high limit of the FAN3 tach channel. Table 113. Register 64h, FAN4 High Limit (Power-On Default FFh) Bit Name R/W Description 7–0 FAN4 High Limit R/W This register contains the high limit of the FAN4 tach channel. Table 114. Register 65h, FAN5 High Limit (Power-On Default FFh) Bit Name R/W Description 7–0 FAN5 High Limit R/W This register contains the high limit of the FAN5 tach channel. Table 115. Register 66h, FAN6 High Limit (Power-On Default FFh) Bit Name R/W Description 7–0 FAN6 High Limit R/W This register contains the high limit of the FAN6 tach channel. Table 116. Register 67h, FAN7 High Limit (Power-On Default FFh) Bit Name R/W Description 7–0 FAN7 High Limit R/W This register contains the high limit of the FAN7 tach channel. Table 117. Register 68h, Int Temp High Limit (Power-On Default 50h (80°C)) Bit Name R/W Description 7–0 Int Temp High Limit R/W This register contains the high limit of the internal temperature channel. Table 118. Register 69h, Int Temp Low Limit (Power-On Default 80h) Bit Name R/W Description 7–0 Int Temp Low Limit R/W This register contains the low limit of the internal temperature channel. Table 119. Register 6Ah, VBAT High Limit (Power-On Default FFh) Bit Name R/W Description 7–0 VBAT High Limit R/W This register contains the high limit of the VBAT analog input channel. Table 120. Register 6Bh, VBAT Low Limit (Power-On Default 00h) Bit Name R/W Description 7–0 VBAT Low Limit R/W This register contains the low limit of the VBAT analog input channel. Table 121. Register 6Ch, AIN8 High Limit (Power-On Default FFh) Bit Name R/W Description 7–0 AIN8 High Limit R/W This register contains the high limit of the AIN8 analog input channel. Table 122. Register 6Dh, AIN8 Low Limit (Power-On Default 00h) Bit Name R/W Description 7–0 AIN8 Low Limit R/W This register contains the low limit of the AIN8 analog input channel. Rev. A | Page 52 of 56 ADM1026 Table 123. Register 6Eh, Ext1 Temp Offset (Power-On Default 00h) Bit Name R/W Description 7–0 Ext1 Temp Offset R/W This register contains the offset value for the external 1 temperature channel. A twos complement number can be written to this register, which is then added to the measured result before it is stored or compared to limits. In this way, a sort of one-point calibration can be done whereby the whole transfer function of the channel can be moved up or down. From a software point of view, this may be a very simple method to vary the characteristics of the measurement channel if the thermal characteristics change for any reason (for instance from one chassis to another), if the measurement point is moved, if a plug-in card is inserted or removed, and so on. Table 124. Register 6Fh, Ext2 Temp Offset (Power-On Default 00h) Bit Name R/W Description 7–0 Ext2 Temp Offset R/W This register contains the offset value for the external 2 temperature channel. A twos complement number can be written to this register, which is then added to the measured result before it is stored or compared to limits. In this way, a sort of one-point calibration can be done whereby the whole transfer function of the channel can be moved up or down. From a software point of view, this may be a very simple method to vary the characteristics of the measurement channel if the thermal characteristics change for any reason (for instance from one chassis to another), if the measurement point is moved, if a plug-in card is inserted or removed, and so on. Rev. A | Page 53 of 56 ADM1026 OUTLINE DIMENSIONS 0.75 0.60 0.45 9.00 BSC SQ 1.60 MAX 37 48 36 1 1.45 1.40 1.35 0.15 0.05 PIN 1 SEATING PLANE 10° 6° 2° (PINS DOWN) VIEW A 7° 3.5 ° 0° 0.08 MAX COPLANARITY SEATING PLANE 7.00 BSC SQ TOP VIEW 0.20 0.09 25 12 13 0.50 BSC VIEW A ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026BBC Figure 63. 48-Lead Thin Plastic Quad Flat Package [LQFP] 7 mm x 7 mm x 1.4 mm Thick (ST-48) Dimensions shown in millimeters Rev. A | Page 54 of 56 24 0.27 0.22 0.17 ADM1026 ORDERING GUIDE Model ADM1026JST ADM1026JST-REEL ADM1026JST-REEL7 ADM1026JSTZ-REEL1 EVAL-ADM1026EB 1 Temperature Range 0°C to 100°C 0°C to 100°C 0°C to 100°C 0°C to 100°C Z = Pb-free part. Rev. A | Page 55 of 56 Package Description 48-Lead LQFP 48-Lead LQFP 48-Lead LQFP 48-Lead LQFP Evaluation Board Package Option ST-48 ST-48 ST-48 ST-48 ADM1026 NOTES © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C02657-0-3/04(A) Rev. A | Page 56 of 56