AN82 HIGH-DENSITY MULTI CHANNEL OC-48 LAYOUT GUIDELINES S i 5 1 0 0 A N D S i 5 11 0 Introduction OC-48 small form-factor hot-pluggable modules (SFP) allow designers to place a large number of OC-48 links in a relatively small amount of space. As the density increases, adjacent channels are more likely to interfere with each other. When the Si5110 or Si5100 OC-48 transceivers are used to receive and transmit through the SFP module, it is necessary to minimize the adjacent channel coupling in order to meet the transmit jitter generation requirements. FOR THE In addition, adjacent devices can couple to surrounding devices if their TTL or high-speed traces can couple to each other. Since PCB fabrication does not allow for solid walls perpendicular to the plane of the board, a "wall" of vias can be used to isolate nearby traces as shown in Figure 1. Vias should be placed along the axis of propagation no farther than 100 mil apart. Diff Pair Via Wall Diff Pair Background The oscillator that generates the timing for the transmit data within the transceiver stores energy in electric and magnetic fields during oscillation. The magnetic fields extend several inches (centimeters) from the device but decrease in magnitude at a rate inversely proportional to the square of the distance. Consequently, distance is key to minimizing the adjacent channel coupling. In addition, energy from other sources can couple into the device through capacitive and mutually-inductive means. These paths effectively reduce the distance that an adjacent carrier appears. Most materials do not provide any change in the permeability of the region at RF and microwave frequencies (Refer to Noise Reduction Techniques in Electronic Systems, 2nd Edition 1988, pp182–7 by Henry W. Ott). The most notable exception is metal. Completely surrounding magnetic fields with sufficiently thick metal isolates the fields. Gnd Planes Magnetic Field Lines Figure 1. Stripline Via Wall Isolation Power Supply Isolation (1.8 V and 3.3 V) The oscillator within the transceiver relies on a clean power supply to provide very low generated jitter. Noise/ interference from adjacent ICs couples electrically through the power planes. Each transceiver device should operate on a separate power island for both the 1.8 V and 3.3 V supplies. Ferrite beads should be used to isolate the islands as shown in Figure 2. VDD VDDIO Layout Guidelines The following layout guidelines are based on results obtained from an experimental board as well as general best-practice layout principles. The implementation of these recommendations should be straightforward. Si5110 Si5110 Si5110 Si5110 Adjacent Channel Traces (High-Speed and TTL) Since the magnetic fields extend beyond the transceiver device, mutual inductance exists between the oscillator and the surrounding metal (traces, power planes, heatsinks, etc.). To minimize the effect of switching currents from both TTL and high-speed I/O, these traces should be run on stripline layers. With a stripline structure, at least one power plane will isolate the traces from the oscillator's magnetic fields, thereby reducing the coupling. Rev. 0.1 6/03 GND Figure 2. Power Supply Isolation Copyright © 2003 by Silicon Laboratories AN82-DS01 AN82 Distance Common Metal Heat-sink Distance is fundamentally important when observing coupling. Adjacent Si5110s should be physically separated by no less than 300 mil (7.6 mm). Adjacent channels can be further separated if alternating transceiver devices are located on opposite sides of a PCB (see Figure 3) or if alternating devices have shorter and longer traces to/from the associated SFP module (see Figure 4). Metal Pedestal 125 mil (min) C O 8 -4 SF P O C 8 -4 P SF O C 8 -4 P SF O C 8 -4 P SF O C 8 -4 P SF O C 8 -4 P SF Si5110 Si5110 Si5110 Si5110 Si5110 Si5110 Si5110 Channels 1, 3, 5 topside Channels 2, 4, 6 bottom side Figure 5. Common Heat-Sink Height Separation Requirement Figure 3. Staggered Device Placement (Opposite Side) O Si5110 C 8 -4 P SF O C 8 -4 P SF O Si5110 Si5110 8 -4 C P SF O C 8 -4 P SF O C 8 -4 P SF O C 8 -4 Summary P SF Si5110 Si5110 Si5110 Figure 4. Si5110 Staggered Device Placement (Same Side) The Si5110 and Si5100 devices are a perfect match for OC-48 SFP modules in both size and feature set. However, care must be taken to minimize interference between adjacent channels on a multi-channel card. Considering the physical channel spacing, power supply filtering, and heat-sinking early in the design will help reduce costly PCB redesigns. For further technical questions regarding the Si5110, and Si5100, please contact a Silicon Laboratories application engineer. Heat-Sinks The Si5110 and Si5100 do not normally require a heatsink and can operate with ambient temperatures at 85 °C during their lifetime. However, if metal heat sinking is required, the minimum spacing between devices will need to be increased because a metal heat sink increases the device-to-device coupling. If metal heat sinks are attached to a common metal shell, it is necessary to separate the heat-sinks above the top-side of the Si5110 or Si5100 by greater than 125 mil. The 125 mil minimum-height gap can be filled by non-metallic heat transfer materials. See Figure 5. 2 PCB Rev. 0.1 AN82 Notes: Rev. 0.1 3 AN82 Contact Information Silicon Laboratories Inc. 4635 Boston Lane Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: [email protected] Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. 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