bq2028 www.ti.com SLUSB22B – OCTOBER 2012 – REVISED NOVEMBER 2012 4Kb EEPROM with Single-Wire HDQ Interface and Temperature Sensor Check for Samples: bq2028 FEATURES DESCRIPTION • The Texas Instruments bq2028 serial 4Kb nonvolatile memory (EEPROM) with integrated temperature sensor and LDO linear regulator provides pack-side memory storage and temperature monitoring for a single-cell system-side battery fuel gauge solution such as the bq27505-E1. 1 • • • • Serial Non-Volatile Memory (NVM) – 512 Byte (4Kb) EEPROM – Provides Battery Pack NVM storage for bq27505-E1 Fuel Gauge: – Manufacturing Data – Operational History – Resistance Tables – State of Health Information Single Wire HDQ Communications Port Integrated 2.5V LDO Linear Regulator – Ultra-low power “shutdown” mode (1µA Typical) via auto-timeout and/or host command – Wake up from shutdown via HDQ break Internal Die-Temperature Sensor – ±5°C Range = –40°C to 85°C – Raw AD to Temperature Conversion Performed by Host Firmware Package – 12-pin, 1490 × 2350 µm WCSP (YZG), 0.625mm Max Thickness, 0.5mm Pitch The bq2028 communicates with the bq27505-E1 gauge over a single-wire HDQ interface with a minimal overhead protocol yet ensures error free data transfer. REGIN bq2028 2.5-V LDO HDQ VDD HDQ and control 512 x 8b EEPROM Internal temperature sensor VSS 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2012, Texas Instruments Incorporated bq2028 SLUSB22B – OCTOBER 2012 – REVISED NOVEMBER 2012 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DEVICE INFORMATION AVAILABLE OPTIONS PRODUCTION PART # bq2028YZGR bq2028YZGT PACKAGE TA TAPE and REEL QUANTITY 12-pin WCSP –40°C to 85°C 3000 250 PIN ASSIGNMENT CSP-12 (bottom view) D3 C3 B3 A3 D2 C2 B2 A2 D1 C1 B1 A1 Figure 1. bq2028 Pin Assignment (Bottom View) PIN DESCRIPTIONS PIN NAME CSP-12 PIN I/O DESCRIPTION TEST3 C3 I/O Reserved for factory test. Connect to VSS in application circuit. REGIN D3 P Regulator input. Typically connected to battery CELL+. VDD D2 P Regulator 2.5V output. Decouple with a 0.47µF cap to VSS. VSS A1, B1, D1, B2, C2 P Ground pin. HDQ A2 I/O HDQ Data pin. Open-drain I/O. Requires external pull-up for proper operation. TEST1 C1 I/O Reserved for factory test. Connect to VSS in application circuit. TEST0 B3 I/O Reserved for factory test. Connect to VSS in application circuit. TEST2 A3 I/O Reserved for factory test. Connect to VSS in application circuit. 2 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links :bq2028 bq2028 www.ti.com SLUSB22B – OCTOBER 2012 – REVISED NOVEMBER 2012 ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) VALUE UNIT MIN MAX VREGIN Supply voltage range –0.3 5.5 V HDQ Open-drain I/O pin –0.3 5.5 V VI Input voltage range to all other pins (TEST0-3) –0.3 VREG25 + 0.3 V ESD HBM for pins other than TEST1, TEST2, TEST3 2 kV TA Operating free-air temperature range –40 85 °C TF Functional temperature –40 100 °C Tstg Storage temperature range –65 150 °C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating condition” is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS TA = 25°C, CLDO25 = 0.47 µF, VREGIN = 3.6V (unless otherwise noted) VREGIN Supply Voltage MIN TYP MAX 2.45 4.5 UNIT V RPUEXT HDQ external pull-up To system-side 2.5V LDO output. Recommend using 10kΩ, 5% resistor. CHDQ HDQ capacitive loading Total external bus capacitance 50 CREGIN External input capacitor for internal LDO between REGIN and VSS 0.1 µF CLDO25 External output capacitor for internal LDO between VDD and VSS Nominal capacitor values specified. Recommend a 5% ceramic X5R type capacitor located close to the device. 0.47 µF 10 22 kΩ 250 pF Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links :bq2028 3 bq2028 SLUSB22B – OCTOBER 2012 – REVISED NOVEMBER 2012 www.ti.com DC ELECTRICAL CHARACTERISTICS TA = –40°C to 85°C, CLDO25 = 0.47 µF, VREGIN = 3.6 V (unless otherwise noted) PARAMETER TEST CONDITION MIN TYP MAX UNIT SUPPLY CURRENT SHUTDOWN Mode (LDO = off) SLEEP Mode (LFO = on; HFO = off) ICC Supply Current (1) IDLE Mode (LFO, HFO = on; CONV= 0) TEMP Read (LFO, HFO = on; CONV = 1) 1 2 20 50 55 110 110 200 EEPROM Read (LFO, HFO = on) 300 600 EEPROM Write (LFO, HFO = on) 2300 5000 2.5 2.6 µA 2.5V LDO REGULATOR VREG25 Regulator output voltage 2.7 V ≤ VREGIN ≤ 4.5 V, IOUT ≤ 10 mA 2.4 2.45 V ≤ VREGIN < 2.7 V (low battery), IOUT ≤ 3 mA 2.4 V OTHER ANALOG: POWER ON RESET, TEMPERATURE SENSOR, INTERNAL VOLTAGE REFERENCE VPOR+ POR Threshold Positive-going input at VDD, TA = 25°C 2.05 2.20 2.31 V VHYSPOR POR Hysteresis TA=25°C 45 115 185 mV VWU+ HDQ Wakeup threshold Positive-going input at HDQ, TA = 25°C 1.2 VHYSWU HDQ Wakeup hysteresis TA = 25°C VASD Auto shutdown threshold VHYSASD Auto shutdown hysteresis V(TEMP) Temperature sensor 1.4 V 505 mV 2.05 2.20 2.31 45 115 185 –1.986 V V mV/°C HDQ INTERFACE VIH Input voltage high VIL Input voltage low VOH Output voltage high Open drain, external pull up to VDD VOL Output voltage low Open-drain IOL = 1mA CI Input capacitance Iitot HDQ input total current Includes leakage plus internal pull-down 2 µA IOL Output low sink current VOL = 0.4V 1 mA RPDINT HDQ internal pull-down For auto-shutdown 5 MΩ (1) 4 1.8 V 0.6 VDD–0.5 V 0.4 10 1.25 V 2.5 V pF An EEPROM write operation is required for proper device initialization following exit from SHUTDOWN, SLEEP, or POWER-ON RESET. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links :bq2028 bq2028 www.ti.com SLUSB22B – OCTOBER 2012 – REVISED NOVEMBER 2012 AC ELECTRICAL CHARACTERISTICS TA = –40°C to 85°C, CLDO25 = 0.47 µF, VREGIN = 3.6V (unless otherwise noted) PARAMETER TEST CONDITION MIN TYP MAX UNIT EEPROM Array Size 128 words x 32 bits = 4Kbits 512 Write Cycle Endurance Bytes 1000 K cycles HDQ Data Access Via 32 bit BUFFER 8 Program time Per word (internal timing only) 6 20 Bits mS Read time Per word (internal timing only) 300 2000 nS HDQ INTERFACE AND MISCELLANEOUS (Refer to Figure 6 and Figure 7) tB Break time tBR Break recovery time tSLWU SLEEP wakeup tSHWU SHUTDOWN wakeup Host drives HDQ Break. Timed from rising edge of first wakeup break pulse to falling edge of next break pulse with first data. tSHUTDN SHUTDOWN time Time delay after VASD threshold is met before SHUTDOWN mode is entered. tASHWU AUTOSHUTDOWN wakeup Time delay after VASD threshold is met or 2 second timeout is met before Host can drive HDQ break for wakeup. tPORWU POR wakeup Power on reset wakeup time before device is ready to receive first HDQ message st 190 µs 40 µs 200 µs 20 ms 2 10 S 2 10 S 35 ms tREGINHDQ REGIN to HDQ REGIN valid to 1 rising edge of HDQ to POR device. (Figure 3) tPOR POR VDD ramp to POR release.(Figure 3) 15 ms tGRST Global reset POR release to GRST release. (Figure 3) tHW1 Host Write 1 time Host drives HDQ 5 50 µs tHW0 Host Write 0 time Host drives HDQ 86 145 µs tCYCH Host cycle time Host drives HDQ 190 tDW1 Device Write 1 time bq2028 drives HDQ 39 41 43 µs tDW0 Device Write 0 time bq2028 drives HDQ 106 111 116 µs tCYCD Device cycle time bq2028 drives HDQ 197 207 217 µs tRSPS Device response time bq2028 drives HDQ 211 222 233 µs tHDQSTDET HDQ Start detect bq2028 filters out very short HDQ pulses 1.98 µs 11 4 ms ms µs 0 A/D CONVERTER f(SAMPLE) Sampling frequency t(CONV) Conversion time V(ADC_IN) Input voltage range Delta Sigma modulator frequency 65.5 SPEED[1:0] = 00 125 SPEED[1:0] = 01 62.50 SPEED[1:0] = 10 31.25 SPEED[1:0] = 11 Internal Vref, TA = 25°C, VTEMP internal channel only kHz ms 7.8125 –0.2 1 V HIGH FREQUENCY OSCILLATOR (HFO) HFOSC Operating frequency HFERR Frequency error HFSTART Start-up time 8.389 TA = –40°C to 85°C –8.0% MHz 8.0% 14 200 µs LOW FREQUENCY OSCILLATOR (LFO) LFOSC Operating frequency LFERR Frequency error LFSTART Start-up time 32.768 TA = –40°C to 85°C –8.0% kHz 8.0% 100 500 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links :bq2028 μs 5 bq2028 SLUSB22B – OCTOBER 2012 – REVISED NOVEMBER 2012 www.ti.com BLOCK DIAGRAM PACK+ VSYS REGIN 2.5V LDO BAT bq2028 VCC HDQ DATA SDA VDD 2.5V LDO LFO Optional TEST0 VCC SCL HDQ & Control HFO TEST1 bq27505-E1 Host Controller HDQ Wakeup / POR + TEST2 BI/TOUT TEST3 SOC_INT BAT_LOW 128 x 32b EEPROM To System / Charger TS Internal Temp. Sensor VSS SRP VSS T SRN _ 10-Bit ADC VCC VM Low-Side Protector CHG VSS DSG PACK- 10mΩ Figure 2. bq2028 Block Diagram Power Modes The bq2028 has multiple operational modes for reduced power consumption. defines which circuits are enabled in each of these operational modes. Table 1. Power Mode Table (1) (1) 6 CIRCUIT SHUT-DOWN SLEEP IDLE HDQ READ/WRITE TEMP READ EEPROM READ EEPROM WRITE Wakeup/POR √ √ √ √ √ √ √ LDO Regulator – √ √ √ √ √ √ 32kHz LFO – √ √ √ √ √ √ 8MHz HFO – – √ √ √ √ √ HDQ Interface – – – √ √ √ √ ADC – – – – √ – – EEPROM Read – – – – – √ – EEPROM Write – – – – – – √ √: Active spacer –: Not in use Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links :bq2028 bq2028 www.ti.com SLUSB22B – OCTOBER 2012 – REVISED NOVEMBER 2012 tPORWU tREGINHDQ tGRST tPOR REGIN HDQ VDD POR 1 GRST (1) Internal digital core reset, held for 4 ms after analog POR deasserted Figure 3. Power Up Sequence tSHWU tGRST tPOR REGIN HDQ VDD POR 1 GRST (1) Internal digital core reset, held for 4 ms after analog POR deasserted Figure 4. Shutdown Wake Up Sequence HDQ Interface The bq2028 supports a single-wire, open-drain communication interface that supports the HDQ protocol as shown in Figure 5. The HDQ protocol is based on the Texas Instruments HDQ standard as discussed in the TI application report (SLUA408A) (http://focus.ti.com.cn/cn/lit/an/slua408a/slua408a.pdf ). The communication protocol is asynchronous return-to-one referenced to Vss. A passive pullup resistance is required to pull the HDQ line to a high state when neither the host nor the slave is pulling the line low during twoway communication over the single wire interface. The interface uses a command-based protocol, where the host sends a command byte to the HDQ slave device. The command directs the slave to either receive or transmit the next byte of data. The last transmitted bit of the command byte determines the direction of the data (read or write) as shown in Figure 7. bq275XX (HDQ master) bq27528 (HDQ slave) VDD HDQ Figure 5. HDQ Interface Connections (single wire configuration) Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links :bq2028 7 bq2028 SLUSB22B – OCTOBER 2012 – REVISED NOVEMBER 2012 tB www.ti.com tBR tDW0 tHW0 tDW1 tHW1 tCYCD tCYCH tB tSLWU, tSHWU tB tBR Figure 6. HDQ Detailed Timing Waveform tRSPS HDQ 8-bit data from HDQ slave Command byte from HDQ master 7-bit address BREAK D0 D1 D3 D2 8-bit data R/W bit D4 D5 D6 D0 D7 D1 D3 D2 D5 D4 D6 D7 D7=1, Write D7=1, Read Figure 7. HDQ 8-bit Mode Read Cycle Device Control Using a register address access method, the HDQ command byte limits addressing to 7 bits so a mapping scheme is necessary to differentiate device control and status registers from EEPROM data. This register and paged EEPROM access scheme is shown in Figure 8. 0x0B ADLOW ~3.5-ms HDQ transfer (LSBs shifted first) CRCT (Target) READ C[1:0] R[3:0] M W/R HDQ8 host 0x0A 0x03 Buffer[3] 0x04 CRCR (Result) 0x21 D[7:0] WRITE Buffer[2] 0x01 Buffer[1] 0x09 Status 0x08 ADCTL2 ADCTL1 HDQ registers 0x20 0x02 Control ADHI 0x00 Buffer[0] 0X0D Row [3:0] 0x07 Page [2:0] 0X31 PageEn [7:0] C[1:0] R[ 3: 0 BUFFER ‘RRRR11 ‘RRRR10 ] Note: If M = 1 and W/R = 1, set MEM_WR mode. . Note: 8 pages @ 64 bytes pre page = 512 bytes total Rows 0 to 15, R[3:0] M 1 = Write 0 = Read 0x0C Previous result, Read-only Write to CRCT triggers MEM_WR or BUF_CRC action. 350 µs TRSPS max A[6:0] CRCH (previous HDQ) Current HDQ CRC 0x05 D[7] ... D[0] A[6] ... W/R A[0] 230 µs Break pulse TB+TBR min CRC-8 logic ‘RRRR01 ‘RRRR00 0 0x03 0x02 0x01 0x00 1 0x07 0x06 0x05 0x04 2 0x0B 0x0A 0x09 0x08 0X34 ... ... ... ... ... ... ... ... ... ... D 0X37 0X36 0X35 E 0X3B 0X3A 0X39 0X38 F 0X3F 0X3E 0X3D 0X3C Pages 0–7, P[2:0] 128 x 32-bit EEPROM Figure 8. Register and EEPROM Access Scheme 8 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links :bq2028 bq2028 www.ti.com SLUSB22B – OCTOBER 2012 – REVISED NOVEMBER 2012 Access to device control and data registers use the “Un-Mapped” address space with the “M” (Map bit) set to ‘0’. Access to the EEPROM space uses a Memory Mapped scheme with the “M” bit set to ‘1’. Refer to Figure 9 for details. Memory Mapped Registers R[3:0] C[1:0] W/R 1 R3 R2 R1 R0 C1 C0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bits 5:2 Bits 1:0 = W/R: Read/Write command (1 = Write, 0 = Read) = Map Bit, M = 1 = Row index: R[3:0] = Column/Buffer index: C[1:0] Unmapped Registers A[5:0] W/R Bit 7 0 A5 A4 A3 A2 A1 A0 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 = W/R: Read/Write command (1 = Write, 0 = Read) Bits 6:5 = Map Bit, M = 0 Bits 4:0 = HDQ register: A[5:0] Range = 0x00 to 0x3F Figure 9. HDQ Command Byte Decode Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links :bq2028 9 bq2028 SLUSB22B – OCTOBER 2012 – REVISED NOVEMBER 2012 www.ti.com 7 HDQ Access Method HDQ Command Format Bit # W/R M =0 M =1 7 6 POR A[5:0] R[3:0] 5 4 3 C[1:0] 2 0 1 (Wait for) HDQ command Read: 0 Map: 0 Command M bit? Write: 1 Command W/R bit? Map: 1 Map: 0 Yes Clear MEM_WR bit, Save R[3:0] Set HDQ data = BUFFER[C] No Yes No Set MEM_WR bit, Save R[3:0] Is MEM_W bit set? Set Register A[5:0] = HDQ data Is PageEn[Page] = 1? Yes Set Status: CRCB_ERR bit Yes Set BUFFER[C] = HDQ data No Set Status: PGEN_ERR bit Yes Set CRCR = CRC(BUFFER[C]) No Map: 1 Prefetch EEPROM[P:R] to BUFFER Yes Is CRCT = CRCR? Set CRCR = 0xFF Is A[5:0] = BUFFER Is A[5:0] = CRCT? Command M bit? Set CRCT = HDQ data Fetch EEPROM[P:R] to BUFFER Set HDQ data = Register A[5:0] Receive HDQ data from host Is CRCT = CRCR? No Set Status: CRCB_ERR bit Set CRCR = 0XFF Yes Return HDQ Data to host Is MEM_WR bit set? No Is A[5:0] = BUFFER? No Copy BUFFER to EEPROM[P:R] Yes Set CRCR = CRC(BUFFER[C]) Read back EEPROM[P:R] Yes Is BUFFER = EEPROM? No Set Status: MEM_ERR bit Clear MR_WR bit Figure 10. HDQ Access Flow Chart 10 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links :bq2028 bq2028 www.ti.com SLUSB22B – OCTOBER 2012 – REVISED NOVEMBER 2012 EEPROM Access The bq2028 provides 512 bytes of EEPROM non-volatile memory storage organized as 128 words x 32 bits. Due to the address limitations of the HDQ interface protocol, the EEPROM is accessed in 8 pages, with 16 rows of 4 bytes each. For IC manufacturing and analog trim data, 16 bytes or 4 words are reserved in last page of data. The access model terminology is listed below: EEPROM = 128x32-bit (512 bytes) non-volatile memory with paged access BUFFER = 32-bit long word in 4x8b volatile Buffer C = 2-bit byte Column index for Buffer: C[1:0] Buffer[C] = 8-bit access to BUFFER at index C. MSB is at byte indexed by C='11‘. P = 3-bit Page index for EEPROM: P[2:0] (8 pages/EEPROM) PAGE[P] = 16x32-bit rows (64 bytes) from EEPROM indexed by [P] R = 4-bit Row index for EEPROM: R[3:0] (16 rows/page) ROW[P,R] = 32-bit long word from EEPROM indexed by [P,R] Pre-Fetch = Automatic copy of an ROW[P,R] to BUFFER before read/write operation M = Mapping operations to access BUFFER and EEPROM: M[1:0] Buffer3 Buffer2 Buffer1 Buffer0 Page_Reg BUFFER Rows 0 to 15, R[3:0] P[2:0] Pages 0–7, P[2:0] 128 x 32-bit EEPROM Figure 11. Memory Map Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links :bq2028 11 bq2028 SLUSB22B – OCTOBER 2012 – REVISED NOVEMBER 2012 www.ti.com HDQ Registers A summary of the Un-Mapped HDQ Registers is provided by Table 2. Table 2. HDQ Un-Mapped Register Summary (1) (2) A[5:0] R/W Register B A[5:0] R/W Register B A[5:0] R/W Register B A[5:0] R/W Register 0x00 R/W Buffer0 – 0x10 – (Reserved) – 0x20 R CRCR – 0x30 R/W (Reserved) 0x01 R/W Buffer1 – 0x11 – (Reserved) – 0x21 R/W CRCT – 0x31 R/W PageEn 0x02 R/W Buffer2 – 0x12 – (Reserved) – 0x22 – (spare) – 0x32 R/W (Trim) 0x03 R/W Buffer3 – 0x13 – (Reserved) – 0x23 – (spare) – 0x33 R/W (Trim) 0x04 R Status – 0x14 – (Reserved) – 0x24 – (Reserved) – 0x34 R/W (Trim) 0x05 R/W Control – 0x15 – (Reserved) – 0x25 – (Reserved) – 0x35 R/W (Trim) 0x06 - (spare) – 0x16 – (Reserved) – 0x26 – (Reserved) – 0x36 R/W (Trim) 0x07 R/W Page – 0x17 – (Reserved) – 0x27 – (Reserved) – 0x37 – (Reserved) 0x08 R/W ADCTL1 – 0x18 – (spare) – 0x28 – (Reserved) – 0x38 – (Reserved) 0x09 R/W ADCTL2 – 0x19 – (spare) – 0x29 – (spare) – 0x39 – (Reserved) 0x0A R ADHI – 0x1A – (spare) – 0x2A – (spare) – 0x3A – (Reserved) 0x0B R ADLOW – 0x1B – (spare) – 0x2B – (spare) – 0x3B – (Reserved) 0x0C R CRCH – 0x1C – (spare) – 0x2C – (Reserved) – 0x3C – (Reserved) 0x0D R Row – 0x1D – (spare) – 0x2D – (Reserved) – 0x3D – (Reserved) 0x0E R DeviceRev – 0x1E – (spare) – 0x2E – (spare) – 0x3E – (Reserved) 0x0F R DeviceID – 0x1F – (spare) – 0x2F – (spare) – 0x3F – (Reserved) (1) (2) B = Defaults "Backed Up" in EEPROM Page[0] and auto-loaded at Power On Reset Page[0] EEPROM Addresses 0x38 to 0x3F contain the TI Die ID but these are not mapped to HDQ registers. 32-bit BUFFER Access (addresses 0x00 through 0x03) Access to the 32-bit words in the EEPROM is provided by a 32-bit BUFFER that is available as 8-bit HDQ registers: Buffer0 [LSB], Buffer1, Buffer2, Buffer[MSB]. 32-BIT BUFFER MS-Byte Buffer3 Name Name Name Name Access Reset 7(MSB) 6 R/W R/W LS-Byte Buffer2 Buffer1 Buffer0 5 4 3 2 Buffer0[7:0] (address 0x00) – Least Significant Byte Buffer1[7:0] (address 0x01) Buffer2[7:0] (address 0x02) Buffer3[7:0] (address 0x03) – Most Significant Byte R/W R/W R/W R/W Undefined 1 0 R/W R/W 1 MEM_ERR R 0 0 CRCB_ERR R 0 Status Register (address 0x04): Name Access Reset 7(MSB) BUSY R 0 6 ADC_DRDY R 0 5 PGEN_ERR R 0 4 MEM_WR R 0 3 RSVD R 0 2 RSTBIT R 0 BUSY (bit 7): Busy flag. This bit is normally ‘0’ and is set to ‘1’ when the device is performing an extended duration function such as device initialization, an ADC measurement or EEPROM write. Upon completion of the function, the BUSY bit will automatically clear to ‘0’. ADC_DRDY (bit 6): ADC Data ready flag. This bit indicates that conversion data is ready in the ADC Data Registers (ADHI and ADLOW). This bit is cleared by setting the CONV bit in the Control register. 12 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links :bq2028 bq2028 www.ti.com SLUSB22B – OCTOBER 2012 – REVISED NOVEMBER 2012 1 – ADC data is ready 0 – ADC data is not ready. PGEN_ERR (bit 5): Page Enable Error flag. This indicates that an EEPROM write was attempted to a page that was not enabled for write-access. MEM_WR (bit 4): Memory Write flag. This bit is set during the EEPROM memory access scheme when the Map bit is set with an HDQ write command. This bit is cleared if the Map bit is set with an HDQ read command or upon completion of an EEPROM program cycle. Refer to Figure 10. RSTBIT (bit 2): This bit is set to ‘1’ when the device has reset due to a Power On Reset (POR) event or a soft reset initiated by the Control:Reset bit. The RSTBIT will remain set to ‘1’ until the Control:RSTCLR bit is set to ‘1’. MEM_ERR (bit 1): This bit is set to ‘1’ when the device detects an EEPROM memory error. Refer to Figure 10. This bit, along with CRCB_ERR, is cleared using the Control:ERRCLR bit. CRCB_ERR (bit 0): This bit is set to ‘1’ when the device detects a BUFFER memory error after computing a CRC check. Refer to Figure 10. This bit, along with MEM_ERR, is cleared using the Control:ERRCLR bit. Control Register (address 0x05): Name Access Reset 7(MSB) CONV R/W 0 6 RSVD R 0 5 RSVD R 0 4 ERRCLR R/W 0 3 SLEEP R/W 0 2 RSTCLR R/W 0 1 RESET R/W 0 0 SHUTDOWN R/W 0 CONV (bit 7): Convert command bit. This bit is used to start an ADC conversion when set to ‘1’ and is automatically cleared at the end of data conversion cycle in order to minimize HDQ traffic. At the start of data conversion, the device sets the Status:BUSY flag and automatically clears the Status:ADC_DRDY flag to indicate data conversion is in progress. When data conversion is complete, both the CONV bit and BUSY flag are cleared and the ADC_DRDY flag is set. To abort an ADC conversion in process, the host can clear the CONV bit to ‘0’. ERRCLR (bit 4): A ‘1’ written to this bit will clear both the Status:MEM_ERR and CRCB_ERR bits. This bit auto-clears itself so a readback always reads ‘0’. SLEEP (bit 3): A ‘1’ written to this bit enables a lower-power mode with the HFO disabled. This bit is automatically cleared upon detection of HDQ communication activity. Therefore a readback of this bit over HDQ will always be ‘0’. Note: If SLEEP mode is commanded, the host should wake up the bq2028 by issuing an HDQ break pulse with no associated data, followed by a wait period of at least 200 us (tSLWU), then send a second HDQ break pulse with the first command. RSTCLR (bit 2): A ‘1’ written to this bit will clear the Status:RSTBIT flag and auto-clear itself so a readback always reads ‘0’. RESET (bit 1): A ‘1’ written to this bit will initiate a full device initialization. The device will auto-clear the RESET bit and set the Status:RSTBIT and Status:BUSY flags at the start of initialization. After initialization is complete the device will clear the BUSY flag. SHUTDOWN (bit 0): A ‘1’ written to this bit will initiate a full device Shutdown. This bit is automatically cleared upon a POR and must be cleared for correct HDQ activity. Therefore a readback of this bit over HDQ will always be ‘0’. Note: If SHUTDOWN mode is commanded, the host should wake up the bq2028 by issuing an HDQ break pulse with no associated data, followed by a wait period of at least 15ms (tSHWU), then send a second HDQ break pulse with the first command. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links :bq2028 13 bq2028 SLUSB22B – OCTOBER 2012 – REVISED NOVEMBER 2012 www.ti.com Page Register (address 0x07): EEPROM Page Register 7(MSB) RSVD R 0 Name Access Reset 6 RSVD R 0 5 RSVD R 0 4 RSVD R 0 3 RSVD R 0 2 R/W 0 1 Page[2:0] R/W 0 0 R/W 0 1 CHAN[1] R/W 0 0 CHAN[0] R/W 0 Page[2:0]: This contains the current 3-bit Page pointer for EEPROM access. ADCTL1 (address 0x08): ADC Control Register 1 Final Product Access Reset 7(MSB) RSVD R/W 0 6 VRVDD R/W 0 5 SPEED[1] R/W 0 4 SPEED[0] R/W 0 3 RSVD R/W 0 2 CHAN[2] R/W 0 RSVD (bit 7) Do not use. VRVDD (bit 6): Voltage reference selection bit. This bit selects which voltage reference (either VDD or internal VREF) is used by the ADC. 1 – Selects VDD as the ADC reference voltage for ratio metric conversions 0 – Selects the internal VREF as the ADC reference voltage SPEED[1:0] (bits 5-4): Conversion speed selection bits. SPEED[1:0] FILTER LENGTH CONVERSION TIME 00 8192 125ms 01 4096 62.5ms 10 2048 31.25ms 11 512 7.8125ms RSVD (bit 3) Do not use. CHAN[2:0] (bits 2–0): ADC Channel selection bits. Set to VTEMP (‘101’) to measure the internal die temperature sensor or set to VSS (‘111’) for measuring ADC offset. 14 CHAN[2:0] ADC INPUT CHANNEL (Product Datasheet) 000 RSVD 001 RSVD 010 RSVD 011 RSVD 100 RSVD 101 VTEMP 110 RSVD 111 VSS Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links :bq2028 bq2028 www.ti.com SLUSB22B – OCTOBER 2012 – REVISED NOVEMBER 2012 ADCTL2 (address 0x09): ADC Control Register 2 Final Product Access Reset 7(MSB) RSVD R 0 6 RSVD R 0 5 RSVD R 0 4 RSVD R 0 3 RSVD R 0 2 RSVD R 0 1 RSVD R 0 0 RSVD R 0 RSVD (bits 7:0): Do not use. ADHI (address 0x0A): ADC High Byte Data Register This register provides the high byte ADC conversion data in 2’s complement format. A full scale (max value) for this register is 7FFFh. A zero scale (min value) for this register is 8000h. 7(MSB) Name Access Reset 6 5 4 3 2 1 0 R 0 R 0 R 0 R 0 3 2 1 0 R 0 R 0 R 0 R 0 ADC[15:8] R 1 R 0 R 0 R 0 ADC[15:8] (bits 7:0): ADC high byte conversion data. ADLOW (address 0x0B): ADC Low Byte Data Register 7(MSB) Name Access Reset 6 5 4 ADC[7:0] R 1 R 0 R 0 R 0 ADC[7:0] (bits 7:0): ADC low byte conversion data. CRCH Register (address 0x0C): HDQ CRC Register The register contains the CRC-8 result of the previous HDQ command + data sequence and is useful for data integrity checks for single HDQ packet transfers. 7(MSB) Name Access Reset 6 5 4 3 2 1 0 R 0 R 0 R 0 R 0 CHRH[7:0] R 0 R 0 R 0 R 0 CHCH[7:0]: CRC-8 data from the previous HDQ packet. Data is computed using the full 16-bit HDQ package sequence included W/R bit, 7-bit command and 8-bit data. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links :bq2028 15 bq2028 SLUSB22B – OCTOBER 2012 – REVISED NOVEMBER 2012 www.ti.com Row Register (address 0x0D): EEPROM Row Register Name Access Reset 7(MSB) RSVD R 0 6 RSVD R 0 5 RSVD R 0 4 RSVD R 0 3 2 1 0 R 0 R 0 Row[3:0] R 0 R 0 Row[3:0]: This contains the current 4-bit Row pointer for a particular page. The value is automatically updated by Mapped access to the EEPROM. DeviceRev Register (address 0x0E): Device Revision Register Name Access Reset 7(MSB) 6 5 R R R 4 3 DeviceRev[7:0] R R DeviceRev[7:0] 2 1 0 R R R DeviceRev[7:0]: The read-only register returns the hardware device revision value The initial revision is 0x01 and increments by 1 for each design revision. DeviceID Register (address 0x0F): Device ID Register 7(MSB) Name Access Reset 6 5 4 3 2 1 0 R R R DeviceID[7:0] R R R R R DeviceID[7:0] = 0x28 DeviceRev[7:0]: This read-only register returns the unique device identification value which provides a method for the host to distinguish the bq2028 from other HDQ devices. The DeviceID for the bq2028 = 0x28. CRCR Register (address 0x20): BUFFER CRC Result Register 7(MSB) Name Access Reset 6 5 4 3 2 1 0 R R R R CRCR[7:0] R R R R Undefined CRCR[7:0]: This register contains the last BUFFER CRC computation result. CRCT Register (address 0x21): BUFFER CRC Target Register 7(MSB) Name Access Reset 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 CRCT[7:0] R/W 0 R/W 0 R/W 0 R/W 0 CRCT[7:0]: This register contains the CRC computation target for verifying the BUFFER contents prior to writing the data to EEPROM. This method is used to prevent EEPROM data corruption due to interrupted HDQ transfers or communication errors. An HDQ write to this register triggers the comparison of the CRC previously calculated as BUFFER data is loaded from the HDQ interface. If the MEM_WR flag is set and the CRCT target register matches the CRCR result register, the device will write the BUFFER to the EEPROM using the current ROW and PAGE register values. Then a read-back of the EEPROM will be rechecked to confirm the integrity of the memory write. Refer to flow chart in Figure 10 for CRC initialization and computations. An HDQ read of this register returns the previously written target value. 16 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links :bq2028 bq2028 www.ti.com SLUSB22B – OCTOBER 2012 – REVISED NOVEMBER 2012 CONTROL2 (address 0x25): CONTROL2 Register Name Access Reset 7(MSB) RSVD R/W 0 6 RSVD R/W 0 5 RSVD R/W 0 4 RSVD R/W 0 3 RSVD R/W 0 2 RSVD R/W 0 1 RSVD R/W 0 0 MANWREN R/W 0 RSVD (bits 7:1): Do not use. MANWREN (Bit 0): A ‘1’ enables write access to the Page 0 Manufacturer’s area registers and associated EEPROM locations 0x30 through 0x3F. Users of the bq2028 may only change the PageEn register (0x031) without adversely changing manufacturing trim data. PageEn Register (address 0x31): Page Enable Register Name Access Reset 7(MSB) 6 5 4 R/W R/W R/W 3 PageEn[7:0] R/W R/W EEPROM Page[0], Address 0x31 2 1 0 R/W R/W R/W PageEn[X]: Each bit maps to the associated EEPROM page and enables write access. An attempt to write to Page[X] with PageEn[X]=0 will cause the PGEN_ERR bit to be set in the Status Register. This register has a hardware write protection feature. To write to this register, the MANWREN bit must be set in the Control 2 Register. This register is automatically loaded at reset with data stored in the EEPROM memory (page 0, byte address 0x31) 1 – Page[X] is writable 0 – Page[X] is read-only CRC FUNCTIONS FOR DATA INTEGRITY For data integrity checks, the bq2028 provides a CRC-8 computation block with the polynomial function of (X8+X5+X4+ 1). The following Python code indicates the parallel computation method where the 8-bit variable ‘c’ is the new data for calculating the CRC and the 8-bit variable ‘prev’ is the previous result if calculating the CRC on multiple data items. To start a new sequence, the ‘prev’ variable is initialized with the value 0xFF. Note: The initialization value of 0xFF is new in spec version 1.5. Previous versions used an initialization value of 0x00. spacer c ^= prev for I in range(8): if (c & 0x80): c = ((c << 1 & 0xff)) ^ 0x31 else: c = (c << 1) & 0xff return c Refer to the table below for example data sequences and the expected CRC: EXAMPLE DATA SEQUENCE (Byte order left to right) CRC 0x00 0xAC 0xAA 0x8B 0xFF 0x00 0x00 0xAA 0xA6 0xAA 0x55 0x1B 0xFF 0x01 0x55 0x7F 0x00 0x01 0x55 0xAA 0xF1 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links :bq2028 17 bq2028 SLUSB22B – OCTOBER 2012 – REVISED NOVEMBER 2012 www.ti.com The CRC-8 function is typically used for verification of EEPROM data integrity via the BUFFER. To prevent EEPROM memory corruption, BUFFER data will not be written to EEPROM without passing a CRC verification check. Refer to the Figure 10 flow-char for the HDQ Access Method related to CRC computation and verification. The additional complexity of this CRC-8 computation method is provided to minimize HDQ overhead traffic when performing data integrity checks on variable length data elements. The CRC-8 function is initiated on every HDQ data transfer with the result of the previous CRC-8 stored in the CRCH register. The CRCH register is typically used for single HDQ data packet integrity checks. Since the HDQ protocol shifts data with the LSB arriving first, the CRC is computed in this order: A0:A6, R/W, D0-D7. Note: This is the opposite bit ordering from the BUFFER CRC-8 computations. Memory Access HDQ host pseudo-code examples 8-bit EEPROM Write (Example is <Byte1>): Crc8 = FnCRC8(Byte1) // Pre-Compute CRC-8 for 8-bit data WRITE ’1RRRR01’, Byte1 // Pre-fetch EEPROM ROW ‘RRRR’, Poke Buffer[1], Set MEM_WR WRITE ’0100001’, Crc8 // Poke Crc8 to CRCT trigger MEM write and re-check READ ’0000100’, Status // Peek Status Register. IF (Status && 0x03) THEN CALL bq2028_Error // B0 = CRCB_ERR, B1 = MEM_ERR spacer 8-bit EEPROM Read (Example is <Byte2>): READ ’1RRRR10’, Byte2 // Fetch ROW ‘RRRR’ to BUFFER, Peek Buffer[2], Clear MEM_WR Crc8 = FnCRC8(Byte2) // Compute CRC-8 on 1 byte read WRITE ’0100001’, Crc8 // Poke Crc8 to CRCT trigger MEM write and re-check READ ’0000100’, Status // Peek Status Register. IF (Status && 0x03) THEN CALL bq2028_Error // B0 = CRCB_ERR, B1 = MEM_ERR spacer 16-bit EEPROM Write (Lower 2-Bytes) Crc8 = FnCRC8(Byte0, Byte1) // Pre-Compute CRC-8 for 16-bit data WRITE ’1RRRR00’, Byte0 // Pre-fetch EEPROM ROW ‘RRRR’, Poke Buffer[0], Set MEM_WR WRITE ’0000001’, Byte1 // Poke Buffer[1] WRITE ’0100001’, Crc8 // Poke Crc8 to CRCT trigger MEM write and re-check READ ’0000100’, Status // Peek Status Register. IF (Status && 0x03) THEN CALL bq2028_Error // B0 = CRCB_ERR, B1 = MEM_ERR spacer 16-bit EEPROM Read (Lower 2-Bytes) READ ’1RRRR00’, Byte0 // Fetch ROW ‘RRRR’ to BUFFER, Peek Buffer[0], Clear MEM_WR READ ’0000001’, Byte1 // Peek Buffer[1] Crc8 = FnCRC8(Byte0, Byte1) // Compute CRC-8 on 2 bytes read WRITE ’0100001’, Crc8 // Poke Crc8 to CRCT trigger MEM write and re-check READ ’0000100’, Status // Peek Status Register. IF (Status && 0x03) THEN CALL bq2028_Error // B0 = CRCB_ERR, B1 = MEM_ERR 18 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links :bq2028 bq2028 www.ti.com SLUSB22B – OCTOBER 2012 – REVISED NOVEMBER 2012 24-bit EEPROM Write (Lower 3-Bytes) Crc8 = FnCRC8(Byte0, Byte2, Byte3) // Pre-Compute CRC-8 for 24-bit data WRITE ’1RRRR00’, Byte0 // Pre-fetch EEPROM ROW ‘RRRR’, Poke Buffer[0], Set MEM_WR WRITE ’0000001’, Byte1 // Poke Buffer[1] WRITE ’0000010’, Byte2 // Poke Buffer[2] WRITE ’0100001’, Crc8 // Poke Crc8 to CRCT trigger MEM write and re-check READ ’0000100’, Status // Peek Status Register. IF (Status && 0x03) THEN CALL bq2028_Error // B0 = CRCB_ERR, B1 = MEM_ERR spacer 24-bit EEPROM Read (Lower 3-Bytes) READ ’1RRRR00’, Byte0 // Fetch ROW ‘RRRR’ to BUFFER, Peek Buffer[0], Clear MEM_WR READ ’0000001’, Byte1 // Peek Buffer[1] READ ’0000010’, Byte2 // Peek Buffer[2] Crc8 = FnCRC8(Byte0, Byte2, Byte3) // Compute CRC-8 on 3 bytes read WRITE ’0100001’, Crc8 // Poke Crc8 to CRCT trigger MEM write and re-check READ ’0000100’, Status // Peek Status Register. IF (Status && 0x03) THEN CALL bq2028_Error // B0 = CRCB_ERR, B1 = MEM_ERR spacer 32-bit EEPROM Write (Full 4-Bytes) Crc8 = FnCRC8(Byte0, Byte1, Byte2, Byte3) // Pre-Compute CRC-8 for 32-bit data WRITE ’1RRRR00’, Byte0 // Pre-fetch EEPROM ROW ‘RRRR’, Poke Buffer[0], Set MEM_WR WRITE ’0000001’, Byte1 // Poke Buffer[1] WRITE ’0000010’, Byte2 // Poke Buffer[2] WRITE ’0000011’, Byte3 // Poke Buffer[3] WRITE ’0100001’, Crc8 // Poke Crc8 to CRCT trigger MEM write and re-check READ ’0000100’, Status // Peek Status Register. IF (Status && 0x03) THEN CALL bq2028_Error // B0 = CRCB_ERR, B1 = MEM_ERR spacer 32-bit EEPROM Read (Full 4-Bytes) READ ’1RRRR00’, Byte0 // Fetch ROW ‘RRRR’ to BUFFER, Peek Buffer[0], Clear MEM_WR READ ’0000001’, Byte1 // Peek Buffer[1] READ ’0000010’, Byte2 // Peek Buffer[2] READ ’0000011’, Byte3 // Peek Buffer[3] Crc8 = FnCRC8(Byte0, Byte1, Byte2, Byte3) // Compute CRC-8 on 3 bytes read WRITE ’0100001’, Crc8 // Poke Crc8 to CRCT trigger MEM write and re-check READ ’0000100’, Status // Peek Status Register. IF (Status && 0x03) THEN CALL bq2028_Error // B0 = CRCB_ERR, B1 = MEM_ERR Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links :bq2028 19 bq2028 SLUSB22B – OCTOBER 2012 – REVISED NOVEMBER 2012 www.ti.com INTERNAL TEMPERATURE SENSOR An internal die temperature sensor is available on the bq2028 to reduce the cost, power, and size of the external components necessary to measure temperature. Temperature sensing uses the VBE method to present a voltage to a delta-sigma ADC converter. The host reads the ADC data over the HDQ interface and uses firmware to convert the data to Kelvin temperature units. ADC data is formatted to 16-bits even though the data conversion performance may be limited to 10 effective bits. An ADC conversion starts when the Control:CONV bit is set to ‘1’ and is automatically cleared at the end of the data conversion cycle . At the start of data conversion, the device sets the Status:BUSY flag and automatically clears the Status:ADC_DRDY flag to indicate data conversion is in progress. When data conversion is complete, both the CONV bit and BUSY flag are cleared and the ADC_DRDY flag is set. To abort an ADC conversion in process, the host can clear the CONV bit to ‘0’. The data in the ADC Data Registers is stored in 2s complement format. Full scale (7FFFh) is referred to the reference voltage (Vref), typically 1.225 V. A hardware protection circuit will not allow the converter to rollover from a full scale value (7FFFh) to a min scale value (8000h). CLOCK GENERATOR CIRCUITS The clock generator circuits are used to generate the internal clocks for the bq2028. The primary internal clocks are derived from the low frequency oscillator (32.768kHz), and the high frequency oscillator (8.389 MHz). The analog oscillator circuits are trimmed for accuracy, and then divided down for use throughout the device in both the analog and digital circuits. The bq2028 makes extensive use of clock gating to dynamically shutdown clocks to modules and interfaces not in use for low power operation. The low frequency oscillator (LFO) is required to run continuously during operation of the device with exception to a shutdown condition. The high frequency oscillator (HFO) is dynamically enabled and disabled as needed. Low Frequency Oscillator Operation The 32.768 kHz low frequency oscillator clock is generated from a fully integrated oscillator circuit with no requirements for external components. This circuit is trimmed for accuracy during factory production. The LFO trim value is stored in EEPROM memory Page 0. The LFO trim value is automatically read from EEPROM and written to the LFO trim register shortly after the device comes out of reset. The LFO output is divided down for various interfaces and modules in the device, as shown in Table 3. Table 3. LFO Clocked Interfaces INTERFACE OR MODULE REQUIRED WHEN: Frequency DIVIDE HFO Trim Circuit HFO is enabled 32.768 kHz LFO Reset Timer Power up of device (4ms) 32.768 kHz LFO HDQ low timeout HDQ line is pulled low for 2sec 128 Hz LFO/256 High Frequency Oscillator Operation The 8.389 MHz high frequency oscillator clock is generated from a fully integrated oscillator circuit with no requirements for external components. The bq2028 trims the 8.389MHz high frequency clock output internally by using an automatic high frequency trim circuit. Using the more accurate 32.768kHz clock as a reference, the high frequency clock is adjusted until it is determined to be within the desired operating frequency. The trim circuit continues to monitor and adjust the 8.389MHz clock as needed. Due to the nature of the trim algorithm, some small changes may be noticed in the 8.389MHz clock as it is adjusted based upon operating conditions and the 32.768kHz reference clock. The HFO output is divided down for various modules in the device. Table 4. HFO Clocked Interfaces INTERFACE OR MODULE REQUIRED WHEN: FREQUENCY DIVIDE HFO Trim Circuit HFO is enabled 8.389 MHz HFO HDQ Communication HDQ interface is enabled 1.049 MHz HFO/8 HDQ Register Access Writing or reading unmapped HDQ registers 1.049 MHz HFO/8 EEPROM Access Reading or programming EEPROM memory 1.049 MHz HFO/8 ADC ADC conversion enabled 65.536 kHz HFO/128 20 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links :bq2028 bq2028 www.ti.com SLUSB22B – OCTOBER 2012 – REVISED NOVEMBER 2012 REVISION HISTORY Changes from Original (October 2012) to Revision A Page • Changed from "Typ." to "Typical" in Features bullet ............................................................................................................. 1 • Deleted footnote "Assured by design. Not production tested" from DC Electrical Characteristics table. ............................. 4 • Deleted footnote "Assured by design. Not production tested" from AC Electrical Characteristics table. ............................. 5 Changes from Revision A (October 2012) to Revision B • Page Added Note 1 to ICC Supply Current ..................................................................................................................................... 4 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links :bq2028 21 PACKAGE OPTION ADDENDUM www.ti.com 24-Jan-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Qty Drawing Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) BQ2028YZGR ACTIVE DSBGA YZG 12 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 BQ2028 BQ2028YZGT ACTIVE DSBGA YZG 12 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 BQ2028 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Only one of markings shown within the brackets will appear on the physical device. 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Addendum-Page 1 Samples PACKAGE MATERIALS INFORMATION www.ti.com 4-Mar-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) BQ2028YZGR DSBGA YZG 12 3000 180.0 8.4 BQ2028YZGT DSBGA YZG 12 250 180.0 8.4 Pack Materials-Page 1 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 1.59 2.45 0.69 4.0 8.0 Q1 1.59 2.45 0.69 4.0 8.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 4-Mar-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) BQ2028YZGR DSBGA YZG 12 3000 210.0 185.0 35.0 BQ2028YZGT DSBGA YZG 12 250 210.0 185.0 35.0 Pack Materials-Page 2 X: Max = 2.4 mm, Min = 2.3 mm Y: Max = 1.54 mm, Min = 1.44 mm IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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