TI1 DS90UB913ATRTVTQ1 25-mhz to 100-mhz 10/12-bit fpd-link iii serializer Datasheet

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DS90UB913A-Q1
SNLS443C – MAY 2013 – REVISED APRIL 2016
DS90UB913A-Q1 25-MHz to 100-MHz 10/12-Bit FPD-Link III Serializer
1 Features
3 Description
•
The DS90UB913A-Q1 device offers an FPD-Link III
interface with a high-speed forward channel and a
bidirectional control channel for data transmission
over a single coaxial cable or differential pair. The
DS90UB913A-Q1 device incorporates differential
signaling on both the high-speed forward channel and
bidirectional control channel data paths. The
serializer/deserializer pair is targeted for connections
between imagers and video processors in an ECU
(Electronic Control Unit). This device is ideally suited
for driving video data requiring up to 12-bit pixel
depth plus two synchronization signals along with
bidirectional control channel bus.
1
•
•
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications AEC-Q100
– Device Temperature Grade 2: -40℃ to +105℃
Ambient Operating Temperature Range
– Device HBM ESD Classification Level ±8kV
– Device CDM ESD Classification Level C6
25-MHz to 100-MHz Input Pixel Clock Support
Programmable Data Payload:
– 10-bit Payload up to 100 MHz
– 12-bit Payload up to 75 MHz
Continuous Low Latency Bidirectional Control
Interface Channel with I2C Support @400 kHz
Embedded Clock with DC-Balanced Coding to
Support AC-Coupled Interconnects
Capable of Driving up to 15m Coaxial or 20m
Shielded Twisted-pair Cables
Robust Power-Over-Coaxial (PoC) Operation
4 Dedicated General Purpose Input/Output
1.8-V, 2.8-V or 3.3-V-Compatible Parallel Inputs
on Serializer
Single Power Supply at 1.8 V
ISO 10605 and IEC 61000-4-2 ESD Compliant
Small Serializer Footprint (5 mm x 5 mm)
•
•
Device Information(1)
PART NUMBER
2 Applications
•
Using TI’s embedded clock technology allows
transparent full-duplex communication over a single
differential pair, carrying asymmetrical-bidirectional
control channel information. This single serial stream
simplifies transferring a wide data bus over PCB
traces and cable by eliminating the skew problems
between parallel data and clock paths. This
significantly saves system cost by narrowing data
paths that in turn reduce PCB layers, cable width,
and connector size and pins. Internal DC-balanced
encoding/decoding is used to support AC-coupled
interconnects.
DS90UB913A-Q1
Automotive
– Surround View Systems (SVS)
– Rear and Front View Cameras
– Driver Monitor Cameras (DMS)
– Remote Satellite RADAR Sensors
Security and Surveillance
Industrial Machine Vision
PACKAGE
WQFN (32)
BODY SIZE (NOM)
5.00 mm x 5.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Schematic
Parallel
Data In
10 or 12
Parallel
Data Out
10 or 12
FPD-Link III
2
Megapixel
Imager/Sensor
HSYNC,
VSYNC
4
2
DS90UB913AQ1
GPO
2
Bidirectional
Control Bus
Serializer
Bidirectional
Control Channel
DS90UB914AQ1
HSYNC,
VSYNC
4
DSP, FPGA/
µ-Processor/
ECU
GPIO
2
Deserializer
Bidirectional
Control Bus
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DS90UB913A-Q1
SNLS443C – MAY 2013 – REVISED APRIL 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
4
4
6
7.1
7.2
7.3
7.4
7.5
7.6
7.7
Absolute Maximum Ratings ...................................... 6
ESD Ratings.............................................................. 6
Recommended Operating Conditions....................... 6
Thermal Information .................................................. 7
Electrical Characteristics........................................... 7
Recommended Serializer Timing For PCLK .......... 10
AC Timing Specifications (SCL, SDA) - I2CCompatible ............................................................... 11
7.8 Bidirectional Control Bus DC Timing Specifications
(SCL, SDA) - I2C-Compatible ................................. 11
7.9 Serializer Switching Characteristics........................ 14
7.10 Typical Characteristics .......................................... 15
8
Detailed Description ............................................ 16
8.2
8.3
8.4
8.5
8.6
9
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Programming ..........................................................
Register Maps .........................................................
16
17
20
25
29
Application and Implementation ........................ 35
9.1 Application Information............................................ 35
9.2 Typical Applications ................................................ 37
10 Power Supply Recommendations ..................... 41
11 Layout................................................................... 42
11.1 Layout Guidelines ................................................. 42
11.2 Layout Example .................................................... 43
12 Device and Documentation Support ................. 45
12.1
12.2
12.3
12.4
12.5
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
45
45
45
45
45
13 Mechanical, Packaging, and Orderable
Information ........................................................... 45
8.1 Overview ................................................................. 16
4 Revision History
Changes from Revision B (December 2014) to Revision C
Page
•
Split document into two separate documents for parts DS90UB913A-Q1 and DS90UB914A-Q1. ...................................... 1
•
Modified Automotive Features ............................................................................................................................................... 1
•
Updated pin description for DIN to include active/inactive outputs corresponding to MODE setting..................................... 4
•
Added pin description to GPO pins to leave open if unused. ................................................................................................ 5
•
Changed Air Discharge ESD Rating (IEC61000-4-2: RD = 330 Ω, CS = 150 pF) to minimum ±25000 V. .......................... 6
•
Added RTV text to Thermal Information table ........................................................................................................................ 7
•
Added GPO[3:0] typical pin capacitances. ............................................................................................................................ 7
•
Changed Differential Output Voltage minimum specification. ............................................................................................... 8
•
Changed Single-Ended Output Voltage minimum specification............................................................................................. 8
•
Added Back Channel Differential Input Voltage minimum specification................................................................................. 8
•
Added Back Channel Single-Ended Input Voltage minimum specification. ........................................................................... 8
•
Updated IDDT for VDD_n=1.89V, VDDIO=3.6V, RL=100Ω, Random Pattern with f=100 MHz, 10-bit mode to typical
value of 65 mA; value is currently 54 mA............................................................................................................................... 9
•
Updated IDDT for VDD_n=1.89V, VDDIO=3.6V, RL=100Ω, Random Pattern with f=75 MHz, 12-bit high freq mode to
typical value of 64 mA; value is currently 54 mA.................................................................................................................... 9
•
Updated IDDT for VDD_n=1.89V, VDDIO=3.6V, RL=100Ω, Random Pattern with f=50 MHz, 12-bit low freq mode to
typical value of 63 mA; value is currently 54 mA. ................................................................................................................. 9
•
Updated frequency ranges for MODE settings and also revised with correct maximum clock periods. Added footnote
and nominal clock period to be in terms of 'T'. (5) .................................................................................................................. 10
•
Deleted Revised jitter freq. test conditions to be > f/20 and also updated typical values for tjit0and tjit2. ............................. 10
•
Updated VOL Output Low Level row with revised IOL currents and max VOL voltages, dependent upon VDDIO voltage. ...... 11
•
Updated Figure 2 title to state ‘“Worst-Case” Test Pattern for Power Consumption’. ......................................................... 12
•
Added footnote that states the following: “UI – Unit Interval is equivalent to one serialized data bit width. The UI
scales with PCLK frequency.” Add below calculations to footnote. 12-bit LF mode 1 UI = 1 / ( PCLK_Freq. x 28 ) 12bit HF mode 1 UI = 1 / ( PCLK_Freq. x 2/3 x 28 ) 10-bit mode 1 UI = 1 / ( PCLK_Freq. /2 x 28 ) ..................................... 14
2
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SNLS443C – MAY 2013 – REVISED APRIL 2016
Revision History (continued)
•
Updated frequency requirements for 10-bit and 12-bit HF modes. 10-bit mode – 50 MHz to 100 MHz; 12-bit HF
mode – 37.5 MHz to 75 MHz; 12-bit LF mode (no change) – 25 MHz to 50 MHz. ............................................................ 16
•
Updated register 0x01[1] default value to be “0”. ................................................................................................................. 29
•
Changed GPO0 Enable for 0x0D[4] to GPO1 Enable.......................................................................................................... 31
•
Added Inject Forward Channel Error Register 0x2D. ........................................................................................................... 34
•
Updated power up sequencing information and timing diagram. ........................................................................................ 35
•
Added description specifying that the voltage applied on VDDIO (1.8V, 3.3V) or VDD_n (1.8V) should be at the input
pin – any board level DC drop should be compensated. .................................................................................................... 41
•
Added 913A EVM layout example image. ........................................................................................................................... 44
Changes from Revision A (June 2013) to Revision B
Page
•
Added datasheet flow and layout to conform with new TI standards. Added the following sections: Device
Comparison Table; Handling Ratings; Application and Implementation; Power Supply Recommendations; Layout;
Device and Documentation Support; Mechanical, Packaging, and Ordering Information .................................................... 1
•
Added additional thermal characteristics................................................................................................................................ 7
•
Changed typo in Vout test condition from RL=500Ω to RL=50Ω. .......................................................................................... 8
•
Changed Figure 6 to use VODp-p and to clarify difference between STP and Coax .............................................................. 12
•
Added Internal Oscillator section to Device Functional Modes ............................................................................................ 22
•
Added reference to Power over Coax Application report ..................................................................................................... 35
•
Added power up sequencing information and timing diagram. ............................................................................................ 35
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DS90UB913A-Q1
SNLS443C – MAY 2013 – REVISED APRIL 2016
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5 Device Comparison Table
PART NUMBER
FPD-III FUNCTION
PACKAGE
TRANSMISSION MEDIA
PCLK FREQUENCY
DS90UB913Q-Q1
Serializer
WQFN RTV (32)
STP
10 to 100 MHz
DS90UB913A-Q1
Serializer
WQFN RTV (32)
Coax or STP
25 to 100 MHz
6 Pin Configuration and Functions
DIN[1]
20
16
GPO[1]
DIN[6]
26
15
GPO[0]
DIN[7]
27
14
VDDCML
VDDD
28
13
DOUT+
DIN[8]
12
DOUT-
DIN[9]
11
VDDT
10
VDDPLL
9
17
29
18
30
19
GPO[2]/
CLKOUT
DIN[2]
21
GPO[3]/
CLKIN
DIN[3]
22
DIN[0]
DIN[4]
23
25
24
31
VDDIO
DIN[5]
32-Pin WQFN
Package RTV
Top View
PDB
2
3
4
5
6
7
VSYNC
PCLK
SCL
SDA
ID[x]
RES
8
MODE
1
HSYNC
DIN[11]
DS90UB913A-Q1
Serializer
32
DIN[10]
DAP = GND
Pin Functions: DS90UB913A-Q1 Serializer
PIN
NAME
I/O
NO.
DESCRIPTION
LVCMOS PARALLEL INTERFACE
19,20,21,22,
23,24,26,27,
29,30,31,32
Inputs,
LVCMOS
w/ pulldown
Parallel Data Inputs. For 10-bit MODE, parallel inputs DIN[0:9] are active. DIN[10:11] are
inactive and should not be used. Any unused inputs (including DIN[10:11]) should be No
Connect. For 12-bit MODE (HF or LF), parallel inputs DIN[0:11] are active. Any unused
inputs should be No Connect.
1
Input,
LVCMOS
w/ pulldown
Horizontal SYNC Input. Note: HS transition restrictions: 1. 12-bit Low-Frequency mode: No
HS restrictions (raw) 2. 12-bit High-Frequency mode: No HS restrictions (raw) 3. 10-bit
mode: HS restricted to no more than one transition per 10 PCLK cycles. Leave open if
unused.
VSYNC
2
Input,
LVCMOS
w/ pulldown
Vertical SYNC Input. Note: VS transition restrictions: 1. 12-bit Low-Frequency mode: No VS
restrictions (raw) 2. 12-bit High-Frequency mode: No VS restrictions (raw) 3. 10-bit HighFrequency mode: VS restricted to no more than one transition per 10 PCLK cycles. Leave
open if unused.
PCLK
3
Input,
LVCMOS
w/ pulldown
Pixel Clock Input Pin. Strobe edge set by TRFB control register.
DIN[0:11]
HSYNC
4
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SNLS443C – MAY 2013 – REVISED APRIL 2016
Pin Functions: DS90UB913A-Q1 Serializer (continued)
PIN
NAME
I/O
NO.
DESCRIPTION
GENERAL PURPOSE OUTPUT (GPO)
GPO[1:0]
GPO[2]/
CLKOUT
GPO[3]/
CLKIN
16,15
Output,
LVCMOS
General-purpose output pins can be configured as outputs; used to control and respond to
various commands. GPO[1:0] can be configured to be the outputs for input signals coming
from GPIO[1:0] pins on the Deserializer or can be configured to be outputs of the local
register on the Serializer. Leave open if unused.
17
Output,
LVCMOS
GPO[2] pin can be configured to be the output for input signal coming from the GPIO[2] pin
on the Deserializer or can be configured to be the output of the local register on the
Serializer. It can also be configured to be the output clock pin when the DS90UB913A-Q1
device is used in the External Oscillator mode. See Device Functional Modes section for a
detailed description of External Oscillator Mode. Leave open if unused.
18
GPO[3] can be configured to be the output for input signals coming from the GPIO[3] pin on
the Deserializer or can be configured to be the output of the local register setting on the
Input/Output,
Serializer. It can also be configured to be the input clock pin when the DS90UB913A-Q1
LVCMOS
Serializer is working with an external oscillator. See Device Functional Modes section for a
detailed description of External Oscillator Mode. Leave open if unused.
BIDIRECTIONAL CONTROL BUS - I2C-COMPATIBLE
SCL
4
Input/Output, Clock line for the bidirectional control bus communication.
Open Drain SCL requires an external pullup resistor to VDDIO.
SDA
5
Input/Output, Data line for the bidirectional control bus communication.
Open Drain SDA requires an external pullup resistor to VDDIO.
MODE
8
Input,
LVCMOS
w/ pulldown
ID[x]
6
Device ID Address Select.
Input, analog The ID[x] pin on the Serializer is used to assign the I2C device address. Resistor (RID) to
Ground and 10-kΩ pullup to 1.8-V rail. See Table 5.
Device mode select.
Resistor (Rmode) to Ground and 10-kΩ pullup to 1.8-V rail. MODE pin on the Serializer can
be used to select whether the system is running off the PCLK from the imager or an external
oscillator. See details in Table 1.
CONTROL AND CONFIGURATION
PDB
9
Input,
LVCMOS
w/ pulldown
RES
7
Input,
LVCMOS
w/ pulldown
Power down Mode Input Pin.
PDB = H, Serializer is enabled and is ON.
PDB = L, Serializer is in Power Down mode. When the Serializer is in Power Down, the PLL
is shutdown, and IDD is minimized. Programmed control register data is NOT retained and
reset to default values.
Reserved.
This pin MUST be tied LOW.
FPD–Link III INTERFACE
DOUT+
DOUT-
13
Input/Output, Non-inverting differential output, bidirectional control channel input. The interconnect must be
CML
AC Coupled with a 0.1-µF capacitor.
12
Inverting differential output, bidirectional control channel input. The interconnect must be AC
Input/Output, Coupled with a 0.1-µF capacitor. For applications using single-ended coaxial interconnect, a
CML
0.047-µF AC coupling capacitor should be placed in series with a 50Ω resistor before
terminating to GND.
POWER AND GROUND (1)
VDDPLL
10
Power,
Analog
PLL Power, 1.8 V ±5%.
VDDT
11
Power,
Analog
Tx Analog Power, 1.8V ±5%.
VDDCML
14
Power,
Analog
CML & Bidirectional Channel Driver Power, 1.8 V ±5%.
VDDD
28
Power,
Digital
Digital Power, 1.8 V ±5%.
VDDIO
25
Power,
Digital
Power for I/O stage. The single-ended inputs and SDA, SCL are powered from VDDIO. VDDIO
can be connected to a 1.8V ±5% or 2.8V ±10% or 3.3V ±10%.
DAP
Ground, DAP
VSS
(1)
DAP must be grounded. DAP is the large metal contact at the bottom side, located at the
center of the WQFN package. Connected to the ground plane (GND) with at least 9 vias.
See Power-Up Requirements and PDB Pin.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
Supply Voltage – VDD_n (1.8 V)
−0.3
2.5
V
Supply Voltage – VDDIO
−0.3
4.0
V
LVCMOS Input Voltage
−0.3
VDDIO + 0.3
V
CML Driver I/O Voltage (VDD)
-0.3
VDD + 0.3
V
150
°C
150
°C
Junction Temperature
−65
Storage temperature range, Tstg
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
Human body model (HBM), per AEC Q100-002 (1)
V(ESD)
Electrostatic
discharge
Charged device model (CDM), per AEC
Q100-011
ESD Rating (IEC 61000-4-2)
RD = 330 Ω, Cs = 150pF
ESD Rating (ISO10605)
RD = 330 Ω, Cs = 150/330 pF
RD = 2 KΩ, Cs = 150/330 pF
(1)
UNIT
±8000
Corner pins (1, 8, 9, 16,
17, 24, 25, 32)
±1000
V
Other pins
Air Discharge
(DOUT+, DOUT-, RIN+, RIN-)
±25000
Contact Discharge
(DOUT+, DOUT-, RIN+, RIN-)
±7000
Air Discharge
(DOUT+, DOUT-, RIN+, RIN-)
±15000
Contact Discharge
(DOUT+, DOUT-, RIN+, RIN-)
±8000
V
AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
Supply Voltage (VDD_n)
1.71
1.8
1.89
V
LVCMOS Supply Voltage (VDDIO= 1.8V) OR
1.71
1.8
1.89
LVCMOS Supply Voltage (VDDIO= 3.3V) OR
3.0
3.3
3.6
LVCMOS Supply Voltage (VDDIO= 2.8V)
2.52
2.8
3.08
Supply Noise
(1)
VDD_n (1.8 V)
25
VDDIO (1.8 V)
25
VDDIO (3.3 V)
50
Operating Free Air Temperature (TA)
–40
PCLK Clock Frequency
25
(1)
6
25
V
mVp-p
105
°C
100
MHz
Supply noise testing was done with minimum capacitors (as shown on Figure 35, Figure 31 on the PCB. A sinusoidal signal is AC
coupled to the VDD_n (1.8 V) supply with amplitude = 25 mVp-p measured at the device VDD_n pins. Bit error rate testing of input to the
Ser and output of the Des with 10-meter cable shows no error when the noise frequency on the Ser is less than 1 MHz. The Des on the
other hand shows no error when the noise frequency is less than 750 kHz.
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7.4 Thermal Information
DS90UB913A-Q1
THERMAL METRIC (1)
RTV (WQFN)
UNIT
32 PINS
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
8.8
RθJB
Junction-to-board thermal resistance
23.4
ψJT
Junction-to-top characterization parameter
0.3
ψJB
Junction-to-board characterization parameter
8.8
RθJC(bot)
Junction-to-case (bottom) thermal resistance
3.4
(1)
34.9
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
7.5 Electrical Characteristics (1) (2) (3)
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LVCMOS DC SPECIFICATIONS 3.3V I/O (SER INPUTS, GPIO, CONTROL INPUTS AND OUTPUTS)
VIH
High Level Input Voltage
VIN = 3 V to 3.6 V
2
VIL
Low Level Input Voltage
VIN = 3 V to 3.6 V
GND
IIN
Input Current
VIN = 0 V or 3.6 V, VIN = 3 V to 3.6 V
VOH
High Level Output Voltage VDDIO = 3 V to 3.6 V, IOH = −4 mA
VOL
Low Level Output Voltage
IOS
Output Short Circuit
Current
VOUT = 0 V
Serializer
GPO Outputs
IOZ
TRI-STATE Output
Current
PDB = 0 V,
VOUT = 0 V or VDD
Serializer
GPO Outputs
CGPO
Pin Capacitance
GPO [3:0]
V
0.8
V
20
µA
2.4
VDDIO
V
GND
0.4
V
–20
VDDIO = 3 V to 3.6 V, IOL = 4 mA
VIN
±1
–15
–20
mA
20
1.5
µA
pF
LVCMOS DC SPECIFICATIONS 1.8V I/O (SER INPUTS, GPIO, CONTROL INPUTS AND OUTPUTS)
VIH
High Level Input Voltage
VIN = 1.71 V to 1.89 V
0.65 VIN
VIN
VIL
Low Level Input Voltage
VIN = 1.71 V to 1.89 V
GND
0.35 VIN
IIN
Input Current
VIN = 0 V or 1.89 V, VIN = 1.71 V to 1.89 V
VOH
High Level Output Voltage VDDIO = 1.71 V to 1.89 V, IOH = −4 mA
VOL
Low Level Output Voltage
IOS
Output Short Circuit
Current
VOUT = 0 V
Serializer
GPO Outputs
IOZ
TRI-STATE Output
Current
PDB = 0 V,
VOUT = 0 V or VDD
Serializer
GPO Outputs
CGPO
Pin Capacitance
GPO [3:0]
(1)
(2)
(3)
–20
20
µA
VDDIO - 0.45
VDDIO
V
GND
0.45
V
VDDIO = 1.71 V to 1.89 V IOL = 4 mA
±1
V
–11
-20
mA
20
1.5
µA
pF
The Electrical Characteristics tables list verified specifications under the listed Recommended Operating Conditions except as otherwise
modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not
verified.
Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD and ΔVOD which are differential voltages.
Typical values represent most likely parametric norms at 1.8 V or 3.3 V, TA = 25°C, and at the Recommended Operation Conditions at
the time of product characterization and are not verified.
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Electrical Characteristics(1)(2)(3) (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LVCMOS DC SPECIFICATIONS 2.8V I/O (SER INPUTS, GPIO, CONTROL INPUTS AND OUTPUTS)
VIH
High Level Input Voltage
VIN = 2.52 V to 3.08 V
0.7 VIN
VIN
VIL
Low Level Input Voltage
VIN = 2.52 V to 3.08 V
GND
0.3 VIN
IIN
Input Current
VIN = 0 V or 3.08 V, VIN = 2.52 V to 3.08 V
VOH
High Level Output Voltage VDDIO = 2.52 V to 3.08 V, IOH = −4 mA
VOL
Low Level Output Voltage
IOS
Output Short Circuit
Current
VOUT = 0 V
Serializer
GPO Outputs
IOZ
TRI-STATE Output
Current
PDB = 0 V,
VOUT = 0 V or VDD
Serializer
GPO Outputs
CGPO
Pin Capacitance
GPO [3:0]
VDDIO =2.52 V to 3.08V IOL = 4 mA
–20
±1
V
20
µA
VDDIO - 0.4
VDDIO
V
GND
0.4
V
–11
–20
mA
20
1.5
µA
pF
CML DRIVER DC SPECIFICATIONS (DOUT+, DOUT-)
VOD
Differential Output Voltage RL = 100 Ω (Figure 6), Back Channel Disabled
640
824
VOUT
Single-Ended Output
Voltage
RL = 50 Ω (Figure 6), Back Channel Disabled
320
412
ΔVOD
Differential Output
Voltage Unbalance
RL = 100 Ω
VOS
Output Offset Voltage
RL = 100 Ω (Figure 6)
ΔVOS
Offset Voltage Unbalance
RL = 100 Ω
IOS
Output Short Circuit
Current
DOUT+ = 0 V or DOUT– = 0 V
Differential Internal
Termination Resistance
Differential across DOUT+ and DOUT–
80
100
120
Single-ended
Termination Resistance
DOUT+ or DOUT–
40
50
60
RT
1
50
mV
50
mV
VDD - VOD/2
1
mV
V
–26
mA
Ω
VID-BC
Back Channel Differential
Input Voltage
260
mV
VIN-BC
Back Channel SingleEnded Input Voltage
130
mV
8
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Electrical Characteristics(1)(2)(3) (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
VDD_n = 1.89 V
VDDIO = 3.6 V
f = 100 MHz, 10-bit
mode
Default Registers
61
80
VDD_n = 1.89 V
VDDIO = 3.6 V
f = 75 MHz, 12-bit
high frequency mode
Default Registers
61
80
VDD_n = 1.89 V
VDDIO = 3.6 V
f = 50 MHz, 12-bit
low frequency mode
Default Registers
61
VDD_n = 1.89 V
VDDIO = 3.6 V
f = 100 MHz, 10-bit
mode
Default Registers
65
VDD_n = 1.89 V
VDDIO = 3.6 V
f = 75 MHz, 12-bit
high frequency mode
Default Registers
64
VDD_n = 1.89 V
VDDIO = 3.6 V
f = 50 MHz, 12-bit
low frequency mode
Default Registers
63
VDDIO = 1.89 V
f = 75 MHz, 12-bit
high frequency mode
Default Registers
1.5
UNIT
SERIALIZER SUPPLY CURRENT
IDDT
IDDT
IDDIOT
IDDTZ
IDDIOTZ
Serializer (Tx)
VDD_n Supply Current
(includes load current)
Serializer (Tx)
VDD_n Supply Current
(includes load current)
Serializer (Tx)
VDDIO Supply Current
(includes load current)
RL = 100 Ω
WORST CASE pattern
(Figure 2)
RL = 100 Ω
RANDOM PRBS-7
pattern
RL = 100 Ω
WORST CASE pattern
(Figure 2)
Serializer (Tx) Supply
Current Power Down
PDB = 0V; All other
LVCMOS Inputs = 0 V
Serializer (Tx) VDDIO
Supply Current Power
Down
PDB = 0V; All other
LVCMOS Inputs = 0 V
VDDIO = 3.6 V
f = 75 MHz, 12-bit
high frequency
mode Default
Registers
mA
mA
80
mA
3
mA
5
8
VDDIO=1.89 V
Default Registers
300
1000
µA
VDDIO = 3.6 V
Default Registers
300
1000
µA
VDDIO = 1.89 V
Default Registers
15
100
µA
VDDIO = 3.6 V
Default Registers
15
100
µA
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7.6 Recommended Serializer Timing For PCLK (1)
(2)
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
TEST CONDITIONS
PIN / FREQ
10-bit mode
50 MHz – 100 MHz
tTCP
Transmit Clock Period
12-bit high frequency mode
37.5 MHz - 75MHz
12-bit low frequency mode
25 MHz - 50MHz
MIN
NOM
MAX
UNIT
10
T
20
ns
13.33
T
26.67
ns
20
T
40
ns
tTCIH
Transmit Clock
Input High Time
0.4T
0.5T
0.6T
ns
tTCIL
Transmit Clock
Input Low Time
0.4T
0.5T
0.6T
ns
0.05T
0.25T
0.3T
ns
0.05T
0.25T
0.3T
ns
0.05T
0.25T
0.3T
ns
10-bit mode
50 MHz – 100 MHz
tCLKT
PCLK Input Transition Time 12-bit high frequency mode
(Figure 7)
37.5 MHz - 75MHz
12-bit low frequency mode
25 MHz - 50MHz
tJIT0
PCLK Input Jitter
(PCLK from imager mode)
Refer to Jitter freq > f/20
f = 25 – 100
MHz
0.01T
ns
tJIT1
PCLK Input Jitter
(External Oscillator mode)
Refer to Jitter freq > f/20
f = 25 – 100
MHz
1T
ns
tJIT2
External Oscillator Jitter
Refer to Jitter freq > f/20
0.01T
ns
(1)
(2)
10
Recommended Input Timing Requirements are input specifications and not tested in production.
T is the period of the PCLK.
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7.7 AC Timing Specifications (SCL, SDA) - I2C-Compatible
Over recommended supply and temperature ranges unless otherwise specified. (Figure 1)
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
Standard Mode
100
kHz
Fast Mode
400
kHz
RECOMMENDED INPUT TIMING REQUIREMENTS
fSCL
SCL Clock Frequency
tLOW
SCL Low Period
Standard Mode
4.7
µs
Fast Mode
1.3
µs
Standard Mode
4.0
µs
Fast Mode
0.6
µs
tHIGH
SCL High Period
tHD:STA
Hold time for a start or a repeated start
condition
Standard Mode
4.0
µs
Fast Mode
0.6
µs
Set Up time for a start or a repeated
start condition
Standard Mode
4.7
µs
Fast Mode
0.6
tSU:STA
tHD:DAT
tSU:DAT
Data Hold Time
Data Set Up Time
tSU:STO
Set Up Time for STOP Condition
tBUF
Bus Free time between Stop and Start
tr
0
3.45
µs
Fast Mode
0
900
ns
Standard Mode
250
ns
Fast Mode
100
ns
Standard Mode
4.0
µs
Fast Mode
0.6
µs
Standard Mode
4.7
µs
Fast Mode
1.3
µs
Standard Mode
SCL & SDA Rise Time
tf
µs
Standard Mode
SCL & SDA Fall Time
1000
ns
Fast Mode
300
ns
Standard Mode
300
ns
Fast Mode
300
ns
Bidirectional Control Bus DC Timing Specifications (SCL, SDA) - I2C-Compatible (1)
7.8
Over recommended supply and temperature ranges unless otherwise specified
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
VDDIO
V
RECOMMENDED INPUT TIMING REQUIREMENTS
VIH
Input High Level
SDA and SCL
0.7*VDDIO
VIL
Input Low Level
SDA and SCL
GND
VHY
Input Hysteresis
VOL
Output Low Level (2)
IIN
Input Current
tR
SDA Rise Time-READ
tF
SDA Fall Time-READ
0.3*VDDIO
>50
SDA, VDDIO = 1.8V, IOL= 0.9 mA
0
0.36
SDA, VDDIO = 3.3V, IOL= 1.6 mA
0
0.4
SDA or SCL, VIN= VDDIO OR GND
−10
V
mV
10
V
µA
SDA, RPU = 10 kΩ, Cb ≤ 400 pF
(Figure 1)
430
ns
20
ns
tSU;DAT
(See Figure 1)
560
ns
tHD;DAT
(See Figure 1)
615
ns
CIN
SDA or SCL
<5
pF
(1)
(2)
Specification is verified by design.
FPD-Link device was designed primarily for point-to-point operation and a small number of attached slave devices. As such the
Minimum IOL pullup current is targeted to lower value than the minimum IOL in the I2C specification.
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SDA
tf
tHD;STA
tLOW
tBUF
tr
tf
tr
SCL
tSU;STA
tHD;STA
tHIGH
tSU;STO
tSU;DAT
tHD;DAT
START
STOP
REPEATED
START
START
Figure 1. Bi-directional Control Bus Timing
Signal Pattern
Device Pin Name
80%
Vdiff
T
80%
20%
PCLK
(RFB = H)
Vdiff = 0V
20%
tLHT
tHLT
Vdiff = (DOUT+) - (DOUT-)
DIN/ROUT
Figure 2. “Worst Case” Test Pattern for Power
Consumption
DOUT+
Figure 3. Serializer CML Output Load and
Transition Times
100 nF
50:
ZDiff = 100:
SCOPE
BW 8 4.0 GHz
100:
50:
DOUT-
100 nF
10/12,
HS,VS
DIN
PARALLEL-TO-SERIAL
Figure 4. Serializer CML Output Load and Transition Times
DOUT+
RL
DOUT-
PCLK
Figure 5. Serializer VOD Setup
Single-Ended
| VOS
V
DOUT+ or DOUT-
V
OUT
OUT
Differential
V
OD
0V
(DOUT+) - (DOUT-)
Figure 6. Serializer VOD Diagram
12
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80%
VDD
80%
tTCP
PCLK
20%
20%
tCLKT
PCLK
0V
VDDIO/2
tCLKT
tDIS
VDDIO/2
VDDIO/2
tDIH
VDDIO
DINn VDDIO/2
Setup
Hold
VDDIO/2
0V
Figure 7. Serializer Input Clock Transition Times
PDB
Figure 8. Serializer Setup/Hold Times
VDDIO/2
PCLK
tPLD
Output Active
TRI-STATE
DOUT±
TRI-STATE
SYMBOL N+2
SYMBOL N+3
| |
SYMBOL N+1
| |
SYMBOL N
| |
DIN
| |
Figure 9. Serializer PLL Lock Time
tSD
SYMBOL N-3
SYMBOL N-2
SYMBOL N-1
| |
| |
| |
SYMBOL N
0V
| |
SYMBOL N-4
| |
|
|
|
DOUT+-
|
PCLK
VDDIO/2
Figure 10. Serializer Delay
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7.9 Serializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
tLHT
CML Low-to-High
Transition Time
RL = 100 Ω (Figure 3)
150
330
ps
tHLT
CML High-to-Low
Transition Time
RL = 100 Ω (Figure 3)
150
330
ps
tDIS
Data Input
Setup to PCLK
tDIH
Data Input
Hold from PCLK
tPLD
Serializer PLL Lock
Time (1) (2)
tSD
Serializer Delay
(2)
2
ns
2
ns
Serializer Data Inputs (Figure 8)
RL = 100 Ω (Figure 9)
1
2
ms
RT = 100 Ω, 10–bit mode
Register 0x03h b[0] (TRFB = 1) (Figure 10)
32.5T
38T
44T
ns
RT = 100 Ω, 12–bit mode
Register 0x03h b[0] (TRFB = 1) (Figure 10)
11.75T
13T
15T
ns
tJIND
Serializer Output
Deterministic Jitter
(3) (4) (5)
Serializer output intrinsic deterministic jitter.
Measured (cycle-cycle) with PRBS-7 test pattern
0.13
UI
tJINR
Serializer Output
Random Jitter (3) (4) (5)
Serializer output intrinsic random jitter
(cycle-cycle). Alternating-1,0 pattern.
0.04
UI
tJINT
Peak-to-peak Serializer
Output Jitter (3) (4) (5)
Serializer output peak-to-peak jitter includes
deterministic jitter, random jitter, and jitter transfer
from serializer input. Measured (cycle-cycle) with
PRBS-7 test pattern.
0.396
UI
λSTXBW
δSTX
δSTXf
(1)
(2)
(3)
(4)
(5)
14
Serializer Jitter
Transfer Function
-3 dB Bandwidth
Serializer Jitter
Transfer Function
(Peaking)
Serializer Jitter
Transfer Function
(Peaking Frequency)
10–bit mode
PCLK = 100 MHz. Default Registers
2.20
12–bit high frequency mode
PCLK = 75 MHz. Default Registers
2.20
12–bit low frequency mode
PCLK = 50 MHz. Default Registers
2.20
10–bit mode
PCLK = 100 MHz. Default Registers
1.06
12–bit high frequency mode
PCLK = 75 MHz. Default Registers
1.09
12–bit low frequency mode
PCLK = 50 MHz. Default Registers
1.16
10–bit mode
PCLK = 100 MHz. Default Registers
400
12–bit high frequency mode
PCLK = 75 MHz. Default Registers
500
12–bit low frequency mode
PCLK = 50 MHz. Default Registers
600
MHz
dB
kHz
tPLD and tDDLT are the times required by the serializer and deserializer to obtain lock when exiting power-down state with an active PCLK
Specification is verified by design.
Typical values represent most likely parametric norms at 1.8 V or 3.3 V, TA = 25°C, and at the Recommended Operation Conditions at
the time of product characterization and are not verified.
Specification is verified by characterization and is not tested in production.
UI – Unit Interval is equivalent to one ideal serialized data bit width. The UI scales with PCLK frequency.
10-bit mode: 1 UI = 1 / ( PCLK_Freq. /2 x 28 )
12-bit HF mode: 1 UI = 1 / ( PCLK_Freq. x 2/3 x 28 )
12-bit LF mode: 1 UI = 1 / ( PCLK_Freq. x 28 )
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7.10 Typical Characteristics
4
2
JITTER TRANSFER (dB)
0
-2
-4
-6
-8
- 10
- 12
- 14
- 16
- 18
1.0E+04
1.0E+05
1.0E+06
1.0E+07
MODULATION FREQUENCY ( Hz)
Figure 11. Typical Serializer Jitter Transfer Function
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8 Detailed Description
8.1 Overview
The DS90UB913A-Q1 is optimized to interface with the DS90UB914A-Q1 using a 50-Ω coax interface. The
DS90UB913A-Q1 will also work with the DS90UB914A-Q1 using an STP interface.
The DS90UB913A/914A FPD- Link III chipsets are intended to link mega-pixel camera imagers and video
processors in ECUs. The Serializer/Deserializer chipset can operate from 25 MHz to 100 MHz pixel clock
frequency. The DS90UB913A-Q1 device transforms a 10/12-bit wide parallel LVCMOS data bus along with a
bidirectional control channel control bus into a single high-speed differential pair. The high speed serial bit stream
contains an embedded clock and DC-balanced information which enhances signal quality to support AC
coupling. The DS90UB914A-Q1 device receives the single serial data stream and converts it back into a 10/12bit wide parallel data bus together with the control channel data bus. The DS90UB913A/914A chipsets can
accept up to:
• 12-bits of DATA + 2 bits SYNC for an input PCLK range of 25 MHz to 50 MHz in the 12-bit low frequency
mode. Note: No HS/VS restrictions (raw).
• 12-bits of DATA + 2 SYNC bits for an input PCLK range of 37.5 MHz to 75 MHz in the 12-bit high frequency
mode. Note: No HS/VS restrictions (raw).
• 10-bits of DATA + 2 SYNC bits for an input PCLK range of 50 MHz to 100 MHz in the 10-bit mode. Note:
HS/VS restricted to no more than one transition per 10 PCLK cycles.
The DS90UB913A/914A chipset offer customers the choice to work with different clocking schemes. The
DS90UB913A/914A chipsets can use an external oscillator as the reference clock source for the PLL (see
section DS90UB913A/914A Operation with External Oscillator as Reference Clock) or PCLK from the imager as
primary reference clock to the PLL (see section DS90UB913A/914A Operation with Pixel Clock from Imager as
Reference Clock).
8.2 Functional Block Diagram
RIN0+ RT
RT
GPO[3:0]
PCLK
PLL
RIN0-
2:1
DOUT-
Output Latch
DOUT+
Decoder
RT
Deserializer
RT
Adaptive Eq.
Serializer
4
Encoder
DIN
HSYNC
VSYNC
Input Latch
10 or
12
10
or
12
ROUT
HSYNC
VSYNC
4
GPIO[3:0]
RIN1+
Clock
Gen
PCLK
LOCK
Clock
Gen
CDR
PASS
RIN1-
Encoder
MODE
DS90UB913AQ - SERIALIZER
16
Encoder
ID[x]
MODE
SEL
Decoder
SCL
FIFO
SDA
I2C Controller
OEN
I2C
Controller
Timing and
Control
PDB
BISTEN
FIFO
Timing and
Control
Decoder
PDB
SDA
SCL
IDx[0]
IDx[1]
DS90UB914AQ - DESERIALIZER
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8.3 Feature Description
8.3.1 Serial Frame Format
The High Speed Forward Channel is composed of 28 bits of data containing video data, sync signals, I2C and
parity bits. This data payload is optimized for signal transmission over an AC-coupled link. Data is randomized,
balanced and scrambled. The 28-bit frame structure changes in the 12-bit low frequency mode, 12-bit high
frequency mode and the 10-bit mode internally and is seamless to the customer. The bidirectional control
channel data is transferred over the single serial link along with the high-speed forward data. This architecture
provides a full duplex low speed forward and backward path across the serial link together with a high speed
forward channel without the dependence on the video blanking phase.
8.3.2 Line Rate Calculations for the DS90UB913A/914A
The DS90UB913A-Q1 device divides the clock internally by divide-by-1 in the 12-bit low frequency mode, by
divide-by-2 in the 10-bit mode and by divide-by-1.5 in the 12-bit high frequency mode. Conversely, the
DS90UB914A-Q1 multiplies the recovered serial clock to generate the proper pixel clock output frequency. Thus
the maximum line rate in the three different modes remains 1.4 Gbps. The following are the formulae used to
calculate the maximum line rate in the different modes:
• For the 12-bit low frequency mode, Line rate = fPCLK*28; for example, fPCLK = 50 MHz, line rate = 50*28 = 1.4
Gbps
• For the 12-bit high frequency mode, Line rate = fPCLK*(2/3)*28; for example, fPCLK = 75 MHz, line rate =
(75)*(2/3)*28 = 1.4 Gbps
• For the 10-bit mode, Line rate = fPCLK/2*28; for example, fPCLK = 100 MHz, line rate = (100/2)*28 = 1.4 Gbps
8.3.3 Error Detection
The chipset provides error detection operations for validating data integrity in long distance transmission and
reception. The data error detection function offers users flexibility and usability of performing bit-by-bit data
transmission error checking. The error detection operating modes support data validation of the following signals:
• Bidirectional control channel data across the serial link
• Parallel video/sync data across the serial link
The chipset provides 1 parity bit on the forward channel and 4 cyclic redundancy check (CRC) bits on the back
channel for error detection purposes. The DS90UB913A/914A chipset checks the forward and back channel
serial links for errors and stores the number of detected errors in two 8-bit registers in the Serializer and the
Deserializer respectively.
To check parity errors on the forward channel, monitor registers 0x1A and 0x1B on the DS90UB914A. If there is
a loss of LOCK, then the counters on registers 0x1A and 0x1B are reset. Whenever there is a parity error on
the forward channel, the PASS pin will go low.
To check CRC errors on the back-channel, monitor registers 0x0A and 0x0B on the Serializer.
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Feature Description (continued)
8.3.4 Synchronizing Multiple Cameras
For applications requiring multiple cameras for frame-synchronization, it is recommended to utilize the General
Purpose Input/Output (GPIO) pins to transmit control signals to synchronize multiple cameras together. To
synchronize the cameras properly, the system controller needs to provide a field sync output (such as a vertical
or frame sync signal) and the cameras must be set to accept an auxiliary sync input. The vertical synchronize
signal corresponds to the start and end of a frame and the start and end of a field. Note this form of
synchronization timing relationship has a non-deterministic latency. After the control data is reconstructed from
the bidirectional control channel, there will be a time variation of the GPIO signals arriving at the different target
devices (between the parallel links). The maximum latency delta (t1) of the GPIO data transmitted across
multiple links is 25 µs.
NOTE
The user must verify that the timing variations between the different links are within their
system and timing specifications.
See Figure 12 for an example of this function.
The maximum time (t1) between the rising edge of GPIO (that is, sync signal) to the time the signal arrives at
Camera A and Camera B is 25 µs.
Serializer A
Camera A
CMOS
Image
Sensor
Deserializer A
DATA
PCLK
DATA
PCLK
I2C
FSYNC
FSO
GPIO
GPO
FSIN
FSYNC
I2C
ECU
Module
Camera B
CMOS
Image
Sensor
Serializer B
Deserializer B
DATA
PCLK
DATA
PCLK
I2C
FSYNC
FSO
GPIO
GPO
FSIN
FSYNC
C
I2C
Figure 12. Synchronizing Multiple Cameras
DES A
GPIO[n] Input
SER B
GPIO[n] Output
|
SER A
GPIO[n] Output
|
DES B
GPIO[n] Input
t1
Figure 13. GPIO Delta Latency
18
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Feature Description (continued)
8.3.5 General Purpose I/O (GPIO) Descriptions
There are 4 GPOs on the Serializer and 4 GPIOs on the Deserializer when the DS90UB913A/914A chipsets are
run off the pixel clock from the imager as the reference clock source. The GPOs on the Serializer can be
configured as outputs for the input signals that are fed into the Deserializer GPIOs. In addition, the GPOs on the
Serializer can behave as outputs of the local register on the Serializer. The GPIOs on the Deserializer can be
configured to be the input signals feeding the GPOs (configured as outputs) on the Serializer. In addition the
GPIOs on the Deserializer can be configured to behave as outputs of the local register on the Deserializer. The
DS90UB913A Serializer GPOs cannot be configured as inputs for remote communication with Deserializer. If the
DS90UB913A/914A chipsets are run off the external oscillator source as the reference clock, then GPO3 on the
Serializer is automatically configured to be the input for the external clock and GPO2 is configured to be the
output of the divide-by-2 clock which is fed into the imager as its reference clock. In this case, the GPIO2 and
GPIO3 on the Deserializer can only behave as outputs of the local register on the Deserializer. The GPIO
maximum switching rate is up to 66 kHz when configured for communication between Deserializer GPIO to
Serializer GPO.
8.3.6 LVCMOS VDDIO Option
1.8-V/2.8-V/3.3-V Serializer inputs are user configurable to provide compatibility with 1.8-V, 2.8-V and 3.3-V
system interfaces.
8.3.7 Pixel Clock Edge Select (TRFB / RRFB)
The TRFB/RRFB selects which edge of the Pixel Clock is used. For the SER, this register determines the edge
that the data is latched on. If TRFB register is 1, data is latched on the Rising edge of the PCLK. If TRFB register
is 0, data is latched on the Falling edge of the PCLK. For the DES, this register determines the edge that the
data is strobed on. If RRFB register is 1, data is strobed on the Rising edge of the PCLK. If RRFB register is 0,
data is strobed on the falling edge of the PCLK.
PCLK
DIN/
ROUT
TRFB/RRFB: 0
TRFB/RRFB: 1
Figure 14. Programmable PCLK Strobe Select
8.3.8 Power Down
The SER has a PDB input pin to ENABLE or power down the device. Enabling PDB on the SER will disable the
link to save power. If PDB = HIGH, the SER will operate at its internal default oscillator frequency when the input
PCLK stops. When the PCLK starts again, the SER locks to the valid input PCLK and transmit the data to the
DES. When PDB = LOW, the high-speed driver outputs are static HIGH. Please refer to Power-Up Requirements
and PDB Pin for power-up requirements.
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8.4 Device Functional Modes
8.4.1 DS90UB913A/914A Operation with External Oscillator as Reference Clock
In some applications, the pixel clock that comes from the imager can have jitter which exceeds the tolerance of
the DS90UB913A/914A chipsets. In this case, the DS90UB913A-Q1 device should be operated by using an
external clock source as the reference clock for the DS90UB913A/914A chipsets. This is the recommended
operating mode. The external oscillator clock output goes through a divide-by-2 circuit in the DS90UB913A-Q1
Serializer and this divided clock output is used as the reference clock for the imager. The output data and pixel
clock from the imager are then fed into the DS90UB913A-Q1 device. Figure 15 shows the operation of the
DS90UB13A/914A chipsets while using an external automotive grade oscillator.
Serializer
Deserializer
FPD Link IIIHigh Speed
Camera Data
DOUT+
10 or 12
Image
Sensor
DATA
HSYNC
DIN[11:0] or
DIN[9:0]
HSYNC,
VSYNC
DOUT-
VSYNC
Pixel Clock
Camera Data
RIN+
RIN-
Bi-Directional
Control Channel
PCLK
10 or 12
ROUT[11:0]
or
ROUT[9:0]
HSYNC,
VSYNC
PCLK
DATA
HSYNC
VSYNC
Pixel Clock
ECU Module
SDA
SDA
SCL
2
SCL
PLL
GPO[1:0]
GPIO[3:0]
SDA
Camera Unit
SCL
Reference Clock
(Ext. OSC/2)
4
GPO[3:0]
GPO[1:0]
Microcontroller
SDA
SCL
GPO3
÷2
GPO2
External
Oscillator
Figure 15. DS90UB913A-Q1/914A-Q1 Operation in the External Oscillator Mode
When the DS90UB913A-Q1 device is operated using an external oscillator, the GPO3 pin on the DS90UB913AQ1 is the input pin for the external oscillator. In applications where the DS90UB913A-Q1 device is operated from
an external oscillator, the divide-by-2 circuit in the DS90UB913A-Q1 device feeds back the divided clock output
to the imager device through GPO2 pin. The pixel clock to external oscillator ratios needs to be fixed for the
12–bit high frequency mode and the 10–bit mode. In the 10-bit mode, the pixel clock frequency divided by
the external oscillator frequency must be 2. In the 12-bit high frequency mode, the pixel clock frequency
divided by the external oscillator frequency must be 1.5. For example, if the external oscillator frequency is
48 MHz in the 10–bit mode, the pixel clock frequency of the imager needs to be twice of the external oscillator
frequency, that is, 96 MHz. If the external oscillator frequency is 48MHz in the 12-bit high frequency mode, the
pixel clock frequency of the imager needs to be 1.5 times of the external oscillator frequency, that is, 72 MHz.
When PCLK signal edge is detected, and 0x03[1] = 0, the DS90UB913A will switch from internal oscillator mode
to an external PCLK. Upon removal of PCLK input, the device will switch back into internal oscillator mode. In
external oscillator mode, GPO2 and GPO3 on the Serializer cannot act as the output of the input signal coming
from GPIO2 or GPIO3 on the Deserializer.
8.4.2 DS90UB913A/914A Operation with Pixel Clock from Imager as Reference Clock
The DS90UB913A/914A chipsets can be operated by using the pixel clock from the imager as the reference
clock. Figure 16 shows the operation of the DS90UB913A/914A chipsets using the pixel clock from the imager. If
the DS90UB913A-Q1 device is operated using the pixel clock from the imager as the reference clock, then the
imager uses an external oscillator as its reference clock. There are 4 GPIOs available in this mode (PCLK from
imager mode).
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Device Functional Modes (continued)
Serializer
Deserializer
FPD-Link III
Camera Data
Image
Sensor
Camera Data
DOUT+
10 or 12
DIN[11:0] or
DIN[9:0]
FV,LV
YUV
HSYNC
VSYNC
YUV
HSYNC
RIN0-
VSYNC
Bi-Directional
Back Channel
SCL
SCL
ROUT[11:0]
or
ROUT[9:0]
FV, LV
DOUT-
SDA
SDA
10 or 12
RIN0+
PCLK
Pixel Clock
4
GPO[3:0]
GPIO[3:0]
GPO
Pixel Clock
Camera Unit
ECU Module
RIN1+
RIN1-
PLL
4
GPIO
SDA
PCLK
SCL
Microcontroller
SDA
SCL
Ext.
Oscillator
Figure 16. DS90UB913A-Q1/914A-Q1 Operation in PCLK mode
8.4.3 MODE Pin on Serializer
The MODE pin on the Serializer can be configured to select if the DS90UB913A-Q1 device is to be operated
from the external oscillator or the PCLK from the imager. The pin must be pulled to VDD(1.8 V, not VDDIO) with a
10-kΩ resistor and a pulldown resistor RMODE) of the recommended value to set the modes shown in Figure 17.
The recommended maximum resistor tolerance is 1%.
1.8V
10k
MODE
RMODE
Serializer
Figure 17. MODE Pin Configuration on DS90UB913A-Q1
Table 1. DS90UB913A-Q1 Serializer
MODE Resistor Value
DS90UB913A-Q1 SERIALIZER MODE RESISTOR VALUE
MODE SELECT
RMODE RESISTOR VALUE (kΩ)
PCLK from imager mode
100
External Oscillator mode
4.7
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8.4.4 Internal Oscillator
When a PCLK is not applied to the DS90UB913A, the serializer will establish the FPD-III link using an internal
oscillator. During normal operation (not BIST) the frequency of the internal oscillator can be adjusted from
DS90UB913A register 0x14[2:1] according to Table 2. In BIST mode, the internal oscillator frequency should only
be adjusted from the DS90UB914A. The BIST frequency can be set by either pin strapping (Table 3) or register
(Table 4). In BIST DS90UB913A register 0x14[2:1] is automatically loaded from the DS90UB914A through the bidirectional control channel.
Table 2. Clock Sources for Forward Channel Frame on the Serializer During Normal Operation
10–BIT
MODE (MHz)
12–BIT
HIGH-FREQUENCY MODE
(MHz)
12–BIT
LOW-FREQUENCY MODE
(MHz)
00
50
37.5
25
01
100
75
50
10
50
37.5
25
11
25
-
-
DS90UB913A-Q1
Reg 0x14 [2:1]
8.4.5 Built In Self Test
An optional At-Speed Built In Self Test (BIST) feature supports the testing of the high-speed serial link and lowspeed back channel. This is useful in the prototype stage, equipment production, and in-system test and also for
system diagnostics.
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8.4.6 BIST Configuration and Status
The chipset can be programmed into BIST mode using either pins or registers on the DES only. By default, BIST
configuration is controlled through pins. BIST can be configured via registers using BIST Control register (0x24).
Pin-based configuration is defined as follows:
• BISTEN = HIGH: Enable the BIST mode, BISTEN = LOW: Disable the BIST mode.
• Deserializer GPIO0 and GPIO1: Defines the BIST clock source (PCLK vs. various frequencies of internal
OSC)
Table 3. BIST Pin Configuration
DESERIALIZER GPIO[0:1]
OSCILLATOR SOURCE
BIST FREQUENCY (MHz)
00
External PCLK
PCLK or External Oscillator
01
Internal
~50
10
Internal
~25
Table 4. BIST Register Configuration
DS90UB914A-Q1
Reg 0x24 [2:1]
10–BIT
MODE
12–BIT
HIGH-FREQUENCY MODE
12–BIT
LOW-FREQUENCY MODE
00
PCLK
PCLK
PCLK
01
100 MHz
75 MHz
50 MHz
10
50 MHz
37.5 MHz
25 MHz
11
25 MHz
-
-
BIST mode provides various options for the PCLK source. Either external pins (GPIO0 and GPIO1) or registers
can be used to program the BIST to use external PCLK or various OSC frequencies. Refer to Table 3 for pin
settings. The BIST status can be monitored real-time on the PASS pin. For every frame with error(s), the PASS
pin toggles low for one-half PCLK period. If two consecutive frames have errors, PASS will toggle twice to allow
counting of frames with errors. Once the BIST is done, the PASS pin reflects the pass/fail status of the last BIST
run only for one PCLK cycle. The status can also be read through I2C for the number of frames in errors. BIST
status register retains results until it is reset by a new BIST session or a device reset. To evaluate BIST in
external oscillator mode, both the external oscillator and PCLK need to be present. For all practical purposes, the
BIST status can be monitored from the BIST Error Count register 0x25 on the DS90UB914A Deserializer.
8.4.7 Sample BIST Sequence
Step 1. For the DS90UB913A/914A FPD-Link III chipset, BIST Mode is enabled via the BISTEN pin of
DS90UB914A-Q1 FPD-Link III deserializer. The desired clock source is selected through the deserializer GPIO0
and GPIO1 pins as shown in Table 3.
Step 2. The DS90UB913A-Q1 Serializer BIST pattern is enabled through the back channel. The BIST pattern is
sent through the FPD-Link III to the deserializer. Once the serializer and deserializer are in the BIST mode and
the deserializer acquires Lock, the PASS pin of the deserializer goes high and BIST starts checking FPD-Link III
serial stream. If an error in the payload is detected, the PASS pin will switch low for one half of the clock period.
During the BIST test, the PASS output can be monitored and counted to determine the payload error rate.
Step 3. To stop the BIST mode, the deserializer BISTEN pin is set LOW. The deserializer stops checking the
data. The final test result is not maintained on the PASS pin. To monitor the BIST status, check the BIST Error
Count register, 0x25 on the Deserializer.
Step 4. The link returns to normal operation after the deserializer BISTEN pin is low. Figure 19 shows the
waveform diagram of a typical BIST test for two cases. Case 1 is error free, and Case 2 shows one with multiple
errors. In most cases, it is difficult to generate errors due to the robustness of the link (differential data
transmission etc.), thus they may be introduced by greatly extending the cable length, faulting the interconnect,
or by reducing signal condition enhancements (Rx equalization).
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Normal
Step 1: DES in BIST
BIST
Wait
Step 2: Wait, SER in BIST
BIST
start
Step 3: DES in Normal
Mode - check PASS
BIST
stop
Step 4: DES/SER in Normal
Figure 18. AT-Speed BIST System Flow Diagram
DES Outputs
BISTEN
(DES)
LOCK
PCLK
(RFB = L)
Case 1 - Pass
ROUT[0:11],
HS, VS
DATA
(internal)
PASS
Prior Result
PASS
PASS
X
X
X
FAIL
Prior Result
Normal
Case 2 - Fail
X = bit error(s)
DATA
(internal)
BIST
Result
Held
BIST Test
BIST Duration
Normal
Figure 19. BIST Timing Diagram
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8.5 Programming
8.5.1 Programmable Controller
An integrated I2C slave controller is embedded in the DS90UB913A-Q1 Serializer. It must be used to configure
the extra features embedded within the programmable registers or it can be used to control the set of
programmable GPIOs.
8.5.2 Description of Bidirectional Control Bus and I2C Modes
The I2C-compatible interface allows programming of the DS90UB913A-Q1, DS90UB914A-Q1, or an external
remote device (such as image sensor) through the bidirectional control channel. Register programming
transactions to/from the DS90UB913A-Q1/914A-Q1 chipset are employed through the clock (SCL) and data
(SDA) lines. These two signals have open drain I/Os and both lines must be pulled-up to VDDIO by an external
resistor. Pullup resistors or current sources are required on the SCL and SDA busses to pull them high when
they are not being driven low. A logic LOW is transmitted by driving the output low. Logic HIGH is transmitted by
releasing the output and allowing it to be pulled-up externally. The appropriate pullup resistor values will depend
upon the total bus capacitance and operating speed. The DS90UB913A I2C bus data rate supports up to 400
kbps according to I2C fast mode specifications.
Bus Activity:
Master
SDA Line
S
Stop
Start
For further description of general I2C communication, please refer to application note Understanding the I2C Bus
(SLVA704). For more information on choosing appropriate pullup resistor values, please refer to application note
I2C Bus Pullup Resistor Calculation (SLVA689).
Register
Address
Slave
Address
7-bit Address
Data
P
0
A
C
K
A
C
K
A
C
K
Bus Activity:
Slave
S
Register
Address
Slave
Address
7-bit Address
S
0
A
C
K
Bus Activity:
Slave
N
A
C
K
Slave
Address
7-bit Address
A
C
K
Stop
SDA Line
Start
Bus Activity:
Master
Start
Figure 20. Write Byte
P
1
A
C
K
Data
Figure 21. Read Byte
SDA
1
2
6
MSB
LSB
R/W
Direction
Bit
Acknowledge
from the Device
7-bit Slave Address
SCL
ACK
LSB
MSB
7
8
9
N/ACK
Data Byte
*Acknowledge
or Not-ACK
1
2
8
Repeated for the Lower Data Byte
and Additional Data Transfers
START
9
STOP
Figure 22. Basic Operation
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Programming (continued)
SDA
SCL
S
P
STOP condition
START condition, or
START repeat condition
Figure 23. Start and Stop Conditions
8.5.3 I2C Pass-Through
I2C pass-through provides a way to access remote devices at the other end of the FPD-Link III interface. This
option is used to determine if an I2C instruction is transferred over to the remote I2C bus. For example, when the
I2C master is connected to the deserializer and I2C pass-through is enabled on the deserializer, any I2C traffic
targeted for the remote serializer or remote slave will be allowed to pass through the deserializer to reach those
respective devices.
See Figure 24 for an example of this function and refer to application note: I2C over DS90UB913/4 FPD-Link III
with Bidirectional Control Channel (SNLA222).
If master controller transmits I2C transaction for address 0xA0, the DES A with I2C pass-through enabled will
transfer I2C commands to remote Camera A. The DES B with I2C pass-through disabled, any I2C commands
will NOT be passed on the I2C bus to Camera B.
DS90UB913AQ
CMOS
Image
Sensor
DIN[11:0]
,HS,VS
PCLK
SDA
SCL
Camera A
Slave ID: (0xA0)
CMOS
Image
Sensor
DS90UB914AQ
ROUT[11:0],
HS,VS,
PCLK
2
I C
SER A:
Remote I2C _MASTER Proxy
DES A: I2C_SLAVE
Local
I2C_PASS_THRU Enabled
DS90UB913AQ
DS90UB914AQ
DIN[11:0]
,HS,VS
PCLK
SDA
SCL
Camera B
Slave ID: (0xA0)
SDA
SCL
2
I C
ECU
Module
ROUT[11:0],
HS,VS,
PCLK
2
I C
SER B:
Remote I2C_MASTER Proxy
2
I C
SDA
SCL
DES B: I2C_SLAVE
Local
I2C_PASS_THRU Disabled
PC
Master
Figure 24. I2C Pass-Through
8.5.4 Slave Clock Stretching
The I2C-compatible interface allows programming of the DS90UB913A-Q1, DS90UB914A-Q1, or an external
remote device (such as image sensor) through the bidirectional control. To communicate and synchronize with
remote devices on the I2C bus through the bidirectional control channel/MCU, the chipset utilizes bus clock
stretching (holding the SCL line low) during data transmission; where the I2C slave pulls the SCL line low
on the 9th clock of every I2C transfer (before the ACK signal). The slave device will not control the clock and
only stretches it until the remote peripheral has responded. The I2C master must support clock stretching to
operate with the DS90UB913A/914A chipset.
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Programming (continued)
8.5.5 ID[x] Address Decoder on the Serializer
The ID[x] pin on the Serializer is used to decode and set the physical slave address of the Serializer (I2C only) to
allow up to five devices on the bus connected to the Serializer using only a single pin. The pin sets one of the 6
possible addresses for each Serializer device. The pin must be pulled to VDD (1.8 V, not VDDIO) with a 10-kΩ
resistor and a pull-down resistor (RID) of the recommended value to set the physical device address. The
recommended maximum resistor tolerance is 1%.
1.8V
10k
VDDIO
ID[x]
RPU
RPU
RID
HOST
Serializer
SCL
SCL
SDA
SDA
To other Devices
Figure 25. ID[x] Address Decoder on the Serializer
Table 5. ID[x] Resistor Value for DS90UB913A-Q1 Serializer
ID[x] RESISTOR VALUE — DS90UB913A-Q1 SERIALIZER
Resistor RID (kΩ)
(1% Tolerance)
Address 7'b
Address 8'b 0 appended
(WRITE)
0
0x58
0xB0
2
0x59
0xB2
4.7
0x5A
0xB4
8.2
0x5B
0xB6
14
0x5C
0xB8
100
0x5D
0xBA
8.5.6 Multiple Device Addressing
Some applications require multiple camera devices with the same fixed address to be accessed on the same I2C
bus. The DS90UB913A provides slave ID matching/aliasing to generate different target slave addresses when
connecting more than two identical devices together on the same bus. This allows the slave devices to be
independently addressed. Each device connected to the bus is addressable through a unique ID by programming
of the Slave alias register on Deserializer. This will remap the Slave alias address to the target SLAVE_ID
address; up to 8 ID Alias's are supported in sensor mode when slaves are attached to the DS90UB913A
serializer. In display mode, when the external slaves are at the deserializer the DS90UB913A supports one ID
Alias. The ECU Controller must keep track of the list of I2C peripherals in order to properly address the target
device.
See Figure 26 for an example of this function.
• ECU is the I2C master and has an I2C master interface
• The I2C interfaces in DES A and DES B are both slave interfaces
• The I2C protocol is bridged from DES A to SER A and from DES B to SER B
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The I2C interfaces in SER A and SER B are both master interfaces
If master controller transmits I2C slave 0xA0, DES A (address 0xC0), with pass through enabled, will forward the
transaction to remote Camera A. If the controller transmits slave address 0xA4, the DES B 0xC2 will recognize
that 0xA4 is mapped to 0xA0 and will be transmitted to the remote Camera B. If controller sends command to
address 0xA6, the DES B (address 0xC2), with pass through enabled, will forward the transaction to slave device
0xA2.
Camera A
DS90UB913AQ
Slave ID: (0xA0)
CMOS
Image
Sensor
ROUT[11:0],
HS, VS,
PCLK
DIN[11:0]
, HS, VS,
PCLK
2
SDA
SCL
I C
PC/
SER A: ID[x](0xB0)
EEPROM
Slave ID: (0xA2)
Camera B
DS90UB913AQ
Slave ID: (0xA0)
CMOS
Image
Sensor
DS90UB914AQ
DES A: ID[x](0xC0)
SLAVE_ID0_ALIAS(0xA0)
SLAVE_ID0_ID(0xA0)
SLAVE_ID1_ALIAS(0xA2)
SLAVE_ID1_ID(0xA2)
PC/
EEPROM
Slave ID: (0xA2)
ECU
Module
DS90UB914AQ
ROUT[11:0],
HS, VS,
PCLK
DIN[11:0]
, HS, VS,
PCLK
SDA
SCL
SDA
SCL
2
I C
2
I C
SER B: ID[x](0xB2)
SDA
SCL
2
I C
DES B: ID[x](0xC2)
SLAVE_ID0_ALIAS(0xA4)
SLAVE_ID0_ID(0xA0)
SLAVE_ID1_ALIAS(0xA6)
SLAVE_ID1_ID(0xA2)
PC
Master
Figure 26. Multiple Device Addressing
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8.6 Register Maps
Table 6. DS90UB913A-Q1 Control Registers (1)
Addr
(Hex)
0x00
0x01
Name
Bits
Field
7:1
DEVICE ID
R/W
I2C Device ID
RW
(1)
Description
7-bit address of Serializer; 0x58'h.
0xB0'h
(101_1000'b) default.
(1011_0000'b
0: Device ID is from ID[x].
)
1: Register I2C Device ID overrides ID[x].
0
Serializer ID SEL
7
RSVD
6
RDS
RW
0
Digital Output Drive Strength.
1: High Drive Strength.
0: Low Drive Strength.
5
VDDIO Control
RW
1
Auto Voltage Control.
1: Enable.
0: Disable.
4
VDDIO MODE
RW
1
VDDIO Voltage set.
1: VDDIO = 3.3 V.
0: VDDIO = 1.8 V.
3
ANAPWDN
RW
0
This register can be set only through local I2C access.
1: Analog power down. Powers down the analog block
in the Serializer.
0: No effect.
2
RSVD
Reserved.
1
DIGITAL
RESET1
RW
0
1: Resets the digital block except for register values.
Does not affect device I2C Bus or Device ID. This bit
is self-clearing.
0: Normal Operation.
0
DIGITAL
RESET0
RW
0
1: Digital Reset, resets the entire digital block including
all register values. This bit is self-clearing.
0: Normal Operation.
Reserved.
Power and Reset
0x02
0x03
Default
Reserved.
General
Configuration
7
RX CRC Checker
Enable
RW
1
Back-channel CRC Checker Enable.
1: Enable.
0: Disable.
6
TX Parity
Generator Enable
RW
1
Forward channel Parity Generator Enable.
1: Enable.
0: Disable.
5
CRC Error Reset
RW
0
Clear CRC Error Counters.
This bit is NOT self-clearing.
1: Clear Counters.
0: Normal Operation.
0
Automatically Acknowledge I2C Remote Write.
The mode works when the system is LOCKed.
1: Enable: When enabled, I2C writes to the
Deserializer (or any remote I2C Slave, if I2C PASS
ALL is enabled) are immediately acknowledged
without waiting for the Deserializer to acknowledge the
write. The accesses are then remapped to address
specified in 0x06.
0: Disable.
0
1: Enable Forward Control Channel pass-through of all
I2C accesses to I2C IDs that do not match the
Serializer I2C ID. The I2C accesses are then
remapped to address specified in register 0x06.
0: Enable Forward Control Channel pass-through only
of I2C accesses to I2C IDs matching either the
remote Deserializer ID or the remote I2C IDs.
1
I2C Pass-Through Mode.
1: Pass-Through Enabled. DES Alias 0x07 and Slave
Alias 0x09.
0: Pass-Through Disabled.
4
I2C Remote Write
Auto
Acknowledge
3
I2C PassThrough All
2
I2C PassThrough
RW
RW
RW
To ensure optimum device functionality, It is recommended to NOT write to any RESERVED registers.
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Register Maps (continued)
Table 6. DS90UB913A-Q1 Control Registers(1) (continued)
Addr
(Hex)
Name
Bits
1
0x03
Field
R/W
OV_CLK2PLL
RW
RW
7
RSVD
Reserved.
6
RSVD
Reserved.
5
MODE_
OVERRIDE
RW
0
Allows overriding mode select bits coming from backchannel.
1: Overrides MODE select bits.
0: Does not override MODE select bits.
4
MODE_UP_
TO_DATE
R
0
1: Status of mode select from Deserializer is up-todate.
0: Status is NOT up-to-date.
3
Pin_MODE_
12–bit High
Frequency
R
0
1: 12-bit high frequency mode is selected.
0: 12-bit high frequency mode is not selected.
2
Pin_MODE_
10–bit mode
R
0
1: 10-bit mode is selected.
0: 10-bit mode is not selected.
Reserved.
Mode Select
DES Alias
7:1
0
SlaveID
7:1
0
30
RSVD
Reserved.
Deserializer
Device ID
RW
0x00'h
7-bit Deserializer Device ID Configures the I2C Slave
ID of the remote Deserializer. A value of 0 in this field
disables I2C access to the remote Deserializer. This
field is automatically configured by the Bidirectional
Control Channel once RX Lock has been detected.
Software may overwrite this value, but should also
assert the FREEZE DEVICE ID bit to prevent
overwriting by the Bidirectional Control Channel.
Freeze Device ID
RW
0
1: Prevents auto-loading of the Deserializer Device ID
by the bidirectional control channel. The ID will be
frozen at the value written.
0: Update.
0x00'h
7-bit Remote Deserializer Device Alias ID Configures
the decoder for detecting transactions designated for
an I2C Deserializer device. The transaction will be
remapped to the address specified in the DES ID
register.
A value of 0 in this field disables access to the remote
Deserializer.
DES ID
0
0x08
1
Pixel Clock Edge Select.
1: Parallel Interface Data is strobed on the Rising
Clock Edge.
0: Parallel Interface Data is strobed on the Falling
Clock Edge.
TRFB
7:1
0x07
0
0
1:0
0x06
Description
1:Enabled : When enabled this register overrides the
clock to PLL mode (External Oscillator mode or Direct
PCLK mode) defined through MODE pin and allows
selection through register 0x35 in the Serializer.
0: Disabled : When disabled, Clock to PLL mode
(External Oscillator mode or Direct PCLK mode) is
defined through MODE pin on the Serializer.
General
Configuration
0x04
0x05
Default
Deserializer
ALIAS ID
RW
RSVD
Reserved.
SLAVE ID
7-bit Remote Slave Device ID Configures the physical
I2C address of the remote I2C Slave device attached
to the remote Deserializer. If an I2C transaction is
addressed to the Slave Alias ID, the transaction will be
remapped to this address before passing the
transaction across the Bidirectional Control Channel to
the Deserializer and then to remote slave. A value of
0 in this field disables access to the remote I2C slave.
RSVD
RW
0x00'h
Reserved.
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Register Maps (continued)
Table 6. DS90UB913A-Q1 Control Registers(1) (continued)
Addr
(Hex)
0x09
Name
Slave Alias
Bits
7:1
0
Field
R/W
SLAVE ALIAS ID
RW
Default
Description
0x00'h
7-bit Remote Slave Device Alias ID Configures the
decoder for detecting transactions designated for an
I2C Slave device attached to the remote Deserializer.
The transaction will be remapped to the address
specified in the Slave ID register. A value of 0 in this
field disables access to the remote I2C Slave.
RSVD
Reserved.
0x0A
CRC Errors
7:0
CRC Error Byte 0
R
0x00'h
Number of back-channel CRC errors during normal
operation. Least Significant byte.
0x0B
CRC Errors
7:0
CRC Error Byte 1
R
0x00'h
Number of back-channel CRC errors during normal
operation. Most Significant byte.
7:5
Rev-ID
R
0x0'h
Revision ID.
0x0: Production Revision ID.
4
RX Lock Detect
R
0
1: RX LOCKED.
0: RX not LOCKED.
3
BIST CRC
Error Status
R
0
1: CRC errors in BIST mode.
0: No CRC errors in BIST mode.
2
PCLK Detect
R
0
1: Valid PCLK detected.
0: Valid PCLK not detected.
0
1: CRC error is detected during communication with
Deserializer.
This bit is cleared upon loss of link or assertion of
CRC ERROR RESET in register 0x04.
0: No effect.
R
0
1: Cable link detected.
0: Cable link not detected.
This includes any of the following faults:
— Cable Open.
— '+' and '-' shorted.
— Short to GND.
— Short to battery.
RW
0
Local GPIO Output Value. This value is output on the
GPIO pin when the GPIO function is enabled. The
local GPIO direction is Output, and remote GPIO
control is disabled.
1
Remote GPIO Control.
1: Enable GPIO control from remote Deserializer. The
GPIO pin needs to be an output, and the value is
received from the remote Deserializer.
0: Disable GPIO control from remote Deserializer.
0x0C
General Status
1
0x0D
GPO[0]
and GPO[1]
Configuration
DES Error
R
0
LINK Detect
7
GPO1 Output
Value
6
GPO1 Remote
Enable
5
RSVD
4
GPO1 Enable
RW
1
1: GPIO enable.
0: Tri-state.
3
GPO0 Output
Value
RW
0
Local GPIO Output Value. This value is output on the
GPIO pin when the GPIO function is enabled. The
local GPIO direction is Output, and remote GPIO
control is disabled.
2
GPO0 Remote
Enable
1
Remote GPIO Control.
1: Enable GPIO control from remote Deserializer. The
GPIO pin needs to be an output, and the value is
received from the remote Deserializer.
0: Disable GPIO control from remote Deserializer.
1
RSVD
0
GPO0 Enable
RW
Reserved.
RW
Reserved.
RW
1
1: GPIO enable.
0: Tri-state.
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Register Maps (continued)
Table 6. DS90UB913A-Q1 Control Registers(1) (continued)
Addr
(Hex)
0x0E
Name
GPO[2]
and GPO[3]
Configuration
Bits
Default
Description
0
Local GPIO Output Value. This value is output on the
GPIO pin when the GPIO function is enabled. The
local GPIO direction is Output, and remote GPIO
control is disabled.
RW
0
Remote GPIO Control.
1: Enable GPIO control from remote Deserializer. The
GPIO pin needs to be an output, and the value is
received from the remote Deserializer.
0: Disable GPIO control from remote Deserializer.
GPO3 Direction
RW
1
1: Input.
0: Output.
4
GPO3 Enable
RW
1
1: GPIO enable.
0: Tri-state.
3
GPO2 Output
Value
RW
0
Local GPIO Output Value. This value is output on the
GPIO pin when the GPIO function is enabled. The
local GPIO direction is Output, and remote GPIO
control is disabled.
2
GPO2 Remote
Enable
1
Remote GPIO Control.
1: Enable GPIO control from remote Deserializer. The
GPIO pin needs to be an output, and the value is
received from the remote Deserializer.
0: Disable GPIO control from remote Deserializer.
1
RSVD
0
GPO2 Enable
7
6
GPO3 Remote
Enable
5
4:3
2
RW
RW
Reserved.
RW
1
0
1: GPIO enable.
0: Tri-state.
RSVD
Reserved.
SDA Output
Delay
00
SDA Output Delay This field configures output delay
on the SDA output. Setting this value will increase
output delay in units of 50ns. Nominal output delay
values for SCL to SDA are:
00: ~350 ns
01: ~400 ns
10: ~450 ns
11: ~500 ns
0
Disable Remote Writes to Local Registers Setting this
bit to a 1 will prevent remote writes to local device
registers from across the control channel. This
prevents writes to the Serializer registers from an I2C
master attached to the Deserializer. Setting this bit
does not affect remote access to I2C slaves at the
Serializer.
0
Speed up I2C Bus Watchdog Timer.
1: Watchdog Timer expires after approximately 50
microseconds.
0: Watchdog Timer expires after approximately 1
second.
0
1. Disable I2C Bus Watchdog Timer When the I2C
Watchdog Timer may be used to detect when the I2C
bus is free or hung up following an invalid termination
of a transaction. If SDA is high and no signaling
occurs for approximately 1 second, the I2C bus will
assumed to be free. If SDA is low and no signaling
occurs, the device will attempt to clear the bus by
driving 9 clocks on SCL.
0: No effect.
Local Write
Disable
RW
RW
I2C Master
Config
1
32
R/W
GPO3 Output
Value
7:5
0x0F
Field
I2C Bus Timer
Speed up
I2C Bus Timer
Disable
RW
RW
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Register Maps (continued)
Table 6. DS90UB913A-Q1 Control Registers(1) (continued)
Addr
(Hex)
0x10
0x11
Name
Bits
Field
7
RSVD
R/W
Default
Reserved.
6:4
SDA Hold Time
RW
0x1'h
Internal SDA Hold Time. This field configures the
amount of internal hold time provided for the SDA
input relative to the SCL input. Units are 50 ns.
3:0
I2C Filter Depth
RW
0x7'h
I2C Glitch Filter Depth. This field configures the
maximum width of glitch pulses on the SCL and SDA
inputs that will be rejected. Units are 10 ns.
0x82'h
I2C Master SCL High Time This field configures the
high pulse width of the SCL output when the Serializer
is the Master on the local I2C bus. Units are 50 ns for
the nominal oscillator clock frequency. The default
value is set to provide a minimum (4 µs + 1 µs of rise
time for cases where rise time is very fast) SCL high
time with the internal oscillator clock running at 26
MHz rather than the nominal 20 MHz.
I2C Control
SCL High Time
Description
7:0
SCL High Time
RW
0x12
SCL LOW Time
7:0
SCL Low Time
RW
0x82'h
I2C SCL Low Time This field configures the low pulse
width of the SCL output when the Serializer is the
Master on the local I2C bus. This value is also used as
the SDA setup time by the I2C Slave for providing
data prior to releasing SCL during accesses over the
Bidirectional Control Channel. Units are 50 ns for the
nominal oscillator clock frequency. The default value is
set to provide a minimum (4.7 µs + 0.3 µs of fall time
for cases where fall time is very fast) SCL low time
with the internal oscillator clock running at 26MHz
rather than the nominal 20MHz.
0x13
General Purpose
Control
7:0
GPCR[7:0]
RW
0x00'h
1: High.
0: Low.
7:3
RSVD
Reserved.
Clock Source
Allows choosing different OSC clock frequencies for
forward channel frame.
OSC Clock Frequency in Functional Mode when OSC
mode is selected or when the selected clock source is
not present, for example, missing PCLK/ External
Oscillator. See Table 2 for oscillator clock frequencies
when PCLK/ External Clock is missing.
0x14
BIST Control
2:1
0
RW
RSVD
Reserved.
0x15 0x1D
0x1E
Reserved.
BCC Watchdog
Control
7:1
BCC Watchdog
Timer
RW
0
BCC Watchdog
Timer Disable
RW
0x1F 0x29
0x2A
0x0'h
The watchdog timer allows termination of a control
channel transaction if it fails to complete within a
0x7F'h
programmed amount of time. This field sets the
(111_1111'b)
Bidirectional Control Channel Watchdog Timeout value
in units of 2 ms. This field should not be set to 0.
0
1: Disables BCC Watchdog Timer operation.
0: Enables BCC Watchdog Timer operation.
Reserved.
CRC Errors
7:0
BIST Mode CRC
Errors Count
0x2B 0x2C
R
0x00'h
Number of CRC Errors in the back channel when in
BIST mode.
Reserved.
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Register Maps (continued)
Table 6. DS90UB913A-Q1 Control Registers(1) (continued)
Addr
(Hex)
Name
Bits
7
0x2D
Field
Force Forward
Channel Error
R/W
Default
RW
0
Inject Forward
Channel Error
6:0
Force BIST Error
RW
0x2E 0x34
34
1: Forces 1 (one) error over forward channel frame in
normal operating mode. Self clearing bit.
0: No error.
N: Forces N number of errors in BIST mode. This
register MUST be set BEFORE BIST mode is enabled.
BIST Error Count Register on the deserializer (i.e.
0x25 on 914A device) should be read AFTER BIST
mode is disabled for the correct number of errors
incurred while in BIST mode.
0: No error.
Reserved.
7:4
0x35
0x00'h
Description
PLL Clock
Overwrite
RSVD
Reserved.
3
PIN_LOCK to
External
Oscillator
Status of mode select pin.
1: Indicates External Oscillator mode is selected by
mode-resistor.
0: External Oscillator mode is not selected by moderesistor.
2
RSVD
1
LOCK to External
Oscillator
0
LOCK2OSC
RW
0
Reserved.
RW
0
RW
1
Affects only when 0x03[1]=1 (OV_CLK2PLL) and
0x35[0]=0.
1: Routes GPO3 directly to PLL.
0: Allows PLL to lock to PCLK.
Affects only when 0x03[1]=1 (OV_CLK2PLL).
1: Allows internal OSC clock to feed into PLL.
0: Allows PLL to lock to either PCLK or external clock
from GPO3.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The DS90UB913A was designed as a serializer to support automotive camera designs. Automotive cameras are
often located in remote positions such as bumpers or trunk lids, and a major component of the system cost is the
wiring. For this reason it is desirable to minimize the wiring to the camera. This chipset allows the video data,
along with a bidirectional control channel, and power to all be sent over a single coaxial cable. The chipset is
also able to transmit over STP and is pin-to-pin/backwards compatible with the DS90UB913Q.
9.1.1 Power Over Coax
See application report Sending Power over Coax in DS90UB913A Designs for more details.
9.1.2 Power-Up Requirements and PDB Pin
The PDB pin on the device must be ramped after the VDDIO and VDD_n supplies have reached their required
operating voltage levels. It is recommended to assert PDB = HIGH with an RC filter network to help ensure
proper sequencing of the PDB pin after settling of the power supplies. Please refer to Power Down for device
operation when powered down.
Common applications will tie the VDDIO and VDD_n supplies to the same power source of 1.8V typically. This is an
acceptable method for ramping the VDDIO and VDD_n supplies. The main constraint here is that the VDD_n supply
does not lead in ramping before the VDDIO system supply. This is noted in Figure 27 with the requirement of t1≥ 0.
t0
1.8 V or 3.3 V
VDDIO
GND
t2
1.8V
VDD_n
GND
t1
VDDIO
PDB
GND
Figure 27. Suggested Power-Up Sequencing
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Application Information (continued)
Table 7. Power-Up Sequencing Constraints for DS90UB913A-Q1
Symbol
36
Description
Test Conditions
Min
t0
VDDIO Rise Time
VIL to VIH on rising edge; Monotonic
signal ramp is required
0.05
t1
VDDIO to VDD_n Delay
VIL of rising edge (VDDIO) to VIL of rising
edge (VDD_n)
0
t2
VDD_n Rise Time
VPDB < VIL_VDDIO; VIL to VIH on rising
edge; Monotonic signal ramp is required
0.05
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Typ
Max
Units
1.5
ms
ms
1.5
ms
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9.1.3 AC Coupling
The SER/DES supports only AC-coupled interconnects through an integrated DC-balanced decoding scheme.
External AC-coupling capacitors must be placed in series in the FPD-Link III signal path as illustrated in
Figure 28. For applications utilizing single-ended 50-Ω coaxial cable, the unused data pin (DOUT–, RIN–) should
utilize a 0.047-µF capacitor and should be terminated with a 50-Ω resistor.
DOUT+
RIN+
DOUT-
RIN-
SER
DES
Figure 28. AC-Coupled Connection (STP)
DOUT+
RIN+
DOUT-
RIN-
SER
DES
50Q
50Q
Figure 29. AC-Coupled Connection (Coaxial)
For high-speed FPD–Link III transmissions, the smallest available package should be used for the AC coupling
capacitor. This will help minimize degradation of signal quality due to package parasitics. The I/O’s require a 0.1µF AC coupling capacitors to the line.
9.1.4 Transmission Media
The DS90UB913A/914A chipset is intended to be used in a point-to-point configuration through a shielded
coaxial cable. The Serializer and Deserializer provide internal termination to minimize impedance discontinuities.
The interconnect (cable and connectors) should have a differential impedance of 100 Ω, or a single-ended
impedance of 50 Ω. The maximum length of cable that can be used is dependent on the quality of the cable
(gauge, impedance), connector, board(discontinuities, power plane), the electrical environment (for example,
power stability, ground noise, input clock jitter, PCLK frequency, etc). The resulting signal quality at the receiving
end of the transmission media may be assessed by monitoring the differential eye opening of the serial data
stream. A differential probe should be used to measure across the termination resistor at the CMLOUTP/N pins.
Please refer to Cable Requirements for the DS90UB913A & DS90UB914A or contact TI for a channel
specification regarding cable loss parameters and further details on adaptive equalizer loss compensation.
9.2 Typical Applications
9.2.1 Coax Application
DS90UB913AQ
Serializer
DS90UB914AQ
Deserializer
FPD-Link III
Camera Data
DOUT+
10 or 12
Image
Sensor
DATA
HSYNC
DIN[11:0] or
DIN[9:0]
HSYNC,
VSYNC
VSYNC
Pixel Clock
4
DOUT-
Camera Data
10 or 12
RIN+
50Q
50Q
RIN-
ROUT[11:0]
or
ROUT[9:0]
HSYNC,
VSYNC
PCLK
PCLK
Bi-Directional
Control Channel
GPO[3:0]
GPIO[3:0]
GPO[3:0]
SDA
Camera Unit
SCL
DATA
HSYNC
VSYNC
Pixel Clock
4
GPIO[3:0]
SDA
SDA
SCL
SCL
ECU Module
Microcontroller
SDA
SCL
Figure 30. Coax Application Block Diagram
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Typical Applications (continued)
9.2.1.1 Design Requirements
For the typical coax design applications, use the following as input parameters:
Table 8. Coax Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
VDDIO
1.8 V, 2.8 V, or 3.3 V
VDD_n
1.8 V
AC Coupling Capacitors for DOUT±
0.1 µF, 0.047 µF (For the unused data pin, DOUT– )
PCLK Frequency
50 MHz (12-bit low frequency), 75 MHz (12-bit high frequency), 100
MHz (10-bit)
9.2.1.2 Detailed Design Procedure
Figure 31 shows the typical connection of a DS90UB913A-Q1 Serializer using a coax interface.
DS90UB913A-Q1
VDDIO
C8
VDDIO
C3
1.8 V
VDDT
C9
C4
C13
1.8 V
DIN0
DIN1
DIN2
DIN3
DIN4
DIN5
DIN6
LVCMOS
Parallel
Bus
DIN7
DIN8
DIN9
DIN10
DIN11
HS
VS
PCLK
1.8 V
VDDPLL
C5
C14
C10
FB1
1.8 V
VDDCML
C6
C11
C15
C7
C12
FB2
1.8 V
VDDD
C1
Serial
FPD-Link III
Interface
DOUT+
DOUTC2
1.8 V
10 kQ
RTERM
MODE
10 kQ
RID
ID[X]
RID
LVCMOS
Control
Interface
PDB
GPO[0]
GPO[1]
GPO[2]
GPO[3]
GPO
Control
Interface
VDDIO
RPU
I2C
Bus
Interface
RPU
SCL
FB3
RES
SDA
FB4
C16
DAP (GND)
C17
Optional
Optional
NOTE:
C1 = 0.1 µF (50 WV)
C2 = 0.047 µF (50 WV)
C3 ± C7 = 0.01 µF
C8 - C12 = 0.1 µF
C13 - C14 = 4.7 µF
C15 = 22 µF
C16 - C17 = >100 pF
RTERM = 50 Ÿ
RPU = 1 kŸ to 4.7 kŸ
RID (see ID[x] Resistor Value Table)
FB1 - FB4: Impedance = 1 kŸ (@ 100 MHz)
low DC resistance (<1 Ÿ)
The "Optional" components shown are
provisions to provide higher system noise
immunity and will therefore result in higher
performance.
Figure 31. DS90UB913A-Q1 Typical Connection Diagram — Pin Control (Coax)
38
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100 MHz TX Pixel Clock
(1 V/DIV)
CML Data Throughput
(100 mV/DIV)
Magnitude (50 mV/DIV)
9.2.1.3 Application Curves
Time (200 ps/DIV)
Time (2.5 ns/DIV)
Figure 32. Coax Eye Diagram at 1.4-Gbps Line Rate (100MHz Pixel Clock) from Deserializer CML Loop-through
Output (CMLOUT±)
Figure 33. Coax Eye Diagram with 100-MHz TX Pixel Clock
Overlay from Deserializer CML Loop-through Output
(CMLOUT±)
9.2.2 STP Application
DS90UB913AQ
Serializer
DS90UB914AQ
Deserializer
FPD-Link III
Camera Data
DOUT+
10 or 12
Image
Sensor
DIN[11:0] or
DIN[9:0]
HSYNC,
VSYNC
DATA
HSYNC
DOUT-
VSYNC
Pixel Clock
4
Camera Data
10 or 12
RIN+
RIN-
ROUT[11:0]
or
ROUT[9:0]
HSYNC,
VSYNC
Bi-Directional
Control Channel
PCLK
PCLK
GPO[3:0]
Camera Unit
SCL
VSYNC
Pixel Clock
GPIO[3:0]
SDA
SDA
SCL
SCL
ECU Module
4
GPIO[3:0]
GPO[3:0]
SDA
DATA
HSYNC
Microcontroller
SDA
SCL
Figure 34. STP Application Block Diagram
9.2.2.1 Design Requirements
For the typical STP design applications, use the following as input parameters
Table 9. STP Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
VDDIO
1.8 V, 2.8 V, or 3.3 V
VDD_n
1.8 V
AC Coupling Capacitors for DOUT±
0.1 µF
PCLK Frequency
50 MHz (12-bit low frequency), 75 MHz (12-bit high frequency), 100
MHz (10-bit)
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9.2.2.2 Detailed Design Procedure
Figure 35 shows a typical connection of a DS90UB913A-Q1 Serializer using an STP interface.
DS90UB913A-Q1
VDDIO
VDDIO
C8
1.8 V
VDDT
C3
C4
C9
C13
1.8 V
DIN0
DIN1
DIN2
DIN3
DIN4
DIN5
DIN6
LVCMOS
Parallel
Bus
DIN7
DIN8
DIN9
DIN10
DIN11
HS
VS
PCLK
1.8 V
VDDPLL
C5
C14
C10
FB1
1.8 V
VDDCML
C6
C11
C15
C7
C12
FB2
1.8 V
VDDD
C1
Serial
FPD-Link III
Interface
DOUT+
DOUTC2
10 kQ
MODE
1.8 V
RID
10 kQ
LVCMOS
Control
Interface
ID[X]
RID
PDB
GPO[0]
GPO[1]
GPO[2]
GPO[3]
GPO
Control
Interface
VDDIO
RPU
I2C
Bus
Interface
RPU
SCL
FB3
RES
SDA
FB4
C16
DAP (GND)
C17
NOTE:
C1 - C2 = 0.1 µF (50 WV)
C3 ± C7 = 0.01 µF
C8 - C12 = 0.1 µF
C13 - C14 = 4.7 µF
C15 = 22 µF
C16 - C17 = >100 pF
RPU = 1 kQ to 4.7 kQ
RID (see ID[x] Resistor Value Table)
FB1 - FB4: Impedance = 1 kQ (@ 100 MHz)
low DC resistance (<1 Q)
The "Optional" components shown are
provisions to provide higher system noise
immunity and will therefore result in higher
performance.
Optional
Optional
Figure 35. DS90UB913A-Q1 Typical Connection Diagram — Pin Control (STP)
100 MHz TX Pixel Clock
(1 V/DIV)
CML Data Throughput
(100 mV/DIV)
Magnitude (100 mV/DIV)
9.2.2.3 Application Curves
Time (200 ps/DIV)
Time (2.5 ns/DIV)
Figure 36. STP Eye Diagram at 1.4-Gbps Line Rate (100MHz Pixel Clock) from Deserializer CML Loop-through
Output (CMLOUT±)
40
Figure 37. STP Eye Diagram with 100-MHz TX Pixel Clock
Overlay from Deserializer CML Loop-through Output
(CMLOUT±)
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10 Power Supply Recommendations
This device is designed to operate from an input core voltage supply of 1.8 V. Some devices provide separate
power and ground terminals for different portions of the circuit. This is done to isolate switching noise effects
between different sections of the circuit. Separate planes on the PCB are typically not required. Terminal
description tables typically provide guidance on which circuit blocks are connected to which power terminal pairs.
In some cases, an external filter may be used to provide clean power to sensitive circuits such as PLLs. The
voltage applied on VDDIO (1.8V, 2.8V, 3.3V) or other power supplies making up VDD_n (1.8V) should be at the
input pin - any board level DC drop should be compensated (i.e. ferrite beads in the path of the power supply
rails).
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11 Layout
11.1 Layout Guidelines
Circuit board layout and stack-up for the Ser/Des devices should be designed to provide low-noise power feed to
the device. Good layout practice will also separate high frequency or high-level inputs and outputs to minimize
unwanted stray noise pickup, feedback and interference. Power system performance may be greatly improved by
using thin dielectrics (2 to 4 mils) for power / ground sandwiches. This arrangement provides plane capacitance
for the PCB power system with low-inductance parasitics, which has proven especially effective at high
frequencies, and makes the value and placement of external bypass capacitors less critical. External bypass
capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the
range of 0.01 µF to 0.1 µF. Tantalum capacitors may be in the 2.2-µF to 10-µF range. Voltage rating of the
tantalum capacitors should be at least 5X the power supply voltage being used.
Surface mount capacitors are recommended due to their smaller parasitics. When using multiple capacitors per
supply pin, locate the smaller value closer to the pin. A large bulk capacitor is recommend at the point of power
entry. This is typically in the 50-µF to 100-µF range and will smooth low frequency switching noise. It is
recommended to connect power and ground pins directly to the power and ground planes with bypass capacitors
connected to the plane with via on both ends of the capacitor. Connecting power or ground pins to an external
bypass capacitor will increase the inductance of the path.
A small body size X7R chip capacitor, such as 0603, is recommended for external bypass. Its small body size
reduces the parasitic inductance of the capacitor. The user must pay attention to the resonance frequency of
these external bypass capacitors, usually in the range of 20 to 30 MHz. To provide effective bypassing, multiple
capacitors are often used to achieve low impedance between the supply rails over the frequency of interest. At
high frequency, it is also a common practice to use two vias from power and ground pins to the planes, reducing
the impedance at high frequency.
Some devices provide separate power for different portions of the circuit. This is done to isolate switching noise
effects between different sections of the circuit. Separate planes on the PCB are typically not required. Pin
Description tables typically provide guidance on which circuit blocks are connected to which power pin pairs. In
some cases, an external filter many be used to provide clean power to sensitive circuits such as PLLs.
Use at least a four layer board with a power and ground plane. Locate LVCMOS signals away from the
differential lines to prevent coupling from the LVCMOS lines to the differential lines. Closely-coupled differential
lines of 100 Ω are typically recommended for differential interconnect. The closely coupled lines help to ensure
that coupled noise will appear as common-mode and thus is rejected by the receivers. The tightly coupled lines
will also radiate less.
Information on the WQFN style package is provided in TI Application Note: AN-1187/SNOA401.
11.1.1
Interconnect Guidelines
See SNLA008 for full details.
• Use 100 Ω coupled differential pairs
• Use the S/2S/3S rule in spacings
– – S = space between the pair
– – 2S = space between pairs
– – 3S = space to LVCMOS signal
• Minimize the number of Vias
• Use differential connectors when operating above 500 Mbps line speed
• Maintain balance of the traces
• Minimize skew within the pair
Additional general guidance can be found in the LVDS Owner’s Manual - available in PDF format from the Texas
Instrument web site at: www.ti.com/lvds.
42
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11.2 Layout Example
Stencil parameters such as aperture area ratio and the fabrication process have a significant impact on paste
deposition. Inspection of the stencil prior to placement of the WQFN package is highly recommended to improve
board assembly yields. If the via and aperture openings are not carefully monitored, the solder may flow
unevenly through the DAP. Stencil parameters for aperture opening and via locations are shown below:
Figure 38. No Pullback WQFN, Single Row Reference Diagram
Table 10. No Pullback WQFN Stencil Aperture Summary for DS90UB913A-Q1
DEVICE
PIN
COUNT
DS90UB913A-Q1
32
MKT DWG
PCB I/O PAD
SIZE (mm)
PCB
PITCH
(mm)
PCB DAP
SIZE(mm)
STENCIL I/O
APERTURE
(mm)
STENCIL
DAP
APERTURE
(mm)
NUMBER OF
DAP
APERTURE
OPENINGS
GAP
BETWEEN
DAP
APERTURE
(Dim A mm)
RTV
0.25 x 0.6
0.5
3.1 x 3.1
0.25 x 0.7
1.4 x 1.4
4
0.2
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Figure 39. DS90UB913A-Q1 Serializer Example Layout
The following PCB layout examples are derived from the layout design of the DS90UB913A-Q1 Evaluation
Module (SNLU135). These graphics and additional layout description are used to demonstrate both proper
routing and proper solder techniques when designing in this Serializer.
44
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SNLS443C – MAY 2013 – REVISED APRIL 2016
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• DS90UB913A-CXEVM & DS90UB914A-CXEVM REV A User's Guide, SNLU135
• I2C over DS90UB913/4 FPD-Link III with Bidirectional Control Channel, SNLA222
• Sending Power Over Coax in DS90UB913A Designs, SNLA224
• Soldering Specifications Application Report, SNOA549
• IC Package Thermal Metrics Application Report, SPRA953
• Leadless Leadframe Package (LLP) Application Report, SNOA401
• LVDS Owner's Manual, SNLA187
• Cable Requirements for the DS90UB913A & DS90UB914A, SNLA229
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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45
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
DS90UB913ATRTVJQ1
ACTIVE
WQFN
RTV
32
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 105
UB913AQ
DS90UB913ATRTVRQ1
ACTIVE
WQFN
RTV
32
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 105
UB913AQ
DS90UB913ATRTVTQ1
ACTIVE
WQFN
RTV
32
250
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 105
UB913AQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2016
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Apr-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
DS90UB913ATRTVJQ1
WQFN
RTV
32
2500
330.0
12.4
5.3
5.3
1.3
8.0
12.0
Q1
DS90UB913ATRTVRQ1
WQFN
RTV
32
1000
178.0
12.4
5.3
5.3
1.3
8.0
12.0
Q1
DS90UB913ATRTVTQ1
WQFN
RTV
32
250
178.0
12.4
5.3
5.3
1.3
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Apr-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DS90UB913ATRTVJQ1
WQFN
RTV
32
2500
367.0
367.0
35.0
DS90UB913ATRTVRQ1
WQFN
RTV
32
1000
213.0
191.0
55.0
DS90UB913ATRTVTQ1
WQFN
RTV
32
250
213.0
191.0
55.0
Pack Materials-Page 2
MECHANICAL DATA
RTV0032A
SQA32A (Rev B)
www.ti.com
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