DS64MB201
DS64MB201 Dual Lane 2:1/1:2 Mux/Buffer with Equalization and De-Emphasis
Literature Number: SNLS307B
DS64MB201
Dual Lane 2:1/1:2 Mux/Buffer with Equalization and
De-Emphasis
General Description
Features
The DS64MB201 is a dual lane 2:1 multiplexer and 1:2 switch
or fan-out buffer with signal conditioning suitable for SATA/
SAS and other high-speed bus applications up to 6.4 Gbps.
The device performs both receive equalization and transmit
de-emphasis, allowing maximum flexibility of physical placement within a system. The receiver's continuous time linear
equalizer (CTLE) provides a boost of up to +33 dB at 3 GHz
and is capable of opening an input eye that is completely
closed due to inter-symbol interference (ISI) induced by the
interconnect medium. The transmitter features a programmable output de-emphasis driver and allows amplitude
voltage levels to be selected from 600 mVp-p to 1200 mVp-p
to suit multiple application scenarios. The signal conditioning
settings are programmable via control pin settings or SMBus
interface.
To enable seamless upgrade from SAS/SATA 3.0 Gbps to 6.0
Gbps data rates without compromising physical reach,
DS64MB201 automatically detects the incoming data rate
and selects the optimal de-emphasis pulse width. The device
detects the out-of-band (OOB) idle and active signals of the
SAS/SATA specification and passes through with minimum
signal distortion.
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Up to 6.4 Gbps dual lane 2:1 mux, 1:2 switch or fan-out
Adjustable receive equalization up to +33 dB gain
Adjustable transmit de-emphasis up to −12 dB
Adjustable transmit VOD
<0.25 UI of residual DJ at 6.4 Gbps with 40” FR4 trace
SATA/SAS: OOB signal pass-through
Adjustable electrical IDLE detect threshold
Low power
Signal conditioning programmable via pin selection or
SMBus interface
Single 2.5V supply operation
>6 kV HBM ESD Rating
3.3V tolerant SMBus interface
High speed signal flow–thru pinout package: 54-pin LLP
(10 mm x 5.5 mm)
Applications
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■
SATA (1.5, 3.0 and 6 Gbps)
SAS (1.5, 3.0 and 6 Gbps)
XAUI (3.125 Gbps), RXAUI (6.25 Gbps)
sRIO – Serial Rapid I/O
Fibre Channel (4.25 Gbps)
10GBase-CX4, InfiniBand (SDR & DDR)
FR-4 backplane traces
Typical Application
30076480
© 2011 National Semiconductor Corporation
300764
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DS64MB201 Dual Lane 2:1/1:2 Mux/Buffer with Equalization and De-Emphasis
March 1, 2011
DS64MB201
Pin Diagram
300764505
DS64MB201 Pin Diagram 54L LLP
Ordering Information
NSID
Qty
Spec
Package
DS64MB201SQ
Tape & Reel Supplied As 2,000 Units
NOPB
SQA54A
DS64MB201SQE
Tape & Reel Supplied As 250 Units
NOPB
SQA54A
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2
DS64MB201
Pin Descriptions
Pin Name
Pin Number
I/O, Type
Pin Description
Differential High Speed I/O's
SIA0+, SIA0-,
SIA1+, SIA1-
45, 44,
40, 39
I, CML
Inverting and non-inverting CML differential inputs to the equalizer. A gated
on-chip 50Ω termination resistor connects SIA_n+ to VDD and SIA_n- to VDD
when enabled.
SOA0+, SOA0-,
SOA1+, SOA1-
35, 34,
31, 30
O
Inverting and non-inverting low power differential signaling 50Ω outputs with
de-emphasis. Fully compatible with AC coupled CML inputs.
SIB0+, SIB0-,
SIB1+, SIB1-
43, 42,
38, 37
I, CML
Inverting and non-inverting CML differential inputs to the equalizer. A gated
on-chip 50Ω termination resistor connects SIB_n+ to VDD and SIB_n- to VDD
when enabled.
SOB0+, SOB0-,
SOB1+, SOB1-
33, 32,
29, 28
O
Inverting and non-inverting low power differential signaling 50Ω outputs with
de-emphasis. Fully compatible with AC coupled CML inputs.
DIN0+, DIN0-,
DIN1+, DIN1-
10, 11,
15, 16
I, CML
Inverting and non-inverting CML differential inputs to the equalizer. A gated
on-chip 50Ω termination resistor connects SIB_n+ to VDD and SIB_n- to VDD
when enabled.
O
Inverting and non-inverting low power differential signaling 50Ω outputs with
de-emphasis. Fully compatible with AC coupled CML inputs.
DOUT0+, DOUT0-, 3, 4,
DOUT1+, DOUT1- 7, 8
Control Pins — Shared (LVCMOS)
ENSMB
48
I, LVCMOS w/ System Management Bus (SMBus) enable pin.
internal pull- HIGH = Register Access: Provides access to internal digital registers to
down
control such functions as equalization, de-emphasis, VOD, rate, channel
powerdown, and idle detection threshold.
LOW = Pin Mode: Access to the SMBus registers are disabled and control
pins are used to program VOD, rate, idle detection, equalization and deemphasis settings.
Please refer to “SMBus configuration Registers” section and Electrical
Characteristics - Serial Management Bus Interface for detailed information.
ENSMB = 1 (SMBUS MODE)
SDA, SCL
49, 50
I, LVCMOS
ENSMB = 1
The SMBus SDA (data input/output bi-directional) and SCL (clock input) pins
are enabled.
AD[3:0]
54, 53, 47, 46 I, LVCMOS w/ ENSMB = 1
internal pull- SMBus Slave Address Inputs. In SMBus mode, these pins are the user set
down
SMBus slave address inputs.
ENSMB = 0 (NORMAL PIN MODE)
EQA,
EQB,
EQD
46,
49,
53
I, Float,
LVCMOS
EQA/B/D, 3–level input controls the level of equalization.
EQA controls the level of equalization of the SIA0 and SIA1 inputs.
EQB controls the level of equalization of the SIB0 and SIB1 inputs.
EQD controls the level of equalization of the DIN0 and DIN1 inputs.
The pins are active only when ENSMB is de-asserted (Low).
When ENSMB goes high the SMBus control registers provide independent
control of each lane. See Table 1
DEMA,
DEMB,
DEMD
47,
50,
54
I, Float,
LVCMOS
DEMA/B/D, 3–level input controls the level of de-emphasis.
DEMA controls the level of de-emphasis of the SOA0 and SOA1 outputs.
DEMB controls the level of de-emphasis of the SOB0 and SOB1 outputs.
DEMD controls the level of de-emphasis of the DOUT0 and DOUT1 outputs.
The pins are active only when ENSMB is de-asserted (Low).
When ENSMB goes High the SMBus control registers provide independent
control of each lane. See Table 2
3
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DS64MB201
Pin Name
Pin Number
I/O, Type
Pin Description
Control Pins — Both Modes (LVCMOS)
RATE
21
I, Float,
LVCMOS
RATE, 3–level input controls the pulse width of de-emphasis of the output.
RATE = 0 forces ~3 Gbps,
RATE = 1 forces ~6 Gbps,
RATE = Float enables auto rate detection. See Table 2
TXIDLEDO
24
I, Float,
LVCMOS
TXIDLEDO, 3–level input controls the driver output.
TXIDLEDO = 0 disables the signal detect/squelch function for DOUT.
TXIDLEDO = 1 forces the DOUT to be muted (electrical idle).
TXIDLEDO = Float enables the signal auto detect/squelch function for DOUT
and the signal detect voltage threshold level can be adjusted using the
SD_TH pin. See Table 3
TXIDLESO
25
I, Float,
LVCMOS
TXIDLESO, 3–level input controls the driver output.
TXIDLESO = 0 disables the signal detect/squelch function for SOUT.
TXIDLESO = 1 forces the SOUT to be muted (electrical idle).
TXIDLESO = Float enables the signal auto detect/squelch function for SOUT
and the signal detect voltage threshold level can be adjusted using the
SD_TH pin. See Table 3
FANOUT
26
I, LVCMOS w/ FANOUT = 1 enables both A/B outputs for broadcast mode.
internal pull- FANOUT = 0 disables one of the outputs depending on the SEL0, SEL1 pin.
down
See Table 5
SEL0, SEL1
19, 20
I, LVCMOS w/ SEL0 is for lane 0, SEL1 is for lane 1
internal pull- SEL0, SEL1 = 0 selects B input and B output.
down
SEL0, SEL1 = 1 selects A input and A output. See Table 5
VOD0, VOD1
22, 23
I, LVCMOS w/ VOD[1:0] adjusts the output differential amplitude voltage level on all outputs.
internal pull- 00 set output VOD = 600 mVp-p (Default)
down
01 sets output VOD = 800 mVp-p
10 sets output VOD = 1000 mVp-p
11 sets output VOD = 1200 mVp-p
Note: VOD should be set to a minimum of 1000 mV to achieve stated DE
levels.
27
I, ANALOG
Threshold select pin for electrical idle detect threshold. Float pin for default
130 mVp-p (differential).
See Table 4
VDD
9, 14, 36, 41,
51
Power
2.5V Power supply pins.
GND
DAP, 52
Power
DAP is the large metal contact at the bottom side, located at the center of the
54 pin LLP package. It should be connected to the GND plane with at least 4
via to lower the ground impedance and improve the thermal performance of
the package.
NOTE: DAP is the primary GND
NC
1, 2, 5, 6, 12,
13, 17, 18
Analog
SD_TH
Power
No Connect — Leave pin open
1 = HIGH, 0 = LOW, FLOAT = 3rd input state.
FLOAT condition; Do not drive pin; pin is internally biased to mid level with 50 kΩ pull-up/pull-down.
Internal pulled-down = Internal 30 kΩ pull-down resistor to GND is present on the input.
Input edge rate for LVCMOS/FLOAT inputs must be faster than 50 ns from 10–90%.
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4
Thermal Resistance
-0.5V to +3.0V
-0.5V to +4.0V
-0.5V to (VDD+0.5V)
-0.5V to (VDD+0.5V)
-0.5V to (VDD+0.5V)
+105°C
-40°C to +125°C
11.5°C/W
θJA, No Airflow, 4 layer JEDEC
19.1°C/W
Recommended Operating
Conditions
Supply Voltage
VDD to GND
Ambient Temperature
(Note 4)
SMBus (SDA, SCL)
CML Differential Input
Voltage
Supply Noise Tolerance
up to 50 MHz, (Note 5)
Maximum Package Power Dissipation at 25°C
SQA54A Package
4.21 W
Derate SQA54A Package
52.6mW/°C above +25°C
ESD Rating
HBM, STD - JESD22-A114C
θJC
≥6 kV
Min
Typ
Max
Units
-40
2.5
25
+85
V
°C
3.6
2.0
V
Vp-p
0
0
100
mVP-P
Electrical Characteristics
Over recommended operating supply and temperature ranges with default register settings unless other specified. (Note 3)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
850
950
mW
11
mW
3.6
V
POWER
PD
Power Dissipation
2.5V Operation
EQx = 0, DEMx = 0 dB,
K28.5 pattern,
VOD = 1.0 V p-p
Channel powerdown (Note 7)
LVCMOS / LVTTL DC SPECIFICATIONS
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
0
0.8
V
IIH
Input High Current
VIN = 3.3V
-15
+15
μA
IIL
Input Low Current
VIN = 0V
-15
+15
μA
2.0
CML RECEIVER INPUTS (IN_n+, IN_n-)
RLRX-DIFF
Rx Differential Return Loss
(SDD11),
(Note 2)
150 MHz – 1.5 GHz
-20
150 MHz – 3.0 GHz
-13.5
150 MHz – 6.0 GHz
-8
RLRX-CM
Rx Common Mode Input Return
Loss (SCC11)
150 MHz – 3.0 GHz, (Note 2)
RRX-IB
Rx Impedance Balance (SDC11)
150 MHz – 3.0 GHz, (Note 2)
IIN
Maximum current allowed at IN+
or IN- input pin.
RIN
Input Resistance
Single ended to VDD, (Note 2)
RITD
Input Differential Impedance
between
IN+ and IN-
(Note 2)
RITIB
Input Differential Impedance
Imbalance
(Note 2)
RICM
Input Common Mode Impedance (Note 2)
20
VRX-DIFF
Differential Rx peak to peak
voltage
DC voltage,
SD_TH = 20 kΩ to GND
VRX-SD_TH
Electrical Idle detect threshold
(differential)
SD_TH = Float, (Note 8), Figure 5
-10
dB
-27
dB
−30
+30
mA
Ω
50
115
Ω
5
Ω
40
Ω
0.1
1.2
V
40
175
mVp-p
85
5
dB
100
25
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DS64MB201
CDM, STD - JESD22-C101-C
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (VDD)
LVCMOS Input/Output Voltage
Differential Input Voltage
Differential Output Voltage
Analog (SD_TH)
Junction Temperature
Storage Temperature
≥250 V
≥1250 V
MM, STD - JESD22-A115-A
Absolute Maximum Ratings (Note 1)
DS64MB201
Symbol
Parameter
Conditions
Min
Typ
Max
Units
500
600
700
mVP-P
1100
1265
1450
mVP-P
DIFFERENTIAL OUTPUTS (OUT_n+, OUT_n-)
VOD
Output Differential Voltage Swing RL = 50 Ω ±1% to GND (AC coupled with 10
with de-emphasis disabled
nF), 6.4 Gbps, (Note 6)
DEMA = DEMB = 0 dB,
VOD1–0 = 00
VOD1–0 = 11
VOCM
TTX-RF
Output Common-Mode Voltage
Transmitter Rise/ Fall Time
Single-ended measurement DC-Coupled
with 50Ω termination,
(Note 2)
VDD –
1.4
20% to 80% of differential output voltage,
measured within 1” from output pins, (Note
2, Note 6), Figure 1
65
TRF-DELTA
Tx rise/fall mismatch
20% to 80% of differential output voltage,
(Note 2, Note 6)
RLTX-DIFF
Tx Differential Return Loss
(SDD22),
(Note 2)
Repeating 1100b (D24.3) pattern,
VOD = 1.0 Vp-p,
150 MHz – 1.5 GHz
-11
1.5 GHz – 3.0 GHz
-10
RLTX-CM
RTX-IB
0.1
UI
dB
-5
Repeating 1100b (D24.3) pattern,
VOD = 1.0 Vp-p, (Note 2)
50 MHz – 3.0 GHz
-10
dB
Tx Impedance Balance
(SDC22)
Repeating 1100b (D24.3) pattern,
VOD = 1.0 Vp-p, (Note 2)
50 MHz – 3.0 GHz
-30
dB
ROTD
Output Differential Impedance
between OUT+ and OUT-
(Note 2)
ROTIB
Output Differential Impedance
Imbalance
(Note 2)
ROCM
Output Common Mode
Impedance
(Note 2)
VTX-CM-DELTA
Common Mode Voltage Delta
Minimum Temperature for OOB signal passbetween active burst and electrical through is -10C.
Idle of an OOB signal
VIN = 800 mVp-p, at 3 Gbps, (Note 9)
TPD
ps
3 GHz – 6.0 GHz
Tx Output Short Circuit Current
Limit
TID
85
Tx Common Mode Return Loss
(SCC22)
ITX-SHORT
TDI
V
85
20
100
25
90
mA
125
Ω
5
Ω
35
Ω
±40
mV
Max time to transition to valid
electrical idle after leaving active
burst in OOB signaling
Minimum Temperature for OOB signal passthrough is -10C.
VIN = 800 mVp-p, at 3 Gbps, Figure 3
6.5
9.5
ns
Max time to transition to valid
active burst after leaving idle in
OOB signaling
Minimum Temperature for OOB signal passthrough is -10C.
VIN = 800 mVp-p, at 3 Gbps, Figure 3
5.5
8.0
ns
Differential Propagation Delay
(Low to High and High to Low
Edge
Propagation delay measure at midpoint
crossing between input to output
150
200
250
ps
120
170
EQx[1:0] = 11, DEMx[1:0] = —6 dBFigure 2
220
ps
TLSK
Lane to Lane Skew in a Single Part VDD = 2.5V, TA = 25C
EQz[1:0] = OFF, DEMx[1:0] = 0 dB
27
ps
TPPSK
Part to Part Propagation Delay
Skew
VDD = 2.5V, TA = 25C
35
ps
TSM
Switch/Mux Time
Time to switch/mux between A and B input/
output signals
150
ns
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Parameter
Conditions
Min
Typ
Max
Units
Residual Deterministic Jitter at 6.4 Tx Launch Amplitude = 0.8 to
Gbps
1.2 Vp–p, 40” 4–mil FR4 trace,
ENSMB = 1, EQ setting = 0x3B, DEMx[1:0] =
0dB, VOD = 1.0 Vp-p, K28.5, SD_TH = float
(Note 2)
0.12
0.25
UIP-P
Residual Deterministic Jitter at 3.2 Tx Launch Amplitude = 0.8 to
Gbps
1.2 Vp–p, 40” 4–mil FR4 trace,
EQ setting = 0x3C, DEMx[1:0] = 0dB, VOD =
1.0 Vp-p, K28.5, SD_TH = float
(Note 2)
0.05
0.125
UIP-P
EQUALIZATION
DJ1
DJ2
RJ
Random Jitter
Tx Launch Amplitude = 0.8 to
1.2 Vp–p, Repeating 1100b (D24.3) pattern
0.5
psrms
DE-EMPHASIS
DJ3
DJ4
Residual Deterministic Jitter at 6.4 Tx Launch Amplitude = 0.8 to
Gbps
1.2 Vp–p, 10” 4–mil FR4 trace,
EQx = off, DEMx = −6 dB,
VOD = 1.0 Vp-p, K28.5, RATE = 1
(Note 2)
0.09
0.20
UIP-P
Residual Deterministic Jitter at 3.2 Tx Launch Amplitude = 0.8 to
Gbps
1.2 Vp–p, 20” 4–mil FR4 trace,
EQx = off, DEMx = −6 dB,
VOD = 1.0 Vp-p, K28.5, RATE = 0
(Note 2)
0.07
0.18
UIP-P
Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the
device should not be operated beyond such conditions. Absolute Maximum Numbers are guaranteed for a junction temperature range of -40°C to +125°C. Models
are validated to Maximum Operating Voltages only.
Note 2: Typical values represent most likely parametric norms at VDD = 2.5V, TA = 25°C., and at the Recommended Operation Conditions at the time of product
characterization and are not guaranteed.
Note 3: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 4: OOB signal pass-through limited to a minimum ambient temperature of -10C
Note 5: Allowed supply noise (mVP-P sine wave) under typical conditions.
Note 6: Measured with clock-like {11111 00000} pattern.
Note 7: Measured with ENSMB = 1, all channels disabled using SMBus registers 0x01 and 0x02, and EQ in bypass (Default)
Note 8: Measured at package pins of receiver. Less than 65 mVp-p is IDLE, greater than 175 mVp-p is ACTIVE. SD_TH pin connected with resistor to GND
overrides this default setting.
Note 9: Common-mode voltage (VCM) is expressed mathematically as the average of the two signal voltages with respect to local ground.
VCM = (A + B) / 2, A = OUT+, B = OUT-.
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DS64MB201
Symbol
DS64MB201
Electrical Characteristics — Serial Management Bus Interface
Over recommended operating supply and temperature ranges unless other specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
0.8
V
3.6
V
SERIAL BUS INTERFACE DC SPECIFICATIONS
VIL
Data, Clock Input Low Voltage
VIH
Data, Clock Input High Voltage
IPULLUP
Current Through Pull-Up Resistor High Power Specification
or Current Source
VDD
Nominal Bus Voltage
ILEAK-Bus
Input Leakage Per Bus Segment
ILEAK-Pin
Input Leakage Per Device Pin
CI
Capacitance for SDA and SDC
RTERM
External Termination Resistance VDD3.3,
pull to VDD = 2.5V ± 5% OR 3.3V ± (Note 10, Note 11, Note 12)
10%
VDD2.5,
(Note 10, Note 11, Note 12)
2.1
(Note 10)
4
mA
2.375
3.6
V
-200
+200
µA
-15
(Note 10, Note 11)
µA
10
pF
2000
Ω
1000
Ω
SERIAL BUS INTERFACE TIMING SPECIFICATIONS. See Figure 4
FSMB
Bus Operating Frequency
TBUF
Bus Free Time Between Stop and
Start Condition
(Note 13)
10
4.7
µs
THD:STA
Hold time after (Repeated) Start
At IPULLUP, Max
Condition. After this period, the first
clock is generated.
4.0
µs
TSU:STA
Repeated Start Condition Setup
Time
4.7
µs
TSU:STO
Stop Condition Setup Time
4.0
µs
THD:DAT
Data Hold Time
300
ns
TSU:DAT
Data Setup Time
250
TTIMEOUT
Detect Clock Low Timeout
TLOW
Clock Low Period
THIGH
Clock High Period
(Note 13)
TLOW:SEXT
Cumulative Clock Low Extend
Time (Slave Device)
(Note 13)
tF
Clock/Data Fall Time
tR
Clock/Data Rise Time
tPOR
Time in which a device must be
operational after power-on reset
(Note 13)
(Note 13)
25
100
ns
35
4.7
4.0
kHz
ms
µs
50
µs
2
ms
(Note 13)
300
ns
(Note 13)
1000
ns
500
ms
Note 10: Recommended value. Parameter not tested in production.
Note 11: Recommended maximum capacitance load per bus segment is 400pF.
Note 12: Maximum termination voltage should be identical to the device supply voltage.
Note 13: Compliant to SMBus 2.0 physical layer specification. See System Management Bus (SMBus) Specification Version 2.0, section 3.1.1 SMBus common
AC specifications for details.
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DS64MB201
Timing Diagrams
30076452
FIGURE 1. LPDS Output Transition Times
30076453
FIGURE 2. Propagation Delay Timing Diagram
30076454
FIGURE 3. Idle Timing Diagram
30076494
FIGURE 4. SMBus Timing Parameters
9
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DS64MB201
pin selections for 3 Gbps, 6 Gbps, and auto detect. The receiver electrical idle detect threshold is also programmable
via an optional external resistor on the SD_TH pin.
SMBUS Mode:
When in SMBus mode the VOD amplitude level, equalization
and de-emphasis are all programmable on a individual lane
basis, instead of grouped by sides as in the pin mode case.
Upon assertion of ENSMB pins EQx and DEMx functions revert to register control immediately. The EQx and DEMx pins
are converted to AD0-AD3 SMBus address pins. The other
external control pins remain active unless their respective
registers are written to, in which case they are ignored until
ENSMB is driven low. On power-up and when ENSMB is
driven low all registers are reset to their default state.
Functional Description
The DS64MB201 is a 2–lane signal conditioning 2:1 multiplexer and 1:2 switch or fan-out buffer optimized for PCB FR4
trace and cable interconnects up to 6 Gbps data rate. The
DS64MB201 operates in two modes: Pin Control Mode
(ENSMB = 0) and SMBus Mode (ENSMB = 1).
Pin Control Mode:
When in pin mode (ENSMB = 0) , the transceiver is configurable with external pins. Equalization and de-emphasis can
be selected via pin for each side independently. When deemphasis is asserted VOD is automatically increased per the
De-Emphasis table below for improved performance over
lossy media. Rate optimization is also pin controllable, with
TABLE 1. Equalization Input Select Pins for SIA, SIB and DIN (3–Level Input)
EQA, EQB, EQD
Equalization Level
0
9 dB at 3 GHz
Float (No Connect)
13.5 dB at 3 GHz
1
18.4 dB at 3 GHz
Note: F = Float (No Connect), 1 = High and 0 = Low.
TABLE 2. De-Emphasis Input Select Pins for SOA, SOB and DOUT (3–Level Input)
RATE
DEMA,
DEMB,
DEMD
0/F
0
0/F
1
1/F
1/F
0
1
De-Emphasis DE Pulse Width
Level (typ)
(typ)
VOD (typ)
-3.5 dB
330 ps
VOD = 1000 mVp-p
-2 dB
330 ps
VOD = 1200 mVp-p
-6 dB
330 ps
VOD = 1000 mVp-p
-3 dB
330 ps
VOD = 1200 mVp-p
-3.5 dB
200 ps
VOD = 1000 mVp-p
-2 dB
200 ps
VOD = 1200 mVp-p
-6 dB
200 ps
VOD = 1000 mVp-p
-3 dB
200 ps
VOD = 1200 mVp-p
0/F
F
-9 dB
250 ps
enhanced
VOD = 1200 mVp-p
1/F
F
-12 dB
160 ps
enhanced
VOD = 1200 mVp-p
Note: F = Float (No Connect), 1 = High and 0 = Low. Enhanced DE pulse width provides de-empahsis on second bit.
When RATE = F (auto rate detection active), the DE level and pulse width settings follow detected rate. RATE = 0 is 3 Gbps and
RATE = 1 is 6 Gbps. De-emphasis should only be used with VOD = 1000 mVp-p or 1200 mVp-p. VOD less then 1000 mVp-p is
not recommended with de-emphasis. Please refer to VOD1 and VOD0 pin description to set the output differential voltage level.
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10
TXIDLEDO/SO
Function
0
This state is for lossy media, dedicated Idle threshold detect circuit disabled, output follows input based
on EQ settings. Idle state not guaranteed.
Float
Float enables automatic idle detection. Idle on the input is passed to the output. Internal 50KΩ resistors
hold TXIDLEDO/SO pin at a mid level - don't connect this pin if the automatic idle detect function is desired.
This is the default state. Output in Idle if differential input signal less than value set by SD_TH pin.
1
Manual override, output in electrical Idle. Differential inputs are ignored.
TABLE 4. Receiver Electrical Idle Detect Threshold Adjust
SD_TH resistor value (Ω)
Receiver Electrical Idle Detect Threshold (DIFF p-p)
Float (no resistor required)
130 mV (default condition)
0
225 mV
80k
20 mV
SD_TH resistor value can be set from 0 through 80k ohms to achieve desired idle detect threshold, see Figure 5
30076493
FIGURE 5. Typical Idle Threshold vs. SD_TH resistor value
11
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DS64MB201
TABLE 3. Idle Control (3–Level Input)
DS64MB201
Device Connection Paths
The lanes of the DS64MB201 can be configured either as a 2:1 multiplexer, 1:2 switch or fan-out buffer. The controller side is
muxed to the disk drive side. The below table shows the logic for the multiplexer and switch functions.
TABLE 5. Logic Table of Switch and Mux Control
FANOUT
SEL0
SEL1
0
0
0
DOUT0 connects to SIB0.
DOUT1 connects to SIB1.
DIN0 connects to SOB0. SOA0 is in idle (output muted).
DIN1 connects to SOB1. SOA1 is in idle (output muted).
0
0
1
DOUT0 connects to SIB0.
DOUT1 connects to SIA1.
DIN0 connects to SOB0. SOA0 is in idle (output muted).
DIN1 connects to SOA1. SOB1 is in idle (output muted).
0
1
0
DOUT0 connects to SIA0.
DOUT1 connects to SIB1.
DIN0 connects to SOA0. SOB0 is in idle (output muted).
DIN1 connects to SOB1. SOA1 is in idle (output muted).
0
1
1
DOUT0 connects to SIA0.
DOUT1 connects to SIA1.
DIN0 connects to SOA0. SOB0 is in idle (output muted).
DIN1 connects to SOA1. SOB1 is in idle (output muted).
1
0
0
DOUT0 connects to SIB0.
DOUT1 connects to SIB1.
DIN0 connects to SOB0 and SOA0.
DIN1 connects to SOB1 and SOA1.
1
0
1
DOUT0 connects to SIB0.
DOUT1 connects to SIA1.
DIN0 connects to SOB0 and SOA0.
DIN1 connects to SOA1 and SOB1.
1
1
0
DOUT0 connects to SIA0.
DOUT1 connects to SIB1.
DIN0 connects to SOA0 and SOB0.
DIN1 connects to SOB1 and SOA1.
1
1
1
DOUT0 connects to SIA0.
DOUT1 connects to SIA1.
DIN0 connects to SOA0 and SOB0.
DIN1 connects to SOA1 and SOB1.
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Function — connection path
12
TRANSFER OF DATA VIA THE SMBUS
During normal operation the data on SDA must be stable during the time when SDC is High.
There are three unique states for the SMBus:
START: A High-to-Low transition on SDA while SDC is High
indicates a message START condition.
STOP: A Low-to-High transition on SDA while SDC is High
indicates a message STOP condition.
IDLE: If SDC and SDA are both High for a time exceeding
tBUF from the last detected STOP condition or if they are High
for a total exceeding the maximum specification for tHIGH then
the bus will transfer to the IDLE state.
The System Management Bus interface is compatible to SMBus 2.0 physical layer specification. ENSMB must be pulled
high to enable SMBus mode and allow access to the configuration registers.
The DS64MB201 has the AD[3:0] inputs in SMBus mode.
These pins set the SMBus slave address inputs. The AD[3:0]
pins have internal pull-down. When left floating or pulled low
the AD[3:0] = 0000'b, the device default address byte is A0'h.
Based on the SMBus 2.0 specification, the DS64MB201 has
a 7-bit slave address of 1010000'b. The LSB is set to 0'b (for
a WRITE), thus the 8-bit value is 1010 0000'b or A0'h. The
bold bits indicate the AD[3:0] pin map to the slave address
bits [4:1]. The device address byte can be set with the use of
the AD[3:0] inputs. Below are some examples.
AD[3:0] = 0001'b, the device address byte is A2'h
AD[3:0] = 0010'b, the device address byte is A4'h
AD[3:0] = 0100'b, the device address byte is A8'h
AD[3:0] = 1000'b, the device address byte is B0'h
The SDC and SDA pins are 3.3V LVCMOS signaling and include high-Z internal pull up resistors. External low
impedance pull up resistors maybe required depending upon
SMBus loading and speed. Note, these pins are not 5V tolerant.
SMBUS TRANSACTIONS
The device supports WRITE and READ transactions. See
Register Description table for register address, type (Read/
Write, Read Only), default value and function information.
When SMBus is enabled, all outputs of the DS64MB201 must
use one of the following De-emphasis settings (Table 6).
The driver de-emphasis value is set on a per lane basis using
6 different registers. Each register (0x18, 0x26, 0x2E, 0x35,
0x3C, 0x43) requires one of the following De-emphasis settings when in SMBus mode. The VOD for each output should
be set via register write or pin control to be a minimum of 1000
mV.
TABLE 6. De-Emphasis Register Settings (must write one of the following when in SMBus mode)
De-Emphasis Value
Register Setting
3 Gbps Operation
6 Gbps Operation
0.0 dB
0x01
10” trace or 1 meter 28 awg cable
5” trace or 0.5 meter 28 awg cable
-3.5 dB
0xE8
20” trace or 2 meters 28 awg cable 10” trace or 1meters 28 awg cable
-6 dB
0x88
25” trace or 3 meters cable
20” trace or 2 meters cable
-9 dB
0x90
5 meters 28 awg cable
3 meters 28 awg cable
-12 dB
0xA0
8 meters 28 awg cable
5 meters 28 awg cable
7.
8.
9.
The Device drives an ACK bit “0”.
The Device drives the 8-bit data value (register contents).
The Host drives a NACK bit “1”indicating end of the
READ transfer.
10. The Host drives a STOP condition.
The READ transaction is completed, the bus goes IDLE and
communication with other SMBus devices may now occur.
WRITING A REGISTER
To write a register, the following protocol is used (see SMBus
2.0 specification).
1. The Host drives a START condition, the 7-bit SMBus
address, and a “0” indicating a WRITE.
2. The Device (Slave) drives the ACK bit (“0”).
3. The Host drives the 8-bit Register Address.
4. The Device drives an ACK bit (“0”).
5. The Host drive the 8-bit data byte.
6. The Device drives an ACK bit (“0”).
7. The Host drives a STOP condition.
The WRITE transaction is completed, the bus goes IDLE and
communication with other SMBus devices may now occur.
RECOMMENDED SMBUS REGISTER SETTINGS
When SMBus mode is enabled (ENSMB = 1), the default register settings are not configured to an appropriate level. Below
is the recommended settings to configure the EQ, VOD and
DE to a medium level that supports interconnect length of 20
inches FR4 trace or 3 to 5 meters of cable length. Please refer
to Table 1, Table 2, Table 6, Table 7for additional information
and recommended settings.
1. Reset the SMBus registers to default values:
Write 01'h to 0x00.
2. Set de-emphasis to -6 dB for all lanes:
Write 88'h to 0x18, 0x26, 0x2E, 0x35, 0x3C, 0x43.
3. Set equalization to external pin level EQ[1:0] = 00 (~9 dB
at 3 GHz) for all lanes:
Write 30'h to 0x0F, 0x16, 0x1D, 0x24, 0x2C, 0x3A.
4. Set VOD = 1.0 Vp-p for all lanes:
Write 0F'h to 0x17, 0x25, 0x2D, 0x34, 0x3B, 0x42.
READING A REGISTER
To read a register, the following protocol is used (see SMBus
2.0 specification).
1. The Host drives a START condition, the 7-bit SMBus
address, and a “0” indicating a WRITE.
2. The Device (Slave) drives the ACK bit (“0”).
3. The Host drives the 8-bit Register Address.
4. The Device drives an ACK bit (“0”).
5. The Host drives a START condition.
6. The Host drives the 7-bit SMBus Address, and a “1”
indicating a READ.
13
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DS64MB201
System Management Bus (SMBus)
and Configuration Registers
DS64MB201
TABLE 7. SMBus Register Map
Address Register Name
Bit (s) Field
Type Default
Description
0x00
7:1
Reserved
R/W
Set bits to 0.
0
Reset
Reset
0x00
SMBus Reset
1: Reset registers to default value
0x01
PWDN lanes
7:0
PWDN CHx
R/W
0x00
Power Down per lane
[7]: NC — SOB1
[6]: DIN1 — SOA1
[5]: NC — SOB0
[4]: DIN0 — SOA0
[3]: SIB1 — DOUT1
[2]: SIA1 — NC
[1]: SIB0 — DOUT0
[0]: SIA0 — NC
00'h = all lanes enabled
FF'h = all lanes disabled
0x02
PWDN Control
7:1
Reserved
R/W
0x00
Set bits to 0.
0
PWDN Control
7:3
Reserved
2
SEL1
0: Selects SIB1 input and SOB1 output
1: Selects SIA1 input and SOA1 output
1
SEL0
0: Selects SIB0 input and SOB0 output
1: Selects SIA0 input and SOA0 output
0
FANOUT
0: Enable only A or B output depends on SEL1 and
SEL0 (See Mux Control Truth Table)
1: Enable both SOAn and SOBn output
0x03
0x08
SEL / FANOUT
Control
Pin Control Override 7:5
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Reserved
0: Normal operation
1: Enable PWDN control in Register 0x01
R/W
R/W
0x00
0x00
Set bits to 0.
Set bits to 0.
4
Override IDLE
0: Allow IDLE pin control
1: Block IDLE pin control
3
Reserved
Set bit to 0.
2
Override RATE
0: Allow RATE pin control
1: Block RATE pin control
1
Override SEL
0: Allow SEL pin control
1: Block SEL pin control
0
Override
FANOUT
0: Allow FANOUT pin control
1: Block FANOUT pin control
14
0x12
0x15
0x16
0x17
SIA0
EQ Control
7:6
Reserved
R/W
0x20
Set bits to 0.
5:0
SIA0 EQ
SIA0
IDLE Threshold
7:4
Reserved
3:0
IDLE threshold
DOUT0
IDLE RATE Select
7:6
Reserved
5
IDLE auto
0: Allow IDLE_sel control in Bit 4
1: Automatic IDLE detect
4
IDLE select
0: Output is ON (SD is disabled)
1: Output is muted (electrical idle)
3:2
Reserved
Set bits to 0.
1
RATE auto
0: Allow RATE_sel control in Bit 0
1: Automatic RATE detect
0
RATE select
0: 2.5 to 3.2 Gbps
1: 5.0 to 6.4 Gbps
SIB0
EQ Control
7:6
Reserved
5:0
SIB0 EQ
DOUT0
VOD Control
7
Reserved
6:0
DOUT0 VOD
SIA0 EQ Control - total of 24 levels
(3 gain stages with 8 settings)
[5]: Enable EQ
[4:3]: Gain Stage Control
[2:0]: Boost Level Control
Register [EN] [GST] [BST] = Hex Value
100000 = 20'h = Bypass (Default)
101010 = 2A'h = 5 dB at 3 GHz
110000 = 30'h = 9 dB at 3 GHz
110010 = 32'h = 11.7 dB at 3 GHz
111001 = 39'h = 14.6 dB at 3 GHz
110101 = 35'h = 18.4 dB at 3 GHz
110111 = 37'h = 20 dB at 3 GHz
111011 = 3B'h = 21.2 dB at 3 GHz
111101 = 3D'h = 28.4 dB at 3 GHz
R/W
0x00
Set bits to 0.
De-assert = [3:2], assert = [1:0]
00 = 110 mV, 70 mV (Default)
01 = 150 mV, 110 mV
10 = 170 mV, 130 mV
11 = 190 mV, 150 mV
R/W
R/W
0x00
0x20
Set bits to 0.
Set bits to 0.
SIB0 Control - total of 24 levels
(3 gain stages with 8 settings)
[5]: Enable EQ
[4:3]: Gain Stage Control
[2:0]: Boost Level Control
Register [EN] [GST] [BST] = Hex Value
100000 = 20'h = Bypass (Default)
101010 = 2A'h = 5 dB at 3 GHz
110000 = 30'h = 9 dB at 3 GHz
110010 = 32'h = 11.7 dB at 3 GHz
111001 = 39'h = 14.6 dB at 3 GHz
110101 = 35'h = 18.4 dB at 3 GHz
110111 = 37'h = 20 dB at 3 GHz
111011 = 3B'h = 21.2 dB at 3 GHz
111101 = 3D'h = 28.4 dB at 3 GHz
R/W
0x03
Set bit to 0.
DOUT0 VOD Control
03'h = 600 mV (Default)
07'h = 800 mV
0F'h = 1000 mV
1F'h = 1200 mV
3F'h = Reserved
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DS64MB201
0x0F
DS64MB201
0x18
DOUT0
DE Control
7:0
DOUT0 DEM
R/W
0x03
DOUT0 DEM Control
[7]: DEM TYPE (Compatibility = 0 / Enhanced = 1)
[6:0]: DEM Level Control
Register [TYPE] [Level Control] = Hex Value
00000001 = 01'h = 0.0 dB
00111000 = E8'h = −3.5 dB
10001000 = 88'h = −6.0 dB
10010000 = 90'h = −9.0 dB
10100000 = A0'h = −12.0 dB
0x19
SIB0
IDLE Threshold
7:4
Reserved
R/W
0x00
Set bits to 0.
3:0
IDLE threshold
SIA1
EQ Control
7:6
Reserved
5:0
SIA1 EQ
SIA1
IDLE Threshold
7:4
Reserved
3:0
IDLE threshold
DOUT1
IDLE RATE Select
7:6
Reserved
5
IDLE auto
0: Allow IDLE_sel control in Bit 4
1: Automatic IDLE detect
4
IDLE select
0: Output is ON (SD is disabled)
1: Output is muted (electrical idle)
3:2
Reserved
Set bits to 0.
1
RATE auto
0: Allow RATE_sel control in Bit 0
1: Automatic RATE detect
0
RATE select
0: 2.5 to 3.2 Gbps
1: 5.0 to 6.4 Gbps
0x1D
0x20
0x23
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De-assert = [3:2], assert = [1:0]
00 = 110 mV, 70 mV (Default)
01 = 150 mV, 110 mV
10 = 170 mV, 130 mV
11 = 190 mV, 150 mV
R/W
0x20
Set bits to 0.
SIA1 EQ Control - total of 24 levels
(3 gain stages with 8 settings)
[5]: Enable EQ
[4:3]: Gain Stage Control
[2:0]: Boost Level Control
Register [EN] [GST] [BST] = Hex Value
100000 = 20'h = Bypass (Default)
101010 = 2A'h = 5 dB at 3 GHz
110000 = 30'h = 9 dB at 3 GHz
110010 = 32'h = 11.7 dB at 3 GHz
111001 = 39'h = 14.6 dB at 3 GHz
110101 = 35'h = 18.4 dB at 3 GHz
110111 = 37'h = 20 dB at 3 GHz
111011 = 3B'h = 21.2 dB at 3 GHz
111101 = 3D'h = 28.4 dB at 3 GHz
R/W
0x00
Set bits to 0.
De-assert = [3:2], assert = [1:0]
00 = 110 mV, 70 mV (Default)
01 = 150 mV, 110 mV
10 = 170 mV, 130 mV
11 = 190 mV, 150 mV
R/W
16
0x00
Set bits to 0.
SIB1
EQ Control
7:6
Reserved
5:0
SIB1 EQ
DOUT1
VOD Control
7
Reserved
6:0
DOUT1 VOD
0x26
DOUT1
DE Control
7:0
DOUT1 DEM
R/W
0x03
DOUT1 DEM Control
[7]: DEM TYPE (Compatibility = 0 / Enhanced = 1)
[6:0]: DEM Level Control
Register [TYPE] [Level Control] = Hex Value
00000001 = 01'h = 0.0 dB
00111000 = E8'h = −3.5 dB
10001000 = 88'h = −6.0 dB
10010000 = 90'h = −9.0 dB
10100000 = A0'h = −12.0 dB
0x27
SIB1
IDLE Threshold
7:4
Reserved
R/W
0x00
Set bits to 0.
3:0
IDLE threshold
SOA0
IDLE RATE Select
7:6
Reserved
5
IDLE auto
0: Allow IDLE_sel control in Bit 4
1: Automatic IDLE detect
4
IDLE select
0: Output is ON (SD is disabled)
1: Output is muted (electrical idle)
3:2
Reserved
Set bits to 0.
1
RATE auto
0: Allow RATE_sel control in Bit 0
1: Automatic RATE detect
0
RATE select
0: 2.5 to 3.2 Gbps
1: 5.0 to 6.4 Gbps
0x25
0x2B
R/W
0x20
Set bits to 0.
SIB1 EQ Control - total of 24 levels
(3 gain stages with 8 settings)
[5]: Enable EQ
[4:3]: Gain Stage Control
[2:0]: Boost Level Control
Register [EN] [GST] [BST] = Hex Value
100000 = 20'h = Bypass (Default)
101010 = 2A'h = 5 dB at 3 GHz
110000 = 30'h = 9 dB at 3 GHz
110010 = 32'h = 11.7 dB at 3 GHz
111001 = 39'h = 14.6 dB at 3 GHz
110101 = 35'h = 18.4 dB at 3 GHz
110111 = 37'h = 20 dB at 3 GHz
111011 = 3B'h = 21.2 dB at 3 GHz
111101 = 3D'h = 28.4 dB at 3 GHz
R/W
0x03
Set bit to 0.
DOUT1 VOD Control
03'h = 600 mV (Default)
07'h = 800 mV
0F'h = 1000 mV
1F'h = 1200 mV
3F'h = Reserved
De-assert = [3:2], assert = [1:0]
00 = 110 mV, 70 mV (Default)
01 = 150 mV, 110 mV
10 = 170 mV, 130 mV
11 = 190 mV, 150 mV
R/W
17
0x00
Set bits to 0.
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DS64MB201
0x24
DS64MB201
0x2C
DIN0
EQ Control
R/W
0x20
7:6
Reserved
5:0
DIN0 EQ
SOA0
VOD Control
7
Reserved
6:0
SOA0 VOD
0x2E
SOA0
DE Control
7:0
SOA0 DEM
R/W
0x03
SOA0 DEM Control
[7]: DEM TYPE (Compatibility = 0 / Enhanced = 1)
[6:0]: DEM Level Control
Register [TYPE] [Level Control] = Hex Value
00000001 = 01'h = 0.0 dB
00111000 = E8'h = −3.5 dB
10001000 = 88'h = −6.0 dB
10010000 = 90'h = −9.0 dB
10100000 = A0'h = −12.0 dB
0x2F
DIN0
IDLE Threshold
7:4
Reserved
R/W
0x00
Set bits to 0.
3:0
IDLE threshold
SOB0
IDLE RATE Select
7:6
Reserved
5
IDLE auto
0: Allow IDLE_sel control in Bit 4
1: Automatic IDLE detect
4
IDLE select
0: Output is ON (SD is disabled)
1: Output is muted (electrical idle)
3:2
Reserved
Set bits to 0.
1
RATE auto
0: Allow RATE_sel control in Bit 0
1: Automatic RATE detect
0
RATE select
0: 2.5 to 3.2 Gbps
1: 5.0 to 6.4 Gbps
7
Reserved
6:0
SOB0 VOD
0x2D
0x32
0x34
SOB0
VOD Control
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Set bits to 0.
DIN0 EQ Control - total of 24 levels
(3 gain stages with 8 settings)
[5]: Enable EQ
[4:3]: Gain Stage Control
[2:0]: Boost Level Control
Register [EN] [GST] [BST] = Hex Value
100000 = 20'h = Bypass (Default)
101010 = 2A'h = 5 dB at 3 GHz
110000 = 30'h = 9 dB at 3 GHz
110010 = 32'h = 11.7 dB at 3 GHz
111001 = 39'h = 14.6 dB at 3 GHz
110101 = 35'h = 18.4 dB at 3 GHz
110111 = 37'h = 20 dB at 3 GHz
111011 = 3B'h = 21.2 dB at 3 GHz
111101 = 3D'h = 28.4 dB at 3 GHz
R/W
0x03
Set bit to 0.
SOA0 VOD Control
03'h = 600 mV (Default)
07'h = 800 mV
0F'h = 1000 mV
1F'h = 1200 mV
3F'h = Reserved
De-assert = [3:2], assert = [1:0]
00 = 110 mV, 70 mV (Default)
01 = 150 mV, 110 mV
10 = 170 mV, 130 mV
11 = 190 mV, 150 mV
R/W
R/W
0x00
0x03
Set bits to 0.
Set bit to 0.
SOB0 VOD Control
03'h = 600 mV (Default)
07'h = 800 mV
0F'h = 1000 mV
1F'h = 1200 mV
3F'h = Reserved
18
SOB0
DE Control
7:0
SOB0 DEM
R/W
0x03
SOB0 DEM Control
[7]: DEM TYPE (Compatibility = 0 / Enhanced = 1)
[6:0]: DEM Level Control
Register [TYPE] [Level Control] = Hex Value
00000001 = 01'h = 0.0 dB
00111000 = E8'h = −3.5 dB
10001000 = 88'h = −6.0 dB
10010000 = 90'h = −9.0 dB
10100000 = A0'h = −12.0 dB
0x39
SOA1
IDLE RATE Select
7:6
Reserve
R/W
0x00
Set bits to 0.
5
IDLE auto
0: Allow IDLE_sel control in Bit 4
1: Automatic IDLE detect
4
IDLE select
0: Output is ON (SD is disabled)
1: Output is muted (electrical idle)
3:2
Reserved
Set bits to 0.
1
RATE auto
0: Allow RATE_sel control in Bit 0
1: Automatic RATE detect
0
RATE select
0: 2.5 to 3.2 Gbps
1: 5.0 to 6.4 Gbps
DIN1
EQ Control
7:6
Reserved
5:0
DIN1 EQ
SOA1
VOD Control
7
Reserved
6:0
SOA1 VOD
0x3C
SOA1
DE Control
7:0
SOA1 DEM
R/W
0x03
SOA1 DEM Control
[7]: DEM TYPE (Compatibility = 0 / Enhanced = 1)
[6:0]: DEM Level Control
Register [TYPE] [Level Control] = Hex Value
00000001 = 01'h = 0.0 dB
00111000 = E8'h = −3.5 dB
10001000 = 88'h = −6.0 dB
10010000 = 90'h = −9.0 dB
10100000 = A0'h = −12.0 dB
0x3D
DIN1
IDLE Threshold
7:4
Reserved
R/W
0x00
Set bits to 0.
3:0
IDLE threshold
0x3A
0x3B
R/W
0x20
Set bits to 0.
DIN1 EQ Control - total of 24 levels
(3 gain stages with 8 settings)
[5]: Enable EQ
[4:3]: Gain Stage Control
[2:0]: Boost Level Control
Register [EN] [GST] [BST] = Hex Value
100000 = 20'h = Bypass (Default)
101010 = 2A'h = 5 dB at 3 GHz
110000 = 30'h = 9 dB at 3 GHz
110010 = 32'h = 11.7 dB at 3 GHz
111001 = 39'h = 14.6 dB at 3 GHz
110101 = 35'h = 18.4 dB at 3 GHz
110111 = 37'h = 20 dB at 3 GHz
111011 = 3B'h = 21.2 dB at 3 GHz
111101 = 3D'h = 28.4 dB at 3 GHz
R/W
0x03
Set bit to 0.
SOA1 VOD Control
03'h = 600 mV (Default)
07'h = 800 mV
0F'h = 1000 mV
1F'h = 1200 mV
3F'h = Reserved
De-assert = [3:2], assert = [1:0]
00 = 110 mV, 70 mV (Default)
01 = 150 mV, 110 mV
10 = 170 mV, 130 mV
11 = 190 mV, 150 mV
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DS64MB201
0x35
DS64MB201
0x40
7:6
Reserved
5
IDLE auto
0: Allow IDLE_sel control in Bit 4
1: Automatic IDLE detect
4
IDLE select
0: Output is ON (SD is disabled)
1: Output is muted (electrical idle)
3:2
Reserved
Set bits to 0.
1
RATE auto
0: Allow RATE_sel control in Bit 0
1: Automatic RATE detect
0
RATE select
0: 2.5 to 3.2 Gbps
1: 5.0 to 6.4 Gbps
SOB1
VOD Control
7
Reserved
6:0
SOB1 VOD
0x43
SOB1
DE Control
7:0
SOB1 DEM
R/W
0x03
SOB1 DEM Control
[7]: DEM TYPE (Compatibility = 0 / Enhanced = 1)
[6:0]: DEM Level Control
Register [TYPE] [Level Control] = Hex Value
00000001 = 01'h = 0.0 dB
00111000 = E8'h = −3.5 dB
10001000 = 88'h = −6.0 dB
10010000 = 90'h = −9.0 dB
10100000 = A0'h = −12.0 dB
0x47
Global VOD Adjust
7:2
Reserved
R/W
0x02
Set bits to 0.
1:0
VOD Adjust
0x42
SOB1
IDLE RATE Select
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R/W
R/W
0x00
0x03
Set bits to 0.
Set bit to 0.
SOB1 VOD Control
03'h = 600 mV (Default)
07'h = 800 mV
0F'h = 1000 mV
1F'h = 1200 mV
3F'h = Reserved
00 = -25.0%
01 = -12.5%
10 = +0.0% (Default)
11 = +12.5%
20
DS64MB201
Typical Performance
Unless otherwise noted, Typical Performance is measured at room temperature and nominal supply voltage.
30076460
FIGURE 6. Electrical Specification DJ1: 40" 4-mil microstrip trace on Input
Datarate: 6.4 Gbps
Input Pattern: K28.5
Signal Conditioning: EQ Setting = 3B'h
30076461
FIGURE 7. Electrical Specification DJ2: 40" 4-mil microstrip trace on Input
Datarate: 3.2 Gbps
Input Pattern: K28.5
Signal Conditioning: EQ Setting = 3C'h
21
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DS64MB201
30076462
FIGURE 8. Electrical Specification DJ3: 10" 4-mil microstrip trace on Output
Datarate: 6.4 Gbps
Input Pattern: K28.5
Signal Conditioning: EQ Setting = 20'h (Bypass) and DE Setting = 88'h
30076463
FIGURE 9. Electrical Specification DJ4: 20" 4-mil microstrip trace on Output
Datarate: 3.2 Gbps
Input Pattern: K28.5
Signal Conditioning: EQ Setting = 20'h (Bypass) and DE Setting = 88'h
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22
GENERAL RECOMMENDATIONS
The DS64MB201 is a high performance circuit capable of delivering excellent performance. Careful attention must be paid
to the details associated with high-speed design as well as
providing a clean power supply. Refer to the LVDS Owner's
Manual for more detailed information on high speed design
tips to address signal integrity design issues.
PCB LAYOUT CONSIDERATIONS FOR DIFFERENTIAL
PAIRS
The CML inputs and LPDS outputs must have a controlled
differential impedance of 100Ω. It is preferable to route differential lines exclusively on one layer of the board, particularly for the input traces. The use of vias should be avoided if
possible. If vias must be used, they should be used sparingly
and must be placed symmetrically for each side of a given
differential pair. Route the differential signals away from other
signals and noise sources on the printed circuit board. See
AN-1187 for additional information on LLP packages.
23
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DS64MB201
POWER SUPPLY BYPASSING
Two approaches are recommended to ensure that the
DS64MB201 is provided with an adequate power supply.
First, the supply (VDD) and ground (GND) pins should be
connected to power planes routed on adjacent layers of the
printed circuit board. The layer thickness of the dielectric
should be minimized so that the VDD and GND planes create
a low inductance supply with distributed capacitance. Second, careful attention to supply bypassing through the proper
use of bypass capacitors is required. A 0.01 μF bypass capacitor should be connected to each VDD pin such that the
capacitor is placed as close as possible to the DS64MB201.
Smaller body size capacitors can help facilitate proper component placement. Additionally, three capacitors with capacitance in the range of 2.2 μF to 10 μF should be incorporated
in the power supply bypassing design as well. These capacitors can be either tantalum or an ultra-low ESR ceramic.
Applications Information
DS64MB201
Physical Dimensions inches (millimeters) unless otherwise noted
54-pin LLP Package (5.5 mm x 10 mm x 0.8 mm, 0.5 mm pitch)
Order Number: DS64MB201SQ — Tape & Reel Supplied As 2,000 Units,
DS64MB201SQE — Tape & Reel Supplied As 250 Units
Package Number: SQA54A
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24
DS64MB201
Notes
25
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DS64MB201 Dual Lane 2:1/1:2 Mux/Buffer with Equalization and De-Emphasis
Notes
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