PRELIMINARY CY7C1051DV33 8-Mbit (512K x 16) Static RAM Functional Description[1] Features • High speed The CY7C1051DV33 is a high-performance CMOS Static RAM organized as 512K words by 16 bits. — tAA = 10 ns • Low active power Write to the device by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte LOW Enable (BLE) is LOW, then data from IO pins (IO0–IO7), is written into the location specified on the address pins (A0–A18). If Byte HIGH Enable (BHE) is LOW, then data from IO pins (IO8–IO15) is written into the location specified on the address pins (A0–A18). — ICC = 110 mA @ 10 ns • Low CMOS standby power • • • • • — ISB2 = 20 mA 2.0V data retention Automatic power-down when deselected TTL-compatible inputs and outputs Easy memory expansion with CE and OE features Available in lead-free 48-ball FBGA and 44-pin TSOP II packages Read from the device by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte LOW Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on IO0–IO7. If Byte HIGH Enable (BHE) is LOW, then data from memory will appear on IO8 to IO15. See the “Truth Table” on page 8 for a complete description of Read and Write modes. The input/output pins (IO0–IO15) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or a Write operation (CE LOW, and WE LOW) is in progress. The CY7C1051DV33 is available in a 44-pin TSOP II package with center power and ground (revolutionary) pinout, as well as a 48-ball fine-pitch ball grid array (FBGA) package. Logic Block Diagram 512K × 16 ARRAY SENSE AMPS A0 A1 A2 A3 A4 A5 A6 A7 A8 ROW DECODER INPUT BUFFER IO0–IO7 IO8–IO15 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 COLUMN DECODER BHE WE CE OE BLE Note 1. For guidelines on SRAM system design, please refer to the “System Design Guidelines” Cypress application note, available on the internet at www.cypress.com. Cypress Semiconductor Corporation Document #: 001-00063 Rev. *C • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised March 9, 2007 [+] Feedback CY7C1051DV33 PRELIMINARY Selection Guide –10 Unit Maximum Access Time 10 ns Maximum Operating Current 110 mA Maximum CMOS Standby Current 20 mA Pin Configurations[2] 48-ball Mini FBGA TSOP II (Top View) (Top View) 1 BLE 2 OE 3 A0 4 A1 5 A2 6 NC A IO 8 BHE A3 A4 CE IO 0 B IO 9 IO10 A5 A6 IO 1 IO 2 C VSS IO11 A17 A7 IO3 VCC A0 A1 A2 A3 A4 CE IO 0 IO 1 IO 2 IO 3 VCC VSS IO 4 IO 5 IO 6 IO 7 WE A5 A6 A7 A8 A9 D VCC IO 12 NC A16 IO 4 VSS E IO 14 IO 13 A14 A15 IO 5 IO 6 F IO 15 NC A12 A13 WE IO 7 G A18 A8 A9 A10 A11 NC H 1 44 2 3 43 42 4 41 40 39 38 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A17 A16 A15 OE BHE BLE IO 15 IO 14 IO 13 IO 12 VSS VCC IO 11 IO 10 IO 9 IO 8 A18 A14 A13 A12 A11 A10 \ Note 2. NC pins are not connected on the die Document #: 001-00063 Rev. *C Page 2 of 11 [+] Feedback CY7C1051DV33 PRELIMINARY Maximum Ratings Current into Outputs (LOW)......................................... 20 mA (Exceeding the maximum ratings may impair the useful life of the device. These are for user guidelines, they are not tested.) Static Discharge Voltage............. ...............................>2001V Storage Temperature ................................. –65°C to +150°C Latch-up Current...................................................... >200 mA Ambient Temperature with Power Applied............................................. –55°C to +125°C Operating Range [3] Supply Voltage on VCC to Relative GND (per MIL-STD-883, Method 3015) .... –0.5V to +4.6V Ambient Temperature VCC –40°C to +85°C 3.3V ± 0.3V Range DC Voltage Applied to Outputs in High-Z State[3] ....................................–0.3V to VCC + 0.3V Industrial DC Input Voltage[3] .................................–0.3V to VCC + 0.3V DC Electrical Characteristics Over the Operating Range Parameter Description –10 Test Conditions Min Unit Max VOH Output HIGH Voltage VCC = Min, IOH = –4.0 mA VOL Output LOW Voltage VCC = Min, IOL = 8.0 mA 0.4 V VIH Input HIGH Voltage 2.0 VCC + 0.3 V VIL[3] Input LOW Voltage –0.3 0.8 V IIX Input Leakage Current –1 +1 μA IOZ Output Leakage Current GND < VOUT < VCC, Output Disabled ICC VCC Operating Supply Current VCC = Max, f = fMAX = 1/tRC 2.4 GND < VI < VCC V +1 μA 100 MHz 110 mA 83 MHz 100 66 MHz 90 40 MHz 80 –1 ISB1 Automatic CE Power Down Max VCC, CE > VIH Current —TTL Inputs VIN > VIH or VIN < VIL, f = fMAX 40 mA ISB2 Automatic CE Power Down Max VCC, CE > VCC – 0.3V, Current —CMOS Inputs VIN > VCC – 0.3V or VIN < 0.3V, f = 0 20 mA Capacitance[4] Parameter Description CIN Input Capacitance COUT IO Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 3.3V Max. Unit 12 pF 12 pF Thermal Resistance[4] Parameter Description ΘJA Thermal Resistance (Junction to Ambient) ΘJC Thermal Resistance (Junction to Case) Test Conditions FBGA Package TSOP II Package Unit Still Air, soldered on a 3 × 4.5 inch, four-layer printed circuit board 28.31 51.43 °C/W 11.4 15.8 °C/W Notes 3. VIL (min) = –2.0V and VIH (max) = VCC + 2.0V for pulse durations of less than 20 ns. 4. Tested initially and after any design or process changes that may affect these parameters Document #: 001-00063 Rev. *C Page 3 of 11 [+] Feedback CY7C1051DV33 PRELIMINARY AC Test Loads and Waveforms[5] Z = 50Ω 3.0V OUTPUT 50 Ω * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT 30 pF* GND 1.5V Rise Time: 1 V/ns (a) ALL INPUT PULSES 90% 90% 10% 10% Fall Time: 1 V/ns (b) High-Z Characteristics R 317Ω 3.3V OUTPUT R2 351Ω 5 pF (c) AC Switching Characteristics[6] Over the Operating Range Parameter Description –10 Min Max Unit Read Cycle tpower[7] VCC(typical) to the first access 100 μs tRC Read Cycle Time 10 ns tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE LOW to Data Valid 10 ns tDOE OE LOW to Data Valid 5 ns tLZOE OE LOW to Low-Z 10 3 tHZOE OE HIGH to tLZCE CE LOW to Low-Z[9] ns 0 High-Z[8, 9] ns 5 3 High-Z[8, 9] ns ns ns tHZCE CE HIGH to 5 tPU CE LOW to Power Up tPD CE HIGH to Power Down 10 ns tDBE Byte Enable to Data Valid 5 ns tLZBE Byte Enable to Low-Z tHZBE Byte Disable to High-Z 0 ns ns 0 ns 6 ns Notes 5. AC characteristics (except High-Z) are tested using the load conditions shown in Figure (a). High-Z characteristics are tested for all speeds using the test load shown in Figure (c). 6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V. 7. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed. 8. tHZOE, tHZCE, tHZBE and tHZWE are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads.Transition is measured when the outputs enter a high impedance state. 9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, tHZBE is less than tLZBE, and tHZWE is less than tLZWE for any given device. Document #: 001-00063 Rev. *C Page 4 of 11 [+] Feedback CY7C1051DV33 PRELIMINARY AC Switching Characteristics[6] Over the Operating Range (continued) Parameter –10 Description Min Unit Max Write Cycle[10, 11] tWC Write Cycle Time 10 ns tSCE CE LOW to Write End 7 ns tAW Address Setup to Write End 7 ns tHA Address Hold from Write End 0 ns tSA Address Setup to Write Start 0 ns tPWE WE Pulse Width 7 ns tSD Data Setup to Write End 5 ns tHD Data Hold from Write End 0 ns tLZWE WE HIGH to Low-Z[9] 3 ns High-Z[8, 9] tHZWE WE LOW to tBW Byte Enable to End of Write 5 ns 7 ns Data Retention Characteristics Over the Operating Range Parameter Conditions[12] Description VDR VCC for Data Retention ICCDR Data Retention Current tCDR[4] tR[13] Chip Deselect to Data Retention Time Min Max 2.0 VCC = VDR = 2.0V, CE > VCC – 0.3V, VIN > VCC – 0.3V or VIN < 0.3V V 20 Operation Recovery Time Unit mA 0 ns tRC ns Data Retention Waveform DATA RETENTION MODE VCC 3.0V tCDR VDR > 2V 3.0V tR CE Notes 10. The internal Write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a Write, and the transition of either of these signals can terminate the Write. The input data setup and hold timing should be referenced to the leading edge of the signal that terminates the Write. 11. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. 12. No inputs may exceed VCC + 0.3V 13. Full device operation requires linear VCC ramp from VDR to VCC(min) > 50 μs or stable at VCC(min) > 50 μs. Document #: 001-00063 Rev. *C Page 5 of 11 [+] Feedback CY7C1051DV33 PRELIMINARY Switching Waveforms Read Cycle No. 1[14, 15] tRC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID Read Cycle No. 2 (OE Controlled)[15, 16] ADDRESS tRC CE tACE OE tHZOE tDOE BHE, BLE tLZOE tHZCE tDBE tLZBE DATA OUT HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tHZBE DATA VALID HIGH IMPEDANCE tPD tPU 50% 50% IICC CC IISB SB Notes 14. Device is continuously selected. OE, CE, BHE or BHE or both= VIL. 15. WE is HIGH for Read cycle. 16. Address valid prior to or coincident with CE transition LOW. Document #: 001-00063 Rev. *C Page 6 of 11 [+] Feedback CY7C1051DV33 PRELIMINARY Switching Waveforms (continued) Write Cycle No. 1 (CE Controlled)[17, 18] tWC ADDRESS CE tSA tSCE tAW tHA tPWE WE tBW BHE, BLE tSD tHD DATAI/O Write Cycle No. 2 (BLE or BHE Controlled) tWC ADDRESS BHE, BLE tSA tBW tAW tHA tPWE WE tSCE CE tSD tHD DATAI/O Notes 17. Data I/O is high-impedance if OE or BHE or BLE or both = VIH. 18. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. Document #: 001-00063 Rev. *C Page 7 of 11 [+] Feedback CY7C1051DV33 PRELIMINARY Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled, OE LOW) tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE tBW BHE, BLE tHZWE tSD tHD DATA I/O tLZWE Truth Table CE OE WE BLE BHE I/O0–I/O7 I/O8–I/O15 Mode Power H X X X X High-Z High-Z Power-down Standby (ISB) L L H L L Data Out Data Out Read All Bits Active (ICC) L L H L H Data Out High-Z Read Lower Bits Only Active (ICC) L L H H L High-Z Data Out Read Upper Bits Only Active (ICC) L X L L L Data In Data In Write All Bits Active (ICC) L X L L H Data In High-Z Write Lower Bits Only Active (ICC) L X L H L High-Z Data In Write Upper Bits Only Active (ICC) L H H X X High-Z High-Z Selected, Outputs Disabled Active (ICC) Ordering Information Speed (ns) 10 Ordering Code Package Diagram Package Type CY7C1051DV33-10BAXI 51-85106 48-ball FBGA (Pb-Free) CY7C1051DV33-10ZSXI 51-85087 44-pin TSOP II (Pb-Free) Operating Range Industrial Please contact your local Cypress sales representative for availability of these parts. Document #: 001-00063 Rev. *C Page 8 of 11 [+] Feedback CY7C1051DV33 PRELIMINARY Package Diagrams Figure 1. 48-Ball FBGA (7.00 mm x 8.5 mm x 1.2 mm) (51-85106) BOTTOM VIEW TOP VIEW A1 CORNER Ø0.05 M C Ø0.25 M C A B A1 CORNER Ø0.30±0.05(48X) 1 2 3 4 5 6 6 4 3 2 1 C C F G D E 2.625 8.50±0.10 E 0.75 A B 5.25 A B D 8.50±0.10 5 F G H H 1.875 A A B 0.75 7.00±0.10 3.75 7.00±0.10 0.15(4X) 0.15 C 0.21±0.05 0.53±0.05 0.25 C B 51-85106-*E Document #: 001-00063 Rev. *C 1.20 MAX. 0.36 SEATING PLANE C Page 9 of 11 [+] Feedback PRELIMINARY CY7C1051DV33 Package Diagrams (continued) Figure 2. 44-pin TSOP II (51-85087) 51-85087-*A All products and company names mentioned in this document may be the trademarks of their respective holders. Document #: 001-00063 Rev. *C Page 10 of 11 © Cypress Semiconductor Corporation, 2006-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback CY7C1051DV33 PRELIMINARY Document History Page Document Title: CY7C1051DV33 8-Mbit (512K x 16) Static RAM Document Number: 001-00063 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 342195 See ECN PCI New Data Sheet *A 380574 See ECN SYT Redefined ICC values for Com’l and Ind’l temperature ranges ICC (Com’l): Changed from 110, 90 and 80 mA to 110, 100 and 95 mA for 8, 10 and 12 ns speed bins respectively ICC (Ind’l): Changed from 110, 90 and 80 mA to 120, 110 and 105 mA for 8, 10 and 12 ns speed bins respectively Changed the Capacitance values from 8 pF to 10 pF on Page # 3 *B 485796 See ECN NXR Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 North First Street” to “198 Champion Court” Removed -8 and -12 Speed bins from product offering, Removed Commercial Operating Range option, Modified Maximum Ratings for DC input voltage from -0.5V to -0.3V and VCC + 0.5V to VCC + 0.3V Changed the Description of IIX from Input Load Current to Input Leakage Current. Changed tHZBE from 5 ns to 6 ns Updated footnote #7 on High-Z parameter measurement Added footnote #11 Updated the Ordering Information table and Replaced Package Name column with Package Diagram. *C 866000 See ECN NXR Changed ball E3 from VSS to NC in FBGA pin configuration Document #: 001-00063 Rev. *C Page 11 of 11 [+] Feedback