April 2004 AS7C3256A ® 3.3V 32K X 8 CMOS SRAM (Common I/O) Features • TTL-compatible, three-state I/O • 28-pin JEDEC standard packages - 300 mil SOJ - 8 × 13.4 mm TSOP 1 • ESD protection ≥ 2000 volts • Latch-up current ≥ 200 mA • • • • Pin compatible with AS7C3256 Industrial and commercial temperature options Organization: 32,768 words × 8 bits High speed - 10/12/15/20 ns address access time - 5, 6, 7, 8 ns output enable access time • Very low power consumption: ACTIVE - 180mW max @ 10 ns • Very low power consumption: STANDBY - 7.2 mW max CMOS I/O • Easy memory expansion with CE and OE inputs Logic block diagram Pin arrangement 28-pin TSOP 1 (8×13.4 mm) VCC 28-pin SOJ (300 mil) Input buffer 256 X 128 X 8 Array (262,144) Sense amp I/O7 Row decoder A0 A1 A2 A3 A4 A5 A6 A7 I/O0 Column decoder OE A11 A9 A8 A13 WE VCC A14 A12 A7 A6 A5 A4 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 AS7C3256A WE Control A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 AS7C3256A GND 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 OE circuit CE A A A A A A A 8 9 10 11 12 13 14 Selection guide -10 -12 -15 -20 Unit Maximum address access time 10 12 15 20 ns Maximum output enable access time 5 6 7 8 ns Maximum operating current 50 45 40 35 mA Maximum CMOS standby current 2 2 2 2 mA 4/23/04; v.2.0 Alliance Semiconductor P. 1 of 9 Copyright © Alliance Semiconductor. All rights reserved. AS7C3256A ® Functional description The AS7C3256A is a 3.3V high-performance CMOS 262,144-bit Static Random-Access Memory (SRAM) device organized as 32,768 words × 8 bits. It is designed for memory applications requiring fast data access at low voltage, including PentiumTM, PowerPCTM, and portable computing. Alliance’s advanced circuit design and process techniques permit 3.3V operation without sacrificing performance or operating margins. The device enters standby mode when CE is high. CMOS standby mode consumes 7.2 mW. Normal operation offers 75% power reduction after initial access, resulting in significant power savings during CPU idle, suspend, and stretch mode. Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 5, 6, 7, 8 ns are ideal for high-performance applications. The chip enable (CE) input permits easy memory expansion with multiple-bank memory organizations. A write cycle is accomplished by asserting chip enable (CE) and write enable (WE) LOW. Data on the input pins I/O0-I/O7 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting chip enable (CE) and output enable (OE) LOW, with write enable (WE) high. The chip drives I/O pins with the data word referenced by the input address. When chip enable or output enable is high, or write enable is low, output drivers stay in high-impedance mode. All chip inputs and outputs are TTL-compatible. Operation is from a single 3.3 ±0.3V supply. The AS7C3256A is packaged in high volume industry standard packages. Absolute maximum ratings Parameter Symbol Min Max Unit Voltage on VCC relative to GND Vt1 –0.5 +5.0 V Voltage on any pin relative to GND Vt2 –0.5 VCC + 0.5 V Power dissipation PD – 1.0 W Storage temperature (plastic) Tstg –65 +150 oC Ambient temperature with VCC applied Tbias –55 +125 o DC current into outputs (low) IOUT – 20 C mA Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Truth table CE WE OE Data Mode H X X High Z Standby (ISB, ISB1) L H H High Z Output disable (ICC) L H L DOUT Read (ICC) L L X DIN Write (ICC) Key: X = Don’t care, L = Low, H = High 4/23/04; v.2.0 Alliance Semiconductor P. 2 of 9 AS7C3256A ® Recommended operating conditions Parameter Symbol Min Typical Max Unit Supply voltage VCC 3.0 3.3 3.6 V Input voltage VIH** VIL* 2.0 – VCC+0.5 V -0.5 – 0.8 V 70 o – 85 oC -15 -20 Ambient operating temperature commercial TA industrial 0 TA – –40 C * V min = –1.0V for pulse width less than 5ns. ** IL VIH max = VCC + 2.0V for pulse width less than 5ns. DC operating characteristics (over the operating range)1 -10 Parameter Sym Input leakage current |ILI| Test conditions VCC = Max, Vin = GND to VCC Output leakage V = Max, |ILO| CC current VOUT = GND to VCC Operating VCC = Max, CE ≤ VIL power supply ICC f = fMax, IOUT = 0mA current ISB Standby power supply current Output voltage VCC = Max, CE > VIH f = fMax VCC = Max, CE > VCC–0.2V ISB1 VIN < 0.2V or VIN > VCC–0.2V, f = 0 VOL IOL = 8 mA, VCC = Min VOH IOH = –4 mA, VCC = Min -12 Min Max Min Max Min Max Min Max Unit – 1 – 1 – 1 – 1 µA – 1 – 1 – 1 – 1 µA – 50 – 45 – 40 – 35 mA – 20 – 20 – 20 – 20 mA – 2.0 – 2.0 – 2.0 – 2.0 mA – 0.4 – 0.4 – 0.4 – 0.4 V 2.4 – 2.4 – 2.4 – 2.4 – V Capacitance (f = 1MHz, Ta = room temperature, VCC = NOMINAL)2 Parameter Symbol Signals Test conditions Max Unit Input capacitance CIN A, CE, WE, OE Vin = 0V 5 pF I/O capacitance CI/O I/O Vin = Vout = 0V 7 pF 4/23/04; v.2.0 Alliance Semiconductor P. 3 of 9 AS7C3256A ® Read cycle (over the operating range)3,9 -10 Parameter Symbol Min -12 -15 -20 Max Min Max Min Max Min Max Unit Notes Read cycle time tRC 10 – 12 – 15 – 20 – ns Address access time tAA – 10 – 12 – 15 – 20 ns 3 Chip enable (CE) access time tACE – 10 – 12 – 15 – 20 ns 3 Output enable (OE) access time tOE – 5 – 6 – 7 – 8 ns Output hold from address change tOH 3 – 3 – 3 – 3 – ns 5 CE LOW to output in low Z tCLZ 3 – 3 – 3 – 3 – ns 4, 5 CE HIGH to output in high Z tCHZ – 3 – 3 – 4 – 5 ns 4, 5 OE LOW to output in low Z tOLZ 0 – 0 – 0 – 0 – ns 4, 5 OE HIGH to output in high Z tOHZ – 3 – 3 – 4 – 5 ns 4, 5 Power up time tPU 0 – 0 – 0 – 0 – ns 4, 5 Power down time tPD – 10 – 12 – 15 – 20 ns 4, 5 Key to switching waveforms Rising input Falling input Undefined output/don’t care Read waveform 1 (address controlled)3,6,7,9 tRC Address tOH tAA Dout Data valid Read waveform 2 (CE controlled)3,6,8,9 tRC1 CE tOE OE tOLZ tOHZ tCHZ tACE Dout Data valid tCLZ Supply current 4/23/04; v.2.0 tPU tPD 50% Alliance Semiconductor ICC ISB 50% P. 4 of 9 AS7C3256A ® Write cycle (over the operating range)11 -10 Parameter -12 -15 -20 Symbol Min Max Min Max Min Max Min Max Unit Write cycle time tWC 10 – 12 – 15 – 20 – ns Chip enable to write end tCW 8 – 8 – 10 – 12 – ns Address setup to write end tAW 8 – 8 – 10 – 12 – ns Address setup time tAS 0 – 0 – 0 – 0 – ns Write pulse width tWP 7 – 8 – 9 – 12 – ns Write recovery time tWR 0 – 0 – 0 – 0 – ns Address hold from end of write tAH 0 – 0 – 0 – 0 – ns Data valid to write end tDW 5 – 6 – 8 – 10 – ns Data hold time tDH 0 – 0 – 0 – 0 – ns 4, 5 Write enable to output in high Z tWZ – 5 – 6 – 7 – 8 ns 4, 5 Output active from write end tOW 3 – 3 – 3 – 3 – ns 4, 5 Write waveform 1 (WE controlled)10,11 tWC tAW tAH Address tWR tWP WE tAS tDW Din tDH Data valid tWZ tOW Dout Write waveform 2 (CE controlled)10,11 tAW tWC tAH Address tAS tWR tCW CE tWP WE tWZ Din tDW tDH Data valid Dout 4/23/04; v.2.0 Alliance Semiconductor P. 5 of 9 Notes AS7C3256A ® AC test conditions - Output load: see Figure B Input pulse level: GND to 3.0V. See Figure A. Input rise and fall times: 2 ns. See Figure A. Input and output timing reference levels: 1.5V. +3.3V +3.0V GND 90% 10% 90% 2 ns 10% Figure A: Input pulse Dout 350Ω Thevenin equivalent 320Ω C13 Dout 168Ω +1.72V GND Figure B: Output load Notes 1 2 3 4 5 6 7 8 9 10 11 12 13 During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification. This parameter is sampled, but not 100% tested. For test conditions, see AC Test Conditions, Figures A, B. These parameters are specified with CL = 5pF, as in Figures B. Transition is measured ±500mV from steady-state voltage. This parameter is guaranteed, but not tested. WE is High for read cycle. CE and OE are Low for read cycle. Address valid prior to or coincident with CE transition Low. All read cycle timings are referenced from the last valid address to the first transitioning address. N/A All write cycle timings are referenced from the last valid address to the first transitioning address. N/A C=30pF, except on High Z and Low Z parameters, where C=5pF. 4/23/04; v.2.0 Alliance Semiconductor P. 6 of 9 AS7C3256A ® Package diagrams 28-pin SOJ D e 28-pin SOJ Min Max in inches B A A1 E1 E2 Seating Plane b Pin 1 c A2 E 28-pin TSOP1 b A A1 A2 B b c D E E1 E2 e 0.148 0.026 - 0.095 0.105 0.026 0.032 0.016 0.020 0.007 0.010 0.720 0.730 0.255 0.275 0.295 0.305 0.330 0.340 0.050 BSC e 28-pin TSOP1 8×13.4 mm Min Max c L A2 D Hd α E 4/23/04; v.2.0 0.128 Alliance Semiconductor A A1 A A1 A2 b c D e E Hd L α 1.00 1.20 0.05 0.15 0.91 1.05 0.17 0.27 0.10 0.20 11.70 11.90 0.55 nominal 7.90 8.10 13.20 13.60 0.50 0.70 0° 5° P. 7 of 9 AS7C3256A ® Ordering information Temperature Package / Access time Plastic SOJ, 300 mil TSOP 8x13.4mm 10 ns 12 ns 15 ns 20 ns Commercial AS7C3256A-10JC AS7C3256A-12JC AS7C3256A-15JC AS7C3256A-20JC Industrial AS7C3256A-10JI AS7C3256A-12JI AS7C3256A-15JI AS7C3256A-20JI Commercial AS7C3256A-10TC AS7C3256A-12TC AS7C3256A-15TC AS7C3256A-20TC Industrial AS7C3256A-10TI AS7C3256A-12TI AS7C3256A-15TI AS7C3256A-20TI Note: Add suffix ‘N’to the above part number for lead free parts. (Ex. AS7C3256A-10JIN) Part numbering system AS7C 3 Voltage: SRAM prefix 3 = 3.3V supply 4/23/04; v.2.0 256A –XX X Packages: Device number Access time J = SOJ 300 mil T = TSOP 8x13.4mm Alliance Semiconductor C or I X Temperature range: C = 0 oC to 70 0C N= Lead Free Part I = -40C to 85C P. 8 of 9 ® AS7C3256A ® Alliance Semiconductor Corporation 2575, Augustine Drive, Santa Clara, CA 95054 Tel: 408 - 855 - 4900 Fax: 408 - 855 - 4999 Copyright © Alliance Semiconductor All Rights Reserved Part Number: AS7C3256A Document Version: v.2.0 www.alsc.com © Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such lifesupporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.