LSTD EBL2449A1-15UFL Dual-mode uart hci module Datasheet

A
Datasheet
BT830 Bluetooth v4.0 Dual-Mode UART HCI
Module
Version 1.6
BT830 - SA
BT830 - ST
BT830
Datasheet
REVISION HISTORY
Revision
1.0
1.1
Date
23 July 2014
10 Nov 2014
Changes
Initial Version
Updated pin definitions
Approved By
Jonathan Kaye
Jonathan Kaye
1.2
1.3
10 Aug 2015
30 Sept 2015
Added Tape/Reel information
Added additional antenna information
Jonathan Kaye
Andrew Chen
1.4
1.5
15 Dec 2015
17 Aug 2016
Replaced tray image with new one
Changed Hardware Integration Guide to Datasheet.
Maggie Teng
Sue White
1.6
31 Aug 2016
Updated Declaration of Conformity
Tom Smith
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BT830
Datasheet
CONTENTS
1
Scope ..................................................................................................................................................................5
2
Operational Description .....................................................................................................................................5
3
Block Diagram and Descriptions.........................................................................................................................6
4
Specifications......................................................................................................................................................7
5
Pin Definitions ....................................................................................................................................................8
6
DC Electrical Characteristic ............................................................................................................................. 10
7
RF Characteristics ............................................................................................................................................ 12
8
Interface .......................................................................................................................................................... 12
8.1 PIO .............................................................................................................................................................. 12
8.2 WLAN Coexistence Interface ...................................................................................................................... 12
8.3 UART Interface ........................................................................................................................................... 13
8.4 PCM Interface ............................................................................................................................................. 13
8.5 GCI Interface ............................................................................................................................................... 15
8.6 Slots and Sample Formats .......................................................................................................................... 16
8.7 PCM Timing Information ............................................................................................................................. 16
8.8 PCM Slave Timing ....................................................................................................................................... 19
8.9 PCM Slave Mode Timing Parameters ......................................................................................................... 19
8.10 PCM_CLK and PCM_SYNC Generation ....................................................................................................... 20
8.11 PCM Configuration ..................................................................................................................................... 20
8.12 Digital Audio Interface (I²S) ........................................................................................................................ 21
9
Power Supply and Regulation ......................................................................................................................... 23
9.1 Voltage Regulator Enable and Reset .......................................................................................................... 23
9.2 Power Sequencing ...................................................................................................................................... 24
10
Antenna Performance ..................................................................................................................................... 24
10.1 Multilayer Chip Antenna ............................................................................................................................ 24
10.2 NanoBlade .................................................................................................................................................. 26
11
Mechanical Dimensions and Land Pattern ...................................................................................................... 27
11.1 BT830-SA Mechanical Drawing .................................................................................................................. 27
11.2 BT830-ST Mechanical Drawing ................................................................................................................... 28
12
Implementation Note ...................................................................................................................................... 29
12.1 PCB Layout on Host PCB ............................................................................................................................. 29
12.1.1
Antenna Keep-out and Proximity to Metal or Plastic ....................................................................... 29
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BT830
Datasheet
12.1.2
13
DC Power Supply Options for Using BT830 Module ......................................................................... 30
Application Note for Surface Mount Modules ................................................................................................ 30
13.1 Introduction ................................................................................................................................................ 30
13.2 Shipping ...................................................................................................................................................... 30
13.2.1
Tray Package ..................................................................................................................................... 30
13.2.2
Tape and Reel Package Information ................................................................................................. 31
13.3 Reflow Parameters ..................................................................................................................................... 32
14
FCC and IC Regulatory ..................................................................................................................................... 34
14.1 Documentation Requirements ................................................................................................................... 34
15
European Union Regulatory ............................................................................................................................ 37
15.1 EU Declarations of Conformity - BT830-SA and BT830-ST ......................................................................... 37
16
Ordering Information ...................................................................................................................................... 38
16.1 General Comments..................................................................................................................................... 38
17
Bluetooth SIG Approvals ................................................................................................................................. 39
17.1 Application Note: Subsystem Combinations .............................................................................................. 39
17.1.1
Laird Customer Declaration ID Procedure ........................................................................................ 39
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BT830
Datasheet
SCOPE
This document describes key hardware aspects of the Laird BT830 Bluetooth HCI modules. This document is
intended to assist device manufacturers and related parties, with the integration of this module into their host
devices. Data in this document are drawn from a number of sources including data sheets for the CSR8811.
Because the BT830 is currently in development stage, this document is preliminary and the information in this
document is subject to change. Visit www.lairdtech.com to obtain the most recent version of this document.
OPERATIONAL DESCRIPTION
The BT830 series of UART HCI devices are designed to meet the needs of OEMs adding
robust Bluetooth connectivity and using embedded Bluetooth stacks within their products.
Leveraging the market-leading CSR8811 chipset, the BT830 series provides exceptionally low
power consumption with outstanding range. Supporting the latest Bluetooth v4.0
specification with EDR (Enhanced Data Rate), the Laird BT830 series enables OEMs to
accelerate their development time for leveraging either Classic Bluetooth or Bluetooth Low
Energy (BLE) into their operating system-based devices.
With a footprint as small as 8.5 x 13 mm, yet output power at 7 dBm, these modules are ideal
for applications where designers need high performance in minimal size. For maximum
flexibility in systems integration, the modules are designed to support a UART interface
plus GPIO and additionally I2S and PCM audio interfaces.
BT830-SA module
BT830 –ST module
These modules present an HCI interface and have native support for Windows and Linux Bluetooth software
stacks. All BT830 series devices are fully qualified as Bluetooth Hardware Controller Subsystem products. This
allows designers to integrate their existing pre-approved Bluetooth host and profile subsystem stacks to gain a
Bluetooth END product approval for their products.
The BT830 series is engineered to provide excellent RF performance with integrated antenna and additional
band pass filters. It further reduces regulatory and testing requirements for OEMs and ensures a hassle free
development cycle.
A fully featured, low-cost developer’s kit is available for prototyping, debug, and integration testing of the BT830
series modules and further reduces risk and time in development cycles.
BT830-SA
BT830-ST
2.1











BTv4.0 Dual Mode UART HCI Module (Integrated Antenna)
BTv4.0 Dual Mode UART HCI Module (SMT Pad for External Antenna)
Features and Benefits
2.2
Bluetooth v4.0 - dual mode (Classic Bluetooth and BLE)
Compact footprint
3-wire Wi-Fi coexistence scheme
High antenna radiation gain and efficiency
Good interference rejection for multi-com system (GSM/WCDMA)
Class 1 output – 7 dBm
UART, GPIO, I2S, and PCM
Industrial temperature range
Bluetooth hardware controller subsystem
FCC, IC, and CE approvals
Host Wake up
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







Application Areas
Medical devices
ePOS terminals
Barcode scanners
Industrial cable replacement
M2M connectivity
Automotive Diagnostic Equipment
Personal Digital Assistants (PDA)
Bluetooth HID device (keyboard,
mouse, and joystick)
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BT830
Datasheet
BLOCK DIAGRAM AND DESCRIPTIONS
Figure 2: BT830 module block diagram
CS8811A08
(Main chip)
The BT830 is based on the CSR8811A08 dual mode chip. The chip is a single-chip radio with
on-chip LDO regulators and baseband IC for Bluetooth 2.4 GHz systems including EDR to 3
Mbps.
Dedicated signal and baseband processing is included for full Bluetooth operation. The chip
provides PCM/I2S and UART interfaces. Up to four general purpose I/Os are available for
general use such as Wi-Fi coexistence or general indicators.
Note: The purpose of the SPI interface is to access the module’s inner settings such as
selecting different WLAN CO-EXIST scheme. The SPI interface can also be used to
place the module in RF test mode. You cannot use the module over the SPI
interface for normal operation as the main host interface.
Antenna
Options
BT830-SA – The antenna is a ceramic monopole chip antenna.
BT830-ST – Provides a SMT pad for connecting an external antenna.
Band Pass
Filter
The band pass filter filters the out-of-band emissions from the transmitter to meet the
specific regulations for type approvals of various countries.
Crystal
The embedded 26 MHz crystal is used for generating the clock for the entire module.
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BT830
Datasheet
SPECIFICATIONS
Table 1: BT830 specifications
Categories
Wireless
Specification
Host Interface
Feature
Bluetooth®
Frequency
Implementation
V4.0 Dual Mode
2.402 - 2.480 GHz
Maximum Transmit
Power
Class 1
+7 dBm from antenna
Receive Sensitivity
Range
Data Rates
UART
GPIO
-89 dBm
Circa 100 meters
Up to 3 Mbps (over the air)
RX, TX, CTS, RTS
Six configurable lines
(1.8V/3.3V configurable by VDD_PADS)
Host Controller Interface over UART
3 wire CSR schemes supported
(Unity-3 and Unity-3e)
3.3V +/-10%
Note: See Implementation Note for details on different DC
power selections on the BT830.
Idle Mode ~4.3 mA (Master; ACL link; No traffic)
File Transfer ~7.1 mA (Master; ACL link; Transmit)
Multilayer ceramic antenna with up to 40% efficiency.
SMT pad for external antenna
8.5 x 13 x 1.6 mm (BT830 - module)
-30°C to +85°C
-40°C to +85°C
Lead-free and RoHS compliant
1-Year Warranty
Hardware Controller Subsystem Approved
All BT830 series (BT830-SA; BT830-ST)
Operational Modes
Coexistence
HCI
802.11 (Wi-Fi)
Supply Voltage
Supply
Power Consumption
Current
Antenna Option
Internal (BT830-SA)
External (BT830-ST)
Dimensions
Operating
Storage
Lead Free
Warranty
Bluetooth®
FCC / IC / CE
Physical
Environmental
Miscellaneous
Approvals
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BT830
Datasheet
PIN DEFINITIONS
Table 2: BT830 pin definitions
#
Pin Name
I/O
1
VDD_PADS
DC voltage input
Supply
Domain
(1.75V-3.6V)
2
GND
GND
-
Positive DC supply for configuring
digital I/O level.
Ground
3
PIO2
VDD_PADS
Programmable input/output line
NC
4
UART_RTS
VDD_PADS
UART request to send, active low
NC
5
UART_TX
VDD_PADS
UART data output, active high
NC
6
UART_CTS
VDD_PADS
UART clear to send, active low
NC
7
UART_RX
VDD_PADS
UART data input, active high
NC
8
VREG_EN_RST#
Bidirectional, tristate, with weak
internal pulldown
Bidirectional, tristate,
with weak
internal pull-up
Bidirectional, tristate,
with weak
internal pull-up
Bidirectional, tristate,
with weak
internal pull-up
Bidirectional, tristate,
with weak
internal pull-up
Input with strong
internal pulldown
VDD_PADS
N/A
9
VREG_IN_HV
Analogue
regulator input
3.3V
Take high to enable internal
regulators. Also acts as active low
reset. Maximum voltage is
VDD_PADS.
Module main DC power supply;
Input to internal high-voltage
regulator
10
VREG_OUT_HV
1.8V
GND
GND
GND
GND
Output from internal high-voltage
regulator and input to low-voltage
internal regulators.
Ground
Ground
Ground
Ground
N/C
11
12
13
14
Analogue
regulator
input/output
GND
GND
GND
GND
15
16
17
GND
GND
RF
GND
GND
-
Ground
Ground
BT830-ST – RF signal out (50 ohm)
BT830-SA – No connection
GND
GND
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Description
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If
Unused…
N/A
GND
N/A
GND
GND
GND
GND
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BT830
Datasheet
#
Pin Name
I/O
Supply
Domain
VDD_PADS
18
19
GND
PCM_SYNC/
SPI_CS#/
PIO23
GND
Bidirectional, tristate, with weak
internal pulldown
20
PCM_CLK/
SPI_CLK/ PIO24
Bidirectional, tristate, with weak
internal pulldown
VDD_PADS
21
PCM_IN/
SPI_MOSI/
PIO21
Input, tri-state,
with weak
internal pulldown
VDD_PADS
22
PCM_OUT/
SPI_MISO/
PIO22
Output, tri-state,
with weak
internal pulldown
VDD_PADS
23
24
GND
PIO0/
32K_CLK_IN
VDD_PADS
25
PIO1/
BT_ACTIVE
26
PIO9/
BT_PRIORITY
GND
Bidirectional, tristate, with weak
internal pulldown
Bidirectional, tristate, with weak
internal pulldown
Bidirectional, tristate, with weak
internal pulldown
27
PIO4/
WLAN_ACTIVE
28
SPI_PCM#_SEL
29
30
Description
Ground
PCM synchronous data sync SPI
chip select, active low
programmable input/output line
*See Note 1.
PCM synchronous data clock
SPI clock
Programmable input/output line
*See Note 1.
If
Unused…
GND
NC
NC
PCM synchronous data input
SPI data input
Programmable input/output line
*See Note 1.
PCM synchronous data output
SPI data output
Programmable input/output line
*See Note 1.
Ground
Programmable input/output line
and 32kHz sleep clock input
NC
VDD_PADS
Programmable input/output line;
Wi-Fi and BT 3-wire coexistance
NC
VDD_PADS
Programmable input/output line;
Wi-Fi and BT 3-wire coexistance
NC
Bidirectional, tristate, with weak
internal pulldown
Input with weak
internal pulldown
VDD_PADS
Programmable input/output line;
Wi-Fi and BT 3-wire coexistance
NC
VDD_PADS
NC
PIO3/
Host Wake up
Bidirectional, tristate, with weak
internal pulldown
VDD_PADS
Control line to select SPI or PCM
interface, high = SPI, low = PCM
*See Note 1.
Programmable input/output line;
Host wake up from BT, active High.
GND
GND
-
Ground
GND
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NC
GND
NC
NC
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BT830
Datasheet
Note 1:
The purpose of the SPI interface is to access the module’s inner settings such as selecting different
WLAN CO-EXIST scheme. The SPI interface can also be used to put the module in RF test mode. You
cannot use the module over the SPI interface for normal operation as the main host interface.
DC ELECTRICAL CHARACTERISTIC
Table 3: Absolute maximum ratings
Rating
Min
Max
Unit
Storage temperature
VREG_IN_HV
VREG_OUT_HV
-40
2.3
1.7
+85
4.8
2.0
⁰C
V
V
VDD_PADS
Other terminal voltages
-0.4
-0.4
3.6
VDD_PADS + 0.4 V
V
V
Min
-30
3.0
1.75
1.75
VDD_PADS
Max
+85
3.6
1.95
3.6
VDD_PADS
Unit
⁰C
V
V
V
V
Table 4: Recommended operating conditions
Rating
Operating temperature
VREG_IN_HV
VREG_OUT_HV
VDD_PADS
VREG_EN_RST#
Table 5: High-voltage Linear Regulator
Normal Operation
Input voltage (VREG_IN_HV)
Output voltage (VREG_OUT_HV)
Temperature coefficient
Output noise
(frequency range 100Hz to100kHz)
Settling time (settling time
within 10% of final value)
Output current
Min
3.0
1.75
-200
-
Typ
3.3
1.85
-
Max
3.6
1.95
200
0.4
Unit
V
V
ppm/⁰C
mV rms
-
-
5
µs
-
-
100
mA
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BT830
Datasheet
Table 6: Digital I/O Characteristics
Normal Operation
Min
Typ
VIL input logic level low
Input Voltage
-0.4
-
Max
Unit
0.4
V
VIH input logic level high
0.7 x
VDD_PADS
Output Voltage
VDD_PADS
+ 0.4
V
VOL output logic level low,
IOL = 4.0 mA
VOH output logic level high,
IOL = 4.0 mA
-
-
0.4
V
0.75 x
VDD_PADS
-
-
V
-10
150
-0.33
5.0
5.0
µA
µA
µA
µA
pF
Input and Tristate Currents
-150
-40
10
40
-5
-1.0
0.33
1.0
1.0
-
Strong pull-up
Strong pull-down
Weak pull-up
Weak pull-down
CI input capacitance
Table 7: Current Consumption
Normal Operation
Idle
Inquiry
File Transfer (ACL)
Transmit (Master)
Receive (Slave)
Avg.
5
891
7.1
11.5
292
448
LE Connected (Master)
LE Scan (Master)
Unit
mA
µA
mA
mA
µA
µA
Current consumption values are taken with:




VREG_IN_HV pin = 3.15V
RF TX power set to 0dBm
XTAL used with PSKEY_LP_XTAL_LVL = 8
LEDs disconnected
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RF CHARACTERISTICS
Table 8: RF Characteristics
RF Characteristics, VREG_IN_HV/VDD_PADS Min
= 3.3V @ room
temperature unless otherwise specified
Maximum RF Transmit Power
RF power variation over temperature range
RF power variation over supply voltage range
RF power variation over BT band
RF power control range
-21
20 dB band width for modulated carrier
ACP
F = F0 ± 2MHz
Typ.
Max
7
1.5
BT. Spec.
8
20
1000
-20
0.2
3
8
F = F0 ± 3MHz
-40
F = F0 > 3MHz
-40
Unit
dBm
dB
dB
dB
dBm
kHz
Drift rate
ΔF1avg
5
165
≤20
140<175
kHz
kHz
ΔF1max
168
140<175
kHz
ΔF2avg / ΔF1avg
0.9
>=0.8
Table 9: BDR and EDR receiver sensitivity
RF Characteristics, VREG_IN_HV/VDD_PADS =
3.3V @ room temp.
Sensitivity for 0.1% BER
Packet Type
Min
Typ
Max
BT. Spec.
Unit
-70
dBm
dBm
DH1
DH3
-87
-87
DH5
2-DH5
-87
-91
dBm
dBm
Sensitivity variation over BT band
3-DH5
All
-85
3
dBm
dB
Sensitivity variation over temperature range
All
TBD
dB
INTERFACE
8.1
PIO
PIO lines are configured through software to have either weak or strong pull-ups or pull-downs. All PIO lines are
configured as inputs with weak pull-downs at reset and have additional individual bus-keeper configuration.
8.2
WLAN Coexistence Interface
Dedicated hardware is provided to implement a variety of WLAN coexistence schemes. The following are
supported:


Channel skipping AFH
Priority signaling
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

Channel signaling
Host passing of channel instructions
The BT830 supports the following WLAN coexistence schemes:


Unity-3
Unity-3e
More information is available in the BT830 Configuration File application note, available on the documentation
tab of the BT830 Product Page at Lairdtech.com.
8.3
UART Interface
This is a standard UART interface for communicating with other serial devices. The CSR8811 UART interface
provides a simple mechanism for communicating with other serial devices using the RS-232 protocol.
Figure 1: Signals that implement the UART function
The above figure shows the four signals that implement the UART function. When BT830 is connected to
another digital device, UART_RX and UART_TX transfer data between the two devices. The remaining two
signals, UART_CTS and UART_RTS, implement RS232 hardware flow control where both are active low
indicators. The default configuration of UART is 115200 bauds; None parity check; 1 stop bit; 8 bits per byte.
Note:
8.4
With a standard PC, an accelerated serial port adapter card is required to communicate with the UART
at its maximum data rate.
PCM Interface
The audio PCM interface on the BT830 supports the following:









Continuous transmission and reception of PCM encoded audio data over Bluetooth.
Processor overhead reduction through hardware support for continual transmission and reception of PCM
data.
A bidirectional digital audio interface that routes directly into the baseband layer of the firmware. It does
not pass through the HCI protocol layer.
Hardware on the BT830 for sending data to and from a SCO connection.
Up to three SCO connections on the PCM interface at any one time.
PCM interface master, generating PCM_SYNC and PCM_CLK.
PCM interface slave, accepting externally generated PCM_SYNC and PCM_CLK.
Various clock formats including:
– Long Frame Sync
– Short Frame Sync
GCI timing environments.
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Datasheet


13-bit or 16-bit linear, 8-bit µ-law, or A-law companded sample formats.
Receives and transmits on any selection of three of the first four slots following PCM_SYNC.
The PCM configuration options are enabled by setting PSKEY_PCM_CONFIG32.
8.4.1 PCM Interface Master/Slave
When configured as the master of the PCM interface, the BT830 generates PCM_CLK and PCM_SYNC.
Figure 2: PCM Interface Master
Figure 3: PCM Interface Slave
8.4.2 Long Frame Sync
Figure 4: Long Frame Sync (shown with 8-bit Companded Sample)
Long Frame Sync indicates a clocking format that controls the transfer of PCM data words or samples. In Long
Frame Sync, the rising edge of PCM_SYNC indicates the start of the PCM word. When the BT830 is configured as
PCM master, generating PCM_SYNC and PCM_CLK, then PCM_SYNC is eight bits long. When the BT830 is
configured as PCM Slave, PCM_SYNC is from one cycle PCM_CLK to half the PCM_SYNC rate.
BT830 samples PCM_IN on the falling edge of PCM_CLK and transmits PCM_OUT on the rising edge. PCM_OUT is
configurable as high impedance on the falling edge of PCM_CLK in the LSB position or on the rising edge.
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8.4.3 Short Frame Sync
In Short Frame Sync, the falling edge of PCM_SYNC indicates the start of the PCM word. PCM_SYNC is always
one clock cycle long.
Figure 5: Short Frame Sync (Shown with 16-bit Sample)
As with Long Frame Sync, BT830 samples PCM_IN on the falling edge of PCM_CLK and transmits PCM_OUT on
the rising edge. PCM_OUT is configurable as high impedance on the falling edge of PCM_CLK in the LSB position
or on the rising edge.
8.4.4 Multi-Slot Operation
More than one SCO connection over the PCM interface is supported using multiple slots. Up to three SCO
connections are carried over any of the first four slots.
Figure 6: Multi-slot operation with 2 Slots and 8-bit companded samples
8.5
GCI Interface
BT830 is compatible with the GCI, a standard synchronous 2B+D ISDN timing interface. The two 64 kbps B
channels are accessed when this mode is configured.
Figure 7: Multi-slot operation
The start of frame is indicated by the rising edge of PCM_SYNC and runs at 8 kHz.
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8.6
Slots and Sample Formats
BT830 receives and transmits on any selection of the first four slots following each sync pulse. Slot durations are
either 8 or 16 clock cycles:


8 clock cycles for 8-bit sample formats
16 clock cycles for 8-bit, 13-bit, or 16-bit sample formats
BT830 supports:
 13-bit linear, 16-bit linear, and 8-bit µ-law or A-law sample formats
 A sample rate of 8 ksps
 Little or big endian bit order
 For 16-bit slots, the three or eight unused bits in each slot are filled with sign extension, padded with zeros
or a programmable 3-bit audio attenuation compatible with some codecs.
Figure 8: 16-bit slot Length and sample formats
8.7
PCM Timing Information
Table 10: PCM Timing information
Symbol
fmclk
Parameter
PCM_CLK frequency
4MHz DDS generation.
Frequency selection is
programmable.
48MHz DDS generation.
Frequency selection is
programmable.
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Min
-
Typ
128
Max
-
Unit
kHz
-
kHz
256
512
2.9
-
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Symbol
tmclkh (a)
Parameter
PCM_SYNC frequency for SCO connection
PCM_CLK high
4MHz DDS generation
Min
980
Typ
8
-
Max
-
Unit
kHz
ns
tmclkl a)
-
PCM_CLK low
PCM_CLK jitter
730
-
-
21
ns
ns
pk-pk
Delay time from
4MHz DDS generation
PCM_CLK high to
48MHz DDS generation
PCM_SYNC high
Delay time from PCM_CLK high to valid PCM_OUT
-
-
20
40.83
ns
ns
-
-
20
ns
Delay time from
PCM_CLK low to
PCM_SYNC low (long
frame sync only)
-
-
20
40.83
ns
ns
tdmclksynch
tdmclkpout
tdmclklsyncl
4MHz DDS generation
48MHz DDS generation
4MHz DDS generation
48MHz DDS generation
(a) Assumes normal system clock operation. Figures vary during low-power modes, when system clock speeds
are reduced.
Table 11: PCM Master Mode Timing Parameters
Symbol
tdmclkhsyncl
tdmclklpoutz
tdmclkhpoutz
tsupinclkl
thpinclkl
Parameter
Delay time from
4MHz DDS generation
PCM_CLK high to
48MHz DDS generation
PCM_SYNC low
Delay time from PCM_CLK low to PCM_OUT
high impedance
Delay time from PCM_CLK high to PCM_OUT
high impedance
Set-up time for PCM_IN valid to PCM_CLK low
Hold time for PCM_CLK low to PCM_IN invalid
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Min
-
Typ
-
Max
20
40.83
Unit
ns
ns
-
-
20
ns
-
-
20
ns
20
0
-
-
ns
ns
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Figure 9: PCM Master Timing Long Frame Sync
Figure 10: PCM Master Timing Short Frame Sync
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8.8
PCM Slave Timing
Symbol
fsclk
fsclk
tsclkl
Parameter
PCM clock frequency (Slave mode: input)
Min
64
Typ
-
Max
2048
Unit
kHz
PCM clock frequency (GCI mode)
PCM_CLK low time
128
200
-
4096
-
kHz
ns
tsclkh
PCM_CLK high time
200
-
-
ns
8.9
PCM Slave Mode Timing Parameters
Symbol
thsclksynch
tsusclksynch
tdpout
tdsclkhpout
tdpoutz
tsupinsclkl
thpinsclkl
Parameter
Hold time from PCM_CLK low to PCM_SYNC high
Set-up time for PCM_SYNC high to PCM_CLK low
Min
2
20
Typ
-
Max
-
Unit
ns
ns
Delay time from PCM_SYNC or PCM_CLK, whichever is
later, to valid PCM_OUT data (long frame sync only)
Delay time from CLK high to PCM_OUT valid data
Delay time from PCM_SYNC or PCM_CLK low, whichever
is later, to PCM_OUT data line high impedance
Set-up time for PCM_IN valid to CLK low
Hold time for PCM_CLK low to PCM_IN invalid
-
-
15
ns
-
-
15
20
ns
ns
20
2
-
-
ns
ns
Figure 11: PCM Slave Timing Long Frame Sync
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Figure 12: PCM Slave Timing Short Frame Sync
8.10 PCM_CLK and PCM_SYNC Generation
BT830 has two methods of generating PCM_CLK and PCM_SYNC in master mode:


Generating these signals by DDS from BT830internal 4MHz clock. Using this mode limits PCM_CLK to 128,
256 or 512 kHz and PCM_SYNC to 8 kHz.
Generating these signals by DDS from an internal 48MHz clock enables a greater range of frequencies to be
generated with low jitter but consumes more power. To select this second method, set bit to
48M_PCM_CLK_GEN_EN in PSKEY_PCM_CONFIG32. When in this mode and with long frame sync, the
length of PCM_SYNC is either 8 or 16 cycles of PCM_CLK, determined by LONG_LENGTH_SYNC_EN in
PSKEY_PCM_CONFIG32.
Equation 8.1 describes PCM_CLK frequency when generated from the internal 48MHz clock:
Equation 8.1: PCM_CLK Frequency Generated Using the Internal 48MHz Clock
Set the frequency of PCM_SYNC relative to PCM_CLK using Equation 8.2:
Equation 8.2: PCM_SYNC Frequency Relative to PCM_CLK
CNT_RATE, CNT_LIMIT and SYNC_LIMIT are set using PSKEY_PCM_LOW_JITTER_CONFIG. As an example, to
generate PCM_CLK at 512kHz with PCM_SYNC at 8kHz, set SKEY_PCM_LOW_JITTER_CONFIG to 0x08080177.
8.11 PCM Configuration
Configure the PCM by using PSKEY_PCM_CONFIG32 and PSKEY_PCM_LOW_JITTER_CONFIG (see your PSKey
file). The default for PSKEY_PCM_CONFIG32 is 0x00800000.
For example: First slot following sync is active, 13-bit linear voice format, long frame sync and interface master
generating 256kHz PCM_CLK from 4MHz internal clock with no tri-state of PCM_OUT).
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8.12 Digital Audio Interface (I²S)
The digital audio interface supports the industry standard formats for I²S, left-justified or right-justified. The
interface shares the same pins as the PCM interface which means each audio bus is mutually exclusive in its
usage. Table 12 lists these alternative functions. Figure 11 shows the timing diagram.
Table 12: Alternative Functions of the Digital Audio Bus Interface on the PCM Interface.
PCM Interface
PCM_OUT
I²S Interface
SD_OUT
PCM_IN
PCM_SYNC
SD_IN
WS
PCM_CLK
SCK
Figure 13: PCM Configuration
The internal representation of audio samples within BT830is 16-bit and data on SD_OUT is limited to 16-bit per
channel.
Table 13: Digital Audio Interface Slave Timing
Symbol
-
Parameter
SCK Frequency
Min
-
Typ
-
Max
6.2
Unit
MHz
tch
tcl
WS Frequency
SCK high time
SCK low time
80
80
-
96
-
kHz
ns
ns
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Table 14: I²S Slave Mode Timing
Symbol
tssu
tsh
topd
tisu
tih
Parameter
WS valid to SCK high set-up time
Min
20
Typ
-
Max
-
Unit
ns
SCK high to WS invalid hold time
SCK low to SD_OUT valid delay time
2.5
-
-
20
ns
ns
SD_IN valid to SCK high set-up time
SCK high to SD_IN invalid hold time
20
2.5
-
-
ns
ns
Figure 14: Digital Audio Interface Slave Timing
Table 15: Digital Audio Interface Master Timing
Symbol
-
Parameter
SCK Frequency
WS Frequency
Min
-
Typ
-
Max
6.2
96
Unit
MHz
kHz
Table 16: I²S Master Mode Timing Parameters, WS and SCK as Outputs
Symbol
tspd
topd
tisu
tih
Parameter
SCK low to WS valid delay time
SCK low to SD_OUT valid delay
time
SD_IN valid to SCK high set-up
time
SCK high to SD_IN invalid hold
time
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Min
-
Typ
-
Max
39.27
18.44
Unit
ns
ns
18.44
-
-
ns
0
-
-
ns
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Figure 15: Digital Audio Interface Master Timing
POWER SUPPLY AND REGULATION
BT830 can be powered by either of the two sources listed below:
Method #1 – Apply 3.3 V on pin-9, High-voltage linear regulator input (VREG_IN_HV), to generate the main 1.8 V
out put on pin-10 (VREG_OUT_HV).
A minimum 1.5μF capacitor must be connected to the Pin-10 (VREG_OUT_HV). Low ESR capacitors such
as multilayer ceramic types should be used. In this case, the VDD_PADS can be either 3.3V or 1.8V.
Method #2 – Apply 1.8V on pin-10 High-voltage linear regulator output (VREG_OUT_HV), to generate the
internal voltage for the system. Be sure to left Pin-9 un-connected in this method. In this case, the VDD_PADS
can only be set at 1.8V.
Note: The I/O signal voltage level (VDD_PADS) should be equal or less than the power supply mentioned
voltage above.
9.1
Voltage Regulator Enable and Reset
A single pin, VREG_EN_RST#, controls both the high-voltage linear regulator enables and the digital reset
function. The VREG_EN_RST# pin remains active controlling the reset function if the HV linear regulator is not
used; the pin must be driven high to take the device out of reset.
The regulator is enabled by taking the VREG_EN_RST# pin above 1.0V. The regulator can also be controlled by
the software.
The VREG_EN_RST# is also connected internally to the reset function, and is powered from the VDD_PADS
supply, so voltages above VDD_PADS must not be applied to this pin. The VREG_EN_RST# pin is pulled down
internally.
The VREG_EN_RST# pin is an active low reset. Assert the reset signal for a period greater than five milliseconds
to ensure a full reset.
Note:
The regulator enables are released as soon as VREG_EN_RST# is low, so the regulators shut down.
Therefore do not take VREG_EN_RST# low for less than five millilseconds, as a full reset is not
guaranteed.
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Other reset sources are:
- Power-on reset
- Via a software-configured watchdog timer
A warm reset function is also available under software control. After a warm reset the RAM data
remains available.
9.2
Power Sequencing
CSR recommends that all power supplies are powered at the same time. The order of powering the supplies
relative to the I/O supply, VDD_PADS to VREG_IN_HV or VREG_OUT_HV, is not important.
ANTENNA PERFORMANCE
10.1 Multilayer Chip Antenna
Figure 16 illustrates this antenna’s performance.
Unit in dBi @2.44GHz
AT3216-B2R7HAA
XY-plane
XZ-plane
YZ-plane
Peak
Avg.
Peak
Avg.
Peak
Avg.
-2.2
-5.9
-0.7
-5.0
-1.3
-3.7
Efficiency
40%
Figure 16: BT830 gain table for the multilayer chip antenna
Figure 17: Network Analyzer output
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XY-plane
Unit : dBi
Peak gain
Avg. gain
-2.2
-5.9
Peak gain
Avg. gain
XZ-plane
-0.7
-5.0
YZ-plane
Peak gain
-1.3
Avg. gain
-3.7
XY-plane
X
Y
XZ-plane
Z
X
YZ-plane
Z
Y
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10.2 NanoBlade
The following describes the performance of the NanoBlue antenna (EBL2449A1-15UFL):
Parameter
Frequency Range
Performance
2.4-2.5 GHz
Gain
2.0 dBi
Polarization
Linear
Impedance
50 ohms
VSWR
<2.0:1
Dimensions (L x W x H)
1.88 in x .5 in x .032 in
Weight
2 grams
XY-plane
XZ-plane
YZ-plane
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MECHANICAL DIMENSIONS AND LAND PATTERN
11.1 BT830-SA Mechanical Drawing
Note:
Dimensions are in millimetres (mm).
Tolerances: .xx
±0.03 mm for PCB PAD; +/0.15mm for module size.
.x
±1.3 mm
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11.2
BT830-ST Mechanical Drawing
Note:
Dimensions are in millimetres (mm).
Tolerances: .xx
±0.03 mm for PCB PAD; +/0.15mm for module size.
.x
±1.3 mm
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IMPLEMENTATION NOTE
12.1 PCB Layout on Host PCB
Checklist (for PCB):
 Must locate the BT830 module close to the edge of PCB.
 Use solid GND plane on inner layer (for best EMC and RF performance).
 Place GND vias as close to module GND pads as possible
 Route traces to avoid noise being picked up on VCC supply.
 Antenna Keep-out area:
– Ensure there is no copper in the antenna keep-out area on any layers of the host PCB.
– Keep all mounting hardware and metal clear of the area to allow proper antenna radiation.
– For best antenna performance, place the BT830 module on the edge of the host PCB, preferably in
the corner with the antenna facing the corner.
– A different host PCB thickness dielectric will have small effect on antenna.
Figure 18: Recommend Antenna keep-out area (in White) used on the BT830-SA
12.1.1 Antenna Keep-out and Proximity to Metal or Plastic
Checklist (for metal /plastic enclosure):




Minimum safe distance for metals without seriously compromising the antenna (tuning) is 40 mm
top/bottom and 30 mm left or right.
Metal close to the BT830-SA chip monopole antenna (bottom, top, left, right, any direction) will have
degradation on the antenna performance. The amount of degradation is entirely system dependent which
means some testing by customers is required (in their host application).
Any metal closer than 20 mm starts to significantly degrade performance (S11, gain, radiation efficiency).
It is best that the customer tests the range with mock-up (or actual prototype) of the product to assess
effects of enclosure height (and material whether metal or plastic).
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12.1.2 DC Power Supply Options for Using BT830 Module


Using DC power 3.3 V
Power the on Pin-9 (VREG_IN_HV) with 3.3 V and pull-high on Pin-8 (VREG_EN_RST#) to turn on the
internal regulator. The BT830 module generates 1.8 V output on Pin-10 (VREG_OUT_HV) which can supply
to the other DC pin of the board.
Using DC power 1.8 V
Leave the Pin-9 (VREG_IN_HV) no connection, power the Pin-10 (VREG_OUT_HV) with 1.8 V and pull-high
on Pin-8 (VREG_EN_RST#) to turn on the internal regulator.
APPLICATION NOTE FOR SURFACE MOUNT MODULES
13.1 Introduction
Laird surface mount modules are designed to conform to all major manufacturing guidelines. This application
note is intended to provide additional guidance beyond the information that is presented in the user manual.
This application note is considered a living document and is updated as new information is presented.
The modules are designed to meet the needs of a number of commercial and industrial applications. They are
easy to manufacture and they conform to current automated manufacturing processes.
13.2 Shipping
13.2.1 Tray Package
Modules are shipped in ESD
(Electrostatic Discharge) safe trays
that can be loaded into most
manufacturers pick and place
machines. Layouts of the trays are
provided in Error! Reference s
ource not found..
Figure 19: Shipping tray layout
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13.2.2 Tape and Reel Package Information
Note:
Ordering information for Tape and Reel packaging is an addition of T/R to the end of the full module
part number. For example, BT830 becomes BT830-Sx-xx-T/R.
Figure 20: Reel specifications
Figure 21: Tape specifications
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There are 2500 BT830 modules taped in a reel (and packaged in a pizza box) and five boxes per carton (12,500
modules per carton). Reel, boxes, and carton are labeled with the appropriate labels. See Figure 22.
13.2.2.1 Packaging Process
Figure 22: BT800 packaging process
13.3 Reflow Parameters
Prior to any reflow, it is important to ensure the modules were packaged to prevent moisture absorption. New
packages contain desiccate (to absorb moisture) and a humidity indicator card to display the level maintained
during storage and shipment. If directed to bake units on the card, see Table 17 and follow instructions specified
by IPC/JEDEC J-STD-033. A copy of this standard is available from the JEDEC website:
http://www.jedec.org/sites/default/files/docs/jstd033b01.pdf
Note:
The shipping tray cannot be heated above 65°C. If baking is required at the higher temperatures
displayed in in Table 17, the modules must be removed from the shipping tray.
Any modules not manufactured before exceeding their floor life should be re-packaged with fresh desiccate and
a new humidity indicator card. Floor life for MSL (Moisture Sensitivity Level) 3 devices is 168 hours in ambient
environment 30°C/60%RH.
Table 17: Recommended baking times and temperatures
MSL 125°C
Baking Temp.
Saturated
@ 30°C/85%
3
9 hours
90°C/≤ 5%RH
Baking Temp.
Floor Life Limit
+ 72 hours
@ 30°C/60%
7 hours
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Saturated
@ 30°C/85%
33 hours
40°C/ ≤ 5%RH
Baking Temp.
Floor Life Limit
+ 72 hours
@ 30°C/60%
23 hours
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Saturated
@ 30°C/85%
13 days
Floor Life Limit
+ 72 hours @
30°C/60%
9 days
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Laird surface mount modules are designed to be easily manufactured, including reflow soldering to a PCB.
Ultimately it is the responsibility of the customer to choose the appropriate solder paste and to ensure oven
temperatures during reflow meet the requirements of the solder paste. Laird surface mount modules conform
to J-STD-020D1 standards for reflow temperatures.
Important: During reflow, modules should not be above 260° and not for more than 30 seconds.
Figure 13-23: Recommended Reflow Temperature
Temperatures should not exceed the minimums or maximums presented in Table 18.
Table 18: Recommended Maximum and minimum temperatures
Specification
Value
Unit
Temperature Inc./Dec. Rate (max)
Temperature Decrease rate (goal)
1~3
2-4
°C / Sec
°C / Sec
Soak Temp Increase rate (goal)
Flux Soak Period (Min)
.5 - 1
70
°C / Sec
Sec
Flux Soak Period (Max)
Flux Soak Temp (Min)
120
150
Sec
°C
Flux Soak Temp (max)
Time Above Liquidous (max)
190
70
°C
Sec
Time Above Liquidous (min)
Time In Target Reflow Range (goal)
50
30
Sec
Sec
Time At Absolute Peak (max)
Liquidous Temperature (SAC305)
5
218
Sec
°C
Lower Target Reflow Temperature
Upper Target Reflow Temperature
Absolute Peak Temperature
240
250
260
°C
°C
°C
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FCC AND IC REGULATORY
Model
BT830
US/FCC
SQGBT830
CANADA/IC
3147A-BT830
BT830
DVK-BT830
SQGBT830
SQGBT830
3147A-BT830
3147A-BT830
The BT830 family has been designed to operate with the antenna listed below having a maximum gain of 0.5
dBi. The required antenna impedance is 50 ohms.
Item
1
2
Part Number
AT3216-B2R7HAA
S181FL-L-RMM-2450S
Mfg.
ACX
Nearson
Type
Ceramic
Dipole
Gain (dBi)
0.5
2.0
Connector
N/A
UFL
3
4
EBL2449A1-15UFL
MAF94190
Laird
Laird
PCB Dipole
Dipole
2.0
2.0
UFL
UFL
5
WRR2400-IP04-B
(MAF94019)
Laird
Dipole
1.5
UFL
14.1 Documentation Requirements
In order to ensure regulatory compliance, when integrating the BT830 into a host device, it is necessary to meet
the documentation requirements set forth by the applicable regulatory agencies. The following sections (FCC,
Industry Canada, and European Union) outline the information that may be included in the user’s guide and
external labels for the host devices into which the BT830 is integrated.
FCC
Note:
You must place “Contains FCC ID: SQG-BT830” on the host product in such a location that it can be
seen by an operator at the time of purchase.
User’s Guide Requirements
The BT830 complies with FCC Part 15 Rules for a Modular Approval. To leverage Laird’s grant, the conditions
below must be met for the host device into which the BT830 is integrated:

The transmitter module is not co-located with any other transmitter or antenna that is capable of
simultaneous operation.
As long as the conditions above are met, further transmitter testing is typically not required. However, the OEM
integrator is still responsible for testing its end-product for any additional compliance requirements required
with this module installed, such as (but not limited to) digital device emissions and PC peripheral requirements.
IMPORTANT:
In the event that the conditions above cannot be met (for example certain device configurations
or co-location with another transmitter), then the FCC authorization is no longer considered valid
and the FCC ID cannot be used on the final product. In these circumstances, the OEM integrator
will be responsible for re-evaluating the end product (including the transmitter) and obtaining a
separate FCC authorization.
When using Laird’s FCC grant for the BT830, the integrator must include specific information in
the user’s guide for the device into which the BT830 is integrated. The integrator must not
Embedded Wireless Solutions Support Center:
http://ews-support.lairdtech.com
www.lairdtech.com/bluetooth
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BT830
Datasheet
provide information to the end user regarding how to install or remove this RF module in the
user’s manual of the device into which the BT830 is integrated. The following FCC statements
must be added in their entirety and without modification into a prominent place in the user’s
guide for the device into which the BT830 is integrated:
IMPORTANT NOTE: To comply with FCC requirements, the BT830 must not be co-located or
operating in conjunction with any other antenna or transmitter.
14.1.1.1 Federal Communication Commission Interference Statement
This equipment has been tested and found to comply with the limits for a Class B digital device,
pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection
against harmful interference in a residential installation. This equipment generates, uses, and can
radiate radio frequency energy and, if not installed and used in accordance with the instructions,
may cause harmful interference to radio communications. However, there is no guarantee that
interference will not occur in a particular installation. If this equipment does cause harmful
interference to radio or television reception, which can be determined by turning the equipment
off and on, the user is encouraged to try to correct the interference by one of the following
measures:
1. Reorient or relocate the receiving antenna.
2. Increase the separation between the equipment and receiver.
3. Connect the equipment into an outlet on a circuit different from that to which the receiver
is connected.
4. Consult the dealer or an experienced radio/TV technician for help.
FCC Caution: Any changes or modifications not expressly approved by the party responsible for
compliance could void the user's authority to operate this equipment.
This device complies with Part 15 of the FCC Rules. Operation is subject to the following two
conditions: (1) This device may not cause harmful interference, and (2) this device must accept
any interference received, including interference that may cause undesired operation.
IMPORTANT NOTE: FCC Radiation Exposure Statement:
This equipment complies with FCC radiation exposure limits set forth for an uncontrolled
environment.
Industry Canada
Note:
You must place “Contains IC ID: 3147A-BT830” on the host product in such a location that it can be
seen by an operator at the time of purchase.
RF Radiation Hazard Warning
Using higher gain antennas and types of antennas not certified for use with this product is not allowed. The
device shall not be co-located with another transmitter.
Cet avertissement de sécurité est conforme aux limites d'exposition définies par la norme CNR-102 at relative
aux fréquences radio.
Embedded Wireless Solutions Support Center:
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www.lairdtech.com/bluetooth
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BT830
Datasheet
This radio transmitter (Contains IC ID: 3147A-BT830) has been approved by Industry Canada to operate with the
antenna types listed in table above with the maximum permissible gain and required antenna impedance for
each antenna type indicated. Antenna types not included in this list, having a gain greater than the maximum
gain indicated for that type, are strictly prohibited for use with this device.
Le présent émetteur radio (Contains IC ID: 3147A-BT830) a été approuvé par Industrie Canada pour fonctionner
avec les types d'antenne énumérés ci-dessous et ayant un gain admissible maximal et l'impédance requise pour
chaque type d'antenne. Les types d'antenne non inclus dans cette liste, ou dont le gain est supérieur au gain
maximal indiqué, sont strictement interdits pour l'exploitation de l'émetteur.
Under Industry Canada regulations, this radio transmitter may only operate using an antenna of a type and
maximum (or lesser) gain approved for the transmitter by Industry Canada. To reduce potential radio
interference to other users, the antenna type and its gain should be so chosen that the equivalent isotropically
radiated power (e.i.r.p.) is not more than that necessary for successful communication.
Conformément à la réglementation d'Industrie Canada, le présent émetteur radio peut fonctionner avec une
antenne d'un type et d'un gain maximal (ou inférieur) approuvé pour l'émetteur par Industrie Canada. Dans le
but de réduire les risques de brouillage radioélectrique à l'intention des autres utilisateurs, il faut choisir le type
d'antenne et son gain de sorte que la puissance isotrope rayonnée équivalente (p.i.r.e.) ne dépasse pas
l'intensité nécessaire à l'établissement d'une communication satisfaisante.
This device complies with Industry Canada license-exempt RSS standard(s). Operation is subject to the following
two conditions: (1) this device may not cause interference, and (2) this device must accept any interference,
including interference that may cause undesired operation of the device.
Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de
licence. L'exploitation est autorisée aux deux conditions suivantes : (1) l'appareil ne doit pas produire de
brouillage, et (2) l'utilisateur de l'appareil doit accepter tout brouillage radioélectrique subi, même si le
brouillage est susceptible d'en compromettre le fonctionnement.
Embedded Wireless Solutions Support Center:
http://ews-support.lairdtech.com
www.lairdtech.com/bluetooth
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Europe: +44-1628-858-940
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BT830
Datasheet
EUROPEAN UNION REGULATORY
The BT830 has been tested for compliance with relevant standards for the EU market. BT830 modules were
tested with a 0.5 dBi chip antenna.
The OEM should consult with a qualified test house before entering their device into an EU member country to
make sure all regulatory requirements have been met for their complete device.
Reference the Declaration of Conformities listed below for a full list of the standards that the modules were
tested to. Test reports are available upon request.
15.1 EU Declarations of Conformity - BT830-SA and BT830-ST
Manufacturer:
Products:
EU Directives:
Conformity Assessment:
Laird
BT830
1999/5/EC – R&TTE
1999/519/EC
2006/95/EC – Low Voltage directive (LVD)
2004/108/EC – Electromagnetic compatibility (EMC)
2014/30/EU – EMC
Annex IV
Reference standards used for presumption of conformity:
Article Number
3.1a
3.1b
3.2
Requirement
2006/95/EC
Low voltage equipment safety
2006/95/EC
RF Exposure
2004/108/EC
Protection requirements with
respect to electromagnetic
compatibility
1999/5/EC
Means of the efficient use of
the radio frequency spectrum
Reference standard(s)
EN 60950-1:2006 +A11:2009 +A1:2010 +A12:2011
+A2:2013
EN 62311:2008
EN 62479:2010
EN 301 489-1 v1.9.2 (2011-09)
EN 301 489-17 v2.2.1 (2012-09)
EN 300 328 v1.9.1 (2015-02)
Declaration:
We, Laird, declare under our sole responsibility that the essential radio test suites have been carried out and
that the above product to which this declaration relates is in conformity with all the applicable essential
requirements of Article 3 of the EU Directive 1999/5/EC, when used for its intended purpose.
Place of Issue:
Date of Issue:
Name of Authorized Person:
Laird
W66N220 Commerce Court, Cedarburg, WI 53012 USA
tel: +1-262-375-4400 fax: +1-262-364-2649
August 2016
Thomas T Smith, Director of EMC Compliance
Signature of Authorized Person:
Embedded Wireless Solutions Support Center:
http://ews-support.lairdtech.com
www.lairdtech.com/bluetooth
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BT830
Datasheet
ORDERING INFORMATION
Part Number
BT830-SA
Description
BTv4.0 Dual Mode UART HCI Module with integrated Antenna
BT830-ST
DVK-BT830
BTv4.0 Dual Mode UART HCI Module – Trace Pin
Development Kit for BT830 Module
16.1 General Comments
This is a preliminary datasheet. Please check with Laird for the latest information before commencing a design. If
in doubt, ask.
Embedded Wireless Solutions Support Center:
http://ews-support.lairdtech.com
www.lairdtech.com/bluetooth
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BT830
Datasheet
BLUETOOTH SIG APPROVALS
17.1 Application Note: Subsystem Combinations
This application note covers the procedure for generating a new Declaration ID for a Subsystem combination on
the Bluetooth SIG website. In the instance of subsystems, a member can combine two or more subsystems to
create a complete Bluetooth End Product solution.
Subsystem listings referenced as an example:
Design Name
Owner
BT830
Laird
Embedded CE
6.0 (Host
Subsystem)
Microsoft
Corporation
Declaration
ID
D023115
Link to listing on the SIG website
B012893
https://www.bluetooth.org/tpg/QLI_viewQDL.cfm?qid=12893
https://www.bluetooth.org/tpg/QLI_viewQDL.cfm?qid=23115
17.1.1 Laird Customer Declaration ID Procedure
This procedure assumes that the member is simply combining two subsystems to create a new design, without
any modification to the existing, qualified subsystems. This is achieved by using the Listing interface on the
Bluetooth SIG website. Figure 24 shows the basic subsystem combination of a controller and host subsystem.
The Controller provides the RF/BB/LM and HCI layers, with the Host providing L2CAP, SDP, GAP, RFCOMM/SPP
and any other specific protocols and profiles existing in the Host subsystem listing. The design may also include a
Profile Subsystem.
The controller provides the RF/BB/LM and HCI layers, with the Host providing L2CAP, SDP, GAP, RFCOMM/SPP
and any other specific protocols and profiles existing in the Host subsystem listing. The design may also include a
Profile Subsystem.
D023115
Figure 24: Basic subsystem combination of a controller and host subsystem
The Qualification Process requires each company to registered as a member of the Bluetooth SIG –
http://www.bluetooth.org
The following link provides a link to the Bluetooth Registration page: https://www.bluetooth.org/login/register/
Embedded Wireless Solutions Support Center:
http://ews-support.lairdtech.com
www.lairdtech.com/bluetooth
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For each Bluetooth Design it is necessary to purchase a Declaration ID. This can be done before starting the new
qualification, either through invoicing or credit card payment. The fees for the Declaration ID will depend on
your membership status, please refer to the following webpage:
https://www.bluetooth.org/en-us/test-qualification/qualification-overview/fees
For a detailed procedure of how to obtain a new Declaration ID for your design, please refer to the following SIG
document:
https://www.bluetooth.org/DocMan/handlers/DownloadDoc.ashx?doc_id=283698&vId=317486
To start the listing, go to: https://www.bluetooth.org/tpg/QLI_SDoc.cfm.
In step 1, select the option, Reference a Qualified Design and enter the Declaration IDs of each subsystem used
in the End Product design. You can then select your pre-paid Declaration ID from the drop down menu or go to
the Purchase Declaration ID page, (please note that unless the Declaration ID is pre-paid or purchased with a
credit card, it will not be possible to proceed until the SIG invoice is paid.
Once all the relevant sections of step 1 are finished, complete steps 2, 3, and 4 as described in the help
document. Your new Design will be listed on the SIG website and you can print your Certificate and DoC.
For further information please refer to the following training material:
https://www.bluetooth.org/en-us/test-qualification/qualification-overview/listing-process-updates
Embedded Wireless Solutions Support Center:
http://ews-support.lairdtech.com
www.lairdtech.com/bluetooth
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