Rohm BD8325FVT-ME2 Built-in secondary-side driver Datasheet

Isolated DC/DC controller IC
Built-in Secondary-side Driver
with Synchronous Rectification
Active Clamp PWM Controller
BD8325FVT-M
●General Description
BD8325FVT-M is a PWM controller intended for Active
clamp, current-mode isolated switching regulator.
This controller provides control outputs for driving
primary-side MOSFET, and outputs with adjustable delay,
which can be used for driving synchronous rectifier
MOSFET on the secondary-side.
Its maximum input voltage is 20V. External startup
regulator can be set at high voltage.
●Features
■
Ideal for Active Clamp /Rest Forward/Flyback
converter
■
Current-mode Control with Dual Mode Over-Current
Protection
■
Synchronization to External Clock
■
Programmable Dead-Time (Turn-On/Turn-Off)
between MAIN and AUX MOSFET by External
Resistor
■
Have Control Outputs for Driving Primary Side
MOSFET; Have Outputs with Adjustable Time for
Driving Synchronous Rectifier MOSFET in
Secondary Side (OUT2F, OUT2R pin)
■
Programmable Oscillator Frequency and Maximum
Duty Cycle by External Resistor
■
Programmable Soft-Start Time by External
Capacitor
■
Programmable Slope Compensation by External
Resistor
■
A Variety of Protection
First Over-Current Protection (Pulse-by-Pulse mode)
Second Over-Current Protection (HICCUP mode)
VCC_UVLO (Input Under-Voltage Protection)
LINE_UVLO (Line Under-Voltage Protection)
●Applications
■
High efficiency/ large current isolated DC/DC
(VINmax=100V)
■
Cellular base station
■
Industrial power supplies
■
Car application
■
10W to 700W SMPS
●Package
TSSOP-B30
W(Typ) x D(Typ) x H(Max)
10.00mm x 7.60mm x 1.00mm
●Typical Application Circuits
VOUT
VLINE
Wake
up
REG
REG
VCC/VDD
CS
LINEUV
VREF
AUX
SS
FB
SAWH
OUT
RTON
RTOFF
RDELON
RDELOFF OUT2F
RDELSLF
RDELSLR1
RDELSLR2 OUT2R
CLKOUT
SYNC
GND
PGND
ERROR
AMP
Fig.1 Typical Application Circuit
○This product has no designed protection against radioactive rays.
○Structure：Silicon Monolithic Integrated Circuit
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2013.11.22 Rev.002
BD8325FVT
● Pin Configuration
(TOP VIEW)
GND
1
30
CLKOUT
CS2
2
29
SAWH
CS1
3
28
SYNC
LINEUV
4
27
VCC
FB
5
26
VDD
VREF
6
25
N.C.
SS/SD
7
24
AUX
RSLP
8
23
N.C.
RDELON
9
22
OUT
RDELOFF2
10
21
N.C.
RTON
11
20
OUT2F
RTOFF
12
19
N.C.
RDELSLF
13
18
OUT2R
RDELOFF1
14
17
N.C.
RDELSLR
15
16
PGND
Fig.2 Pin Configuration (TOP VIEW)
●Pin Description
No
Symbol
Description
No
Symbol
Description
1
2
GND
GND pin
16
PGND
PWR GND
CS2
17
N.C
18
OUT2R
LINEUV
HICCUP mode OCP detecting pin
Current feedback & pulse-by-pulse
OCP detecting pin
UVLO detecting pin
19
N.C
5
FB
Feedback voltage input pin
20
OUT2F
6
VREF
5V regulator output pin
21
N.C
7
SS/SD
Soft-Start time set pin
22
OUT
8
RSLP
Slope compensation ramp set pin
23
N.C
9
RDELON
OUT rise/fall timing set pin
24
AUX
10
RDELOFF2
25
N.C
11
RTON
26
VDD
Power pin of FET driver
12
RTOFF
27
VCC
Power pin of IC controller block
13
RDELSLF
AUX fall timing set pin
Switching frequency and
ON time set pin
Switching frequency and
OFF time set pin
OUT2F rise/fall timing set pin
N.C
Gate control pin for driving
freewheel NMOS in secondary side
N.C
Gate control pin for driving forward
NMOS in secondary side
N.C
Gate control pin for driving MAIN
PWM NMOS in primary side
N.C
Gate control pin for driving
active-clamp PMOS in primary side
N.C
3
CS1
4
28
SYNC
Synchronization signal input pin
14
RDELOFF1
AUX rise timing set pin
29
SAWH
Triangular wave amplitude set pin
15
RDELSLR
OUT2R rise timing set pin
30
CLKOUT
CLK output pin
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BD8325FVT
●Block Diagram
SYNC CLKOUT
VREF
SAWH
④
RSLP
RDELON
INTERNAL_REG
Current Sourse
RDELOFF1
RDELOFF2
VREF
①
⑤
③
5uA
LINEUV
LINEUVLO
1.2V
VCCUVLO
IREF
CLOCK
START
RDELSLF
END
VCC
VREFUVLO
⑥
RDELSLR
VDD
⑬
SAW
RTON
⑮
OUT
SLP
⑭
②
RTOFF
Duty0
VREF
5×ISLP
⑫
PWM
Signal
S Q
PGND
PGND
AUX
OUT2F
0.46V
CS1
R QB
OCP1
0.48V
CLKOUT
PWM offset
PGND
⑨
VREF
15uA
⑩
CS2
1.2V
R
4×R
PGND
⑪
OCP2
VCC_UVLO
VREF_UVLO
⑧
GND
XRESET
SS/SD
OCP2
OUT2R
PGND
0.5V
CLKOUT
TURN
ON/OFF
DELAY
LINEUV
⑦
SOFT START
&
SOFT STOP
15uA
TSD
FB SS/SD
Fig.3 Block Diagram
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BD8325FVT
●Description of Blocks
①Internal Power Supply
This is a regulator for powering the internal circuits via VCC. There is no direct output pin from this block.
②LDO Block
This is the 5V regulator that can provide the power supply for startup block. It should be bypassed by 0.1uF~0.47uF for
stability. The circuit is utilized for the pull-up power supply of FB pin and the power supply for SAWOSC, CLK and SS/SD
block. UVLO function is built-in (4.5V Typ). Once UVLO signal is detected, OUT, AUX, OUT2F and OUT2R pins turn L,
and the capacitor connected to SS/SD pin is also discharged instantaneously. The short current between VREF and
GND is 12mA (Typ).
③UVLO block
This is UVLO detection circuit of VCC, LINE and LDO.
The IC starts up and shuts down based on the sequence on timing chart.
When LINE UVLO signal is reset, 5uA current flows through LINEUV pin while when LINE UVLO is detected, the current
is 0uA. It is possible to adjust the HYS value through the external resistor. Moreover, VCC and VREF’s UVLO
comparators have built-in minimum of 2us noise filters for avoiding error detection.
④Timing Set Block
For simplicity of application, the adjustable function can be achieved through external resistor:
・switching timing of OUT, AUX, OUT2F and OUT2R pin
→ resistors connected from RDELON, RDELOFF1, RDELOFF2, RDELSLF, RDELSLR pin (1.6V typ) to ground
・oscillator frequency and MAX Duty
→ resistors connected from RTON and RTOFF pin (1.6V typ) to ground
・slope compensation amplitude
→ resistor connected from RSLP pin (maximum value of sawtooth wave: 2.5V (typ)) to ground
There is a built-in open detection function such that when it is activated, the outputs are terminated. This is to avoid the
pin opening caused by the incorrect mounting of external resistor.
⑤Synchronization CLK transmitter
When multiple ICs will be use, the synchronization function is implemented so that the frequency remains synchronous.
The master IC provides CLKOUT signal to the slave IC through SYNC pin, and in turn, the slave IC and master IC’s
frequency can be synchronized. The transmitter includes the I/O part of CLK and SYNC pin. By means of extracting the
frequency (at the rising edge) only, the MaxDuty can be set. There is H-side and L-side resistors connected to CLKOUT
pin with a value of 0.6kΩ.
⑥SAWOSC block
The circuit is used for generating clock, duty and slope signal. In the stand-alone operation (external synchronization
inactivated) the voltage of SAWH pin, which determines the amplitude of internal triangular wave, is 2.65V (typ). During
the external synchronization operation, the internal circuits control the SAWH voltage to synchronize with the external
clock. LVP circuit is applied to SAWH pin, and the detection and reset voltage are 1.35V (typ) and 2.6V (typ). As soon as
SAWH LVP signal is detected, OUT, AUX, OUT2F and OUT2R turn L and SS/SD is discharged instantaneously, and
SAWH is pre-charged (10kΩ).
⑦Feedback block
The voltage of SS/SD from block ⑪ is compared with FB voltage; the lower voltage enters the PWM signal generator.
⑧CS1, CS2 control block
This is the block intended for OCP detection.
When CS1 exceeds 0.48V, OCP1 signal is produced and RESET flag of Latch circuit (⑫) is activated. In addition,
OUT=L, AUX=L, OUT2F=L, OUT2R=H and the power transfer from input to output is terminated momentarily. When the
CLK enters into next cycle, the power transfer starts again. As the new cycle starts, the low-side NMOS switch connected
to CS1 pin is ON when CLKOUT=H in order to make sure that the reset signal is removed. With the series of action,
pulse-by-pulse mode OCP protection is observed as shown in the example application design.
When CS2 voltage exceeds 1.2V (typ), OCP2 signal is detected, the IC enters into SOFT_STOP mode and SS/SD pin
starts to be discharged with 15uA current. As CS2 voltage drops to 1.2V (typ) and SS/SD≦ 0.5V, the IC returns to
SOFT_START mode and starts up. Like CS1, the low side NMOS switch connected to CS2 is ON when CLKOUT=H. As
shown in the example application design, if the output is shorted to ground, then the SOFT_START mode and
SOFT_STOP mode alternate, the chip’s HICCUP OCP protection operates.
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BD8325FVT
⑨PWM signal generator
Through the comparator, CS1 related signal is compared with the lower voltage of SS/SD（⑦）and FB pin, and RESET
signal for Latch circuit (⑫) is produced. To be precise, the CS1 level +0.5V and the lower of SS/SD and FB level’s 1/5
are compared and the output pulse is entered into Latch circuit. In addition, when FB is lowered and SS/SD drops to
2.3V (typ), Duty0 signal turns H and RESET signal continues outputting, switching is terminated and Duty is turned to 0%.
Once the switching restarts, Duty0 will not turn H unless the voltage drops to the hysteresis voltage, 2.225V (typ).
⑩RESET condition generator
According to the outputs from each protection circuit, the block controls the signal as shown below:
(1) SS/SD 15uA charge, 15uA discharge, instantaneous discharge
(2) PWM signal（OUT, AUX, OUT2F, OUT2R）OFF
⑪SS charge/discharge controller
According to whether the protection operation is detected, the operation is shown as (1) ～ (3)
(1) 15uA Charge (SOFT_START) condition: when VCC UVLO, VREF UVLO, LINE UVLO, TSD, CS2, SAWH LVP
and external R-OPEN protections are not detected. SS/SD is clamped to VREF5V level.
(2) 15uA Discharge (SOFT_STOP) condition: when LINE, TSD and CS2 protections are detected.
Once detected, the signal is latched. The IC will not restore to SOFT START mode unless SS/SD is 0.5V.
(3) Instantaneous Discharge (discharge resistor R=0.5kΩ) condition: when VCC UVLO, VREF UVLO, SAWH LVP
and R-OPEN protection are detected.
⑫PWM signal latch block
The reference pulse signal of each output pulse is generated by SR-Flipflop.
SET: internal clock signal
RESET: PWM output signal or OCP1 signal or CLKOUT signal (Max Duty)
⑬Turn-on delay/Turn-off delay time generator
According to the dead-times, which are set by the external resistor on OUT, AUX, OUT2F and OUT2R pin in block ④,
dead-times are applied to PWM signal (⑫).
⑭PREDRIVER
The level of VREF5V is shifted to VDD level.
⑮POWMOS
This is the driver’s output stage for driving external MOSFET. It is constituted by NMOS and PMOS and the power supply
is VDD (absolute maximum rating is 20V).
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BD8325FVT
●Absolute Maximum Ratings
Parameter
Symbol
Limit
Unit
Input Voltage
VVCC，VVDD
20
V
OUT, AUX Voltage
VOUT VAUX
-0.3～20
V
IOUTH, IAUXH
2.5
IOUTL IAUXL
2.5
VOUT VAUX
-0.3～20
IOUT2FH， IOUT2RH
IOUT2FL, IOUT2RL
1
OUT, AUX Output Peak Current
OUT2F, OUT2R Voltage
OUT2F, OUT2R
Output Peak Current
*2
*3
V
A
1
Pin Voltage 1
Vpin1
＊1
-0.3～7
V
Pin Voltage 2
Vpin2
＊2
-0.3～20
V
Power Dissipation
*1
A
Pd
1400
*3
mＷ
Operating Temperature
Topr
-40 ～
105
℃
Storage Temperature
Tstg
-55 ～
150
℃
Junction Temperature
Tjmax
150
℃
Vpin1 applicable pin：RDELON, RDELOFF1, RDELOFF2, RDELSLF, RDELSLR, RTON, RTOFF, RSLP,
VREF, CLKOUT, SAWH, FB, SS/SD, CS1, CS2, SYNC, LINEUV.
Vpin2 applicable pin：VCC, VDD, OUT, AUX, OUT2F, OUT2R
ROHM standard board (see below)
Derate by 11.2mW /°C when operating over 25°C
●Operating Ratings
Parameter
Symbol
Min
Typ
Max
Unit
VVCC、VVDD
8
－
18
V
Power supply bypass capacitor
CVCC
4.7
－
－
μF
Oscillator frequency set resistor
(f=250kHz，66.6% Duty)
RTON
36
120
750
kΩ
RTOFF
36
120
750
kΩ
Delay time set resistor
RDEL
20
120
750
kΩ
RSLP resistor
RSLP
43
62
150
kΩ
Frequency range
FOSC
50
－
500
kHz
VREF phase compensation capacitor
CREF
0.1
－
0.47
μF
SAWH output capacitor
CSAWH
0.1
－
1.5
μF
LINEUV voltage
VLINEUV
－
－
5.5
V
Input Voltage
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BD8325FVT
●Electrical Characteristics
Parameter
Test Condition
Symbol
Min
Typ
Max
Unit
ISTARTUP
－
1
2
mA
IDD
－
3
6
mA
VUVLOOFF
8.1
8.5
8.9
ΔVUVLO
0.2
0.5
0.8
LINE UV threshold voltage
VLINEUV
1.176
1.200
1.224
V
LINE UV hysteresis current
ILINEUV
-5.5
-5
-4.5
μA
SS charge current
ISSC
-16.8
-15
-13.2
SS discharge current
ISSD
13.2
15
16.8
VREF1
4.85
5.00
5.15
V
VREF2
4.75
5.00
5.25
V
OVERALL
ICC before start up
ICC when normal
VCC<VUVLO, VCC=7.5V
VVCC=12v, VFB,VCS1,CS2=0V
Outputs not switching
VCC UVLO
UVLO Reset voltage
UVLO Hysteresis
V
LINE UVLO
SOFT_START/SOFT_STOP
μA
VREF output
VREF voltage (1)
VREF voltage (2)
TJ=25℃
0A＜IREF＜5mA
over temperature
VREF short current
VREF=0V, TJ=25℃
ISC
-21
-12
-6
mA
Reference Voltage 1 for set pin
*1
VREFR1
1.544
1.6
1.656
V
Reference Voltage 2 for set pin
*2
VREFR2
1.2
1.6
2.0
V
VRSLPH
2.25
2.5
2.75
V
TJ=25℃
FOSC
237
250
265
-40℃<TJ<105℃,
8V<VCC<18V
FOSC2
225
250
270
Dmatch
63.1
66.6
70.1
%
ISYNC
－
10
15
μA
INTERNAL SLOPE COMPENSATION（RSLP）
RSLP pin max voltage
RSLP=RTON=RTOFF=120kΩ
OSCILATOR／PWM
Oscillator frequency
（RTON = RTOFF = 120kΩ）
PWM MAX Duty
RTON = RTOFF = 120kΩ
kHz
SYNC function
SYNC input current
SYNC=5V
SYNC input High voltage
VSYNCH
3
－
5.5
V
SYNC input Low voltage
VSYNCL
－
－
0.5
V
RCLKOUTH
－
0.6
2
kΩ
RCLKOUTL
－
0.6
2
kΩ
VSAWH
2.45
2.65
2.85
V
CLKOUT output H-side ON Resistance
CLKOUT output L-side ON Resistance
SAWH output voltage
Iout = ±100uA
SYNC=0V
*1 Correspond to RDELON, RDELOFF1, RDELOFF2, RDELSLF, RDELSLR.
*2 Correspond to RTON, RTOFF. LIMIT is wider than *1.
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BD8325FVT
●Electrical Characteristics
Parameter
Test Condition
Symbol
Duty0 Reset Threshold Voltage
FB sweep up
VDUTY0A
Duty0 Detection Threshold Voltage
FB sweep down
VDUTY0B
CURRENT SENSE
Min
Typ
Max
0.083
＊
VREF
0.08
＊
VREF
0.09
＊
VREF
0.092
＊
VREF
0.089
＊
VREF
0.1
＊
VREF
0.101
＊
VREF
0.098
＊
VREF
0.110
＊
VREF
Unit
V
V
CS1 Level Shift Voltage
VLVL
V
Current Limit Voltage (1)
Cycle-by-Cycle
VCS1
0.087
＊
VREF
0.096
＊
VREF
0.105
＊
VREF
V
Current Limit Voltage (2)
Hiccup mode
VCS2
0.216
＊
VREF
0.24
＊
VREF
0.264
＊
VREF
V
OUTPUT (For driving Primary side FET，applied to OUT, AUX pin )
H-side ON Resistance
IOUT= -200mA ,VDD=10V
RMSOH
－
1
1.5
L-side ON Resistance
IOUT=+200mA ,VDD=10V
RMSOL
－
1
1.5
Ω
OUTPUT (For driving secondary side FET，applied to OUT2F，OUT2R pin )
H-side ON Resistance
IOUT= -100mA ,VDD=10V
RSROH
－
1.6
2.90
L-side ON Resistance
IOUT=+100mA ,VDD=10V
RSROL
－
1.50
2.70
TRDELON
87
175
263
ns
TRDELOFF1
17
35
53
ns
TRDELOFF2
60
120
180
ns
TRDELSLF
60
120
180
ns
TRDELSLR
30
60
90
ns
Ω
OUTPUT Delay time
Delay time 1
(OUT2R_off to OUT_on)
Delay time 2
(OUT2R_off to AUX_off)
Delay time 3
(OUT_off to AUX_on)
Delay time 4
(OUT2R_off to OUT2F_on)
Delay time 5
(OUT_off to OUT2R_on)
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TSZ22111・15・001
CLOAD=1000pF,
RG=3.6Ω
RDELON=120kΩ
CLOAD=1000pF,
RG=3.6Ω
RDELOFF1=120kΩ
CLOAD=1000pF,
RG=3.6Ω
RDELOFF2=120kΩ
CLOAD=1000pF,
RG=3.6Ω
RDELSLF=120kΩ
CLOAD=1000pF,
RG=3.6Ω
RDELSLR=120kΩ
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BD8325FVT
●Typical Performance Characteristics (Reference data)
100
3.4
3.2
90
3.0
I_VCC [mA]
Efficiency [%]
95
85
2.8
2.6
80
2.4
75
FB= SS= 0V
2.2
2.0
70
0
2
4
6
Output Current [A]
8
10
9
11
13
Fig.4 Efficiency-Output Current
19
5.5
5.4
5
5.3
5.2
VREF [V]
4
VREF [V]
17
Fig.5 I_VCC - VCC
6
3
2
5.1
5.0
4.9
4.8
4.7
1
0
15
VCC[V]
I_VREF= 0mA
4.6
0
5
10
I_VREF [mA]
15
20
Fig.6 I_VREF - VREF
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TSZ22111・15・001
4.5
-50
0
50
Temp [°C]
100
150
Fig.7 VREF - Temp
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BD8325FVT
280
69
68.5
270
68
67.5
Max Duty [%]
Frequency [kHz]
260
250
240
66.5
66
65.5
230
65
RTON= 120kΩ
RTOFF= 120kΩ
220
210
67
-50
0
50
100
Temp [°C]
RTON= 120kΩ
RTOFF= 120kΩ
64.5
64
150
-40
Fig.8 Frequency - Temp
10
60
Temp [°C]
110
Fig.9 Max Duty - Temp
3.2
100.00
3.1
3.0
10.00
TRTON (us)
TRTON [us]
2.9
2.8
2.7
2.6
2.5
1.00
2.4
2.3
2.2
0.10
10
100
RTON [kΩ]
1000
Fig.10 TRTON - RTON
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TSZ22111・15・001
RTON= 120kΩ
RTOFF= 120kΩ
-50
0
50
100
Temp [°C]
150
Fig.11 TRTON - Temp
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BD8325FVT
1.6
10.00
TRTOFF [us]
TRTOFF [us]
1.5
1.00
1.4
1.3
1.2
1.1
0.10
1
10
100
RTOFF [kΩ]
1000
RTON= 120kΩ
RTOFF= 120kΩ
-50
1.4
6
1.35
5.8
100
150
5.6
1.3
1.25
1.2
1.15
1.1
5.4
5.2
5
4.8
4.6
4.4
1.05
1
50
Temp [°C]
Fig.13 TRTOFF - RTOFF
LINEUV Current [uA]
Line UVLO Threshold Voltage [V]
Fig.12 TRTOFF - RTOFF
0
V_LINEUV= 1.3V
4.2
-50
0
50
100
Temp [°C]
150
-50
0
50
Temp [°C]
100
150
Fig.15 I_LINEUV – VLINEUV
Fig.14 LINEUV Threshold - Temp
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BD8325FVT
1.40
CS2(OCP) Threshold Voltage [V]
CS1(OCP) Threshold Voltage [V]
0.60
0.55
0.50
0.45
0.40
0.35
0.30
1.35
1.30
1.25
1.20
1.15
1.10
1.05
1.00
-50
0
50
Temp [°C]
100
150
-50
100
150
Fig.17 CS2 (OCP) Threshold - Temp
70
17.0
16.5
60
16.0
50
OUT Duty [%]
15.5
I_SS/SD[uA]
50
Temp [°C]
Fig.16 CS1 (OCP) Threshold – Temp
15.0
14.5
14.0
40
30
20
13.5
13.0
RTON= 120kΩ
RTOFF= 120kΩ
10
12.5
12.0
0
0
-50
0
50
Temp [℃]
100
150
Fig.18 I_SS/SD – Temp
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© 2012 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
2.0
2.5
3.0
FB Voltage [V]
3.5
4.0
Fig.19 OUT Duty - VFB
12/30
TSZ02201-0Q3Q0AJ83250-1-2
BD8325FVT
1000
240
200
T_RDELON [ns]
T_RDELON [ns]
220
180
100
160
140
120
10
10
100
RDELON [kΩ]
1000
100
RDELON=120kΩ
-50
0
50
100
Temp [°C]
150
Fig.21 TRDELON - Temp
Fig.20 TRDELON - RTON
80
1000
70
T_RDELOFF1 [ns]
T_RDELOFF1[ns]
60
100
50
40
30
20
RDELOFF1=120kΩ
10
10
10
100
RDELOFF1 [kΩ]
1000
Fig.22 TRDELOFF1 – RTOFF1
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© 2012 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
0
-50
0
50
Temp [°C]
100
150
Fig.23 TRDELOFF1 - Temp
13/30
TSZ02201-0Q3Q0AJ83250-1-2
BD8325FVT
1000
160
T_RDELOFF2 [ns]
T_RDELOFF2 [ns]
140
100
120
100
80
60
10
10
100
RDELOFF2 [kΩ]
40
1000
RDELOFF2=120kΩ
-50
Fig.24 TRDELOFF2 – RDELOFF2
0
50
Temp [°C]
100
150
Fig.25 TRDELOFF2 - Temp
160
1000
T_RDELSLF [ns]
T_RDELSLF[ns]
140
100
120
100
80
60
10
10
100
RDELSLF [kΩ]
1000
Fig.26 TRDELSLF - RDELSLF
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© 2012 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
40
RDELSLF=120kΩ
-50
0
50
Temp [°C]
100
150
Fig.27 TRDELSLF - RDELSLF
14/30
TSZ02201-0Q3Q0AJ83250-1-2
BD8325FVT
80
1000
70
T_RDELSLR [ns]
T_RDELSLR[ns]
60
100
50
40
30
20
10
10
10
100
RDELSLR [kΩ]
0
1000
Fig.28 TRDELSLR - RDELSLR
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© 2012 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
RDELSLF=120kΩ
-40
10
60
Temp[°C]
110
Fig.29 TRDELSLR - RDELSLR
15/30
TSZ02201-0Q3Q0AJ83250-1-2
BD8325FVT
●Functional Details and Operation
1．The setting of startup regulator
The external startup regulator is necessary in case of power supply above 18V. The output of startup regulator is
assumed to be 10-12V and the min value should be above 9V.
The maximum consumed current is 4mA.
2．Handling of N.C. pin
17, 19, 21, 23, 25 pin are NC pins. As they include GND, please don’t connect them to any node, just make them in
floating state. Adjacent pin short protection is invalid.
3．Output signal for driving NchFET / PchFET
Regarding NchFET driving signal (OUT), active-clamp PchFET driving signal (AUX) in primary side and driving
signal(OUT2F,OUT2R) in secondary side, the signals’ output resistance is small and can be adjusted by external resistor so
that the driving signal can be applied to multiple converter requirements. As expected, the spike noise becomes big when
the external resistor is small. Please use appropriate resistor to adjust the slew rate.
4．Range of external resistor connected to adjustable pin
There are several adjustable pins connected by external resistor. The resistors (RDELON, RDELOFF1, RDELOFF2,
RDELSLF, RDELSLR) can set the switching Frequency, Duty (RTON/RTOFF), Dead-time of primary and secondary side as
well as the dead-time between primary side and secondary side (P.2,3). Set the above resistors in the range as shown in
P.6. Take note that if the resistance is out of range, the IC may break or weaken because of open detection. The estimated
formulas of switching Frequency and Max Duty are shown below:
TRTON  22.22  10 12  RTON
TRTOFF  11.11 10 12  RTOFF
1
TRTON  TRTOFF
TRTON
MaxDuty 
TRTON  TRTOFF
fosc 
5．Protection function
The protection functions of the IC are the following:
・VCC UVLO
UVLO signal will reset when VCC=8.5V and will be detected when VCC=8V. There is a 2us
(min) noise filter.
・VREF UVLO
Once VCCUVLO signal is removed, VREF(5V) starts up.
UVLO signal will reset when VREF=4.6V (typ) and will be detected when VREF=4.5V (typ).
There is a 2us noise filter.
・LINE UVLO
It is determined by the resistance voltage divider between LINE and GND. When UVLO signal
has been reset, 5uA source current flows out. The current combined with external resistor
determines the hysteresis. Once LINEUV signal is detected, the IC enters into SOFT_STOP
mode and SS/SD pin starts to be discharged by 15uA current. If LINEUV signal is reset and
SS/SD≦ 0.5V, the IC starts up in SOFT START mode. The absolute maximum rating of
LINEUV pin is 7V and its’ rating of operation is 5.5V.
・SAWH_LVP
When SAWH < 1.35V (typ), SAWH_LVP signal is detected. The switching operation is stopped
and SS/SD pin is discharged instantaneously. The external capacitor connected to SAWH pin
begins to be charged quickly (several hundred mA). If the SAWH becomes 2.6V (typ),
SAWH_LVP signal will reset and the quick discharge will stop, and SS/SD will start to be
charged (soft start).
・TSD
Protects the IC from thermal runaway caused by the excessive rise of temperature. TSD
(Thermal Shutdown) protection is activated when the chip’s internal temperature is 170℃ and
the IC restarts when the temperature drops to 150℃. Like LINE UVLO, TSD will also make the
IC into SOFT STOP mode. In consideration of the power dissipation during actual use, it is
necessary to consider heat design with sufficient margin. Application design should never make
use of the thermal shutdown circuit.
・CS1, CS2
The IC has two OCP protection modes, Pulse-by-Pulse and Hiccup. The Cycle-by-Cycle mode
terminates the conduction cycle if CS1 voltage becomes 0.48V (typ). The OFF latch is reset and
conduction is ON when CLKOUT=H→L in the next cycle.
If the voltage on CS2 pin exceeds 1.2V (typ), the IC enters Hiccup mode protection. While in the
Hiccup mode, the IC enters into SOFT START mode as well as LINEUV. If the over load
condition sustains, the IC will alternate between SOFT START mode and SOFT STOP mode. If
Hiccup mode will not be used, CS2 pin should be shorted to GND pin.
・R_OPEN
When the pins of RTON, RTOFF, RDELON, RDELOFF1, RDELOFF2, RDELSLF, RDELSLR,
RSLP are OPEN, the protection is activated. OUT, AUX, OUT2F, OUT2R stop switching
instantaneously (L level) and the capacitor connected to SS/SD pin is discharged
instantaneously.
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TSZ22111・15・001
16/30
TSZ02201-0Q3Q0AJ83250-1-2
BD8325FVT
6．Operation of SS/SD pin, VREF.
When power on
When VCCUVLO signal is reset, VREF starts up and in turn, VREF UVLO and SAWH LVP
signal will also reset. If LINE UVLO, OCP and TSD signals are not detected, the capacitor
connected to SS/SD pin starts to be charged (15uA typ). The voltage of SS/SD pin is clamped
by VREF.
When power off
When LINEUV signal is detected, the capacitor connected to SS/SD pin starts to be discharged
(-15uA).
If VCC UVLO signal is detected, VREF is discharged naturally. Besides, the rise/fall time is
determined by the formula T=CV/Ichg (Idischg)
7． SOFT STOP mode
In addition to the protection condition of #6, when LINE UVLO, TSD or CS2 signal is detected, the IC enters SOFT
STOP mode. During this mode, in consideration of external device and the heat caused by CS2 detection or TSD detection,
OUT pin is OFF directly. However, AUX, OUT2F and OUT2R pins continue switching to avoid over-current and over-voltage
to happen (refer to the timing chart). Moreover, SS/SD pin is discharged by 15uA current, and the Duty of AUX, OUT2F,
OUT2R gradually decrease as SS/SD voltage decreases. When SS/SD voltage drops to 2.215Vtyp (Duty0 is detected),
AUX, OUT2F and OUT2R will stop switching. If SS/SD voltage is discharged to 0.5V and the other protections are not
activated, then SS pin starts to be charged again and the output starts up in SOFT START mode automatically.
8．PWM operation
As shown in Fig.30, Slope signal is generated through CLKOUT signal, which is generated from RTON, RTOFF and
SAWH voltage. The slope signal is buffered and outputted to RSLP pin. The current flowing through RSLP pin is
proportional to SLOPE voltage, and in addition the current is amplified 5 times and outputted to CS1 pin. The slope current
is overlapped with sensing current and converted to the voltage on external resistor RS for the stability of the peak current
mode control loop. The voltage signal is shifted up by 0.5V (CS1 Level Shift Voltage) and transmitted to INP input of PWM
comparator. However, the other input INN voltage is one fifth of FB_SS_L, which is the lower voltage within FB and SS pin.
If two input signals are compared and the PWM latch block’s reset signal is outputted, then the PWM pulse width can
be determined. If INN node voltage is above 0.46V (typ) during the sweep up of FB_SS_L, Duty0 turns H and
PWM_Latch_R turns constant H (Duty=0%). Moreover, Duty0 turns H if the INN node voltage drops to 0.445V (typ) during
the sweep down of FB_SS_L.
☆Forward Converter
Current transformer
Primary side
Secondary side
SLOPE
LINE
X5
Timin
g Ch
2.5V
SAWH
(= 2.65Vtyp)
SAW
art
0.5V
CLKOUT
RSLP
OFF Duty
SLOPE
RSLP
IFB
ISLOPE
Slope compensation current is
overlapped with feedback
current at RCS
ON Duty
△V=RS・ISLOPE
( RS >> RF )
RF
RCS
△V=RCS・IFB
Current feedback
through current sense
resistor RCS
☆Current feedback
RS
+
-
CS1
5 times of slope current that
flows through RSLP is
outputted to CS1
High frequency
noise is reduced
through filter RF/CF
☆Voltage feedback
+
-
CLKOUT
CF
R
R
CS1+0.5V
（Changed to current individually
and then overlapped）
INP
5V
Vo
FB
isolated
+
+
-
The lower of FB
and SS is buffered INN
FB_SS_L
4R
+
-
Secondary side
Photo
Cupla
15μA
Primary side
Soft Start
charge
current
15μA
PWN signal is produced through PWM Comp.
Max Duty is determined by CLKOUT.
PWM_Comp_OUT
+
OR
-
OR
Tim
CLKOUT
ing
DUTY0 COMP
R
Ch
art
PWM_Latch_R
(To PWM signal
Latch block)
CLKOUT
Duty0
OR
0.46V/ OCP(CS1 detection)
0.445V
SS/SD
Soft Down
discharge
current
PWM COMP
+
-
Soft Start
/Soft Stop
0.5V
R
When FB_SS_L×1/5 < 0.445V/0.46V,
Duty= 0%
inP
inN
1
SS_FB_L× 5
0.5V offset
PWM_
Comp_OUT
Fig.30 –Simplified Diagram of the PWM Comparator Proximity Circuit
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TSZ22111・15・001
17/30
TSZ02201-0Q3Q0AJ83250-1-2
BD8325FVT
9. Synchronization function
(1) Outline
When multiple ICs will be used, the synchronization function is implemented so that the frequency for all ICs will be
the same.
The master IC provides CLKOUT signal to the slave IC through SYNC pin, and the slave IC and master IC’s
frequency now turn to be synchronized. The transmitter includes the I/O part of CLK and SYNC pin. By means of extracting
the frequency (at the rising edge) only, the Max Duty can be set. There are H side and L side resistors connected to
CLKOUT pin, and the value is 0.6kΩ.When multiples ICs will be used, the synchronization function is implemented so that
the frequency remains synchronous. When the synchronization function operates, the master IC controls the slave ICs and
sets their Max Duty (RTON, RTOFF) and slope compensation (RSLP). The function operates when the master IC’s
CLKOUT pin is connected to slave IC’s SYNC pin.
Synchronization function operates when CLK signal exists on SYNC pin and returns to free running mode when CLK
signal disappears. It is recommended to determine whether synchronization is needed before startup. Take note that
connecting bigger capacitor to SAWH pin will reduce the jitter but prolong the settling time of synchronization. Moreover, the
output may be unstable during capture course, pay attention to it when synchronization function switches or when operation
of IC suddenly stops.
If the synchronization function is not needed, SYNC pin should be connected to GND and CLKOUT pin should be left
open.
Fig.31 Connection example of external synchronization
(2) Operation setting
Frequency setting
: Please set the slave IC’s typical frequency within -3～+0.5% of master IC’s and the external
resistor that programs the frequency should be the of ±0.5% precision.
(example) master IC : RTON=RTOFF=120kΩ(fosc= 250kHz, Max Duty=66.6%) , and the
Max Duty of slave IC is set at 62%
1
245.5kHz 
 251.25kHz
TRTON  TRTOFF
TRTON
MaxDuy 
 0.62
TRTON  TRTOFF
Thus, RTON=113kΩ、RTOFF=137kHz (fosc≒248.0kHz, MaxDuty≒62.3%)
Capacitor connected to SAWH : 0.1u～1.5uF ceramic capacitor
Although connecting big capacitor can reduce the jitter, it takes long time to stabilize the
synchronization course.
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TSZ22111・15・001
18/30
TSZ02201-0Q3Q0AJ83250-1-2
BD8325FVT
(3) Principle of operation
The RTON (determine charge current) and RTOFF (determine discharge current) pins are used to generate SAW
triangular wave, thus the switching frequency and MaxDuty can be set. The RSLP pin is used to set the slope
compensation.
fosc in stand-alone mode is determinded by SAWH voltage
and the sum of TON and TOFF
→ RTON and RTOFF（SAWH varies in external
synchronization mode）
*1 Variation of TON, TOFF is determined by RTON、RTOFF
SAWH(triangular wave top voltage)
SAW*1
SAWL(bottom voltage)≒ 0.5V
TON
SLP*2
(overlaped
with CS)
MaxDuty is determined by the ratio between TON and TOFF → the
ratio between RTON and RTOFF
TOFF
*2 Variation of TON is determined by RTON and RTSLP
The slope of SLP is determined by RSLP
Fig.32 Principle of frequency generation
The internal frequency fosc is compared with external frequency fsync, and the difference is fed back. In this way, the
synchronization like PLL is observed. If fosc＞fsync (the internal frequency fosc is faster), the capacitor connected to
SAWH pin is charged through 100kΩ, and the triangular wave top voltage is leveled up. When fosc is slower, the capacitor
is discharged so that fosc gets near to fsync. The capacitor connected to SAWH pin is used for smoothing the voltage
variation when switching, in this way stable frequency can be outputted.
Power ON
SAWH(top level) decreases
fosc＜fsync（fosc is slow）
→SAWH gets lower (amplitude gets smaller)
→frequency increase
Condition of
synchronization
is not satified
Detect SYNC
pulse
SAWH(top level) increases
fosc＞fsync（fosc is fast）
→SAWH gets higher (amplitude gets bigger)
→frequency decreases
Principle of external synchronization
SAWH_SEL
Stand-alone and
synchronization mode
alternate
2.65V typ
Stand-alone mode
External
synchronization
mode
Edge is not detected
during 2 cycles
Detect SYNC
pulse
More than 2 cycles of
synchronization is intputted
fsync<fosc
Triangular wave
High level
(≒2.65V）
110kΩ
SAWH
SAWH_SEL
(external・Internal frequency comparison)：
internal＞external・・Low(SAWH capacitor is discharged)
internal＜external・・High(SAWH capacitor is charged)
Stand-alone mode fosc is
slower than fsync
Stand-alone mode fosc is
faster than fsync
110kΩ
SAWH_SEL
Master IC detects the edge 3
times of 4 cycles
SAWH：High level of triangular wave.
The node is charged/discharged through the current which
flows through 110kΩ and is controlled by the H/L signal of
SAWH_SEL. SAWH is used as the high level reference
voltage.
Charge SAWH
capacitor
Discharge SAWH
capacitor
Amplitude of
sawtooth wave
gets bigger,
fosc decreases
Amplitude of
sawtooth wave
gets smaller,
fosc increases
Operation chart of synchronization
Related circuit of external synchronization
Fig.33 Principle of external synchronization
9. VCC pin and VDD pin
Connect VDD to VCC with decoupling capacitor. If the resistance is added between VCC pin and VDD pin to prevent
conduction noise, use resistance less than 50Ω.
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TSZ22111・15・001
19/30
TSZ02201-0Q3Q0AJ83250-1-2
BD8325FVT
●Design of Pattern Diagram
(1) The switching voltages on the line of OUT, AUX, OUT2F, OUT2R, SYNC, CLKOUT, (SYNC) pin and the application
board’s switching line are the noise source. Please avoid the sensitive line of FB, LINEUV, CS1, CS2, RSLP, RDELON,
RDELOFF2, RTON, RTOFF, RDELSLF, RDELOFF1, RDELSLR, SS, SAWH and VREF from being wired in parallel
with noise source line. Furthermore, place the external device near the sensitive pin and the GND of external device
should be connected to the low noise GND.
(2) For reducing the parasitic inductance of wire from OUT, AUX, OUT2F, OUT2R to FET gate line, it is better to make the
wire as short as possible. Also, As switching current occurs while driving the FET gate, the current loop area should be
made small.
(3) VCC is the power supply for IC internal analog circuits and it should be immune to external noise. On the one hand,
VDD is the power supply for the output driver and switching noise occurs when the driver works. Therefore, VCC and
VDD should not use the common input capacitor, but individual input capacitor near their pins. Additionally, the GND of
input capacitor connected to VCC pin should be connected to low noise GND. Likewise; the GND pin of the IC also
should be connected to low noise GND.
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TSZ22111・15・001
20/30
TSZ02201-0Q3Q0AJ83250-1-2
BD8325FVT
●Startup timing chart
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TSZ22111・15・001
21/30
TSZ02201-0Q3Q0AJ83250-1-2
BD8325FVT
●SOFT-STOP and Restart Timing Chart
LINE
LINE UVLO
(LINEUV < 1.2V)
or
CS2
CS2 > 1.2V
(TSD is the same)
SOFT_STOP
SS_SD
Duty0 detection
2.225V
If SS< 0.5V, LINEUV > 1.2V
and CS2 < 0.5V
Soft Start begain
(0.5V)
Duty0 is reseted
2.3V
SOFT_START
CLK
(internal
signal)
OUT
According to the slope of SS/SD,
PWM Duty gets longer
According to the slope of SS/SD,
PWM Duty gets shorter
AUX
OUT2F
When SSƒ
2.225V,
AUX,OUT2F,OUT2R
stop switching
If SS< 0.5V, LINEUV > 1.2V and
CS2 < 0.5V ,OUT2R= H• ¨L
OUT2R
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TSZ22111・15・001
22/30
TSZ02201-0Q3Q0AJ83250-1-2
BD8325FVT
●Adjustable Timing Through External Resistor
Fosc = 1 / ( TRTON + TRTOFF )
250kHz typ.
CLKOUT
①-2 TRTOFF
①-1 TRTON
2666n
1333n
PWM signal
(IC internal signal）
②TRDELON
OUT
175n
(NchFET: High=ON)
③TRDELOFF1
②TRDELON´
175n
③TRDELOFF2
35n
AUX
120n
(PchFET: Low=ON)
⑤TRDELSLF
120n
OUT2F
⑤TRDELSLF´
120n
(NchFET: High=ON)
⑥TRDELSLR
60n
OUT2R
(NchFET: High=ON)
* The times above are under the condition:
RTON=RTOFF=RDELON=RDELOFF1=RDELOFF2=RDELSLF=RDELSLR=120kΩ
■ Adjustable timing by external resistor
① TPERIOD ・・・ PWM frequency. Time ① can be adjusted by RRTON，RRTOFF
② TRDELON ・・・ M2R in secondary side turns off ⇒ MMAIN in primary side turns on DELAY TIME(TRDELON´
and TRDELON are linked）
③ TRDELOFF1 ・・・ M2R in secondary side turns off ⇒ MAUX in primary side turns off DELAY TIME
④
TRDELOFF2 ・・・ MMAIN in primary side turns off ⇒ MAUX in primary side turns on DELAY TIME
⑤ TRDELSLF ・・・ M2R in secondary side turns off ⇒ M2F in secondary side turns on DELAY TIME
（TRDELSLF´ and TRDELSLF are linked）
⑥ TRDELSLR ・・・ MMAIN in primary side turns off ⇒ M2R in secondary side turns on DELAY
TIME
primary side
secondary side
Input
Output
LINE
（48V）
Nch
Pch
Nch
(
M2R
)
controlled by
OUT2R
Nch
)(
MAUX
Controlled
by AUX
(
)
MMAIN
controlled
by OUT
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TSZ22111・15・001
M2F
controlled
by OUT2F
(
23/30
)
TSZ02201-0Q3Q0AJ83250-1-2
Low : Active
ON_OFF
GND_PRI
LINE_P
2.2u
2.2u
2.2u
10k
24/30
24k
51k
47k
75k
75k
100k
43k
62k
1u
0.1u
100p
24
24
1.5k
51k 30k
3.3k
820p
470p
RUE002N02
100k
2.2u
RF071M2S
4.3
1k
110
(0)
110
( )
1k
CEEH55S100B
15
SS/SD
RSLP
RDELON
RDELOFF2
RTON
RTOFF
RDESLF
RDELOFF1
RDELSLR
VREF
GND
CS2
CS1
LINEUV
FB
1 U1
30
VREF
10u
(0)
(0)
6.2
10k
SYNC
CLKOUT
6.2
10k
RJK1557DPA RJK1557DPA
CONTROLLER
16
PGND
OUT2R
OUT2F
OUT
AUX
CLKOUT
SAWH
SYNC
VCC
VDD
0.47u
10u
3.6
0.1u
RB160 10k
VA-40
SI7119DN
0.1u
PRIMARY DRIVER
REG
0.1u
0.1u
1u
EE1101
EE1101
PS2801-1
RF071M2S
RF071M2S
TFZ 12B
68k
2.2m
SECONDARY
DRIVER
43
43
13k
1.5k
LM317LIPK
10k
10k
2SCR372P
20
TMAIN
Fig.34 Application Circuit
RF071M2S
1u
2SCR372P
RF071M2S
VIN
CONTROLLER
POWER SUPPLY
PRIMARY
ISOLATION
CURRENT
SENSE
BD8325FVT
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TSZ22111・15・001
2.2uF
3.9k
3.9k
RB160
VA-40
RB160
VA-40
0.1u
0.1u
10
330
470p
IMZ4
2200p
330
10k
BA2904FVM
91k
IMZ4
RJK0854DPB
SECONDARY
+
-
LINE INPUT
0.1u
(0)
(0)
10k
RJK0854DPB
2SCR372P
TL432BIDBZR
6.2k
2200p
1u
0.47u
4.7k
FEED BACK
47k
3.3k
RF071M2S
10u 10u 16SVPF560M
TLZ 10B
1u
10
RF071M2S
SECONDARY OUTPUT
1000p
11
12u
10k
18k
20k
GND_SEC
VOUT
BD8325FVT
●Typical Application Design
A forward converter application design is shown in Fig.31.Input Voltage ranges from 36~70V, output current from 0~8A and
Output Voltage is 12V. The turns-ratio of main transformer is 1.5:1. Switching frequency is 310KHz, Max Duty is 66.6%.
Regarding to over-current protection, CS1 and CS2 are all set to Io≒ 9A.
TSZ02201-0Q3Q0AJ83250-1-2
BD8325FVT
●Power Dissipation
The thermal derating characteristic is shown below.
It is necessary to design the system requirements and board layout so that the junction temperature does not exceed
150℃.
In practical use, take into consideration that the temperature rise may likely to occur because of the heat dissipation of
different PCB layout and other heat source.
< PCB board >
FR4 (glass epoxy) substrate
：
Copper foil surface
：
2,3 layer, back side copper foil ：
114.3mm×76.2mm×1.6mmt
IC land pattern + test leads
74.2mm×74.2mm
1.6
1.4W
Power Dissipation : Pd （W)
1.4
1.2
1
0.8
0.6
0.4
0.2
0
0
25
50
75
100
125
150
Ambient Temperature: Ta(℃)
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BD8325FVT
●I/O Equivalent Circuit
Pin No.
Pin Name
1
GND
16
PGND
18
OUT2R
20
OUT2F
22
OUT
24
AUX
26
VDD
2
CS2
3
CS1
Pin Equivalent Circuit
VDD
OUT
AUX
OUT2F
OUT2R
GND
PGND
Internal
Power Supply
5.2V
CS1
CS2
4
LINEUV
Internal
Power Supply
5.2V
LINEUV
5
FB
VCC
FB
6
VREF
27
VCC
30
CLKOUT
VCC
VREF
CLKOUT
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TSZ02201-0Q3Q0AJ83250-1-2
BD8325FVT
Pin No.
Pin Name
7
SS/SD
Pin Equivalent Circuit
Internal VREF
Power Supply
5.2V
SS/SD
8
RSLP
Internal
Power Supply
5.2V
RSLP
9
RDELON
10
RDELOFF2
11
RTON
12
RTOFF
13
RDELSLF
14
RDELOFF1
15
RDELSLR
28
SAWH
Internal
Power Supply
5.2V
RDELON
RDELOFF1
RDELOFF2
RDELSLF
RDELSLR
RTON
RTOFF
VREF
Internal
Power Supply
5.2V
SAWH
27
SYNC
VREF
SYNC
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TSZ02201-0Q3Q0AJ83250-1-2
BD8325FVT
●Operational Notes
1)
Absolute Maximum Rating
Operating the IC over the absolute maximum ratings may damage the IC. In addition, it is impossible to predict all
destructive situations such as short-circuit modes, open circuit modes, etc. Therefore, it is important to consider circuit
protection measures, like adding a fuse, in case the IC is operated in a special mode exceeding the absolute maximum
ratings.
2)
Power Supply Lines
Back EMF due to the output coil may result to a return current into the IC. Caution should be taken by putting capacitor
between power supply and GND as a pathway for the return current. Consider the effect of temperature and aging on
the capacitance value when using electrolytic capacitors. If the connected power supply does not have sufficient
current absorption capacity, the return current will cause the voltage on the power supply line to rise and may exceed
the absolute maximum ratings. Therefore, it is important to consider circuit protection measures such as adding a
voltage clamp diode between the power supply and GND pins.
3)
GND potential
The potential of GND pin must be the lowest potential of all pins of the IC at all operating conditions. Ensure that no
pins are at a potential below the ground pin at any time, even during transient condition. In particular, when the noise
caused by the switching of OUT, AUX, OUT2F and OUT2R is big, please insert serial resistor to reduce the slew rate.
As the output resistance of the IC is small, please contact ROHM for detailed information about the resistor to be
inserted.
4)
Heat Design
Use a thermal design that allows for a sufficient margin by taking into account the permissible power dissipation (Pd) in
actual operating conditions
5)
Pin Shorting and Incorrect Mounting
Be careful when mounting the IC on printed circuit boards. The IC may be damaged if it is mounted in a wrong
orientation or if pins are shorted together. Short circuit may be caused by conductive particles caught between the pins.
6)
Operation in Strong Magnetic Fields
Be mindful when operating in the presence of strong magnetic fields, as it may cause the IC to malfunction.
7)
Capacitor between VREF and GND
The capacitor between VREF and GND should be above 0.1uF. For suppressing the noise and reducing the fluctuation
on VREF line, please set the capacitor to appropriate value. Furthermore, VREF should not be open; otherwise the
VREF output will be unstable.
8)
Testing on application boards
When testing the IC on an application board, connecting a capacitor directly to a low-impedance output pin may subject
the IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply should
always be turned off completely before connecting or removing it from the test setup during the inspection process. To
prevent damage from electro static discharge, ground the IC during assembly and use similar precautions during
transport and storage.
9)
Input Pins
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them
isolated. P-N junctions are formed at the intersection of the P layers with the N layers of other elements, creating a
parasitic diode or transistor. For example (refer to figure below):
When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.
When GND > Pin B, the P-N junction operates as a parasitic transistor.
Parasitic diodes inevitably occur in the structure of the IC. The operation of parasitic diodes can result in mutual
interference among circuits, operational faults, or physical damage. Therefore, conditions that cause these diodes to
operate, such as applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate) should be
avoided.
Resistor
Transistor (NPN)
Pin A
Pin B
Pin A
N
P+
N
P+
P
N
C
Pin B
B
E
Parasitic
element
N
P+
N
P substrate
Parasitic element
GND
P+
P
B
N
E
P substrate
Parasitic element
GND
C
Parasitic
GND
GND element
Other adjacent elements
Example of monolithic IC structure
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TSZ02201-0Q3Q0AJ83250-1-2
BD8325FVT
10)
Ground wiring pattern
When using both small-signal and large-current GND traces, the two ground traces should be routed separately but
connected to a single ground at the reference point of the application board to avoid fluctuations in the small-signal
ground caused by large currents. Also ensure that the GND traces of external components do not cause variations on
the GND voltage. The power supply and ground lines must be as short and thick as possible to reduce line impedance.
11)
Thermal shutdown circuit
The IC incorporates a built-in thermal shutdown circuit, which is designed to turn off the IC when the internal
temperature of the IC reaches a specified value. It is not designed to protect the IC from damage or guarantee its
operation. Do not continue to operate the IC after this function is activated. Do not use the IC in conditions where this
function will always be activated.
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BD8325FVT
●Ordering part number
B
D
8
3
2
5
Parts. No
F
V
T
-
Package
ME 2
Packaging and forming specification
E2: Embossed tape and reel
●Physical Dimension・Tape and Reel Information
TSSOP-B30
<Tape and Reel Information＞
(Max 10.35(Include. BURR)
Tape
Embossed carrier tape
Quantity
2000pcs
E2
(The Direction is the 1pin of product is at the upper left when you hold
reel on the left hand and you pull out the tape on the right hand)
Direction of feed
Direction of feed
Reel
(Unit : mm)
1Pin
●Marking Diagram
TSSOP-B30 (TOP VIEW)
Part Number Marking
BD8325FVT
LOT Number
1PIN MARK
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Datasheet
Notice
Precaution on using ROHM Products
1.
If you intend to use our Products in devices requiring extremely high reliability (such as medical equipment (Note 1),
aircraft/spacecraft, nuclear power controllers, etc.) and whose malfunction or failure may cause loss of human life,
bodily injury or serious damage to property (“Specific Applications”), please consult with the ROHM sales
representative in advance. Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way
responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of any
ROHM’s Products for Specific Applications.
(Note1) Medical Equipment Classification of the Specific Applications
JAPAN
USA
EU
CHINA
CLASSⅢ
CLASSⅡb
CLASSⅢ
CLASSⅢ
CLASSⅣ
CLASSⅢ
2.
ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor
products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate
safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which
a failure or malfunction of our Products may cause. The following are examples of safety measures:
[a] Installation of protection circuits or other protective devices to improve system safety
[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure
3.
Our Products are not designed under any special or extraordinary environments or conditions, as exemplified below.
Accordingly, ROHM shall not be in any way responsible or liable for any damages, expenses or losses arising from the
use of any ROHM’s Products under any special or extraordinary environments or conditions. If you intend to use our
Products under any special or extraordinary environments or conditions (as exemplified below), your independent
verification and confirmation of product performance, reliability, etc, prior to use, must be necessary:
[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents
[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust
[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,
H2S, NH3, SO2, and NO2
[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves
[e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items
[f] Sealing or coating our Products with resin or other coating materials
[g] Use of our Products without cleaning residue of flux (even if you use no-clean type fluxes, cleaning residue of
flux is recommended); or Washing our Products by using water or water-soluble cleaning agents for cleaning
residue after soldering
[h] Use of the Products in places subject to dew condensation
4.
The Products are not subject to radiation-proof design.
5.
Please verify and confirm characteristics of the final or mounted products in using the Products.
6.
In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse. is applied,
confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power
exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect
product performance and reliability.
7.
De-rate Power Dissipation (Pd) depending on Ambient temperature (Ta). When used in sealed area, confirm the actual
ambient temperature.
8.
Confirm that operation temperature is within the specified range described in the product specification.
9.
ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in
this document.
Precaution for Mounting / Circuit board design
1.
When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product
performance and reliability.
2.
In principle, the reflow soldering method must be used; if flow soldering method is preferred, please consult with the
ROHM representative in advance.
For details, please refer to ROHM Mounting specification
Notice - SS
© 2014 ROHM Co., Ltd. All rights reserved.
Rev.002
Datasheet
Precautions Regarding Application Examples and External Circuits
1.
If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the
characteristics of the Products and external components, including transient characteristics, as well as static
characteristics.
2.
You agree that application notes, reference designs, and associated data and information contained in this document
are presented only as guidance for Products use. Therefore, in case you use such information, you are solely
responsible for it and you must exercise your own independent verification and judgment in the use of such information
contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses
incurred by you or third parties arising from the use of such information.
Precaution for Electrostatic
This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper
caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be
applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,
isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).
Precaution for Storage / Transportation
1.
Product performance and soldered connections may deteriorate if the Products are stored in the places where:
[a] the Products are exposed to sea winds or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2
[b] the temperature or humidity exceeds those recommended by ROHM
[c] the Products are exposed to direct sunshine or condensation
[d] the Products are exposed to high Electrostatic
2.
Even under ROHM recommended storage condition, solderability of products out of recommended storage time period
may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is
exceeding the recommended storage time period.
3.
Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads
may occur due to excessive stress applied when dropping of a carton.
4.
Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of
which storage time is exceeding the recommended storage time period.
Precaution for Product Label
QR code printed on ROHM Products label is for ROHM’s internal use only.
Precaution for Disposition
When disposing Products please dispose them properly using an authorized industry waste company.
Precaution for Foreign Exchange and Foreign Trade act
Since our Products might fall under controlled goods prescribed by the applicable foreign exchange and foreign trade act,
please consult with ROHM representative in case of export.
Precaution Regarding Intellectual Property Rights
1.
All information and data including but not limited to application example contained in this document is for reference
only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any
other rights of any third party regarding such information or data. ROHM shall not be in any way responsible or liable
for infringement of any intellectual property rights or other damages arising from use of such information or data.:
2.
No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any
third parties with respect to the information contained in this document.
Other Precaution
1.
This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.
2.
The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written
consent of ROHM.
3.
In no event shall you use in any way whatsoever the Products and the related technical information contained in the
Products or this document for any military purposes, including but not limited to, the development of mass-destruction
weapons.
4.
The proper names of companies or products described in this document are trademarks or registered trademarks of
ROHM, its affiliated companies or third parties.
Notice - SS
© 2014 ROHM Co., Ltd. All rights reserved.
Rev.002
Datasheet
General Precaution
1. Before you use our Pro ducts, you are requested to care fully read this document and fully understand its contents.
ROHM shall n ot be in an y way responsible or liabl e for fa ilure, malfunction or acci dent arising from the use of a ny
ROHM’s Products against warning, caution or note contained in this document.
2. All information contained in this docume nt is current as of the issuing date and subj ect to change without any prior
notice. Before purchasing or using ROHM’s Products, please confirm the la test information with a ROHM sale s
representative.
3.
The information contained in this doc ument is provi ded on an “as is” basis and ROHM does not warrant that all
information contained in this document is accurate an d/or error-free. ROHM shall not be in an y way responsible or
liable for an y damages, expenses or losses incurred b y you or third parties resulting from inaccur acy or errors of or
concerning such information.
Notice – WE
© 2014 ROHM Co., Ltd. All rights reserved.
Rev.001
Datasheet
BD8325FVT-M - Web Page
Part Number
Package
Unit Quantity
Minimum Package Quantity
Packing Type
Constitution Materials List
RoHS
BD8325FVT-M
TSSOP-B30
2000
2000
Taping
inquiry
Yes