AD AD7689BCPZ 16-bit, 4-channel/8-channel, 250 ksps pulsar adc Datasheet

16-Bit, 4-Channel/8-Channel,
250 kSPS PulSAR ADC
AD7682/AD7689
FEATURES
APPLICATIONS
Battery-powered equipment
Medical instruments: ECG/EKG
Mobile communications: GPS
Personal digital assistants
Power line monitoring
Data acquisition
Seismic data acquisition systems
Instrumentation
Process control
FUNCTIONAL BLOCK DIAGRAM
0.5V TO 4.096V
0.1µF
REFIN
REF
BAND GAP
REF
VDD
1.8V
VIO TO
VDD
AD7682/
AD7689
TEMP
SENSOR
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
2.7V TO 5V
0.5V TO VDD
22µF
CNV
16-BIT SAR
ADC
MUX
ONE-POLE
LPF
SPI SERIAL
INTERFACE
SCK
SDO
DIN
SEQUENCER
COM
07353-001
16-bit resolution with no missing codes
4-channel (AD7682)/8-channel (AD7689) multiplexer with
choice of inputs
Unipolar single ended
Differential (GND sense)
Pseudobipolar
Throughput: 250 kSPS
INL: ±0.5 LSB typical, ±1.5 LSB maximum (±23 ppm or FSR)
Dynamic range: 93.8 dB
SINAD: 92.5 dB @ 20 kHz
THD: −100 dB @ 20 kHz
Analog input range: 0 V to VREF with VREF up to VDD
Multiple reference types
Internal selectable 2.5 V or 4.096 V
External buffered (up to 4.096 V)
External (up to VDD)
Internal temperature sensor
Channel sequencer, selectable 1-pole filter, busy indicator
No pipeline delay, SAR architecture
Single-supply 2.7 V to 5.5 V operation with
1.8 V to 5 V logic interface
Serial interface compatible with SPI, MICROWIRE,
QSPI, and DSP
Power dissipation
3.5 mW @ 2.5 V/200 kSPS
12 mW @ 5 V/250 kSPS
Standby current: 50 nA
20-lead 4 mm × 4 mm LFCSP package
GND
Figure 1.
Table 1. Multichannel 14-/16-Bit PulSAR® ADC
Type
14-Bit
16-Bit
16-Bit
Channels
8
4
8
250 kSPS
AD7949
AD7682
AD7689
500 kSPS
AD7699
ADC Driver
ADA4841-x
ADA4841-x
ADA4841-x
GENERAL DESCRIPTION
The AD7682/AD7689 are 4-channel/8-channel, 16-bit, charge
redistribution successive approximation register (SAR) analogto-digital converters (ADCs) that operate from a single power
supply, VDD.
The AD7682/AD7689 contain all components for use in a
multichannel, low power data acquisition system, including a
true 16-bit SAR ADC with no missing codes; a 4-channel
(AD7682) or 8-channel (AD7689), low crosstalk multiplexer
useful for configuring the inputs as single ended (with or
without ground sense), differential, or bipolar; an internal low
drift reference (selectable 2.5 V or 4.096 V) and buffer; a
temperature sensor; a selectable one-pole filter; and a sequencer
that is useful when channels are continuously scanned in order.
The AD7682/AD7689 use a simple SPI interface for writing to
the configuration register and receiving conversion results. The
SPI interface uses a separate supply, VIO, which is set to the
host logic level. Power dissipation scales with throughput.
Each AD7682/AD7689 is housed in a tiny 20-lead LFCSP with
operation specified from −40°C to +85°C.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2008 Analog Devices, Inc. All rights reserved.
AD7682/AD7689
TABLE OF CONTENTS
Features .............................................................................................. 1
Typical Connection Diagrams.................................................. 17
Applications....................................................................................... 1
Analog Inputs ............................................................................. 18
Functional Block Diagram .............................................................. 1
Driver Amplifier Choice ........................................................... 19
General Description ......................................................................... 1
Voltage Reference Output/Input .............................................. 20
Revision History ............................................................................... 2
Power Supply............................................................................... 21
Specifications..................................................................................... 3
Supplying the ADC from the Reference.................................. 21
Timing Specifications....................................................................... 6
Digital Interface .............................................................................. 22
Absolute Maximum Ratings............................................................ 8
Configuration Register, CFG .................................................... 22
ESD Caution.................................................................................. 8
Pin Configurations and Function Descriptions ........................... 9
Read/Write Spanning Conversion Without a
Busy Indicator............................................................................. 24
Typical Performance Characteristics ........................................... 11
Read/Write Spanning Conversion with a Busy Indicator..... 25
Terminology .................................................................................... 14
Application Hints ........................................................................... 26
Theory of Operation ...................................................................... 15
Layout .......................................................................................... 26
Overview...................................................................................... 15
Evaluating AD7682/AD7689 Performance ............................ 26
Converter Operation.................................................................. 15
Outline Dimensions ....................................................................... 27
Transfer Functions...................................................................... 16
Ordering Guide .......................................................................... 27
REVISION HISTORY
5/08—Revision 0: Initial Version
Rev. 0 | Page 2 of 28
AD7682/AD7689
SPECIFICATIONS
VDD = 2.5 V to 5.5 V, VIO = 2.3 V to VDD, VREF = VDD, all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
RESOLUTION
ANALOG INPUT
Voltage Range
Absolute Input Voltage
Analog Input CMRR
Leakage Current at 25°C
Input Impedance 1
THROUGHPUT
Conversion Rate
Full Bandwidth 2
¼ Bandwidth2
Transient Response
ACCURACY
No Missing Codes
Integral Linearity Error
Differential Linearity Error
Transition Noise
Gain Error 4
Gain Error Match
Gain Error Temperature Drift
Offset Error4
Offset Error Match
Offset Error Temperature Drift
Power Supply Sensitivity
AD7682B/AD7689B
Typ
Max
Conditions/Comments
Min
16
Unipolar mode
Bipolar mode
Positive input, unipolar and bipolar modes
Negative or COM input, unipolar mode
Negative or COM input, bipolar mode
fIN = 250 kHz
Acquisition phase
0
−VREF/2
−0.1
−0.1
VREF/2 − 0.1
VDD = 4.5 V to 5.5 V
VDD = 2.7 V to 4.5 V
VDD = 2.3 V to 2.7 V
VDD = 4.5 V to 5.5 V
VDD = 2.7 V to 4.5 V
VDD = 2.3 V to 2.7 V
Full-scale step, full bandwidth
Full-scale step, ¼ bandwidth
0
0
0
0
0
0
16
−1.5
−1
REF = VDD = 5 V
−30
−2
−2
VDD = 5 V ± 5%
Rev. 0 | Page 3 of 28
VREF/2
68
1
+VREF
+VREF/2
VREF + 0.1
+0.1
VREF/2 + 0.1
V
V
dB
nA
250
200
190
60
50
47
1.8
14.5
±0.5
±0.25
0.5
±2
±0.5
±1
±2
±0.5
±1
±1.5
Unit
Bits
+1.5
+1.5
+30
+2
+2
kSPS
kSPS
kSPS
kSPS
kSPS
kSPS
μs
μs
Bits
LSB 3
LSB
LSB
LSB
LSB
ppm/°C
LSB
LSB
ppm/°C
LSB
AD7682/AD7689
Parameter
AC ACCURACY 5
Dynamic Range
Signal-to-Noise
SINAD
Total Harmonic Distortion
Spurious-Free Dynamic Range
Channel-to-Channel Crosstalk
SAMPLING DYNAMICS
−3 dB Input Bandwidth
Aperture Delay
INTERNAL REFERENCE
REF Output Voltage
REFIN Output Voltage 7
REF Output Current
Temperature Drift
Line Regulation
Long-Term Drift
Turn-On Settling Time
EXTERNAL REFERENCE
Voltage Range
Current Drain
TEMPERATURE SENSOR
Output Voltage 8
Temperature Sensitivity
DIGITAL INPUTS
Logic Levels
VIL
VIH
IIL
IIH
DIGITAL OUTPUTS
Data Format 9
Pipeline Delay 10
VOL
VOH
Conditions/Comments
Min
AD7682B/AD7689B
Typ
Max
Unit
93.8
93.5
92.3
88.8
92.5
33.5
dB 6
dB
dB
dB
dB
dB
90
87
91
88.4
−100
110
−125
dB
dB
dB
dB
dB
Selectable
VDD = 5 V
0.425
1.7
2.5
MHz
ns
2.5 V, @ 25°C
4.096 V, @ 25°C
2.5 V, @ 25°C
4.096 V, @ 25°C
2.490
4.086
2.500
4.096
1.2
2.3
±300
±10
±15
50
5
fIN = 20 kHz, VREF = 5 V
fIN = 20 kHz, VREF = 4.096 V internal REF
fIN = 20 kHz, VREF = 2.5 V internal REF
fIN = 20 kHz, VREF = 5 V
fIN = 20 kHz, VREF = 5 V
−60 dB input
fIN = 20 kHz, VREF = 4.096 V internal REF
fIN = 20 kHz, VREF = 2.5 V internal REF
fIN = 20 kHz
fIN = 20 kHz
fIN = 100 kHz on adjacent channel(s)
92.5
91
87.5
91
VDD = 5 V ± 5%
1000 hours
CREF = 10 μF
REF input
REFIN input (buffered)
250 kSPS, REF = 5 V
2.510
4.106
V
V
V
V
μA
ppm/°C
ppm/V
ppm
ms
VDD + 0.3
VDD − 0.2
50
V
V
μA
283
1
mV
mV/°C
0.5
0.5
@ 25°C
−0.3
0.7 × VIO
−1
−1
ISINK = +500 μA
ISOURCE = −500 μA
VIO − 0.3
Rev. 0 | Page 4 of 28
+0.3 × VIO
VIO + 0.3
+1
+1
V
V
μA
μA
0.4
V
V
AD7682/AD7689
Parameter
POWER SUPPLIES
VDD
VIO
Standby Current 11, 12
Power Dissipation
Energy per Conversion
TEMPERATURE RANGE 13
Specified Performance
Conditions/Comments
Min
Specified performance
Specified performance
Operating range
VDD and VIO = 5 V, @ 25°C
VDD = 2.5 V, 100 SPS throughput
VDD = 2.5 V, 100 kSPS throughput
VDD = 2.5 V, 200 kSPS throughput
VDD = 5 V , 250 kSPS throughput
VDD = 5 V, 250 kSPS throughput with internal reference
2.3
2.3
1.8
TMIN to TMAX
−40
1
AD7682B/AD7689B
Typ
Max
5.5
VDD + 0.3
VDD + 0.3
50
1.7
1.75
3.5
12.5
15.5
50
2.1
4.1
15.9
19.2
+85
Unit
V
V
V
nA
μW
mW
mW
mW
mW
nJ
°C
See the Analog Inputs section.
The bandwidth is set with the configuration register
3
LSB means least significant bit. With the 5 V input range, one LSB is 76.3 μV.
4
See the Terminology section. These specifications include full temperature range variation but not the error contribution from the external reference.
5
With VDD = 5 V, unless otherwise noted.
6
All specifications expressed in decibels are referred to a full-scale input FSR and tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
7
This is the output from the internal band gap.
8
The output voltage is internal and present on a dedicated multiplexer input.
9
Unipolar mode: serial 16-bit straight binary.
Bipolar mode: serial 16-bit twos complement.
10
Conversion results available immediately after completed conversion.
11
With all digital inputs forced to VIO or GND as required.
12
During acquisition phase.
13
Contact an Analog Devices, Inc., sales representative for the extended temperature range.
2
Rev. 0 | Page 5 of 28
AD7682/AD7689
TIMING SPECIFICATIONS
VDD = 4.5 V to 5.5 V, VIO = 2.3 V to VDD, all specifications TMIN to TMAX, unless otherwise noted.
Table 3. 1
Parameter
Conversion Time: CNV Rising Edge to Data Available
Acquisition Time
Time Between Conversions
CNV Pulse Width
Data Write/Read During Conversion
SCK Period
SCK Low Time
SCK High Time
SCK Falling Edge to Data Remains Valid
SCK Falling Edge to Data Valid Delay
VIO Above 4.5 V
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
CNV Low to SDO D15 MSB Valid
VIO Above 4.5 V
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
CNV High or Last SCK Falling Edge to SDO High Impedance
CNV Low to SCK Rising Edge
DIN Valid Setup Time from SCK Falling Edge
DIN Valid Hold Time from SCK Falling Edge
1
Symbol
tCONV
tACQ
tCYC
tCNVH
tDATA
tSCK
tSCKL
tSCKH
tHSDO
tDSDO
Min
Typ
Max
2.2
1.8
4
10
1.4
15
7
7
4
Unit
μs
μs
μs
ns
μs
ns
ns
ns
ns
16
17
18
19
ns
ns
ns
ns
15
17
18
22
25
ns
ns
ns
ns
ns
ns
ns
ns
tEN
tDIS
tCLSCK
tSDIN
tHDIN
See Figure 2 and Figure 3 for load conditions.
Rev. 0 | Page 6 of 28
10
4
4
AD7682/AD7689
VDD = 2.5 V to 4.5 V, VIO = 2.3 V to VDD, all specifications TMIN to TMAX, unless otherwise noted.
Table 4. 1
Parameter
Conversion Time: CNV Rising Edge to Data Available
VDD = 2.7 V to 4.5 V
VDD = 2.3 V to 2.7 V
Acquisition Time
Time Between Conversions
VDD = 2.7 V to 4.5 V
VDD = 2.3 V to 2.7 V
CNV Pulse Width
Data Write/Read During Conversion
SCK Period
SCK Low Time
SCK High Time
SCK Falling Edge to Data Remains Valid
SCK Falling Edge to Data Valid Delay
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
CNV Low to SDO D15 MSB Valid
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
CNV High or Last SCK Falling Edge to SDO High Impedance
CNV Low to SCK Rising Edge
SDI Valid Setup Time from SCK Falling Edge
SDI Valid Hold Time from SCK Falling Edge
Min
tCONV
tCONV
tACQ
tCYC
tCYC
tCNVH
tDATA
tSCK
tSCKL
tSCKH
tHSDO
tDSDO
Max
Unit
3.2
3.4
μs
μs
μs
μs
μs
μs
ns
μs
ns
ns
ns
ns
5
5.2
10
1.4
25
12
12
5
24
30
37
ns
ns
ns
21
27
35
50
ns
ns
ns
ns
ns
ns
ns
tEN
tDIS
tCLSCK
tSDIN
tHDIN
10
5
5
See Figure 2 and Figure 3 for load conditions.
500µA
IOL
1.4V
TO SDO
CL
50pF
500µA
IOH
Figure 2. Load Circuit for Digital Interface Timing
70% VIO
30% VIO
tDELAY
2V OR VIO –
0.5V1
0.8V OR 0.5V2
2V OR VIO – 0.5V1
0.8V OR 0.5V2
2V IF VIO ABOVE 2.5V, VIO – 0.5V IF VIO BELOW 2.5V.
0.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V.
Figure 3. Voltage Levels for Timing
Rev. 0 | Page 7 of 28
07353-003
tDELAY
1
2
Typ
1.8
07353-002
1
Symbol
AD7682/AD7689
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter
Analog Inputs
INx, 1 COM1
REF, REFIN
Supply Voltages
VDD, VIO to GND
VDD to VIO
DIN, CNV, SCK to GND 2
SDO to GND
Storage Temperature Range
Junction Temperature
θJA Thermal Impedance (LFCSP)
θJC Thermal Impedance (LFCSP)
1
2
Rating
GND − 0.3 V to VDD + 0.3 V
or VDD ± 130 mA
GND − 0.3 V to VDD + 0.3 V
−0.3 V to +7 V
±7 V
−0.3 V to VIO + 0.3 V
−0.3 V to VIO + 0.3 V
−65°C to +150°C
150°C
47.6°C/W
4.4°C/W
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
See the Analog Inputs section.
CNV must be low at power up. See the Power Supply section.
Rev. 0 | Page 8 of 28
AD7682/AD7689
20
19
18
17
16
20
19
18
17
16
VDD
IN3
IN2
IN1
IN0
VDD
NC
IN1
NC
IN0
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
AD7682
TOP VIEW
(Not to Scale)
15
14
13
12
11
VIO
SDO
SCK
DIN
CNV
VDD
REF
REFIN
GND
GND
07353-004
NC = NO CONNECT
1
2
3
4
5
PIN 1
INDICATOR
AD7689
TOP VIEW
(Not to Scale)
15
14
13
12
11
VIO
SDO
SCK
DIN
CNV
07353-005
PIN 1
INDICATOR
IN4 6
IN5 7
IN6 8
IN7 9
COM 10
1
2
3
4
5
NC 6
IN2 7
NC 8
IN3 9
COM 10
VDD
REF
REFIN
GND
GND
Figure 5. AD7689 20-Lead LFCSP (QFN) Pin Configuration
Figure 4. AD7682 20-Lead LFCSP (QFN) Pin Configuration
Table 6. Pin Function Descriptions
Pin
No.
1, 20
AD7682
Mnemonic
VDD
AD7689
Mnemonic
VDD
Type 1
P
2
REF
REF
AI/O
3
REFIN
REFIN
AI/O
4, 5
6
GND
NC
GND
IN4
P
AI
7
IN2
IN5
AI
8
NC
IN6
AI
9
IN3
IN7
AI
10
COM
COM
AI
11
CNV
CNV
DI
12
DIN
DIN
DI
13
SCK
SCK
DI
Description
Power Supply. Nominally 2.5 V to 5.5 V when using an external reference and decoupled
with 10 μF and 100 nF capacitors.
When using the internal reference for 2.5 V output, the minimum should be 2.7 V.
When using the internal reference for 4.096 V output, the minimum should be 4.5 V.
Reference Input/Output. See the Voltage Reference Output/Input section.
When the internal reference is enabled, this pin produces a selectable system
reference = 2.5 V or 4.096 V.
When the internal reference is disabled and the buffer is enabled, REF produces a
buffered version of the voltage present on the REFIN pin (VDD – 0.3 V maximum) useful
when using low cost, low power references.
For improved drift performance, connect a precision reference to REF (0.5 V to VDD).
For any reference method, this pin needs decoupling with an external 10 μF capacitor
connected as close to REF as possible. See the Reference Decoupling section.
Internal Reference Output/Reference Buffer Input. See the Voltage Reference
Output/Input section.
When using the internal reference, the internal unbuffered reference voltage is present
and needs decoupling with a 0.1μF capacitor.
When using the internal reference buffer, apply a source between 0.5 V and 4.096 V that
is buffered to the REF pin as described above.
Power Supply Ground.
AD7682: No connection.
AD7689: Analog Input Channel 4.
AD7682: Analog Input Channel 2.
AD7689: Analog Input Channel 5.
AD7682: No connection.
AD7689: Analog Input Channel 6.
AD7682: Analog Input Channel 3.
AD7689: Analog Input Channel 7.
Common Channel Input. All channels [3:0] or [7:0] can be referenced to a common mode
point of 0 V or VREF/2 V.
Convert Input. On the rising edge, CNV initiates the conversion. During conversion, if
CNV is held high, the busy indictor is enabled.
Data Input. This input is used for writing to the 14-bit configuration register. The
configuration register can be written to during and after conversion.
Serial Data Clock Input. This input is used to clock out the data on ADO and clock in data
on DIN in an MSB first fashion.
Rev. 0 | Page 9 of 28
AD7682/AD7689
Pin
No.
14
AD7682
Mnemonic
SDO
AD7689
Mnemonic
SDO
Type 1
DO
15
VIO
VIO
P
16
17
IN0
NC
IN0
IN1
AI
AI
18
IN1
IN2
AI
19
NC
IN3
AI
Description
Serial Data Output. The conversion result is output on this pin synchronized to SCK. In
unipolar modes, conversion results are straight binary; in bipolar modes, conversion
results are twos complement.
Input/Output Interface Digital Power. Nominally at the same supply as the host interface
(1.8 V, 2.5 V, 3 V, or 5 V).
Analog Input Channel 0.
AD7682: No connection.
AD7689: Analog Input Channel 1.
AD7682: Analog Input Channel 1.
AD7689: Analog Input Channel 2.
AD7682: No connection.
AD7689: Analog Input Channel 3.
1
AI = analog input, AI/O = analog input/output, DI = digital input, DO = digital output, and P = power.
Rev. 0 | Page 10 of 28
AD7682/AD7689
TYPICAL PERFORMANCE CHARACTERISTICS
VDD = 2.5 V to 5.5 V, VREF = 2.5 V to 5 V, VIO = 2.3 V to VDD
1.5
1.5
1.0
1.0
0.5
DNL (LSB)
INL (LSB)
0.5
0
0
–0.5
0
16,384
32,768
49,152
65,536
CODES
–1.0
07353-009
–1.5
0
16,384
32,768
49,152
07353-006
–0.5
–1.0
65,536
CODES
Figure 6. Integral Nonlinearity vs. Code, VREF = VDD = 5 V
Figure 9. Differential Nonlinearity vs. Code, VREF = VDD = 5 V
200k
160k
σ = 0.50
VREF = VDD = 5V
180k
σ = 0.78
VREF = VDD = 2.5V
135,207
140k
160k
100k
120k
COUNTS
COUNTS
120k
135,326
124,689
140k
100k
80k
80k
63,257
60k
51,778
60k
40k
20k
20k
0
487
619
0
7FFA 7FFB 7FFC 7FFD 7FFE 7FFF 8000
0
0
8001
8002
CODE IN HEX
6649
1
0
07353-007
0
0
7FFB 7FFC 7FFD 7FFE 7FFF 8000
60
1
8002
8003
Figure 10. Histogram of a DC Input at Code Center
0
0
VREF = VDD = 5V
fS= 250kSPS
fIN = 19.9kHz
SNR = 92.9dB
SINAD = 92.4dB
THD = –102dB
SFDR = 103dB
SECOND HARMONIC = –111dB
THIRD HARMONIC = –104dB
–40
–60
–80
VREF = VDD = 2.5V
fs= 200kSPS
fIN = 19.9kHz
SNR = 88.0dB
SINAD = 87.0dB
THD = –89dB
SFDR = 89dB
SECOND HARMONIC = –105dB
THIRD HARMONIC = –90dB
–20
AMPLITUDE (dB of Full-Scale)
–20
–100
–120
–140
–40
–60
–80
–100
–120
–140
–160
0
25
50
75
100
FREQUENCY (kHz)
125
Figure 8. 20 kHz FFT, VREF = VDD = 5 V
–180
0
25
50
75
FREQUENCY (kHz)
Figure 11. 20 kHz FFT, VREF = VDD = 2.5 V
Rev. 0 | Page 11 of 28
100
07353-011
–160
07353-008
AMPLITUDE (dB of Full-Scale)
4090
8001
CODE IN HEX
Figure 7. Histogram of a DC Input at Code Center
–180
78
07353-010
40k
100
100
95
95
90
90
85
85
80
75
60
0
50
VDD = VREF
VDD = VREF
VDD = VREF
VDD = VREF
70
65
100
150
200
FREQUENCY (kHz)
60
0
50
17.0
SNR @ 2kHz
SINAD @ 2kHz
SNR @ 20kHz
SINAD @ 20kHz
ENOB @ 2kHz
ENOB @ 20kHz
16.5
200
130
–60
125
–65
120
16.0
88
15.0
86
14.5
–75
110
SFDR (dB)
15.5
–70
SFDR = 2kHz
115
ENOB (Bits)
90
–80
105
–85
100
95
SFDR = 20kHz
–90
THD = 20kHz
–95
90
84
14.0
82
–100
85
–105
THD = 2kHz
80
13.5
–110
75
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.5
5.0
13.0
REFERENCE VOLTAGE (V)
–115
70
1.0
07353-013
80
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
–120
5.5
5.0
REFERENCE VOLTAGE (V)
Figure 13. SNR, SINAD, and ENOB vs. Reference Voltage
Figure 16. SFDR and THD vs. Reference Voltage
96
–90
fIN = 20kHz
fIN = 20kHz
VDD = VREF = 5V
94
–95
92
THD (dB)
VDD = VREF = 5V
90
88
–100
VDD = VREF = 2.5V
VDD = VREF = 2.5V
–105
84
–55
–35
–15
5
25
45
65
TEMPERATURE (°C)
85
105
125
–110
–55
–35
–15
5
25
45
65
TEMPERATURE (°C)
Figure 14. SNR vs. Temperature
Figure 17. THD vs. Temperature
Rev. 0 | Page 12 of 28
85
105
125
07353-017
86
07353-014
SNR (dB)
SNR, SINAD (dB)
150
Figure 15. SINAD vs. Frequency
96
92
100
FREQUENCY (kHz)
Figure 12. SNR vs. Frequency
94
= 5V, –0.5dB
= 5V, –10dB
= 2.5V, –0.5dB
= 2.5V, –10dB
THD (dB)
65
75
07353-016
70
= 5V, –0.5dB
= 5V, –10dB
= 2.5V, –0.5dB
= 2.5V, –10dB
07353-041
VDD = VREF
VDD = VREF
VDD = VREF
VDD = VREF
80
07353-012
SINAD (dB)
SNR (dB)
AD7682/AD7689
AD7682/AD7689
3000
100
2.5V INTERNAL REF
4.096V INTERNAL REF
INTERNAL BUFFER, TEMP ON
INTERNAL BUFFER, TEMP OFF
EXTERNAL REF, TEMP ON
EXTERNAL REF, TEMP OFF
VIO
VDD CURRENT (µA)
2500
THD (dB)
–80
–90
–100
–120
0
50
= 5V, –0.5dB
= 2.5V, –0.5dB
= 2.5V, –10dB
= 5V, –10dB
100
150
200
FREQUENCY (kHz)
94
1750
50
1500
40
1250
30
3.0
3.5
4.0
4.5
20
5.5
5.0
VDD SUPPLY (V)
Figure 21. Operating Currents vs. Supply
3000
fIN = 20kHz
180
fS = 200kSPS
2750
160
VDD = VREF = 5V
93
VDD = 5V, INTERNAL 4.096V REF
2500
VDD CURRENT (µA)
92
SNR (dB)
70
60
Figure 18. THD vs. Frequency
95
80
2000
1000
2.5
07353-015
VDD = VREF
VDD = VREF
VDD = VREF
VDD = VREF
–110
2250
90
VIO CURRENT (µA)
2750
–70
fS = 200kSPS
07353-021
–60
91
90
89
VDD = VREF = 2.5V
88
140
2250
120
VDD = 5V, EXTERNAL REF
2000
100
1750
80
1500
60
VDD = 2.5, EXTERNAL REF
87
1250
86
40
–8
–6
–4
–2
1000
–55
07353-018
85
–10
0
INPUT LEVEL (dB)
25
45
65
85
105
20
125
25
VDD = 2.5V, 85°C
20
TDSDO DELAY (ns)
1
0
–1
UNIPOLAR ZERO
UNIPOLAR GAIN
BIPOLAR ZERO
BIPOLAR GAIN
–35
–15
5
15
VDD = 2.5V, 25°C
10
VDD = 5V, 85°C
VDD = 5V, 25°C
5
VDD = 3.3V, 85°C
07353-023
2
VDD = 3.3V, 25°C
25
45
65
85
105
TEMPERATURE (°C)
125
0
07353-020
OFFSET ERROR AND GAIN ERROR (LSB)
5
Figure 22. Operating Currents vs. Temperature
3
–3
–55
–15
TEMPERATURE (°C)
Figure 19. SNR vs. Input Level
–2
–35
0
20
40
60
80
SDO CAPACITIVE LOAD (pF)
100
Figure 23. tDSDO Delay vs. SDO Capacitance Load and Supply
Figure 20. Offset and Gain Errors vs. Temperature
Rev. 0 | Page 13 of 28
120
07353-022
VIO
AD7682/AD7689
TERMINOLOGY
Least Significant Bit (LSB)
The LSB is the smallest increment that can be represented by a
converter. For an analog-to-digital converter with N bits of
resolution, the LSB expressed in volts is
LSB (V) =
VREF
2N
Integral Nonlinearity Error (INL)
INL refers to the deviation of each individual code from a line
drawn from negative full scale through positive full scale. The
point used as negative full scale occurs ½ LSB before the first
code transition. Positive full scale is defined as a level 1½ LSB
beyond the last code transition. The deviation is measured from
the middle of each code to the true straight line (see Figure 25).
Differential Nonlinearity Error (DNL)
In an ideal ADC, code transitions are 1 LSB apart. DNL is the
maximum deviation from this ideal value. It is often specified in
terms of resolution for which no missing codes are guaranteed.
Offset Error
The first transition should occur at a level ½ LSB above analog
ground. The unipolar offset error is the deviation of the actual
transition from that point.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.
Signal-to-(Noise + Distortion) Ratio (SINAD)
SINAD is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc. The value for
SINAD is expressed in decibels.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and is
expressed in decibels.
Spurious-Free Dynamic Range (SFDR)
SFDR is the difference, in decibels, between the rms amplitude
of the input signal and the peak spurious signal.
Effective Number of Bits (ENOB)
ENOB is a measurement of the resolution with a sine wave
input. It is related to SINAD by the formula
ENOB = (SINADdB − 1.76)/6.02
and is expressed in bits.
Gain Error
The last transition (from 111 … 10 to 111 … 11) should occur
for an analog voltage 1½ LSB below the nominal full scale. The
gain error is the deviation in LSB (or percentage of full-scale
range) of the actual level of the last transition from the ideal
level after the offset error is adjusted out. Closely related is the
full-scale error (also in LSB or percentage of full-scale range),
which includes the effects of the offset error.
Aperture Delay
Aperture delay is the measure of the acquisition performance. It
is the time between the rising edge of the CNV input and the
point at which the input signal is held for a conversion.
Channel-to-Channel Crosstalk
Channel-to-channel crosstalk is a measure of the level of
crosstalk between any two adjacent channels. It is measured by
applying a dc to the channel under test and applying a full-scale,
100 kHz sine wave signal to the adjacent channel(s). The
crosstalk is the amount of signal that leaks into the test channel
and is expressed in decibels.
Reference Voltage Temperature Coefficient
Reference voltage temperature coefficient is derived from the
typical shift of output voltage at 25°C on a sample of parts at the
maximum and minimum reference output voltage (VREF) measured at TMIN, T (25°C), and TMAX. It is expressed in ppm/°C as
Transient Response
Transient response is the time required for the ADC to accurately
acquire its input after a full-scale step function is applied.
Dynamic Range
Dynamic range is the ratio of the rms value of the full scale to
the total rms noise measured with the inputs shorted together.
The value for dynamic range is expressed in decibels.
TCVREF (ppm/ °C ) =
VREF ( Max ) – VREF ( Min)
VREF (25°C ) × (TMAX – TMIN )
× 10 6
where:
VREF (Max) = maximum VREF at TMIN, T (25°C), or TMAX.
VREF (Min) = minimum VREF at TMIN, T (25°C), or TMAX.
VREF (25°C) = VREF at 25°C.
TMAX = +85°C.
TMIN = –40°C.
Rev. 0 | Page 14 of 28
AD7682/AD7689
THEORY OF OPERATION
INx+
SWITCHES CONTROL
MSB
32,768C
16,384C
LSB
4C
2C
C
SW+
C
BUSY
REF
COMP
GND
32,768C
16,384C
4C
2C
C
CONTROL
LOGIC
OUTPUT CODE
C
MSB
LSB
SW–
07353-026
CNV
INx– OR
COM
Figure 24. ADC Simplified Schematic
OVERVIEW
CONVERTER OPERATION
The AD7682/AD7689 are 4-channel/8-channel, 16-bit, charge
redistribution successive approximation register (SAR) analog-todigital converters (ADCs). These devices are capable of
converting 250,000 samples per second (250 kSPS) and power
down between conversions. For example, when operating with
an external reference at 1 kSPS, they consumes 17 μW typically,
ideal for battery-powered applications.
The AD7682/AD7689 are successive approximation ADCs
based on a charge redistribution DAC. Figure 24 shows the
simplified schematic of the ADC. The capacitive DAC consists
of two identical arrays of 16 binary-weighted capacitors, which
are connected to the two comparator inputs.
The AD7682/AD7689 contain all of the components for use in a
multichannel, low power data acquisition system, including
•
•
•
•
•
•
16-bit SAR ADC with no missing codes
4-channel/8-channel, low crosstalk multiplexer
Internal low drift reference and buffer
Temperature sensor
Selectable one-pole filter
Channel sequencer
These components are configured through an SPI-compatible,
14-bit register. Conversion results, also SPI compatible, can be
read after or during conversions with the option for reading
back the current configuration.
The AD7682/AD7689 provide the user with an on-chip trackand-hold and do not exhibit pipeline delay or latency.
The AD7682/AD7689 are specified from 2.3 V to 5.5 V and can
be interfaced to any 1.8 V to 5 V digital logic family. They are
housed in a 20-lead, 4 mm × 4 mm LFCSP that combines space
savings and allows flexible configurations. They are pin-for-pin
compatible with the 16-bit AD7699 and 14-bit AD7949.
During the acquisition phase, terminals of the array tied to the
comparator input are connected to GND via SW+ and SW−. All
independent switches are connected to the analog inputs.
Thus, the capacitor arrays are used as sampling capacitors and
acquire the analog signal on the INx+ and INx− (or COM)
inputs. When the acquisition phase is complete and the CNV
input goes high, a conversion phase is initiated. When the
conversion phase begins, SW+ and SW− are opened first. The
two capacitor arrays are then disconnected from the inputs and
connected to the GND input. Therefore, the differential voltage
between the INx+ and INx− (or COM) inputs captured at the
end of the acquisition phase is applied to the comparator inputs,
causing the comparator to become unbalanced. By switching
each element of the capacitor array between GND and CAP, the
comparator input varies by binary-weighted voltage steps
(VREF/2, VREF/4, ... VREF/32,768). The control logic toggles these
switches, starting with the MSB, to bring the comparator back
into a balanced condition. After the completion of this process,
the part returns to the acquisition phase, and the control logic
generates the ADC output code and a busy signal indicator.
Because the AD7682/AD7689 have an on-board conversion
clock, the serial clock, SCK, is not required for the conversion
process.
Rev. 0 | Page 15 of 28
AD7682/AD7689
TRANSFER FUNCTIONS
011...111
111...111
011...110
011...101
111...110
111...101
The ideal transfer characteristic for the AD7682/AD7689 is
shown in Figure 25 and for both unipolar and bipolar ranges
with the internal 4.096 V reference.
100...010
000...010
100...001
000...001
100...000
000...000
–FSR
–FSR + 1LSB
–FSR + 0.5LSB
+FSR – 1LSB
+FSR – 1.5LSB
ANALOG INPUT
07353-027
With the inputs configured for bipolar range (COM = VREF/2 or
paired differentially with INx− = VREF/2), the data outputs are
twos complement.
TWOS
STRAIGHT
COMPLEMENT
BINARY
ADC CODE
With the inputs configured for unipolar range (single ended,
COM with ground sense, or paired differentially with INx− as
ground sense), the data output is straight binary.
Figure 25. ADC Ideal Transfer Function
Table 7. Output Codes and Ideal Input Voltages
Description
FSR − 1 LSB
Midscale + 1 LSB
Midscale
Midscale − 1 LSB
−FSR + 1 LSB
−FSR
Unipolar Analog Input1
VREF = 4.096 V
4.095938 V
2.048063 V
2.048 V
2.047938 V
62.5 μV
0V
Digital Output Code
(Straight Binary Hex)
0xFFFF
0x8001
0x8000
0x7FFF
0x0001
0x0000
1
With COM or INx− = 0 V or all INx referenced to GND.
With COM or INx− = VREF /2.
3
This is also the code for an overranged analog input ((INx+) − (INx−), or COM, above VREF − VGND).
4
This is also the code for an underranged analog input ((INx+) − (INx−), or COM, below VGND).
2
Rev. 0 | Page 16 of 28
Bipolar Analog Input2
VREF = 4.096 V
2.047938 V
62.5 μV
0V
−62.5 μV
−2.047938 V
−2.048 V
Digital Output Code
(Twos Complement Hex)
0x7FFF
0x0001
0x00004
0xFFFF3
0x8001
0x8000
AD7682/AD7689
TYPICAL CONNECTION DIAGRAMS
IN0
100nF
REFIN VDD
REF
0V TO VREF
V–
100nF
100nF
10µF2
V+
ADA4841-x 3
1.8V TO VDD
5V
VIO
AD7682/AD7689
V+
INx
0V TO VREF
ADA4841-x 3
DIN
MOSI
SCK
SCK
SDO
MISO
CNV
SS
V–
0V OR
VREF /2
COM
GND
07353-028
NOTES:
1. INTERNAL REFERENCE SHOWN. SEE VOLTAGE REFERENCE OUTPUT/INPUT SECTION FOR
REFERENCE SELECTION.
2. CREF IS USUALLY A 10µF CERAMIC CAPACITOR (X5R).
3. SEE DRIVER AMPLIFIER CHOICE SECTION FOR ADDITIONAL RECOMMENDED AMPLIFIERS.
4. SEE THE DIGITAL INTERFACE SECTION FOR CONFIGURING AND READING CONVERSION DATA.
Figure 26. Typical Application Diagram with Multiple Supplies
5V
V+
100nF
100nF
10µF2
REF
REFIN VDD
1.8V TO VDD
100nF
VIO
ADA4841-x 3
IN0
AD7682/AD7689
V+
INx
ADA4841-x 3
VREF /2
COM
MOSI
SCK
SDO
MISO
CNV
SS
GND
NOTES:
1. INTERNAL REFERENCE SHOWN. SEE VOLTAGE REFERENCE OUTPUT/INPUT SECTION FOR
REFERENCE SELECTION.
2. CREF IS USUALLY A 10µF CERAMIC CAPACITOR (X5R).
3. SEE DRIVER AMPLIFIER CHOICE SECTION FOR ADDITIONAL RECOMMENDED AMPLIFIERS.
4. SEE THE DIGITAL INTERFACE SECTION FOR CONFIGURING AND READING CONVERSION DATA.
07353-029
VREF p-p
DIN
SCK
Figure 27. Typical Application Diagram Using Bipolar Input
Rev. 0 | Page 17 of 28
AD7682/AD7689
Unipolar or Bipolar
70
Figure 26 shows an example of the recommended connection
diagram for the AD7682/AD7689 when multiple supplies are
available.
65
60
55
CMRR (dB)
Bipolar Single Supply
Figure 27 shows an example of a system with a bipolar input
using single supplies with the internal reference (optional
different VIO supply). This circuit is also useful when the
amplifier/signal conditioning circuit is remotely located with
some common mode present. Note that for any input configuration, the inputs INx are unipolar and always referenced to
GND (no negative voltages even in bipolar range).
ANALOG INPUTS
Input Structure
Figure 28 shows an equivalent circuit of the input structure of
the AD7682/AD7689. The two diodes, D1 and D2, provide ESD
protection for the analog inputs, IN[7:0] and COM. Care must
be taken to ensure that the analog input signal does not exceed
the supply rails by more than 0.3 V because this causes the
diodes to become forward biased and to start conducting
current.
These diodes can handle a forward-biased current of 130 mA
maximum. For instance, these conditions may eventually occur
when the input buffer supplies are different from VDD. In such
a case, for example, an input buffer with a short circuit, the
current limitation can be used to protect the part.
VDD
INx+
OR INx–
OR COM
D1
CPIN
RIN
40
35
30
1
10
100
FREQUENCY (kHz)
1k
10k
Figure 29. Analog Input CMRR vs. Frequency
During the acquisition phase, the impedance of the analog
inputs can be modeled as a parallel combination of the
capacitor, CPIN, and the network formed by the series
connection of RIN and CIN. CPIN is primarily the pin capacitance.
RIN is typically 3.5 kΩ and is a lumped component made up of
serial resistors and the on resistance of the switches. CIN is
typically 27 pF and is mainly the ADC sampling capacitor.
Selectable Low Pass Filter
During the conversion phase, where the switches are opened,
the input impedance is limited to CPIN. While the AD7682/
AD7689 are acquiring, RIN and CIN make a one-pole, low-pass
filter that reduces undesirable aliasing effects and limits the
noise from the driving circuitry. The low-pass filter can be
programmed for the full bandwidth or ¼ of the bandwidth with
CFG[6] as shown in Table 9. Note that the converters
throughout must also be reduced by ¼ when using the filter. If
the maximum throughput is used with the BW set to ¼, the
converter acquisition time, tACQ, will be violated, resulting in
increased THD.
Input Configurations
Figure 30 shows the different methods for configuring the analog
inputs with the configuration register (CFG[12:10]). Refer to
the Configuration Register, CFG, section for more details.
CIN
D2
07353-030
GND
45
07353-031
For this circuit, a rail-to-rail input/output amplifier can be used;
however, the offset voltage vs. input common-mode range
should be noted and taken into consideration (1 LSB = 62.5 μV
with VREF = 4.096 V). Note that the conversion results are in
twos complement format when using the bipolar input
configuration. Refer to the AN-581 Application Note for
additional details about using single-supply amplifiers.
50
Figure 28. Equivalent Analog Input Circuit
This analog input structure allows the sampling of the true
differential signal between INx+ and COM or INx+ and INx−.
(COM or INx− = GND ± 0.1 V or VREF ± 0.1 V). By using these
differential inputs, signals common to both inputs are rejected,
as shown in Figure 29.
Rev. 0 | Page 18 of 28
AD7682/AD7689
CH0+
IN0
CH0+
CH1+
IN1
CH1+
IN1
CH2+
IN2
CH2+
IN2
CH3+
IN3
CH3+
IN3
CH4+
IN4
CH4+
IN4
CH5+
IN5
CH5+
IN5
CH6+
IN6
CH6+
IN6
CH7+
IN7
CH7+
IN7
COM
COM–
COM
GND
A—8 CHANNELS,
SINGLE ENDED
channel pairs are always paired IN (even) = INx+ and IN (odd)
= INx− regardless of CFG[7].
IN0
To enable the sequencer, CFG[2:1] are written to for initializing
the sequencer. After CFG[13:0] are updated, DIN must be held
low while reading data out (at least for Bit 13), or the CFG will
begin updating again.
While operating in a sequence, the CFG can be changed by
writing 012 to CFG[2:1]. However, if changing CFG11 (paired
or single channel) or CFG[9:7] (last channel in sequence), the
sequence reinitializes and converts IN0 (or IN1) after CFG is
updated.
GND
B—8 CHANNELS,
COMMON REFERNCE
Examples
IN0
CH0+ (–)
CH0– (+)
IN1
CH0– (+)
IN1
CH1+ (–)
IN2
CH1+ (–)
IN2
CH1– (+)
IN3
CH1– (+)
IN3
CH2+ (–)
IN4
CH2+
IN4
CH2– (+)
IN5
CH3+
IN5
CH3+ (–)
IN6
CH4+
IN6
CH3– (+)
IN7
CH5+
IN7
COM
COM–
As a first example, scan all IN[7:0] referenced to COM = GND
with temperature sensor.
13
CFG
-
GND
D—COMBINATION
13
CFG
-
Figure 30. Multiplexed Analog Input Configuraitons
•
•
•
1
11 10
INCC
1
0
9
8 7
INx
1 1 1
6
BW
-
5
-
4 3
REF
-
2 1
SEQ
1 0
0
RB
-
12
0
11 10
INCC
0
X
9
8 7
INx
1 0 X
6
BW
-
5
-
4 3
REF
-
2 1
SEQ
1 1
0
RB
-
Source Resistance
The analog inputs can be configured as
•
12
As a second example, scan three paired channels without
temperature sensor and referenced to VREF/2.
COM
GND
C—4 CHANNELS,
DIFFERENTIAL
Only the bits for input and sequencer are highlighted.
IN0
07353-032
CH0+ (–)
Figure 30A, single ended referenced to system ground;
CFG[12:10] = 1112.
Figure 30B, bipolar differential with a common reference
point; COM = VREF/2; CFG[12:10] = 0102.
Unipolar differential with COM connected to a ground
sense; CFG[12:10] = 1102.
Figure 30C, bipolar differential pairs with INx− referenced
to VREF/2; CFG[12:10] = 00X2.
Unipolar differential pairs with INx− referenced to a
ground sense; CFG[12:10] = 10X2.
In this configuration, the INx+ is identified by the channel
in CFG[9:7]. Example: for IN0 = IN1+ and IN1 = IN1−,
CFG[9:7] = 0002; for IN1 = IN1+ and IN0 = IN1−,
CFG[9:7] = 0012.
Figure 30D, inputs configured in any of the above
combinations (showing that the AD7682/AD7689 can be
configured dynamically).
When the source impedance of the driving circuit is low, the
AD7682/AD7689 can be driven directly. Large source
impedances significantly affect the ac performance, especially
total harmonic distortion (THD). The dc performances are less
sensitive to the input impedance. The maximum source impedance depends on the amount of THD that can be tolerated. The
THD degrades as a function of the source impedance and the
maximum input frequency.
DRIVER AMPLIFIER CHOICE
Although the AD7682/AD7689 are easy to drive, the driver
amplifier must meet the following requirements:
•
Sequencer
The AD7682/AD7689 include a channel sequencer useful for
scanning channels in a IN0 to INx fashion. Channels are
scanned as singles or pairs, with or without the temperature
sensor, after the last channel is sequenced.
The sequencer starts with IN0 and finishes with INx set in
CFG[9:7]. For paired channels, the channels are paired
depending on the last channel set in CFG[9:7]. Note that the
Rev. 0 | Page 19 of 28
The noise generated by the driver amplifier must be kept as
low as possible to preserve the SNR and transition noise
performance of the AD7682/AD7689. Note that the AD7682/
AD7689 have a noise much lower than most of the other
16-bit ADCs and, therefore, can be driven by a noisier
amplifier to meet a given system noise specification. The
noise from the amplifier is filtered by the AD7682/AD7689
analog input circuit low-pass filter made by RIN and CIN or
by an external filter, if one is used. Because the typical noise
of the AD7682/AD7689 is 35 μV rms (with VREF = 5 V), the
SNR degradation due to the amplifier is
AD7682/AD7689
SNRLOSS
⎛
⎜
35
= 20 log ⎜
⎜
π
⎜ 35 2 + f −3dB ( Ne N ) 2
2
⎝
⎞
⎟
⎟
⎟
⎟
⎠
AD7682/AD7689 and is thus useful for performing a system
calibration. Note that, when using the temperature sensor, the
output is straight binary referenced from the AD7682/AD7689
GND pin.
where:
f–3dB is the input bandwidth in megahertz of the AD7682/AD7689
(1.7 MHz in full BW or 425 kHz in ¼ BW) or is the cutoff
frequency of an input filter, if one is used.
N is the noise gain of the amplifier (for example, 1 in buffer
configuration).
eN is the equivalent input noise voltage of the op amp, in nV/√Hz.
•
•
For ac applications, the driver should have a THD
performance commensurate with the AD7682/AD7689.
Figure 18 shows THD vs. frequency for the
AD7682/AD7689.
For multichannel, multiplexed applications on each input
or input pair, the driver amplifier and the AD7682/
AD7689 analog input circuit must settle a full-scale step
onto the capacitor array at a 16-bit level (0.0015%). In the
amplifier data sheet, settling at 0.1% to 0.01% is more
commonly specified. This may differ significantly from the
settling time at a 16-bit level and should be verified prior to
driver selection.
Table 8. Recommended Driver Amplifiers
Amplifier
ADA4841-x
AD8655
AD8021
AD8022
OP184
AD8605, AD8615
Typical Application
Very low noise, small, and low power
5 V single supply, low noise
Very low noise and high frequency
Low noise and high frequency
Low power, low noise, and low frequency
5 V single supply, low power
The internal reference is temperature-compensated to within
15 mV. The reference is trimmed to provide a typical drift of
3 ppm/°C.
External Reference and Internal Buffer
For improved drift performance, an external reference can be
used with the internal buffer. The external reference is connected to REFIN, and the output is produced on the REF pin.
An external reference can be used with the internal buffer with
or without the temperature sensor enabled. Refer to Table 9 for
the register details. With the buffer enabled, the gain is unity and is
limited to an input/output of 4.096 V.
The internal reference buffer is useful in multiconverter applications because a buffer is typically required in these applications.
In addition, a low power reference can be used because the
internal buffer provides the necessary performance to drive the
SAR architecture of the AD7682/AD7689.
External Reference
In any of the six voltage reference schemes, an external
reference can be connected directly on the REF pin because the
output impedance of REF is >5 kΩ. To reduce power
consumption, the reference and buffer can be powered down
independently or together for the lowest power consumption.
However, for applications requiring the use of the temperature
sensor, the reference must be active. Refer to Table 9 for register
details. For improved drift performance, an external reference
such as the ADR43x or ADR44x is recommended.
Reference Decoupling
VOLTAGE REFERENCE OUTPUT/INPUT
The AD7682/AD7689 allow the choice of a very low temperature drift internal voltage reference, an external reference, or an
external buffered reference.
The internal reference of the AD7682/AD7689 provide excellent performance and can be used in almost all applications.
There are six possible choices of voltage reference schemes
briefly described in Table 9 with more details in each of the
following sections.
Internal Reference/Temperature Sensor
The internal reference can be set for either 2.5 V or a 4.096 V
output as detailed in Table 9. With the internal reference
enabled, the band gap voltage is also present on the REFIN pin,
which requires an external 0.1 μF capacitor. Because the current
output of REFIN is limited, it can be used as a source if followed
by a suitable buffer, such as the AD8605.
Whether using an internal or external reference, the AD7682/
AD7689 voltage reference output/input, REF, has a dynamic
input impedance and should therefore be driven by a low
impedance source with efficient decoupling between the REF
and GND pins. This decoupling depends on the choice of the
voltage reference but usually consists of a low ESR capacitor
connected to REF and GND with minimum parasitic inductance.
A 10 μF (X5R, 1206 size) ceramic chip capacitor is appropriate
when using the internal reference, the ADR43x/ADR44x
external reference, or a low impedance buffer such as the
AD8031 or the AD8605.
The placement of the reference decoupling capacitor is also
important to the performance of the AD7682/AD7689, as
explained in the Layout section. The decoupling capacitor should
be mounted on the same side as the ADC at the REF pin with a
thick PCB trace. The GND should also connect to the reference
decoupling capacitor with the shortest distance and to the
analog ground plane with several vias.
Enabling the reference also enables the internal temperature
sensor, which measures the internal temperature of the
Rev. 0 | Page 20 of 28
AD7682/AD7689
If desired, smaller reference decoupling capacitor values down
to 2.2 μF can be used with a minimal impact on performance,
especially on DNL.
10000
Regardless, there is no need for an additional lower value
ceramic decoupling capacitor (for example, 100 nF) between the
REF and GND pins.
OPERATING CURRENT (µA)
1000
For applications that use multiple AD7682/AD7689s or other
PulSAR devices, it is more effective to use the internal reference
buffer to buffer the external reference voltage, thus reducing
SAR conversion crosstalk.
The voltage reference temperature coefficient (TC) directly impacts
full scale; therefore, in applications where full-scale accuracy
matters, care must be taken with the TC. For instance, a
±15 ppm/°C TC of the reference changes full scale by ±1 LSB/°C.
VDD = 5V, INTERNAL REF
100
VDD = 5V, EXTERNAL REF
10
VDD = 2.5V, EXTERNAL REF
1
VIO
0.1
0.001
POWER SUPPLY
100
10
1k
10k
SAMPLING RATE (sps)
100k
1M
07353-040
0.010
Figure 32. Operating Currents vs. Sampling Rate
The AD7682/AD7689 use two power supply pins: an analog
and digital core supply (VDD) and a digital input/output
interface supply (VIO). VIO allows direct interface with any
logic between 1.8 V and VDD. To reduce the supplies needed,
the VIO and VDD pins can be tied together. The
AD7682/AD7689 are independent of power supply sequencing
between VIO and VDD. The only restriction is that CNV must
be low when powering up the AD7682/AD7689. Additionally, it
is very insensitive to power supply variations over a wide
frequency range, as shown in Figure 31.
75
SUPPLYING THE ADC FROM THE REFERENCE
For simplified applications, the AD7682/AD7689, with their
low operating current, can be supplied directly using the
reference circuit as shown in Figure 33. The reference line can
be driven by
•
•
The system power supply directly
A reference voltage with enough current output capability,
such as the ADR43x/ADR44x
A reference buffer, such as the AD8605, which can also
filter the system power supply, as shown in Figure 33
•
70
65
5V
5V
10Ω
5V
55
10kΩ
1µF
50
AD8605
1µF
10µF
0.1µF
1
45
REF
40
VDD
VIO
AD7689
35
1
10
100
FREQUENCY (kHz)
1k
10k
1OPTIONAL
07353-034
30
0.1µF
REFERENCE BUFFER AND FILTER.
Figure 33. Example of an Application Circuit
Figure 31. PSRR vs. Frequency
The AD7682/AD7689 power down automatically at the end of
each conversion phase; therefore, the operating currents and
power scale linearly with the sampling rate. This makes the part
ideal for low sampling rates (even of a few hertz) and low
battery-powered applications.
Rev. 0 | Page 21 of 28
07353-035
PSSR (dB)
60
AD7682/AD7689
The SCK frequency required is calculated by
DIGITAL INTERFACE
The AD7682/AD7689 use a simple 4-wire interface and are
compatible with SPI, MICROWIRE™, QSPI™, digital hosts, and
DSPs, for example, Blackfin® ADSP-BF53x, SHARC®, ADSP219x, and ADSP-218x.
The interface uses the CNV, DIN, SCK, and SDO signals and
allows CNV, which initiates the conversion, to be independent
of the readback timing. This is useful in low jitter sampling or
simultaneous sampling applications.
A 14-bit register, CFG[13:0], is used to configure the ADC for
the channel to be converted, the reference selection, and other
components, which are detailed in the Configuration Register,
CFG, section.
When CNV is low, reading/writing can occur during
conversion, acquisition, and spanning conversion (acquisition
plus conversion), as detailed in the following sections. The CFG
word is updated on the first 14 SCK rising edges, and conversion
results are read back on the first 15 (or 16 if busy mode is
selected) SCK falling edges. If the CFG readback is enabled, an
additional 14 SCK falling edges are required to read back the
CFG word associated with the conversion results with the CFG
MSB following the LSB of the conversion result.
A discontinuous SCK is recommended because the part is
selected with CNV low, and SCK activity begins to write a new
configuration word and clock out data.
Note that in the following sections, the timing diagrams
indicate digital activity (SCK, CNV, DIN, SDO) during the
conversion. However, due to the possibility of performance
degradation, digital activity should occur only prior to the safe
data reading/writing time, tDATA, because the AD7682/AD7689
provide error correction circuitry that can correct for an
incorrect bit during this time. From tDATA to tCONV, there is no
error correction and conversion results may be corrupted. The
user should configure the AD7682/AD7689 and initiate the
busy indicator (if desired) prior to tDATA. It is also possible to
corrupt the sample by having SCK or DIN transitions near the
sampling instant. Therefore, it is recommended to keep the
digital pins quiet for approximately 30 ns before and 10 ns after
the rising edge of CNV, using a discontinuous SCK whenever
possible to avoid any potential performance degradation.
Reading/Writing During Conversion, Fast Hosts
When reading/writing during conversion (n), conversion
results are for the previous (n − 1) conversion, and writing the
CFG is for the next (n + 1) acquisition and conversion.
f SCK ≥
Number _ SCK _ Edges
t DATA
The time between tDATA and tCONV is a safe time when digital
activity should not occur, or sensitive bit decisions may be
corrupt.
Reading/Writing During Acquisition, Any Speed Hosts
When reading/writing during acquisition (n), conversion
results are for the previous (n − 1) conversion, and writing is for
the (n + 1) acquisition.
For the maximum throughput, the only time restriction is that
the reading/writing take place during the tACQ (min) time. For
slow throughputs, the time restriction is dictated by throughput
required by the user, and the host is free to run at any speed.
Thus for slow hosts, data access must take place during the
acquisition phase.
Reading/Writing Spanning Conversion, Any Speed Host
When reading/writing spanning conversion, the data access
starts at the current acquisition (n) and spans into the
conversion (n). Conversion results are for the previous (n − 1)
conversion, and writing the CFG is for the next (n + 1)
acquisition and conversion.
Similar to reading/writing during conversion, reading/writing
should only occur up to tDATA. For the maximum throughput,
the only time restriction is that reading/writing take place
during the tACQ (min) + tDATA time.
For slow throughputs, the time restriction is dictated by the
user’s required throughput, and the host is free to run at any
speed. Similar to the reading/writing during acquisition, for
slow hosts, the data access must take place during the
acquisition phase with additional time into the conversion.
Note that data access spanning conversion requires the CNV to
be driven high to initiate a new conversion, and data access is
not allowed when CNV is high. Thus, the host must perform
two bursts of data access when using this method.
CONFIGURATION REGISTER, CFG
The AD7682/AD7689 use a 14-bit configuration register
(CFG[13:0]) as detailed in Table 9 for configuring the inputs,
channel to be converted, one-pole filter bandwidth, reference,
and channel sequencer. The CFG is latched (MSB first) on DIN
with 14 SCK rising edges. The CFG update is edge dependent,
allowing for asynchronous or synchronous hosts.
After the CNV is brought high to initiate conversion, it must be
brought low again to allow reading/writing during conversion.
Reading/writing should only occur up to tDATA and, because this
time is limited, the host must use a fast SCK.
Rev. 0 | Page 22 of 28
AD7682/AD7689
•
•
•
The register can be written to during conversion, during
acquisition, or spanning acquisition/conversion and is updated at
the end of conversion, tCONV (max). There is always a one deep
delay when writing CFG. Note that, at power up, the CFG is
undefined and two dummy conversions are required to update
the register. To preload the CFG with a factory setting, hold
DIN high for two conversions. Thus CFG[13:0] = 0x3FFF. This
sets the AD7682/AD7689 for
13
CFG
12
INCC
11
INCC
10
INCC
9
INx
8
INx
•
IN[7:0] unipolar referenced to GND, sequenced in order
Full bandwidth for one-pole filter
Internal reference/temperature sensor disabled, buffer
enabled
No readback of CFG
Table 9 summarizes the configuration register bit details. See
the Theory of Operation section for more details.
7
INx
6
BW
5
REF
4
REF
3
REF
2
SEQ
1
SEQ
0
RB
Table 9. Configuration Register Description
Bit(s)
[13]
Name
CFG
[12:10]
INCC
[9:7]
INx
[6]
BW
[5:3]
REF
[2:1]
SEQ
0
RB
Description
Configuration update.
0 = Keep current configuration settings.
1 = Overwrite contents of register.
Input channel configuration. Selection of pseudobipolar, pseudodifferential, pairs, single-ended or temperature sensor. Refer to
the Input Configurations section.
Bit 12
Bit 11
Bit 10
Function
0
0
X
Bipolar differential pairs; INx− referenced to VREF/2 ± 0.1 V.
0
1
0
Bipolar; INx referenced to COM = VREF/2 ± 0.1 V.
0
1
1
Temperature sensor.
1
0
X
Unipolar differential pairs; INx− referenced to GND ± 0.1 mV.
1
1
0
Unipolar, IN0 to IN7 referenced to COM = GND ± 0.1 V (GND sense).
1
1
1
Unipolar, IN0 to IN7 referenced to GND.
Input channel selection in binary fashion.
AD7682
AD7689
Bit 9
Bit 8
Bit 7
Channel Bit 9
Bit 8
Bit 7
Channel
0
0
X
IN0
0
0
0
IN0
0
1
X
IN1
0
0
1
IN1
1
0
X
IN2
…
…
…
1
1
X
IN3
1
1
1
IN7
Select bandwidth for low-pass filter. Refer to the Selectable Low Pass Filter section.
0 = ¼ of BW, uses an additional series resistor to further bandwidth limit the noise. Maximum throughout must be reduced to ¼
also.
1 = Full BW.
Reference/buffer selection. Selection of internal, external, external buffered, and enabling of the on-chip temperature sensor.
Refer to the Voltage Reference Output/Input section.
Bit 5
Bit 4
Bit 3
Function
0
0
0
Internal reference, REF = 2.5 V output.
0
0
1
Internal reference, REF = 4.096 V output.
0
1
0
External reference, temperature enabled.
0
1
1
External reference, internal buffer, temperature enabled.
1
1
0
External reference, temperature disabled.
1
1
1
External reference, internal buffer, temperature disabled.
Channel sequencer. Allows for scanning channels in an IN0 to INx fashion. Refer to the Sequencer section.
Bit 2
Bit 1
Function
0
0
Disable sequencer.
0
1
Update configuration during sequence.
1
0
Scan IN0 to INx (set in CFG[9:7]), then temperature.
1
1
Scan IN0 to INx (set in CFG[9:7]).
Read back the CFG register.
0 = Read back current configuration at end of data.
1 = Do not read back contents of configuration.
Rev. 0 | Page 23 of 28
AD7682/AD7689
to begin the CFG update. While CNV is low, both a CFG
update and a data readback take place. The first 14 SCK rising
edges are used to update the CFG, and the first 15 SCK falling
edges clock out the conversion results starting with MSB − 1.
The restriction for both configuring and reading is that they
both occur before the tDATA time of the next conversion elapses.
All 14 bits of CFG[13:0] must be written, or they are ignored. In
addition, if the 16-bit conversion result is not read back before
tDATA elapses, it is lost.
READ/WRITE SPANNING CONVERSION WITHOUT
A BUSY INDICATOR
This mode is used when the AD7682/AD7689 are connected to
any host using an SPI, serial port, or FPGA. The connection
diagram is shown in Figure 34, and the corresponding timing is
given in Figure 35. For SPI, the host should use CPHA = CPOL
= 0. Reading/writing spanning conversion is shown, which
covers all three modes detailed in the Digital Interface section.
A rising edge on CNV initiates a conversion, forces SDO to
high impedance, and ignores data present on DIN. After a
conversion is initiated, it continues until completion
irrespective of the state of CNV. CNV must be returned high
before the safe data transfer time, tDATA, and then held high
beyond the conversion time, tCONV, to avoid generation of the
busy signal indicator.
The SDO data is valid on both SCK edges. Although the rising
edge can be used to capture the data, a digital host using the
SCK falling edge allows a faster reading rate, provided it has an
acceptable hold time. After the 16th (or 30th) SCK falling edge, or
when CNV goes high (whichever occurs first), SDO returns to
high impedance. If CFG readback is enabled, the CFG associated with the conversion result (n − 1) is read back MSB first
following the LSB of the conversion result. A total of 30 SCK
falling edges is required to return SDO to high impedance if
this is enabled.
After the conversion is complete, the AD7682/AD7689 enter
the acquisition phase and power down. When the host brings
CNV low after tCONV (max), the MSB is enabled on SDO. The
host also must enable the MSB of CFG at this time (if necessary)
CNV
SS
SDO
MISO
DIN
MOSI
SCK
SCK
FOR SPI USE CPHA = 0, CPOL = 0.
07353-036
DIGITAL HOST
AD7682/
AD7689
Figure 34. Connection Diagram for the AD7682/AD7689 Without a Busy Indicator
tCYC
> tCONV
tCONV
tCONV
tDATA
tDATA
tCNVH
RETURN CNV HIGH
FOR NO BUSY
RETURN CNV HIGH
FOR NO BUSY
CNV
tACQ
(QUIET
TIME)
CONVERSION (n – 1)
UPDATE (n)
CFG/SDO
SCK
14
CFG
LSB
DIN
16/
30
15
1
tEN END CFG (n)
SDO
LSB + 1
tDIS
END DATA (n – 2)
tSDIN
CFG
MSB
tDSDO
MSB
LSB
tDIS
15
16/
30
CFG
LSB
X
X
tHDIN
CFG
MSB – 1
BEGIN CFG (n + 1) tHSDO
tEN
14
2
ACQUISITION
(n + 1)
UPDATE (n + 1)
CFG/SDO
SEE NOTE
tCLSCK
X
X
(QUIET
TIME)
CONVERSION (n)
ACQUISITION (n)
tEN
END CFG (n + 1)
SEE NOTE
MSB – 1
BEGIN DATA (n – 1)
LSB + 1
tDIS
END DATA (n – 1)
NOTES:
1. THE LSB IS FOR CONVERSION RESULTS OR THE CONFIGURATION REGISTER CFG (n – 1) IF
15 SCK FALLING EDGES = LSB OF CONVERSION RESULTS.
29 SCK FALLING EDGES = LSB OF CONFIGURATION REGISTER.
ON THE 16TH OR 30TH SCK FALLING EDGE, SDO IS DRIVEN TO HIGH IMPENDANCE.
Figure 35. Serial Interface Timing for the AD7682/AD7689 Without a Busy Indicator
Rev. 0 | Page 24 of 28
LSB
tDIS
07353-037
ACQUISITION
(n - 1)
AD7682/AD7689
update. While CNV is low, both a CFG update and a data
readback take place. The first 14 SCK rising edges are used to
update the CFG, and the first 16 SCK falling edges clock out the
conversion results starting with the MSB. The restriction for
both configuring and reading is that they both occur before the
tDATA time elapses for the next conversion. All 14 bits of
CFG[13:0] must be written or they are ignored. Also, if the 16-bit
conversion result is not read back before tDATA elapses, it is lost.
READ/WRITE SPANNING CONVERSION WITH A
BUSY INDICATOR
This mode is used when the AD7682/AD7689 are connected to
any host using an SPI, serial port, or FPGA with an interrupt
input. The connection diagram is shown in Figure 36, and the
corresponding timing is given in Figure 37. For SPI, the host
should use CPHA = CPOL = 1. Reading/writing spanning
conversion is shown, which covers all three modes detailed in
the Digital Interface section.
The SDO data is valid on both SCK edges. Although the rising
edge can be used to capture the data, a digital host using the
SCK falling edge allows a faster reading rate, provided it has an
acceptable hold time. After the optional 17th SCK falling edge,
SDO returns to high impedance. Note that, if the optional SCK
falling edge is not used, the busy feature cannot be detected if
the LSB for the conversion is low.
A rising edge on CNV initiates a conversion, forces SDO to
high impedance, and ignores data present on DIN. After a
conversion is initiated, it continues until completion
irrespective of the state of CNV. CNV must be returned low
before the safe data transfer time, tDATA, and then held low
beyond the conversion time, tCONV, to generate the busy signal
indicator. When the conversion is complete, SDO transitions
from high impedance to low with a pull-up to VIO, which can
be used to interrupt the host to begin data transfer.
If CFG readback is enabled, the CFG associated with the
conversion result (n − 1) is read back MSB first following the
LSB of the conversion result. A total of 31 SCK falling edges is
required to return SDO to high impedance if this is enabled.
After the conversion is complete, the AD7682/AD7689 enter
the acquisition phase and power down. The host must enable
the MSB of CFG at this time (if necessary) to begin the CFG
VIO
AD7682/
AD7689
DIGITAL HOST
SDO
MISO
IRQ
DIN
MOSI
SCK
SCK
FOR SPI USE CPHA = 1, CPOL = 1.
07353-038
SS
CNV
Figure 36. Connection Diagram for the AD7682/AD7689 with a Busy Indicator
tCYC
tCONV
tACQ
tDATA
tCNVH
tDATA
CNV
CONVERSION
(n – 1)
(QUIET
TIME)
CONVERSION (n – 1)
UPDATE (n)
CFG/SDO
SCK
15
16
17/
31
(QUIET
TIME)
CONVERSION (n)
ACQUISITION (n)
UPDATE (n + 1)
CFG/SDO
SEE NOTE
1
2
15
16
17/
31
X
X
X
tHDIN
ACQUISITION
(n + 1)
tSDIN
X
X
CFG
CFG
MSB MSB –1
X
tDIS
END CFG (n)
SDO
LSB
+1
END DATA (n – 2)
BEIGN CFG (n + 1)
MSB
LSB
tEN
tHSDO
tDSDO
tEN
MSB
–1
BEGIN DATA (n – 1)
LSB
+1
tDIS
LSB
END DATA (n – 1) SEE NOTE
NOTES:
1. THE LSB IS FOR CONVERSION RESULTS OR THE CONFIGURATION REGISTER CFG (n – 1) IF
16 SCK FALLING EDGES = LSB OF CONVERSION RESULTS.
30 SCK FALLING EDGES = LSB OF CONFIGURATION REGISTER.
ON THE 17TH OR 31st SCK FALLING EDGE, SDO IS DRIVEN TO HIGH IMPENDANCE.
OTHERWISE, THE LSB REMAINS ACTIVE UNTIL THE BUSY INDICATOR IS DRIVEN LOW.
Figure 37. Serial Interface Timing for the AD7682/AD7689 with a Busy Indicator
Rev. 0 | Page 25 of 28
tDIS
END CFG (n + 1)
tEN
07353-039
DIN
AD7682/AD7689
APPLICATION HINTS
LAYOUT
The printed circuit board that houses the AD7682/AD7689
should be designed so that the analog and digital sections are
separated and confined to certain areas of the board. The pinout of
the AD7682/AD7689, with all its analog signals on the left side
and all its digital signals on the right side, eases this task.
Avoid running digital lines under the device because these
couple noise onto the die unless a ground plane under the
AD7682/AD7689 is used as a shield. Fast switching signals,
such as CNV or clocks, should not run near analog signal paths.
Crossover of digital and analog signals should be avoided.
At least one ground plane should be used. It can be common or
split between the digital and analog sections. In the latter case,
the planes should be joined underneath the AD7682/AD7689.
The AD7682/AD7689 voltage reference input REF has a
dynamic input impedance and should be decoupled with
minimal parasitic inductances. This is done by placing the
reference decoupling ceramic capacitor close to, ideally right up
against, the REF and GND pins and connecting them with wide,
low impedance traces.
Finally, the power supplies VDD and VIO of the AD7682/
AD7689 should be decoupled with ceramic capacitors, typically
100 nF, placed close to the AD7682/AD7689 and connected
using short, wide traces to provide low impedance paths and
reduce the effect of glitches on the power supply lines.
EVALUATING AD7682/AD7689 PERFORMANCE
Other recommended layouts for the AD7682/AD7689 are
outlined in the documentation of the evaluation board for the
AD7682/AD7689 (EVAL-AD7682CBZ/EVAL-AD7689CBZ).
The evaluation board package includes a fully assembled and
tested evaluation board, documentation, and software for
controlling the board from a PC via the evaluation controller
board, EVAL-CONTROL BRD3.
Rev. 0 | Page 26 of 28
AD7682/AD7689
OUTLINE DIMENSIONS
0.60 MAX
4.00
BSC SQ
0.60 MAX
15
PIN 1
INDICATOR
20
16
1
PIN 1
INDICATOR
3.75
BSC SQ
0.50
BSC
2.65
2.50 SQ
2.35
EXPOSED
PAD
(BOTTOM VIEW)
5
TOP VIEW
12° MAX
SEATING
PLANE
10
6
0.25 MIN
0.80 MAX
0.65 TYP
0.30
0.23
0.18
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-1
012508-B
1.00
0.85
0.80
0.50
0.40
0.30
11
Figure 38. 20-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
4 mm × 4 mm Body, Very Thin Quad
(CP-20-4)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD7682BCPZ1
AD7682BCPZRL71
AD7689ACPZ 1
AD7689ACPZRL71
AD7689BCPZ1
AD7689BCPZRL71
EVAL-AD7682CBZ1
EVAL-AD7689CBZ1
EVAL-CONTROL BRD3 2
1
2
Integral
Nonlinearity
±2 LSB max
±2 LSB max
±6 LSB max
±6 LSB max
±2 LSB max
±2 LSB max
No Missing
Code
16 bits
16 bits
15 bits
15 bits
16 bits
16 bits
Temperature
Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Package Description
20-Lead QFN (LFCSP_VQ)
20-Lead QFN (LFCSP_VQ)
20-Lead QFN (LFCSP_VQ)
20-Lead QFN (LFCSP_VQ)
20-Lead QFN (LFCSP_VQ)
20-Lead QFN (LFCSP_VQ)
Evaluation Board
Evaluation Board
Controller Board
Package
Option
CP-20-4
CP-20-4
CP-20-4
CP-20-4
CP-20-4
CP-20-4
Z = RoHS Compliant Part.
This controller board allows a PC to control and communicate with all Analog Devices evaluation boards whose model numbers end in CB.
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Ordering
Quantity
Tray, 490
Reel, 1,500
Tray, 490
Reel, 1,500
Tray, 490
Reel, 1,500
AD7682/AD7689
NOTES
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07353-0-5/08(0)
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