Fuji FA13843P Cmos ic(for switching power supply control) Datasheet

FA13842,13843,13844,13845
■ Dimensions, mm
Á SOP-8
5
8
3.9
The FA1384X series are CMOS current mode control ICs for
off-line and DC-to-DC converters.
These ICs can reduce start-up circuit loss and are optimum for
high efficiency power supplies because of the low power
dissipation achieved through changes in the CMOS fabrication
process.
These ICs can drive a power MOSFET directly.
The high-performance, compact power supply can be
designed with minimal external components .
4
1
4.9
■ Types of FA1384X series
Maximum duty Package
cycle
96%
DIP
SOP
96%
DIP
SOP
48%
DIP
SOP
FA13845P
48%
9.6V±1V
9V±1V
1.7max
0~8°
Á DIP-8
5
8
1
UVLO
Start threshold Stop threshold
FA13842P 16.5V±1V
9V±1V
FA13842N
FA13843P 9.6V±1V
9V±1V
FA13843N
FA13844P 16.5V±1V
9V±1V
FA13844N
1.27±0.2
4
9.3
1.5
3.3
Type
0.4±0.1
2.54±0.25
0.46±0.1
3.0min 4.5max
Note: Pins are fully compatible, but characteristics are not.
When our ICs are applied to a power supply circuit
designed for other manufactures' 384X series, the
characteristics and safety features of the power supply
must be checked.
0.20
•
•
•
•
•
•
•
6.4
CMOS process
Low-power dissipation
Standby current 2µA (max.), start-up current 30µA (max.)
Pulse-by-pulse current limiting
5V bandgap reference
UVLO (Undervoltage lockout) with hysteresis
Maximum duty cycle
FA13842, 13843: 96%
FA13844, 13845: 48%
• Pin-for-pin compatible with UC384X
+0.1
–0.05
■ Features
FA13845N
6.0±0.2
■ Description
CMOS IC
FA13842,Power
13843,Supply
13844,Control
13845
For Switching
+0.1
0.05
0.25 –
7.62
0~15
˚
5˚
0~1
DIP
SOP
1
FA13842, 13843, 13844, 13845
■ Block diagram
Á FA13842, 13843
VCC 7
Pin No. Symbol Function
1
COMP Compensating
UVLO
VCC 5V REF
30V
ENB
8 VREF
2.5V
2
FB
3
ISNS
4
RT/CT
5
6
GND
OUT
7
8
VCC
VREF
UVLO
OUTPUT
ENB
RT/CT 4
OSC
5 GND
ER AMP
FB 2
COMP 1
2R
1R
6 OUT
1V
S Q
FF
R QB
ISNS 3
5V Controlled block
Á FA13844, 13845
VCC 7
UVLO
8 VREF
VCC 5V REF
30V
ENB
Description
Error amplifier output, available
for loop compensation circuit
Feedback
Inverting input of the error
amplifier
Current sensing
Input voltage proportional to
inductor current
Oscillator control Setting oscillation frequency
and maximum duty-cycle with
resistor RT and capacitor CT
Ground
Ground
Output
Output for driving a power
MOSFET
Power supply
Power supply
Reference voltage Reference voltage and
current source charging
capacitor C T through resistor
RT
2.5V
UVLO
OUTPUT
ENB
RT/CT 4
OSC
6 OUT
5 GND
ER AMP
FB 2
COMP 1
2R
1R
1V
TFFQ
CLK
QB
S Q
FF
R QB
ISNS 3
5V ControlIed block
■ Absolute maximum ratings (Ta=25˚C)
Item
Supply voltage
Symbol
VCC
Zener current
Output peak current
IZ
IO
FB/ISNS terminal input voltage
Error amplifier sink current
Total power dissipation
VIN
I SINK
Pd
Thermal resistance
Rθ j-a
Junction temperature
Ambient temperature
Storage temperature
Tj
Ta
Tstg
2
Test condition
Low impedance source
Zener clamp (Icc<10mA)
Source current
Sink current
FB, ISNS
at Ta < 50˚C
Junction-air
DIP
SOP
DIP
SOP
Rating
28
Self limiting
10
400
1
–0.3 to 5.3
10
800
400
125
250
150
–25 to 85
–40 to 150
Unit
V
V
mA
mA
A
V
mA
mW
˚C/W
˚C
˚C
˚C
FA13842, 13843, 13844, 13845
■ Recommended operating conditions
Item
Supply voltage
Oscillation timing capacitor
Oscillation timing resistor
Oscillation frequency
Symbol
VCC
CT
RT
fOSC
Min.
10
0.47
2.0
10
Max.
25
10
100
500
Unit
V
nF
kΩ
kHz
■ Electrical characteristics (Vcc=15V, RT=10kΩ, CT=3.3nF, Ta=25˚C)
Reference voltage section
Item
Reference voltage
Line regulation
Load current regulation
Temperature regulation
Output current at short-circuit
Symbol
VREF
LINE
LOAD
VTC
IOS
Test condition
Tj=25˚C, IL=1mA
Vcc=10 to 25V
IL=0 to 20mA
Ta=–25 to 85˚C
Tj=25˚C
Min.
4.75
Typ.
5.00
±3
±3
±0.3
60
Max.
5.25
±20
±25
Unit
V
mV
mV
mV/˚C
mA
Item
Oscillation frequency
Symbol
fOSC
Min.
49
47
Typ.
52
Voltage stability
Temperature stability
Oscillation amplitude
Discharge current
fdv
fdt
VOSC
IDISCHG
Test condition
Tj=25˚C
Ta=–25 to 85˚C
Vcc=10 to 25V
Ta=–25 to 85˚C
Tj=25˚C
Tj=25˚C
Max.
55
57
±1
Unit
kHz
kHz
%
%/˚C
V
mA
Item
Symbol
Test condition
Min.
Typ.
Max.
Unit
Input voltage
Input leak current
Open-loop gain
Unity gain bandwidth
Output source current
Output sink current
Output voltage
VFB
IFB
AV
fT
ISOURCE
ISINK
VH COMP
VL COMP
COMP=2.5V, Tj=25˚C
2.4
2.5
2.6
±2
65
0.7
–0.8
2
4.0
72
1
–1.0
15
4.5
80
500
V
µA
dB
MHz
mA
mA
V
mV
Symbol
AV IS
VTH IS
IIS
TPD
Test condition
Tj=25˚C
FB=0V
Typ.
3
1.0
–1
150
Max.
3.15
1.1
–5
300
Unit
V/V
V
µA
ns
Oscillator section
±0.25
–0.07
1.6
8.4
Error amplifier section
FB=2.3V, COMP=0V
FB=2.7V, COMP=1V
FB=2.3V, RL=15kΩ to GND
FB=2.7V, RL=15kΩ to VREF
Current sensing section
Item
Voltage gain
Maximum input signal
Input bias current
Delay to output
Tj=25˚C, ISNS to OUT
Min.
2.85
0.9
3
FA13842, 13843, 13844, 13845
Output section
Item
High-level output
Symbol
VOH
Low-level output
VOL
Rise time
Fall time
tr
tf
Test condition
I source=–20mA
I source=–100mA
I sink=20mA
I sink=200mA
CL=1nF, Tj=25˚C
CL=1nF, Tj=25˚C
Min.
14.5
12
Typ.
14.75
13.5
0.15
1.5
40
20
Max.
Test condition
FA13842, 13844
FA13843, 13845
Min.
15.5
8.6
8
Typ.
16.5
9.6
9
7.5
0.6
Max.
17.5
10.6
10
Unit
V
V
V
V
V
Test condition
FA13842, 13843
FA13844, 13845
FB=5V, COMP=Open
Min.
94
47
Typ.
96
48
Max.
98
50
0
Unit
%
%
%
Test condition
FA13842, 13844 Vcc=14V
FA13843, 13845 Vcc=7V
Vcc=Start threshold
Min.
Typ.
Icc=5mA
28
12
3
30
Max.
2
2
30
5
34
Unit
µA
µA
µA
mA
V
0.3
3
150
150
Unit
V
V
V
V
ns
ns
Under-voltage lockout section
Item
Start threshold
Symbol
VTH ON
Min. operating voltage
Hysteresis
VTH OFF
VHYS
FA13842, 13844
FA13843, 13845
PWM section
Item
Maximum duty cycle
Symbol
Dmax
Minimum duty cycle
Dmin
Overall device
Item
Standby current
Symbol
I CCL
Start-up current
Operating current
Zener voltage (Vcc)
I CC ST
I CC OP
VZ
4
FA13842, 13843, 13844, 13845
■ Characteristic curves (Ta=25˚C)
Timing resistance vs. oscillation frequency
FA13842, FA13843
Output dead time vs. oscillation frequency
FA13842, FA13843
100
100
2.2nF
VCC= 15V
Ta= 25˚C
470pF
RT resistance (kΩ)
Output dead time (%)
CT=10nF
10
470pF
2.2nF
CT=10nF
10
VCC= 15V
Ta= 25˚C
1
1
1
10
100
Oscillation frequency (kHz)
1000
Timing resistance vs. oscillation frequency
FA13844, FA13845
10
100
Oscillation frequency (kHz)
Output dead time vs. oscillation frequency
FA13844, FA13845
100
100
VCC= 15V
Ta= 25˚C
470pF
2.2nF
90
RT resistance (kΩ)
Output dead time (%)
CT=10nF
10
80
2.2nF
CT=10nF
60
40
1
10
100
Oscillation frequency (kHz)
100
Oscillation frequency (kHz)
1000
Output max. duty cycle vs. timing resistance
FA13842, FA13843
10
100
Output maximum duty cycle (%)
RT/CT discharge current (mA)
10
1000
RT/CT discharge current vs. temperature
9.5
9
8.5
8
7.5
7
–50
470pF
70
50
VCC= 15V
Ta= 25˚C
1
1000
90
80
70
60
50
40
0
50
Temperature (˚C)
100
150
1
2
5
RT timing resistance (kΩ)
10
5
FA13842, 13843, 13844, 13845
ISNS threshold voltage vs. COMP voltage
COMP source current vs. COMP voltage
1200
0
VCC= 15V
FB= 0V
OUT= off
–200
COMP source current (µA)
ISNS threshold voltage (mV)
1000
800
600
400
200
0
–400
–600
–800
–1000
1
0
4
3
2
COMP voltage (V)
–1200
5
COMP to ISNS offset voltage vs. temperature
1
0
4
3
2
COMP voltage (V)
5
COMP source current vs. temperature
2.5
–800
–900
2
COMP source current (µA)
COMP to ISNS offset voltage (V)
VCC= 15V
COMP= 0V
1.5
1
0.5
–1000
–1100
–1200
–1300
0
–50
0
100
50
150
Temperature (˚C)
Error amp open loop voltage gain and phase vs.
frequency
–1400
–50
VCC= 15V
VREF= 0V
40
Gain
20
180
0
100
1.0k
10k
100k
Frequency (Hz)
1.0M
10M
VREF short circuit current (mA)
Phase ( ˚)
Open loop voltage gain (dB)
Phase
60
–20
70
60
50
40
30
20
0
50
100
Temperature (˚C)
6
150
80
80
–40
10
100
50
Temperature (˚C)
VREF short circuit current vs. temperature
0
100
0
150
FA13842, 13843, 13844, 13845
VCC supply current vs. VCC supply voltage
VCC startup current vs. VCC supply voltage
FA13842, FA13844
8
14
RT= 10kΩ
CT= 3.3nF
OUT= No load
Ta= 25˚C
12
VCC startup current (µA)
7
VCC current (mA)
6
5
4
3
13843/45
1
0
13842/44
2
0
8
6
4
2
20
10
10
30
0
14
14.5
VCC voltage (V)
15
15.5
16
VCC voltage (V)
16.5
17
Output waveform
Vcc=15V, OUT CL=1nF, Ta=25˚C
Vcc=15V, OUT CL=2.2nF, Ta=25˚C
VCC= 15V
OUT CL= 1nF
Ta= 25˚C
2.50V
VCC= 15V
OUT CL= 2.2nF
Ta= 25˚C
25.0ns
2.50V
50.0ns
7
FA13842, 13843, 13844, 13845
1. Oscillator
The oscillation frequency is determined by timing resistance RT
and timing capacitor CT, which are connected to RT/CT
terminal. CT is charged to about 3V through RT from a 5V
reference, and discharged to about 1.4V by the built-in
discharge circuit. (See Fig. 1, 2, 3.)
Blanking pulses are generated in the IC during the CT
discharge period.
The output is fixed in the “low” state by these pulses, and a
fixed dead time is produced. See the characteristic curves on
page 45 for the oscillation frequency, RT and CT.
In the case of FA13844/45, a flip-flop causes the output to be
blanked with every other cycle. Therefore, the switching
frequency of a power MOSFET is 1/2 of the oscillation
frequency determined by RT and CT . (See Fig. 3.)
VCC
7
UVLO
30V
VREF
VCC 5V REF
8
ENB 2.5V
UVLO
OUTPUT
ENB
6
OUT
RT
RS
5 GND
RT/CT
4
CT
ER AMP 2R
OSC
FB 2
COMP 1
ISNS
2. Error amplifier
Inverting input and output are connected to the FB terminal
and COMP terminal, respectively. A 2.5V reference is
connected internally to the non-inverting input.
The output voltage is offset by a diode VF voltage (=0.7V) and
divided by three. The divided voltage is connected to the input
of the current sensing comparator.
Vin
Vcc
1R
1V
3
S Q
FF
R QB
Fig. 1
3V
CT
1.4V
3. Current sensing comparator and PWM latch
The “High” state of the OUT terminal begins at the time CT
starts charging. The OUT terminal turns to “Low” when the
peak inductor current reaches the threshold level controlled by
the error amplifier output (COMP terminal).
The inductor current is converted to a voltage by sensing
resistor RS inserted between GND and the source of a power
MOSFET. This voltage is monitored by the ISNS terminal.
The peak current of inductor “Ipk” is expressed as follows:
0.7V VF
Ipk=(Vcomp–0.7) / (3•RS)
Set
COMP
ISENS
Reset
OUT
Vcomp: a voltage on COMP terminal
The maximum value of the threshold level of the current
sensing comparator is held to 1V. Therefore, the maximum
peak current “Ipk(max)” is as follows:
Ipk(max)=1.0V/RS
Fig. 2
FA13842, 13843
3V
CT
4. Undervoltage lockout (UVLO)
In order to set the IC in the operation mode before the output
stage(OUT terminal) is enabled, two under-voltage lockout
comparators are incorporated to monitor the power supply
voltage (VCC) and reference voltage (VREF).
The threshold level of the VCC comparator is set at 16.5V/9V for
FA13842/44 and 9.6V/9V for FA13843/45. In the standby
mode, in which the VCC is under ON threshold, the power
supply current is maintained at nearly 0 (zero). However, a
maximum current of 30µA is required to change from standby
mode to operating mode .
The threshold level of the VREF comparator is set at about 3.2V/
2.0V.
A 30V zener diode is connected to VCC and GND to protect the
IC against overvoltages.
8
MOSFET
■ Description of each circuit
1.4V
Set
COMP
ISENS
Reset
OUT
Fig. 3
FA13844, 13845
FA13842, 13843, 13844, 13845
DB
~
5. Output stage
An output stage of CMOS inverter composition is incorporated,
thereby making it possible to fully swing the gate voltage of a
power MOSFET to the VCC.
The output stage provides a source current of 400mA and a
sink current of 1A as the peak current capacity. (When VCC is
15V)
The output stage is held in the “Low” state in standby mode.
T1
+
+
AC INPUT
C1
~
R1
D1
+
C2
6. Reference voltage
The 5.0V(±5%) bandgap reference(Tj=25˚C) is built-in.
It is possible to supply a current of about 10mA to an external
circuit in addition to supplying a charge current to the timing
capacitor of the oscillator. (See characteristic curve on page
46.)
Connect a ceramic bypass capacitor of 0.1µF or higher to the
VREF terminal to stabilize this voltage.
7
FA13842
Rs
Fig. 4
Start-up time[sec]
1. Start-up circuit
A typical start-up circuit is shown in Fig. 4.
The AC INPUT voltage charges capacitor C2 and supplies
start-up current to the IC through start-up resistance R1. When
this voltage reaches the ON threshold voltage, the IC reverts to
the operation mode and electric power is supplied from the
bias winding of the transformer thereafter.
Using CMOS process, the start-up current is less than 30µA.
Input:100V AC
C2=47µF
4
■ Design advice
MOSFET
6
C2=22µF
3
2
C2=10µF
1
0
0
800
400
600
Start-up resistance R1 (kΩ)
200
Fig. 5
When the start-up resistance is increased, the charging rate of
capacitor C2 decreases and start-up time increases. Select
the optimum values for R1 and C2.
The relation between the start-up resistance and start-up time
for the circuit indicated in Fig. 4 is shown in Fig. 5.
Fig. 6 indicates a method to increase the start-up resistance to
reduce loss and shorten start-up time. The start-up time is
shortened by reducing the capacitance of C2. The bias current
is supplied from C3 after start-up.
1000
1200
Start-up time
R1
D1
D2
+
+
C2
C3
7
FA13842
6
2. Synchronized operation with external signals
The circuit shown in Fig. 7 allows synchronized operation with
external signals.
Synchronized operation is started when the RT/CT terminal
voltage is raised to about 3V or higher. (Synchronized at
leading edge.)
The external synchronizing signal should be higher than the
free-run frequency.
In the case of FA13844/45, the output frequency of the OUT
terminal is 1/2 that of the synchronizing signal frequency.
Fig. 6
8
REF
4
OSC
RT
Synchronized
CT
C4
2R
+
R2
2
D3
ER AMP
1R
1
5
Fig. 7
9
FA13842, 13843, 13844, 13845
3. Latched shutdown
A typical circuit for latched shutdown is shown in Fig. 8.
The voltage of the OUT terminal is kept low if the voltage of the
COMP terminal is low. The voltage of the COMP terminal
must be set at 0.7V or less in the application temperature
range. (See characteristic curve on page 46 ”COMP to ISNS
offset voltage vs temperature”.)
The source current from the COMP terminal is less than about
1.3mA.
DB
~ +
T1
+
C1
AC INPUT
~
MOSFET
R1
D1
+
C2
Use of a thyristor such as that shown in Fig. 9 is not effective
because the saturation voltage of the thyristor is higher than
0.7V. When a thyristor is used, increase the voltage of the FB
terminal to more than 3V as shown in Fig.10. In the case of a
latched shutdown, it is necessary to supply a current larger
than the hold current of the thyristor structure circuit or of the
thyristor. This current should be provided through a start-up
resistor from the AC input.
7
REF
8
30V
OSC
4
Latched shutdown with a thyristor using the COMP
terminal is not effective.
2R
+
2
R4
1R
ER AMP
D4
Latching signal Tr2
1
5
Tr1
R3
Fig. 8
7
7
REF
8
30V
30V
4
OSC
+
4
Latching signal
SCR2
2R
2
ER AMP
Latching signal
Fig. 9
10
+
ER AMP
R5
5
OSC
2
1R
1
SCR1
REF
8
C5
2R
1R
1
5
Fig. 10
FA13842, 13843, 13844, 13845
3-1 The method of detecting an overvoltage (detection
on primary side)
A typical latched shutdown circuit to protect against
overvoltages detected on the primary side is shown in Fig. 11.
When the secondary voltage increases in the flyback circuit,
the voltage of the bias winding also increases in proportion.
When this voltage increase is detected by zener diode ZD1, a
latched shutdown is accomplished. As the secondary voltage
is detected through a transformer, detection accuracy is low.
3-2 The method of detecting an overvoltage (detection
on secondary side)
A typical latched shutdown circuit to protect against
overvoltages detected on the secondary side is shown in
Fig. 12.
The detected voltage accuracy is high compared to
overvoltage detection on the primary side.
DB
~ +
D6
T1
+
C7
+
C1
AC INPUT
~
R1
D1
R9
+
C2
R6
ZD2
7
FA13842
MOSFET
6
PC1
1
Rs
R8
R4
Tr2
D5
PC1
R7
Tr1
3-3 The method of detecting an overcurrent (detection
of primary current)
A typical primary overcurrent detection circuit is shown in
Fig. 13.
R3
C6
Fig. 12
DB
~ +
3-4 The method of detecting an overcurrent (detection
of secondary current)
A typical secondary overcurrent detection circuit is shown in
Fig. 14.
T1
+
C1
AC INPUT
~
R1
D1
+
C2
R6
7
DB
~ +
T1
FA13842
1
+
C1
AC INPUT
~
3
R12
D5
R4
R1
MOSFET
6
Rs
Tr2
R11
D1
Tr1
+
C2
R6
R3
C6
7
ZD1
FA13842
Rs
DB
~ +
R4
D5
T1
D6
R13
+
+
C1
AC INPUT
C6
R10
Fig. 13
MOSFET
Tr1
R3
C8
6
1
Tr2
Tr3
C7
Tr4
~
R1
Fig. 11
R14
D1
+
C2
R6
PC1
7
FA13842
MOSFET
6
R15
Tr5
1
Rs
R16
R8
R4
Tr2
D5
R7
PC1
Tr1
C6
R3
Fig. 14
11
FA13842, 13843, 13844, 13845
4. Soft start
A soft-start circuit is shown in Fig. 15.
An aproximate soft-start time is determined with the following
calculation. This soft-start time is defined as the time the ISNS
terminal threshold voltage increases from 0V to 1V.
tsoft-start [ms]=4.3•C9[µF]
5. Suppression of noise at the current sensing
terminal
As each cycle current value is monitored in the current mode
control, there is the possibility that a malfunction will occur
even with a relatively low noise level. Therefore, it is
necessary to add a CR filter to reduce the level of noise at the
current sensing terminal. (See Fig. 16.)
6. ON/OFF circuit with an external signal
A typical ON/OFF circuit is shown in Fig. 17.
The output stage (OUT terminal) is enabled when the voltage
at the FB terminal is reduced to less than 2.0V and is disabled
when the FB terminal voltage increases to more than 3V.
Set the voltage of the FB terminal at a maximum of 5.3V in this
case.
8
REF
4
OSC
1mA
+
D7
R17
1MΩ
D8
2
2R
ER AMP
1R
1
C9
5
Fig. 15
DB
~
T1
+
+
C1
AC INPUT
~
MOSFET
6
FA13842
R18
3
C10
Rs
Fig. 16
7
REF
8
30V
R19
4
OSC
2R
+
2
ER AMP
ON/OFF signal
1R
Tr6
1
5
Fig. 17
12
FA13842, 13843, 13844, 13845
7. Feedback circuit
7-1 A method that does not use an internal ER AMP
A method that does not use an internal ER AMP is shown in
Fig. 18. Connect the FB terminal to GND and connect an
optocoupler to the COMP terminal of the ER AMP output for
feedback control.
It is possible to obtain a precise power supply output voltage,
because the output voltage is monitored directly on the
secondary side.
Be sure to connect the FB terminal to the GND in this case.
There is the possibility of a malfunction occuring if the FB
terminal is open.
T1
+
C1
D6
C7
+
MOSFET
R20
1
C11
PC2
R21
2R
2
+
2.5V
R19
Rs
R
PC2
+
3
R22
R18
7-2 A method using an internal ER AMP
A method using an internal ER AMP is shown in Fig. 19.
In the flyback circuit, the bias winding voltages of the
transformer are proportional to the secondary winding voltage.
Therefore, VCC is approximately proportional to the DC output
voltage on the secondary side.
VCC is divided by resistors and monitored at the FB terminal to
control the output voltage.
This feedback circuit consists of a minimal number of external
components. However, regulation of the DC output voltage is
poor because the output voltage is not monitored directly.
C12
C10
R23
Fig. 18
T1
+
D6
+
C7
C1
R1
D1
8. Slope compensation
It is well known that a current mode converter that controls
peak current can oscillate irregularly when the inductor current
is continuous and the duty cycle is greater than 50%.
This irregular oscillation is called subharmonic oscillation.
The period of subharmonic oscillation is equal to the integral
number of the switching periods.
This phenomenon is shown in Fig. 20.
Lu indicates the positive slope of the inductor current. The
slope is determined by the input voltage and the primary
inductance value of the transformer. –Ld indicates the
negative slope, which is determined by the rate of energy
discharge to the secondary side.
Fig. 20 shows the inductor current waveform when T reveals
the oscillation period and Is reveals the control signal of the
peak inductor current. TON and TOFF vary even when having the
same T, Is, Lu and –Ld.
If it is assumed in Fig. 21 that the inductor current varies ∆ iL at
t0, the variation ∆ iL’ of the inductor current at t1 is larger than
∆ iL at t0. Thereafter, this inductor current variation gradually
increases, and as a result, subharmonic oscillation occurs.
+
C2
R26
C13
1
R25
2R
2
+
2.5V
R
R24
+
3
MOSFET
R18
Rs
C10
Fig.19
Is
Lu
-Ld
TON
T
TOFF
T
T
T
Fig. 20
Diverge
∆iL
∆iL´
to
t1
Fig. 21
13
FA13842, 13843, 13844, 13845
Fig. 22 illustrates a case when the inductor current variation
∆ iL’ at t1 is smaller than ∆ iL at t0. In this case, inductor current
variations gradually converges and the inductor current
becomes stable.
It is necessary to apply slope compensation to the control
signals in order to prevent such subharmonic oscillations when
the inductor current is continuous and the duty cycle is greater
than 50%.
Converge
∆iL
∆iL´
to
t1
Fig. 22
The waveform of the inductor current when slope
compensation is applied is shown in Fig. 23.
Slope compensation adds the negative slope of inclination
–Kc to the control signal of the inductor peak current.
∆ iL’ shows the variation of the inductor current at t1 when
slope compensation is not applied, and ∆ iL’ s shows the
variation of the inductor current at t1 when slope compensation
is applied.
Thus, ∆ iL’ can be changed by –Kc, and ∆ IL’ s becomes smaller
when –Kc is large. It is necessary to apply slope
compensation to satisfy the equation ∆ iL ≥ ∆ iL’s, that is,
I –Kc I ≥ I –1/2 Ld I as the condition which achieves stable
operation.
Typical circuits are shown in Fig. 24 and 25.
Is
-Kc
∆iL´
∆iL
Lu
-Ld
∆iL´s
Compensated
Ton
T
to
t1
Fig. 23
Vin
Vcc
7
VREF
UVLO
30V
Tr7
8
Vcc 5VREF
RT
ENB 2.5V
UVLO
6
OUTPUT
ENB
OUT
R18
MOSFET
VCC
R27 CT
Output
RT/CT
R25
4
R24
FB
2
R26 C13
COMP
ISNS
1
OSC
ER AMP 2R
1R
5 GND
1V
Rs
C10
S Q
FF
R QB
3
Fig. 24
Vin
Vcc
7
VREF
UVLO
30V
Tr7
8
Vcc 5VREF
ENB 2.5V
RT
UVLO
OUTPUT
ENB
6
OUT
R18
MOSFET
VCC
R27 CT
Output
RT/CT
4
R25
FB
R24
R26 C13
COMP
ISNS
OSC
ER AMP 2R
2
1
1R
1V
3
Fig. 25
14
5 GND
S Q
FF
R QB
C10
Rs
FA13842, 13843, 13844, 13845
■ Application circuit
DB
T1
~ +
C16
0.022µF
+
C1
400V/220µF
AC80~264V
~
L1
YG902C
D6
4700µF 2 3.3µH
R27
100kΩ
C7
D9
ERA22-10
+ + C17
16V
0~4A
+
C18
1000µF
R1
GND
560kΩ
MOSFET
2SK2101
R29
4.7kΩ
R30
33Ω
C15
470pF
D10
ERA22-10
R28
1kΩ
Rs
0.33Ω
PC2
R20
1.2kΩ
R32 R21
2.2kΩ 10kΩ
R22 560Ω
R31
100Ω
RT
8.2kΩ
VCC
C2
FA13842
7
UVLO
30V
22µF
VREF
VCC 5VREF
ENB 2.5V
UVLO
8
OUTPUT
ENB
COMP
RT/CT
CT
2200pF
6
OUT
+
IC
C12
0.1µF
VR1
5k
D1
ERA91-02
1
4
C11
1000pF FB 2
2R
1R
PC2 R19
1kΩ ISNS3
C10
100pF
D11
ERA91-02
R18
1kΩ
5
OSC
1V
GND
S Q
FF
R QB
C14
0.1µF
Parts tolerances characteristics are not defined in the circuit design
sample shown above. When designing an actual circuit for a
product, you must determine parts tolerances and characteristics for
safe and economical operation.
15