AD AD8372 41 db range, 1 db step size, programmable dual vga Datasheet

41 dB Range, 1 dB Step Size,
Programmable Dual VGA
AD8372
FEATURES
FUNCTIONAL BLOCK DIAGRAM
ENB1
AD8372
REF1
IPC1
OPC1
INC1
RXT1
ONC1
CHANNEL 1
POSTAMP
CLK2
CLK1
SDO1
SDI1
REGISTERS
AND
GAIN DECODER
LCH1
SDO2
SDI2
LCH2
RXT2
OPC2
IPC2
INC2
ENB2
ONC2
CHANNEL 2
POSTAMP
REF2
07051-001
Dual independent digitally controlled VGA
Differential input and output
150 Ω differential input
Open-collector differential output
7.8 dB noise figure to 100 MHz @ maximum gain
HD2/HD3 better than 77 dBc for 1 V p-p differential output
−3 dB bandwidth of 130 MHz
41 dB gain range
1 dB step size ± 0.2 dB
Serial 8-bit bidirectional SPI control interface
Wide input dynamic range
Pin-programmable output stage
Power-down feature
Single 5 V supply: 106 mA per channel
32-lead LFCSP, 5 mm × 5 mm package
Figure 1.
APPLICATIONS
Differential ADC drivers
CMTS upstream direct sampling receivers
CATV modem signal scaling
Generic RF/IF gain stages
Single-ended-to-differential conversion
GENERAL DESCRIPTION
The AD8372 is a dual, digitally controlled, variable gain
amplifier (VGA) that provides precise gain control, high IP3,
and low noise figure. The excellent distortion performance and
moderate signal bandwidth make the AD8372 a suitable
gain control device for a variety of multichannel receiver
applications.
For wide input dynamic range applications, the AD8372
provides a broad 41 dB gain range. The gain is programmed
through a bidirectional 4-pin serial interface. The serial interface consists of a clock, latch, data input, and data output lines
for each channel.
The AD8372 provides the ability to set the transconductance of
the output stage using a single external resistor. The RXT1 and
RXT2 pins provide a band gap derived stable reference voltage
of 1.56 V. Typically 2.0 kΩ shunt resistors to ground are used to
set the maximum gain to a nominal value of 31 dB. The current
setting resistors can be adjusted to manipulate the gain and
distortion performance of each channel. This is a flexible
feature in applications where it is desirable to trade off distortion
performance for lower power consumption.
The AD8372 is powered on by applying the appropriate logic
level to the ENB1, ENB2 pins. When powered down, the AD8372
consumes less than 2.6 mA and offers excellent input-to-output
isolation. The gain setting is preserved when powered down.
Fabricated on an Analog Devices, Inc., high frequency BiCMOS
process, the AD8372 provides precise gain adjustment capabilities
with good distortion performance. The quiescent current of the
AD8372 is typically 106 mA per channel. The AD8372 amplifier
comes in a compact, thermally enhanced 5 mm × 5 mm 32-lead
LFCSP package and operates over the temperature range of
−40°C to +85°C.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2007–2011 Analog Devices, Inc. All rights reserved.
AD8372
TABLE OF CONTENTS
Features .............................................................................................. 1
Typical Performance Characteristics ..............................................8
Applications....................................................................................... 1
Theory of Operation ...................................................................... 10
Functional Block Diagram .............................................................. 1
Single-Ended and Differential Signals..................................... 10
General Description ......................................................................... 1
Passive Filter Techniques........................................................... 10
Revision History ............................................................................... 2
Digital Gain Control .................................................................. 10
Specifications..................................................................................... 3
Driving Analog-to-Digital Converters.................................... 10
Serial Control Interface Timing ................................................. 5
Evaluation Board Schematic ......................................................... 12
Absolute Maximum Ratings............................................................ 6
Outline Dimensions ....................................................................... 13
ESD Caution.................................................................................. 6
Ordering Guide .......................................................................... 13
Pin Configuration and Function Descriptions............................. 7
REVISION HISTORY
6/11—Rev. A to Rev. B
Changes to Table 4............................................................................ 6
Changes to Figure 4 and Table 5..................................................... 7
Added Exposed Pad Notation to Outline Dimensions ............. 13
Changes to Ordering Guide .......................................................... 13
5/08—Rev. 0 to Rev. A
Changes to Features and Figure 1................................................... 1
Changes to Figure 2 and Figure 3................................................... 5
Changes to Figure 9.......................................................................... 8
Changes to Figure 16...................................................................... 12
11/07—Revision 0: Initial Version
Rev. B | Page 2 of 16
AD8372
SPECIFICATIONS
VS = 5 V, T = 25°C, ZS = 150 Ω, ZL = 250 Ω at 35 MHz, 1 V p-p differential output, RXT1 = RXT2 = 2.0 kΩ, unless otherwise noted.
Table 1.
Parameter
DYNAMIC PERFORMANCE
−3 dB Bandwidth
INPUT STAGE
Maximum Input Swing at Each Input Pin
Input Resistance
Common-Mode Input Voltage
CMRR
GAIN
Maximum Voltage Gain
Minimum Voltage Gain
Gain Step Size
Gain Step Accuracy
Gain Flatness
Gain Temperature Sensitivity
Step Response
OUTPUT STAGE
Output Voltage Swing
Output Resistance
Channel Isolation
NOISE/HARMONIC PERFORMANCE
5 MHz
Noise Figure
Second Harmonic
Third Harmonic
Output IP3
Output 1 dB Compression Point
35 MHz
Noise Figure
Second Harmonic
Third Harmonic
Output IP3
Output 1 dB Compression Point
65 MHz
Noise Figure
Second Harmonic
Third Harmonic
Output IP3
Output 1 dB Compression Point
85 MHz
Noise Figure
Second Harmonic
Third Harmonic
Output IP3
Output 1 dB Compression Point
Conditions
Min
VOUT < 1 V p-p, CLOAD < 3pF
Pin IPC1, Pin INC1, Pin IPC2, and Pin INC2
Differential
Gain code = 1x101010 (max gain)
Gain code = 1x101010
Gain code = 1x000001
From gain code 1x000001 to 1x101010
From gain code 1x000001 to 1x101010
Gain code = 1x101010, from 5 MHz to 65MHz
Gain code = 1x101010
For 6 dB gain step, 10% settling
Pin OPC1, Pin ONC1, Pin OPC2, and Pin ONC2
At P1dB, gain code = 1x101010
Differential
Measured at differential output for differential input
applied to alternate channel
Typ
Max
Unit
130
MHz
5
150
2.4
55
V p-p
Ω
V
dB
32
−9
1.0
±0.3
0.7
7.5
20
dB
dB
dB
dB
dB
mdB/°C
ns
9
3.5
55
V p-p
kΩ
dB
7.8
79
91
32
18.2
dB
dBc
dBc
dBm
dBm
7.8
79
87
35
18.1
dB
dBc
dBc
dBm
dBm
7.9
78
85
35
17.9
dB
dBc
dBc
dBm
dBm
8.1
77
85
35
17.7
dB
dBc
dBc
dBm
dBm
Gain code = 1x101010 (max gain)
Gain code = 1x101010 (max gain)
Gain code = 1x101010 (max gain)
Gain code = 1x101010
Rev. B | Page 3 of 16
AD8372
Parameter
POWER INTERFACE
Supply Voltage
Quiescent Current per Channel
Conditions
Typ
4.5
vs. Temperature
Power-Down Current, Both Channels
vs. Temperature
ENABLE INTERFACE
Enable Threshold
ENB1, ENB2 Input Bias Current
GAIN CONTROL INTERFACE
VIH
Input Bias Current
Serial Port Output Feedthrough
Min
Thermal connection made to exposed paddle under
device
−40°C ≤ TA ≤ +85°C
ENB1 and ENB2 low
−40°C ≤ TA ≤ +85°C
Pin ENB1 and Pin ENB2
Minimum voltage to enable the device
ENB1, ENB2 = 0 V
Pin CLK1, Pin CLK2, Pin SDI1, Pin SDI2, Pin SDO1, Pin
SDO2, Pin LCH1, and Pin LCH2
Minimum voltage for a logic high
Worse-case feedthrough from CLK1, CLK2, SDI1,
SDI2, SDO1, SDO2, LCH1, LCH2 to OPC1 and ONC2,
or OPC2 and ONC2
Max
Unit
5.5
V
mA
135
mA
mA
mA
106
1.2
1.3
400
0.8
V
nA
400
−60
V
nA
dB
2.4
Table 2. Gain Code vs. Voltage Gain Look-Up Table
8-Bit Binary Gain Code 1
RW DC 000000
RW DC 000001
RW DC 000010
RW DC 000011
RW DC 000100
RW DC 000101
RW DC 000110
RW DC 000111
RW DC 001000
RW DC 001001
RW DC 001010
RW DC 001011
RW DC 001100
RW DC 001101
RW DC 001110
RW DC 001111
RW DC 010000
RW DC 010001
RW DC 010010
RW DC 010011
RW DC 010100
RW DC 010101
1
8-Bit Binary Gain Code 1
RW DC 010110
RW DC 010111
RW DC 011000
RW DC 011001
RW DC 011010
RW DC 011011
RW DC 011100
RW DC 011101
RW DC 011110
RW DC 011111
RW DC 100000
RW DC 100001
RW DC 100010
RW DC 100011
RW DC 100100
RW DC 100101
RW DC 100110
RW DC 100111
RW DC 101000
RW DC 101001
RW DC 101010
RW DC 101011
Voltage Gain (dB)
< −60
−9
−8
−7
−6
−5
−4
−3
−2
−1
0
+1
+2
+3
+4
+5
+6
+7
+8
+9
+10
+11
RW is the read/write bit. RW = 0 for read mode; RW = 1 for write mode. DC is
the don’t care bit.
Rev. B | Page 4 of 16
Voltage Gain (dB)
+12
+13
+14
+15
+16
+17
+18
+19
+20
+21
+22
+23
+24
+25
+26
+27
+28
+29
+30
+31
+32
< −60
AD8372
SERIAL CONTROL INTERFACE TIMING
tCLK
tPW
CLK1 OR CLK2
tLH
tLS
LCH1 OR LCH2
tDS
SDI1 OR SDI2
tDH
WRITE BIT
DON'T CARE
LSB
LSB + 1
LSB + 2
MSB – 2
MSB – 1
MSB
07051-003
NOTES
1. THE FIRST SDI BIT DETERMINES WHETHER THE PART IS WRITING TO OR READING FROM THE INTERNAL GAIN WORD REGISTER. FOR A
WRITE OPERATION, THE FIRST BIT SHOULD BE A LOGIC 1. THE GAIN WORD BIT IS THEN REGISTERED INTO THE SDI PIN ON CONSECUTIVE
RISING EDGES OF THE CLOCK.
Figure 2. Write Mode Timing Diagram
tLH
tPW
tCLK
tD
CLK1 OR CLK2
tLS
LCH1 OR LCH2
SDI1 OR SDI2
tDH
READ BIT
SDO1 OR SDO2
DC
LSB
DC
DC
DC
DC
LSB + 1
LSB + 2
MSB – 2
MSB – 1
DC
DC
MSB
07051-004
tDS
NOTES
1. THE FIRST SDI BIT DETERMINES WHETHER THE PART IS WRITING TO OR READING FROM THE INTERNAL GAIN WORD REGISTER. FOR A
READ OPERATION, THE FIRST BIT SHOULD BE A LOGIC 0. THE GAIN WORD BIT IS THEN UPDATED AT THE SDO PIN ON CONSECUTIVE
FALLING EDGES OF THE CLOCK.
Figure 3. Read Mode Timing Diagram
Table 3. Serial Programming Timing Parameters
Parameter
Clock Pulse Width (tPW)
Clock Period (tCK)
Write Mode
Setup Time Data vs. Clock (tDS)
Hold Time Data vs. Clock (tDH)
Setup Time Latch vs. Clock (tLS)
Hold Time Latch vs. Clock (tLH)
Read Mode
Clock to Data Out (tD)
Rev. B | Page 5 of 16
Min
10
20
Unit
ns
ns
0.0
1.6
−1.8
2.0
ns
ns
ns
ns
4.5
ns
AD8372
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter
Supply Voltage, VS
ENB1, ENB2, SDI1, SDI2, SDO1, SDO2, CLK1,
CLK2, LCH1, LCH2
Input Voltage, VIPC1, VINC1, VIPC2, VINC2
Internal Power Dissipation
θJA (Exposed Paddle Soldered Down)
θJC (At Exposed Paddle)
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
1
2
Rating
5.5 V
DGDx − 0.5 V to
VS + 500 mV
AGDx − 0.5 V to
VS + 500 mV
1.4 W
34.6°C/W 1, 2
3.6°C/W2
150°C
−40°C to +85°C
−65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Still air.
All values are modeled using a standard 4-layer JEDEC test board with the
pad soldered to the board and thermal vias in the board.
Rev. B | Page 6 of 16
AD8372
32
31
30
29
28
27
26
25
DGD1
INC1
IPC1
REF1
RXT1
AGD1
ENB1
AVS1
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
PIN 1
INDICATOR
AD8372
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
OPC1
ONC1
AGD1
SDO1
SDO2
AGD2
ONC2
OPC2
07051-002
DGD2
INC2
IPC2
REF2
RXT2
AGD2
ENB2
AVS2
9
10
11
12
13
14
15
16
DVS1
LCH1
SDI1
CLK1
CLK2
SDI2
LCH2
DVS2
NOTES
1. THE EXPOSED PAD SHOULD BE CONNECTED
TO AGD1 AND AGD2.
Figure 4. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Mnemonic
DVS1
LCH1
SDI1
CLK1
CLK2
SDI2
LCH2
DVS2
DGD2
INC2
IPC2
REF2
RXT2
AGD2
ENB2
AVS2
OPC2
ONC2
AGD2
SDO2
SDO1
AGD1
ONC1
OPC1
AVS1
ENB1
AGD1
RXT1
REF1
IPC1
INC1
DGD1
EPAD
Description
Digital Supply Pin for Channel 1
Latch Input for Channel 1
Serial Data Input for Channel 1
Clock Input for Channel 1
Clock Input for Channel 2
Serial Data Input for Channel 2
Serial Data Input for Channel 2 Latch Input for Channel 2
Digital Supply Pin for Channel 2
Digital Ground for Channel 2
Negative Input for Channel 2
Positive Input for Channel 2
Reference Voltage for Channel 2
External Bias Setting Resistor Connection for Channel 2
Analog Ground for Channel 2
Chip Enable Pin for Channel 2
Analog Supply Pin for Channel 2
Positive Output for Channel 2
Negative Output for Channel 2
Analog Ground for Channel 2
Serial Data Output for Channel 2
Serial Data Output for Channel 1
Analog Ground for Channel 1
Negative Output for Channel 1
Positive Output for Channel 1
Analog Supply Pin for Channel 1
Chip Enable Pin for Channel 1
Analog Ground for Channel 1
External Bias Setting Resistor Connection for Channel 1
Reference Voltage for Channel 1
Positive Input for Channel 1
Negative Input for Channel 1
Digital Ground for Channel 1
Exposed Pad. The exposed pad should be connected to AGD1 and AGD2.
Rev. B | Page 7 of 16
AD8372
TYPICAL PERFORMANCE CHARACTERISTICS
VS = 5 V, TA = 25°C, ZS = 150 Ω, ZL = 250 Ω, 1 V p-p differential output, both channels enabled, unless otherwise noted.
20
40
OUTPUT REFERRED P1dB (dBm)
VOLTAGE GAIN (dB)
30
20
10
0
–10
19
+25°C
18
+85°C
–40°C
17
16
–20
FREQUENCY (Hz)
15
0
10
40
50
60
70
80
90
Figure 8. P1dB, Maximum Gain
–60
180
9
–65
160
8
140
7
120
6
100
5
80
4
60
3
40
2
20
1
–70
RESISTANCE (Ω)
–75
HD2
–80
HD3
–85
–90
–95
0
10
20
30
40
50
60
70
80
90
FREQUENCY (MHz)
0
07051-006
–100
0
50
100
150
200
0
300
250
FREQUENCY (MHz)
Figure 9. Input Equivalent Parallel Impedance
Figure 6. 2nd and 3rd Harmonic Distortion
70
100
90
60
80
OIP2 – AV = 32
50
70
60
CMRR (dB)
OIP2 – AV = 10
OIP2 – AV = –9
50
40
OIP3 – AV = 10
OIP3 – AV = 32
30
40
30
20
OIP3 – AV = –9
20
10
10
0
0
10
20
30
40
50
60
FREQUENCY (MHz)
70
80
90
07051-007
0
0
10
20
30
40
50
60
70
FREQUENCY (MHz)
Figure 10. CMRR vs. Frequency
Figure 7. OIP2 and OIP3
Rev. B | Page 8 of 16
80
90
100
07051-010
HARMONIC DISTORTION (dBc)
30
FREQUENCY (MHz)
Figure 5. Gain vs. Frequency by Gain Code (All Codes),
Differential In, Differential Out
OIP2/OIP3 (dBm)
20
07051-008
1G
CAPACITANCE (pF)
100M
07051-009
10M
07051-005
–30
1M
AD8372
50
45
AV = 0dB
NOISE FIGURE (dB)
40
35
AV = 10dB
30
25
AV = 20dB
20
15
AV = 32dB
07051-011
10
5
0
20
40
60
80
100
120
140
160
180
200
FREQUENCY (MHz)
20ns/DIV
07051-012
0
Figure 11. Noise Figure vs. Frequency
Figure 13. AD8372 Response to 6 dB Step Change in Gain (Gain Register
Setting 36 to Setting 42); Falling Edge Shown is Serial Clock Input Edge
0
–10
–20
(dB)
–30
–40
–50
–60
–70
–90
1M
10M
100M
1G
FREQUENCY (Hz)
07051-013
–80
Figure 12. Isolation, Input to Opposite Output at Maximum Gain
(To calculate output to output gain, subtract 29 dB from this plot)
Rev. B | Page 9 of 16
AD8372
THEORY OF OPERATION
The AD8372 is a dual differential variable gain amplifier. Each
amplifier consists of a 150 Ω digitally controlled 6 dB attenuator
followed by a 1 dB vernier and a fixed gain transconductance
amplifier.
The differential output on each amplifier consists of a pair of
open-collector transistors. It is recommended that each opencollector output be biased to +5 V with a high value inductor.
A 33 μH inductor, such as the Coilcraft® 1812LS-333XJL, is an
excellent choice for this component. A 250 Ω resistor should be
placed across the differential outputs to provide a current-tovoltage conversion and as a source impedance for passive
filtering, post AD8372.
The gain for each side is based on a 250 Ω differential load and
varies as the RLOAD changes per the following equations:
Gain = 20log(RLOAD/250), for voltage gain
Gain = 10log(RLOAD/250), for power gain
The dependency of the gain on the load is due to the opencollector output stage that is biased using external chokes. The
inductance of the chokes and the resistance of the load determine the low frequency pole of the amplifier. The high frequency
pole is set by the parasitic capacitance of the chokes and outputs
in parallel with the output resistance.
The total supply current of 106 mA per side consists of 70 mA
for the combined outputs and about 36 mA through the power
supply pins. Each side has an external resistor (REXT) to ground
to set the transconductance of the output stage. For optimum
distortion, 106 mA total current per side is recommended,
making the REXT value about 2.0 kΩ. Each side has a 2.4 V
reference pin and that same common-mode voltage appears on
the inputs. This reference should be decoupled using a 0.1 μF
capacitor. The part can be powered down to less than 2.6 mA by
setting the ENB pin low for the appropriate side.
The noise figure of the AD8372 is 7.8 dB at maximum gain and
increases as the gain is reduced. The increase in noise figure is
equal to the reduction in gain.
The linearity of the part measured at the output is first-order
independent of the gain setting.
Layout considerations should include minimizing capacitance
on the outputs by avoiding ground planes under the chokes, and
equalizing the output line lengths for phase balance.
SINGLE-ENDED AND DIFFERENTIAL SIGNALS
The AD8372 is designed to be used by applying differential
signals to the inputs and using the differential output drive of
the device to drive the next device in the signal chain. The
excellent distortion performance of the AD8372 is due
primarily to the use of differential signaling techniques to
cancel various distortion components in the device. In addition,
all ac characterization is done using differential signal paths.
Using this device with either the input or the output in a singleended circuit significantly degrades the overall performance of
the AD8372.
PASSIVE FILTER TECHNIQUES
The AD8372 has a 100 Ω differential input impedance. For
optimal performance, the differential output load should be
250 Ω. When designing passive filters around the AD8372,
these impedances must be taken into account.
DIGITAL GAIN CONTROL
The digital gain control interface consists of the following pins:
SDI, SDO, CLK, and LATCH. The interface is active when the
LATCH pin is shifted low. Gain words are written into the
AD8372 via the SDI pin, and read back from the SDO pin. The
first bit clocked into the data input pin determines whether the
interface is in write or read mode. The second bit is a don’t care
bit, while the remaining six bits program the gain. In read
mode, the SDO pin clocks out the 6-bit gain word, LSB to MSB.
The gain can be programmed between −9 dB and 32 dB in 1 dB
steps. Timing details are given in Figure 2 and Figure 3. The
gain code is given in Table 2.
DRIVING ANALOG-TO-DIGITAL CONVERTERS
The AD8372 is designed with the intention of driving high
speed, high dynamic range ADCs. The circuit in Figure 14
represents a simplified front end of one-half of the AD8372 dual
VGA driving an AD9445 14-bit, 125 MHz analog-to-digital
converter (ADC). The input of the AD8372 is driven
differentially using a 1:3 impedance ratio transformer, which
also matches the 150 Ω input resistance to a 50 Ω source. The
open-collector outputs are biased through the 33 μH inductors
and are ac-coupled from the 142 Ω load resistors that, in
parallel with the 2 kΩ input resistance of the ADC, provide a
250 Ω load for gain accuracy.
The ADC is ac-coupled from the 142 Ω resistors to negate a dc
effect on the input common-mode voltage of the AD9445.
Including the series 33 Ω resistors improves the isolation of the
AD8372 from the switching currents caused by the ADC input
sample and hold. The AD9445 represents a 2 kΩ differential
load and requires a 2 V p-p signal when VREF = 1 V for a fullscale output. This circuit provides variable gain, isolation, and
source matching for the AD9445. Using this circuit with the
AD8372 in a gain of 32 dB (maximum gain), an SFDR
performance of 74.5 dBc is achieved at 85 MHz (see Figure 15).
Rev. B | Page 10 of 16
AD8372
5V
5V
1:3
0.1µF
33µH
142Ω
0.1µF
0.1µF
33Ω
VIN+
½
AD8372
50Ω
VGA
0.1µF
AC
0.1µF
0.1µF 33Ω
AD9445
14
14-BIT ADC
142Ω
5V
07051-018
CKL1
SD01
ENA1
33µH
VIN–
Figure 14. AD8372 Driving an AD9445 ADC
0
FUND: –1.053dBFS
–10 2ND: –74.55dBc
–20 3RD: –86.45dBc
4TH: –91.35dBc
–30 5TH: –89.57dBc
6TH: –91.15dBc
–40
1
SNR: 58.12dBc
SNRFS: 59.18dBc
THD: –73.99dBc
SINAD: 58.01dBc
SFDR: 74.73dBc
WO SPUR: –85.5dBc
NOISE FLOOR: –101.3dB
–50
(dBc)
–60
2
–70
–80
5
–90
6
4
3
–100
–110
–120
ENCODE: 105MHz
SAMPLES: 32768
ANALOG: 19.8766MHz
–140
–150
0
FUND LEAK: 100
HARM LEAK: 3
DC LEAK: 6
5.25 10.50 15.75 21.00 26.25 31.50 36.75 42.00 47.25 52.50
FREQUENCY (MHz)
07051-019
–130
Figure 15. 74.5 dBc SFDR Performance of the AD8372 Driving the AD9445 ADC
Rev. B | Page 11 of 16
Figure 16. AD8372 Evaluation Board Schematic
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
P2
P2
P2
P2
P2
P2
P2
P2
P2
H1-8
H1-7
H1-12
H1-11
H1-10
H1-9
H1-1
DGND
C0603
0
C20
0.1UF
R4
0
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
P2
P2
P2
P2
P2
P2
P2
P2
P2
R0603
R0603
R0603
R0603
R0603
R0603
R0603
P2
R5
0
R6
0
R7
0
R8
0
R10
0
R9
DGND
C0603
1NF
C1
DGND
C0603
TBD
C2
DGND
C0603
TBD
C3
DGND
C0603
TBD
C4
DGND
C0603
TBD
C5
DGND
C0603
TBD
C7
DGND
C0603
TBD
C6
DGND
C0603
1NF
C8
H1-16
H1-15
H1-3
H1-4
H1-5
H1-6
H1-14
H1-13
DGND
DGND
DGND
DGND
DGND
DGND
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
P2
P2
P2
P2
P2
P2
P2
P2
P2
P2
75 OHMS
H1-8
H1-7
H1-12
H1-11
H1-10
H1-9
H1-6
H1-12
H1-1
AGND
C0603
AGND
AGND
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
P2
P2
P2
P2
P2
P2
P2
P2
P2
AGND
R0603
0
A GND
T2
1:3
75 OHMS
A GND
AGND
H1-16
H1-15
H1-3
H1-4
H1-5
H1-6
H1-14
H1-13
R0603
0
R20
50 OHMS
T1
1:3
75 OHMS
C0603
C23
0.1UF
R0603
TBD
R12
C0603
AGND
R0603
R33
TBD
R0603
0
8
7
6
5
4
3
2
1
C24
0.1UF
R42
R0603
R32
TBD
DGND
AGND
AGND
AGND
R2
0.1UF
C32
C0603
R0603
2K
32 31 30 29 28 27 26 25
C0603
H1-6
H1-12
H1-9
H1-10
H1-11
H1-12
H1-6
H1-5
H1-4
H1-3
P1 13
AGND
R1
R0603
2K
P1 12
P1 11
P1 10
P1 9
P1 8
P1 7
P1 6
P1 5
P1 4
P1 3
P1 2
Z1
AD8372
A GND
A GND
W2
P1 25
P1 24
P1 23
P1 22
P1 21
P1 20
H1-13
R0603
TBD
10K
C10
0
R0603
C0603
AGND
C0603
R0603
R0603
0.1UF
C13
1NF
C12
AGND
C0603
TBD
C9
AGND
C0603
C16
1NF
C0603
P1 19
P1 18
P1 17
P1 16
P1 15
P1 14
AGND
0
R13
0
R14
1812
0
H1-7
SDO2
SDO1
1812
0
R23
AGND
AGND
R0603
0
R49
1812
C1206
TBD
L5
L4
33UH
R25
0
R0603
H1-15
R24
0
R0603
DGND
DGND
H1-13
113
R38
R0603
R0603
113
AGND
24.9_1%
R44
AGND
R0603
R0603
R0603
AGND
AGND
AGND
3528
C33
10UF
24.9_1%
R45
R0603
3
2
1
S EC
T4
3
2
1
S EC
AGND
RED
TES TLOOP
0
R28
0.1UF
C15
R0603
R0603
C1206
TBD
L6
A GND
AGND
3528
10UF
C34
50 OHMS
DGND
ONC1
OPC1
ONC2
ORANGE
TE STLOOP
R0603
AGND
50 OHMS
50 OHMS
AGND
VSS
0
R27
0
R29
H1-15
50 OHMS
R0603
C0603
0
R30
0.1UF
C14
C0603
AGND
VDD
PRI
6
4
PRI
6
4
H1-1
T3
100 OHMS
24.9_1%
R46
24.9_1%
R43
100 OHMS
R0603
TBD
R21
100 OHMS
R0603
100 OHMS
R26
TBD
R0603
0.1UF
C28
R37
R36
113
R0603
C0603
R35
113
0.1UF
C29
C0603
0.1UF
C18
C0603
100 OHMS
0.1UF
C11
C0603
100 OHMS
100 OHMS
H1-15
L3
33UH
R22
R0603
H1-15
L2
33UH
100 OHMS
100 OHMS
1812
R0603
H1-15
L1
33UH
AGND
100 OHMS
R16
0
0.1UF
C17
C0603
R0603
H1-15
TBD
R3
AGND
SDO2
SDO1
AGND
R18
10K
H1-15
H1-12
H1-6
R0603
R0603
TBD
R47
H1-7
R17
17
18
19
20
21
22
23
24
R48
R0603
OCP2
ONC2
AGD2
SDO2
SDO1
AGD1
ONC1
OPC1
AGND
W1
9 10 11 12 13 14 15 16
C19
0.1UF
P1 1
AGND
DGND
DVS2
LCH2
SDI2
CLK2
CLK1
SDI1
LCH1
DVS1
75 OHMS
0.1UF
C26
C0603
AGND
75 OHMS
R0603
TBD
R40
50 OHMS
0.1UF
C27
C0603
75 OHMS
R19
P2
R0603
R34
TBD
R0603
0
R41
R0603
0
6
75 OHMS
0.1UF
C25
C0603
C22
0.1UF
R0603
0
R39
75 OHMS
R0603
R31
TBD
50 OHMS
50 OHMS
AGND
IPC2
P2
H1-1
H1-9
H1-10
H1-11
H1-5
H1-4
H1-3
DGND
C0603
0
C21
0.1UF
W3
W4
P RI
S EC
R15
DGD1
DGD2
A GND
INC1
INC2
R0603
AGD1
R11
IPC1
IPC2
W5
W6
W7
W8
REF1
REF2
H1-1
4
ENB1
4
3
2
1
RXT1
RXT2
3
2
1
SE C
P RI
Rev. B | Page 12 of 16
6
AGND
AVS1
ADG2
INC1
ENB2
IPC1
AVS2
AD8372 CHAR BD
OPC2
AD8372
EVALUATION BOARD SCHEMATIC
INC2
07051-014
AD8372
OUTLINE DIMENSIONS
0.60 MAX
5.00
BSC SQ
0.60 MAX
PIN 1
INDICATOR
0.50
BSC
4.75
BSC SQ
0.50
0.40
0.30
12° MAX
17
16
0.80 MAX
0.65 TYP
0.30
0.23
0.18
1
3.25
3.10 SQ
2.95
EXPOSED
PAD
(BOTTOM VIEW)
9
8
0.25 MIN
3.50 REF
0.05 MAX
0.02 NOM
SEATING
PLANE
32
0.20 REF
COPLANARITY
0.08
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
011708-A
TOP
VIEW
1.00
0.85
0.80
PIN 1
INDICATOR
25
24
Figure 17. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
5 mm × 5 mm Body, Very Thin Quad
(CP-32-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
AD8372ACPZ-WP
AD8372ACPZ-R7
AD8372-EVALZ
1
Temperature
Range
−40°C to +85°C
−40°C to +85°C
Package Description
32-Lead Lead Frame Chip Scale Package [LFCSP_VQ], Waffle Pack
32-Lead Lead Frame Chip Scale Package [LFCSP_VQ], 7” Tape
and Reel
Evaluation Board
Z = RoHS Compliant Part.
Rev. B | Page 13 of 16
Package
Option
CP-32-2
CP-32-2
Ordering
Quantity
36
1,500
AD8372
NOTES
Rev. B | Page 14 of 16
AD8372
NOTES
Rev. B | Page 15 of 16
AD8372
NOTES
©2007–2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07051-0-6/11(B)
Rev. B | Page 16 of 16