ON CAT25640LE-G 64-kb spi serial cmos eeprom Datasheet

CAT25640
64-Kb SPI Serial CMOS
EEPROM
Description
The CAT25640 is a 64−Kb Serial CMOS EEPROM device
internally organized as 8Kx8 bits. This features a 64−byte page write
buffer and supports the Serial Peripheral Interface (SPI) protocol. The
device is enabled through a Chip Select (CS) input. In addition, the
required bus signals are clock input (SCK), data input (SI) and data
output (SO) lines. The HOLD input may be used to pause any serial
communication with the CAT25640 device. The device features
software and hardware write protection, including partial as well as
full array protection.
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SOIC−8
V SUFFIX
CASE 751BD
UDFN−8*
HU3 SUFFIX
CASE 517AX
TDFN−8*
VP2 SUFFIX
CASE 511AK
PDIP−8
L SUFFIX
CASE 646AA
UDFN−8
HU4 SUFFIX
CASE 517AZ
TSSOP−8
Y SUFFIX
CASE 948AL
Features
•
•
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•
•
•
•
•
•
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•
20 MHz (5 V) SPI Compatible
1.8 V to 5.5 V Supply Voltage Range
SPI Modes (0,0) & (1,1)
64−byte Page Write Buffer
Self−timed Write Cycle
Hardware and Software Protection
Block Write Protection
− Protect 1/4, 1/2 or Entire EEPROM Array
Low Power CMOS Technology
1,000,000 Program/Erase Cycles
100 Year Data Retention
Industrial and Extended Temperature Range
PDIP, SOIC, TSSOP 8−lead, TDFN and UDFN 8−pad Packages
This Device is Pb−Free, Halogen Free/BFR Free, and RoHS
Compliant
PIN CONFIGURATION
CS
1
VCC
SO
HOLD
WP
SCK
VSS
SI
PDIP (L), SOIC (V), TSSOP (Y),
TDFN* (VP2), UDFN* (HU3), UDFN (HU4)
* Not recommended for new designs
VCC
PIN FUNCTION
Pin Name
SI
CS
CAT25640
WP
SO
HOLD
SCK
CS
Chip Select
SO
Serial Data Output
WP
Write Protect
VSS
Ground
SI
VSS
Serial Data Input
SCK
Figure 1. Functional Symbol
Function
HOLD
VCC
Serial Clock
Hold Transmission Input
Power Supply
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 19 of this data sheet.
© Semiconductor Components Industries, LLC, 2012
May, 2012 − Rev. 10
1
Publication Order Number:
CAT25640/D
CAT25640
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters
Ratings
Units
Operating Temperature
−45 to +130
°C
Storage Temperature
−65 to +150
°C
Voltage on any Pin with Respect to Ground (Note 1)
−0.5 to +6.5
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The DC input voltage on any pin should not be lower than −0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than −1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns.
Table 2. RELIABILITY CHARACTERISTICS (Note 2)
Symbol
Parameter
NEND (Note 3)
TDR
Endurance
Data Retention
Min
Units
1,000,000
Program / Erase Cycles
100
Years
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
3. Page Mode, VCC = 5 V, 25°C.
Table 3. D.C. OPERATING CHARACTERISTICS
(VCC = 1.8 V to 5.5 V, TA = −40°C to +85°C and VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C, unless otherwise specified.)
Symbol
ICCR
ICCW
ISB1
ISB2
IL
ILO
Parameter
Test Conditions
Max
Units
10 MHz / −40°C to 85°C
2
mA
5 MHz / −40°C to 125°C
2
Write, VCC = 5.5 V,
SO open
10 MHz / −40°C to 85°C
3
5 MHz / −40°C to 125°C
3
VIN = GND or VCC, CS = VCC,
WP = VCC, VCC = 5.5 V
TA = −40°C to +85°C
1
TA = −40°C to +125°C
2
VIN = GND or VCC, CS = VCC,
WP = GND, VCC = 5.5 V
TA = −40°C to +85°C
3
TA = −40°C to +125°C
5
Supply Current
(Read Mode)
Read, VCC = 5.5 V,
SO open
Supply Current
(Write Mode)
Standby Current
Standby Current
Input Leakage Current
VIN = GND or VCC
Output Leakage
Current
CS = VCC,
VOUT = GND or VCC
VIL
Input Low Voltage
VIH
Input High Voltage
VOL1
Output Low Voltage
VCC ≥ 2.5 V, IOL = 3.0 mA
VOH1
Output High Voltage
VCC ≥ 2.5 V, IOH = −1.6 mA
VOL2
Output Low Voltage
VCC < 2.5 V, IOL = 150 mA
VOH2
Output High Voltage
VCC < 2.5 V, IOH = −100 mA
Min
mA
mA
−2
2
mA
TA = −40°C to +85°C
−1
1
mA
TA = −40°C to +125°C
−1
2
−0.5
0.3 VCC
V
0.7 VCC
VCC + 0.5
V
0.4
V
VCC − 0.8 V
V
0.2
VCC − 0.2 V
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2
mA
V
V
CAT25640
Table 4. D.C. OPERATING CHARACTERISTICS − NEW PRODUCT (Rev F)
(VCC = 1.8 V to 5.5 V, TA = −40°C to +85°C and VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C, unless otherwise specified.)
Symbol
ICCR
ICCW
ISB1
ISB2
IL
ILO
Parameter
Supply Current
(Read Mode)
Supply Current
(Write Mode)
Standby Current
Standby Current
Test Conditions
Max
Units
VCC = 1.8 V, fSCK = 5 MHz
0.2
mA
VCC = 2.5 V, fSCK =10 MHz
0.3
VCC = 5.5 V, fSCK = 20 MHz
0.6
Read, SO open /
−40°C to +125°C
2.5 V< VCC < 5.5 V,
fSCK = 10 MHz
0.6
Write, CS = VCC/
−40°C to +85°C
VCC = 1.8 V
0.8
VCC = 2.5 V
1.4
VCC = 5.5 V
2
Write, CS = VCC/
−40°C to +125°C
2.5 V< VCC < 5.5 V
2
VIN = GND or VCC,
CS = VCC, WP = VCC,
VCC = 5.5 V
TA = −40°C to +85°C
1
TA = −40°C to +125°C
3
VIN = GND or VCC,
CS = VCC, WP = GND,
VCC = 5.5 V
TA = −40°C to +85°C
3
TA = −40°C to +125°C
5
Read, SO open /
−40°C to +85°C
Input Leakage Current
VIN = GND or VCC
Output Leakage
Current
CS = VCC
VOUT = GND or VCC
Min
mA
mA
mA
−2
2
mA
TA = −40°C to +85°C
−1
1
mA
TA = −40°C to +125°C
−1
2
VIL
Input Low Voltage
−0.5
0.3 VCC
V
VIH
Input High Voltage
0.7 VCC
VCC + 0.5
V
VOL1
Output Low Voltage
VCC > 2.5 V, IOL = 3.0 mA
0.4
V
VOH1
Output High Voltage
VCC > 2.5 V, IOH = −1.6 mA
VOL2
Output Low Voltage
VCC < 2.5 V, IOL = 150 mA
VOH2
Output High Voltage
VCC < 2.5 V, IOH = −100 mA
VCC − 0.8 V
V
0.2
VCC − 0.2 V
V
V
Table 5. PIN CAPACITANCE (Note 4) (TA = 25°C, f = 1.0 MHz, VCC = +5.0 V)
Symbol
COUT
CIN
Test
Conditions
Output Capacitance (SO)
Input Capacitance (CS, SCK, SI, WP, HOLD)
Min
Typ
Max
Units
VOUT = 0 V
8
pF
VIN = 0 V
8
pF
4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
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CAT25640
Table 6. A.C. CHARACTERISTICS − MATURE PRODUCT
(TA = −40°C to +85°C (Industrial) and TA = −40°C to +125°C (Extended).) (Notes 5, 8)
VCC = 1.8 V − 5.5 V / −405C to +855C
VCC = 2.5 V − 5.5 V
VCC = 2.5 V − 5.5 V / −405C to +1255C
−405C to +855C
Min
Max
Min
Max
Units
fSCK
Clock Frequency
DC
5
DC
10
MHz
tSU
Data Setup Time
40
20
ns
tH
Data Hold Time
40
20
ns
tWH
SCK High Time
75
40
ns
tWL
SCK Low Time
75
40
ns
tLZ
Symbol
Parameter
HOLD to Output Low Z
50
25
ns
tRI (Note 6)
Input Rise Time
2
2
ms
tFI (Note 6)
Input Fall Time
2
2
ms
tHD
HOLD Setup Time
0
0
ns
tCD
HOLD Hold Time
10
10
ns
tV
Output Valid from Clock Low
75
0
40
0
ns
tHO
Output Hold Time
tDIS
Output Disable Time
50
20
ns
ns
tHZ
HOLD to Output High Z
100
25
ns
tCS
CS High Time
50
20
ns
tCSS
CS Setup Time
20
15
ns
tCSH (Note 8)
CS Hold Time
30
20
ns
tCNS
CS Interactive Setup Time
20
15
ns
tCNH
CS Interactive Hold Time
20
15
ns
tWPS
WP Setup Time
10
10
ns
tWPH
WP Hold Time
100
60
ns
tWC (Note 7)
Write Cycle Time
5
5
ms
5. AC Test Conditions:
Input Pulse Voltages: 0.3 VCC to 0.7 VCC
Input rise and fall times: ≤ 10 ns
Input and output reference voltages: 0.5 VCC
Output load: current source IOL max/IOH max; CL = 50 pF
6. This parameter is tested initially and after a design or process change that affects the parameter.
7. tWC is the time from the rising edge of CS after a valid write sequence to the end of the internal write cycle.
8. All Chip Select (CS) timing parameters are defined relative to the positive clock edge (Figure 2). tCSH timing specification is valid
for die revision E and higher. The die revision E is identified by letter “E” or a dedicated marking code on top of the package. For
previous product revision (Rev. D) the tCSH is defined relative to the negative clock edge.
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CAT25640
Table 7. A.C. CHARACTERISTICS – NEW PRODUCT (Rev F) (VCC = 1.8 V to 5.5 V, TA = −40°C to +85°C (Industrial) and
VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C, unless otherwise specified.) (Note 9)
VCC = 1.8 V − 5.5 V
−405C to +855C
Symbol
Parameter
VCC = 2.5 V − 5.5 V
−405C to +1255C
VCC = 4.5 V − 5.5 V
−405C to +855C
Min
Max
Min
Max
Min
Max
Units
5
DC
10
DC
20
MHz
fSCK
Clock Frequency
DC
tSU
Data Setup Time
20
10
5
ns
tH
Data Hold Time
20
10
5
ns
tWH
SCK High Time
75
40
20
ns
tWL
SCK Low Time
75
40
20
ns
tLZ
HOLD to Output Low Z
50
25
25
ns
tRI (Note 10)
Input Rise Time
2
2
2
ms
tFI (Note 10)
Input Fall Time
2
2
2
ms
tHD
HOLD Setup Time
0
0
0
ns
tCD
HOLD Hold Time
10
10
5
ns
tV
Output Valid from Clock Low
tHO
Output Hold Time
tDIS
Output Disable Time
tHZ
70
0
35
0
HOLD to Output High Z
20
0
ns
ns
50
20
20
ns
100
25
25
ns
tCS
CS High Time
80
40
20
ns
tCSS
CS Setup Time
30
30
15
ns
tCSH
CS Hold Time
30
30
20
ns
tCNS
CS Inactive Setup Time
20
20
15
ns
tCNH
CS Inactive Hold Time
20
20
15
ns
tWPS
WP Setup Time
10
10
10
ns
tWPH
WP Hold Time
10
tWC (Note 11)
10
Write Cycle Time
5
10
ns
5
5
ms
9. AC Test Conditions:
Input Pulse Voltages: 0.3 VCC to 0.7 VCC
Input rise and fall times: ≤ 10 ns
Input and output reference voltages: 0.5 VCC
Output load: current source IOL max/IOH max; CL = 30 pF
10. This parameter is tested initially and after a design or process change that affects the parameter.
11. tWC is the time from the rising edge of CS after a valid write sequence to the end of the internal write cycle.
Table 8. POWER−UP TIMING (Notes 10, 12)
Symbol
Parameter
Max
Units
tPUR
Power−up to Read Operation
1
ms
tPUW
Power−up to Write Operation
1
ms
12. tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
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5
CAT25640
Pin Description
Functional Description
SI: The serial data input pin accepts op−codes, addresses
and data. In SPI modes (0,0) and (1,1) input data is latched
on the rising edge of the SCK clock input.
SO: The serial data output pin is used to transfer data out of
the device. In SPI modes (0,0) and (1,1) data is shifted out
on the falling edge of the SCK clock.
SCK: The serial clock input pin accepts the clock provided
by the host and used for synchronizing communication
between host and CAT25640.
CS: The chip select input pin is used to enable/disable the
CAT25640. When CS is high, the SO output is tri−stated (high
impedance) and the device is in Standby Mode (unless an
internal write operation is in progress). Every communication
session between host and CAT25640 must be preceded by a
high to low transition and concluded with a low to high
transition of the CS input.
WP: The write protect input pin will allow all write
operations to the device when held high. When WP pin is
tied low and the WPEN bit in the Status Register (refer to
Status Register description, later in this Data Sheet) is set to
“1”, writing to the Status Register is disabled.
HOLD: The HOLD input pin is used to pause transmission
between host and CAT25640, without having to retransmit
the entire sequence at a later time. To pause, HOLD must be
taken low and to resume it must be taken back high, with the
SCK input low during both transitions. When not used for
pausing, the HOLD input should be tied to VCC, either
directly or through a resistor.
The CAT25640 device supports the Serial Peripheral
Interface (SPI) bus protocol, modes (0,0) and (1,1). The
device contains an 8−bit instruction register. The instruction
set and associated op−codes are listed in Table 9.
Reading data stored in the CAT25640 is accomplished by
simply providing the READ command and an address.
Writing to the CAT25640, in addition to a WRITE
command, address and data, also requires enabling the
device for writing by first setting certain bits in a Status
Register, as will be explained later.
After a high to low transition on the CS input pin, the
CAT25640 will accept any one of the six instruction
op−codes listed in Table 9 and will ignore all other possible
8−bit combinations. The communication protocol follows
the timing from Figure 2.
Table 9. INSTRUCTION SET
Instruction
Op−code
WREN
0000 0110
Enable Write Operations
Operation
WRDI
0000 0100
Disable Write Operations
RDSR
0000 0101
Read Status Register
WRSR
0000 0001
Write Status Register
READ
0000 0011
Read Data from Memory
WRITE
0000 0010
Write Data to Memory
tCS
CS
tCSS
tCNH
tWH
tWL
tCSH
tCNS
SCK
tSU
tH
tRI
tFI
VALID
IN
SI
tV
tV
tDIS
tHO
SO
HI−Z
VALID
OUT
Figure 2. Synchronous Data Timing
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HI−Z
CAT25640
Status Register
The Status Register, as shown in Table 10, contains a
number of status and control bits.
The RDY (Ready) bit indicates whether the device is busy
with a write operation. This bit is automatically set to 1 during
an internal write cycle, and reset to 0 when the device is ready
to accept commands. For the host, this bit is read only.
The WEL (Write Enable Latch) bit is set/reset by the
WREN/WRDI commands. When set to 1, the device is in a
Write Enable state and when set to 0, the device is in a Write
Disable state.
The BP0 and BP1 (Block Protect) bits determine which
blocks are currently write protected. They are set by the user
with the WRSR command and are non−volatile. The user is
allowed to protect a quarter, one half or the entire memory,
by setting these bits according to Table 11. The protected
blocks then become read−only.
The WPEN (Write Protect Enable) bit acts as an enable for
the WP pin. Hardware write protection is enabled when the
WP pin is low and the WPEN bit is 1. This condition
prevents writing to the status register and to the block
protected sections of memory. While hardware write
protection is active, only the non−block protected memory
can be written. Hardware write protection is disabled when
the WP pin is high or the WPEN bit is 0. The WPEN bit, WP
pin and WEL bit combine to either permit or inhibit Write
operations, as detailed in Table 12.
Table 10. STATUS REGISTER
7
6
5
4
3
2
1
0
WPEN
0
0
0
BP1
BP0
WEL
RDY
Table 11. BLOCK PROTECTION BITS
Status Register Bits
BP1
BP0
Array Address Protected
Protection
0
0
None
No Protection
0
1
1800−1FFF
Quarter Array Protection
1
0
1000−1FFF
Half Array Protection
1
1
0000−1FFF
Full Array Protection
Table 12. WRITE PROTECT CONDITIONS
WPEN
WP
WEL
Protected Blocks
Unprotected Blocks
Status Register
0
X
0
Protected
Protected
Protected
0
X
1
Protected
Writable
Writable
1
Low
0
Protected
Protected
Protected
1
Low
1
Protected
Writable
Protected
X
High
0
Protected
Protected
Protected
X
High
1
Protected
Writable
Writable
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CAT25640
WRITE OPERATIONS
Write Enable and Write Disable
The CAT25640 device powers up into a write disable
state. The device contains a Write Enable Latch (WEL)
which must be set before attempting to write to the memory
array or to the status register. In addition, the address of the
memory location(s) to be written must be outside the
protected area, as defined by BP0 and BP1 bits from the
status register.
The internal Write Enable Latch and the corresponding
Status Register WEL bit are set by sending the WREN
instruction to the CAT25640. Care must be taken to take the
CS input high after the WREN instruction, as otherwise the
Write Enable Latch will not be properly set. WREN timing
is illustrated in Figure 3. The WREN instruction must be
sent prior to any WRITE or WRSR instruction.
The internal write enable latch is reset by sending the
WRDI instruction as shown in Figure 4. Disabling write
operations by resetting the WEL bit, will protect the device
against inadvertent writes.
CS
SCK
0
SI
SO
0
0
0
0
1
1
0
HIGH IMPEDANCE
Dashed Line = mode (1, 1)
Figure 3. WREN Timing
CS
SCK
SI
SO
0
0
0
0
0
1
0
HIGH IMPEDANCE
Dashed Line = mode (1, 1)
Figure 4. WRDI Timing
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8
0
CAT25640
Byte Write
Page Write
Once the WEL bit is set, the user may execute a write
sequence, by sending a WRITE instruction, a 16−bit address
and data as shown in Figure 5. Only 13 significant address
bits are used by the CAT25640. The rest are don’t care bits,
as shown in Table 13. Internal programming will start after
the low to high CS transition. During an internal write cycle,
all commands, except for RDSR (Read Status Register) will
be ignored. The RDY bit will indicate if the internal write
cycle is in progress (RDY high), or the device is ready to
accept commands (RDY low).
After sending the first data byte to the CAT25640, the host
may continue sending data, up to a total of 64 bytes,
according to timing shown in Figure 6. After each data byte,
the lower order address bits are automatically incremented,
while the higher order address bits (page address) remain
unchanged. If during this process the end of page is
exceeded, then loading will “roll over” to the first byte in the
page, thus possibly overwriting previously loaded data.
Following completion of the write cycle, the CAT25640 is
automatically returned to the write disable state.
Table 13. BYTE ADDRESS
Device
Address Significant Bits
Address Don’t Care Bits
# Address Clock Pulses
A12 − A0
A15 − A13
16
CAT25640
CS
0
1
2
3
4
5
6
7
8
21
22 23
24
25
26 27
28
29
30 31
SCK
OPCODE
SI
0
0
0
0
0
0
DATA IN
BYTE ADDRESS*
1
0
A0 D7 D6 D5 D4 D3 D2 D1 D0
AN
HIGH IMPEDANCE
SO
Dashed Line = mode (1, 1)
* Please check the Byte Address Table (Table 13)
Figure 5. Byte WRITE Timing
CS
0
1
2
3
4
5
6
7
8
21
SCK
0
0
0
0
0
0
23 24−31 32−39 24+(N−1)x8−1 .. 24+(N−1)x8
24+Nx8−1
BYTE ADDRESS*
OPCODE
SI
22
1
0
AN
DATA IN
A0
Data Data Data
Byte 1 Byte 2 Byte 3
HIGH IMPEDANCE
SO
Dashed Line = mode (1, 1)
Data Byte N
7..1
0
* Please check the Byte Address Table (Table 13)
Figure 6. Page WRITE Timing
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CAT25640
Write Status Register
Write Protection
The Status Register is written by sending a WRSR
instruction according to timing shown in Figure 7. Only bits
2, 3 and 7 can be written using the WRSR command.
The Write Protect (WP) pin can be used to protect the
Block Protect bits BP0 and BP1 against being inadvertently
altered. When WP is low and the WPEN bit is set to “1”,
write operations to the Status Register are inhibited. WP
going low while CS is still low will interrupt a write to the
status register. If the internal write cycle has already been
initiated, WP going low will have no effect on any write
operation to the Status Register. The WP pin function is
blocked when the WPEN bit is set to “0”. The WP input
timing is shown in Figure 8.
CS
0
1
2
3
4
5
6
7
8
9
10
11
1
7
6
5
4
12
13
14
15
2
1
0
SCK
OPCODE
SI
0
0
0
0
0
0
0
MSB
HIGH IMPEDANCE
SO
Dashed Line = mode (1, 1)
Figure 7. WRSR Timing
tWPS
tWPH
CS
SCK
WP
WP
Dashed Line = mode (1, 1)
Figure 8. WP Timing
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DATA IN
3
CAT25640
READ OPERATIONS
Read from Memory Array
address, and the read cycle can be continued indefinitely.
The read operation is terminated by taking CS high.
To read from memory, the host sends a READ instruction
followed by a 16−bit address (see Table 13 for the number
of significant address bits).
After receiving the last address bit, the CAT25640 will
respond by shifting out data on the SO pin (as shown in
Figure 9). Sequentially stored data can be read out by simply
continuing to run the clock. The internal address pointer is
automatically incremented to the next higher address as data
is shifted out. After reaching the highest memory address,
the address counter “rolls over” to the lowest memory
Read Status Register
To read the status register, the host simply sends a RDSR
command. After receiving the last bit of the command, the
CAT25640 will shift out the contents of the status register on
the SO pin (Figure 10). The status register may be read at
any time, including during an internal write cycle. While the
internal write cycle is in progress, the RDSR command will
output the contents of the status register.
CS
0
1
2
3
4
5
6
7
8
9
20 21
10
22 23
24
25
26 27
28 29
30
SCK
OPCODE
SI
0
0
0
0
0
0
BYTE ADDRESS*
1
1
A0
AN
DATA OUT
HIGH IMPEDANCE
SO
7
Dashed Line = mode (1, 1)
* Please check the Byte Address Table (Table 13)
6
5
4
3
2
1
0
MSB
Figure 9. READ Timing
CS
0
1
2
3
4
5
6
7
1
0
1
8
9
10
6
5
11
12
13
14
2
1
SCK
OPCODE
SI
SO
0
0
0
0
0
DATA OUT
HIGH IMPEDANCE
7
MSB
Dashed Line = mode (1, 1)
Figure 10. RDSR Timing
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11
4
3
0
CAT25640
Hold Operation
below the POR trigger level. This bi−directional POR
behavior protects the device against ‘brown−out’ failure
following a temporary loss of power.
The CAT25640 device powers up in a write disable state
and in a low power standby mode. A WREN instruction
must be issued prior to any writes to the device.
After power up, the CS pin must be brought low to enter
a ready state and receive an instruction. After a successful
byte/page write or status register write, the device goes into
a write disable mode. The CS input must be set high after the
proper number of clock cycles to start the internal write
cycle. Access to the memory array during an internal write
cycle is ignored and programming is continued. Any invalid
op−code will be ignored and the serial output pin (SO) will
remain in the high impedance state.
The HOLD input can be used to pause communication
between host and CAT25640. To pause, HOLD must be
taken low while SCK is low (Figure 11). During the hold
condition the device must remain selected (CS low). During
the pause, the data output pin (SO) is tri−stated (high
impedance) and SI transitions are ignored. To resume
communication, HOLD must be taken high while SCK is low.
Design Considerations
The CAT25640 device incorporates Power−On Reset
(POR) circuitry which protects the internal logic against
powering up in the wrong state. The device will power up
into Standby mode after VCC exceeds the POR trigger level
and will power down into Reset mode when VCC drops
CS
tCD
tCD
SCK
tHD
tHD
HOLD
tHZ
HIGH IMPEDANCE
SO
tLZ
Dashed Line = mode (1, 1)
Figure 11. HOLD Timing
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12
CAT25640
PACKAGE DIMENSIONS
PDIP−8, 300 mils
CASE 646AA−01
ISSUE A
SYMBOL
MIN
NOM
A
E1
5.33
A1
0.38
A2
2.92
3.30
4.95
b
0.36
0.46
0.56
b2
1.14
1.52
1.78
c
0.20
0.25
0.36
D
9.02
9.27
10.16
E
7.62
7.87
8.25
E1
6.10
6.35
7.11
e
PIN # 1
IDENTIFICATION
MAX
2.54 BSC
eB
7.87
L
2.92
10.92
3.30
3.80
D
TOP VIEW
E
A2
A
A1
c
b2
L
e
eB
b
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MS-001.
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13
CAT25640
PACKAGE DIMENSIONS
SOIC 8, 150 mils
CASE 751BD−01
ISSUE O
E1
E
SYMBOL
MIN
A
1.35
1.75
A1
0.10
0.25
b
0.33
0.51
MAX
c
0.19
0.25
D
4.80
5.00
E
5.80
6.20
E1
3.80
e
PIN # 1
IDENTIFICATION
NOM
4.00
1.27 BSC
h
0.25
0.50
L
0.40
1.27
θ
0º
8º
TOP VIEW
D
h
A1
θ
A
c
e
b
L
END VIEW
SIDE VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
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14
CAT25640
PACKAGE DIMENSIONS
TSSOP8, 4.4x3
CASE 948AL−01
ISSUE O
b
SYMBOL
MIN
NOM
A
E1
E
MAX
1.20
A1
0.05
A2
0.80
b
0.19
0.15
0.90
1.05
0.30
c
0.09
D
2.90
3.00
3.10
E
6.30
6.40
6.50
E1
4.30
4.40
4.50
0.20
e
0.65 BSC
L
1.00 REF
L1
0.50
θ
0º
0.60
0.75
8º
e
TOP VIEW
D
A2
c
q1
A
A1
L1
SIDE VIEW
L
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-153.
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15
CAT25640
PACKAGE DIMENSIONS
TDFN8, 2x3
CASE 511AK−01
ISSUE A
D
A
e
b
E2
E
PIN#1
IDENTIFICATION
A1
PIN#1 INDEX AREA
D2
TOP VIEW
SYMBOL
MIN
SIDE VIEW
NOM
A
0.70
0.75
0.80
0.00
0.02
0.05
A2
0.45
0.55
0.65
A2
0.20 REF
A3
b
0.20
0.25
0.30
D
1.90
2.00
2.10
D2
1.30
1.40
1.50
E
2.90
3.00
3.10
E2
1.20
1.30
1.40
e
L
BOTTOM VIEW
MAX
A1
A3
FRONT VIEW
0.50 TYP
0.20
0.30
L
0.40
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MO-229.
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16
CAT25640
PACKAGE DIMENSIONS
UDFN8, 2x3
CASE 517AX−01
ISSUE O
D
A
DETAIL A
DAP SIZE 1.3 x 1.8
E
PIN #1
IDENTIFICATION
E2
A1
PIN #1 INDEX AREA
D2
TOP VIEW
SYMBOL
MIN
NOM
MAX
A
0.45
0.50
0.55
A1
0.00
0.02
0.05
A3
b
L
0.127 REF
K
b
0.20
0.25
0.30
D
1.90
2.00
2.10
D2
1.50
1.60
1.70
E
2.90
3.00
3.10
E2
0.10
0.20
0.30
e
0.50 TYP
K
0.10 REF
L
BOTTOM VIEW
SIDE VIEW
0.30
0.35
e
DETAIL A
A3
A
0.40
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MO-229.
A1
FRONT VIEW
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17
CAT25640
PACKAGE DIMENSIONS
UDFN8, 2x3 EXTENDED PAD
CASE 517AZ−01
ISSUE O
D
b
A
e
L
DAP SIZE 1.8 x 1.8
E2
E
PIN #1
IDENTIFICATION
A1
PIN #1 INDEX AREA
D2
TOP VIEW
SIDE VIEW
SYMBOL
MIN
NOM
MAX
A
0.45
0.50
0.55
A1
0.00
0.02
0.05
A3
b
0.127 REF
0.20
0.25
0.30
D
1.95
2.00
2.05
D2
1.35
1.40
1.45
E
2.95
3.00
3.05
E2
1.25
1.30
1.35
e
L
BOTTOM VIEW
DETAIL A
0.065 REF
A3 A
FRONT VIEW
0.50 REF
0.25
0.30
0.35
A3
Notes:
(1) All dimensions are in millimeters.
(2) Refer JEDEC MO-236/MO-252.
0.0 - 0.05
DETAIL A
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18
0.065 REF
Copper Exposed
CAT25640
ORDERING INFORMATION
Device Order Number
Specific
Device
Marking
(Note 13)
Package Type
Temperature Range
Lead
Finish
CAT25640HU3I−GT3
S6V
UDFN8
−40°C to +85°C
NiPdAu
Tape & Reel,
3,000 Units / Reel
CAT25640HU4E−GT3
S6U
UDFN8−EP
−40°C to +125°C
NiPdAu
Tape & Reel,
3,000 Units / Reel
CAT25640HU4I−GT3
S6U
UDFN8−EP
−40°C to +85°C
NiPdAu
Tape & Reel,
3,000 Units / Reel
CAT25640LE−G
25640F
PDIP−8
−40°C to +125°C
NiPdAu
Tube, 50 Units
CAT25640LI−G
25640F
PDIP−8
−40°C to +85°C
NiPdAu
Tube, 50 Units
CAT25640VE−GT3
25640F
SOIC −8, JEDEC
−40°C to +125°C
NiPdAu
Tape & Reel,
3,000 Units / Reel
CAT25640VI−G
25640F
SOIC−8, JEDEC
−40°C to +85°C
NiPdAu
Tube, 100 Units
CAT25640VI−GT3
25640F
SOIC−8, JEDEC
−40°C to +85°C
NiPdAu
Tape & Reel,
3,000 Units / Reel
CAT25640VP2I−GT3
(Note 15)
S6T
TDFN−8
−40°C to +85°C
NiPdAu
Tape & Reel,
3,000 Units / Reel
CAT25640YE−GT3
S64F
TSSOP−8
−40°C to +125°C
NiPdAu
Tape & Reel,
3,000 Units / Reel
CAT25640YI−G
S64F
TSSOP−8
−40°C to +85°C
NiPdAu
Tube, 100 Units
CAT25640YI−GT3
S64F
TSSOP−8
−40°C to +85°C
NiPdAu
Tape & Reel,
3,000 Units / Reel
Shipping (Note 14)
13. For New Product (Rev F)
14. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
15. Not recommended for new designs.
16. For detailed information and a breakdown of device nomenclature and numbering systems, please see the ON Semiconductor Device
Nomenclature document, TND310/D, available at www.onsemi.com
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: [email protected]
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Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
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19
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
CAT25640/D