Analogic AAT3236IJS-35-T1 300ma cmos high performance ldo Datasheet

AAT3236
300mA CMOS High Performance LDO
General Description
Features
The AAT3236 is a MicroPower™ Low Dropout
Linear Regulator designed to deliver a continuous
300mA output load current and is capable of handling short duration current peaks up to 500mA.
With a very small footprint SOT23-5 package it is
ideally suited for portable applications where low
noise, high power supply ripple rejection, extended
battery life and small size are critical. The AAT3236
features fast transient response and low output self
noise for powering sensitive RF circuitry. Other features include low quiescent current, typically
100µA, and low dropout voltage, typically 300mV at
full output load current. The device has internal output short circuit protection and thermal shutdown to
prevent damage under extreme conditions.
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The AAT3236 is available in a space saving
SOT23-5 or SC70JW-8 package in 7 factory programmed voltages of 2.5V, 2.7V, 2.8V, 2.85V, 3.0V,
3.3V, or 3.5V.
500mA Peak Output Current
Low Dropout - Typically 300mV at 300mA
Guaranteed 300mA Output
High accuracy ±1.5%
100µA Quiescent Current
High Power Supply Ripple Rejection
• 70 dB at 1kHz
• 50 dB at 10kHz
Very low self noise 45µVrms/rtHz
Noise reduction bypass capacitor
Short circuit protection
Over-Temperature protection
Shutdown mode for longer battery life
Low temperature coefficient
7 Factory programmed output voltages
SOT-23 5-pin or SC70JW 8-pin package
Preliminary Information
The AAT3236 also features a low-power shutdown
mode for longer battery life. A bypass pin is provided to improve PSRR performance by connecting an external capacitor from the AAT3236's reference output to ground.
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PowerLinear™
Applications
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Cellular Phones
Notebook Computers
Portable Communication Devices
Personal Portable Electronics
Typical Application
VIN
VOUT
IN
ON/OFF
AAT3236
EN
OUT
BYP
GND
1µF
GND
3236.2001.11.0.9
10nF
2.2µF
GND
1
AAT3236
300mA CMOS High Performance LDO
Pin Descriptions
Pin #
Symbol
Function
SOT23-5
SC70JW-8
1
5, 6
IN
2
8
GND
3
7
EN
Enable pin - this pin is internally pulled high. When pulled low
the PMOS pass transistor turns off and all internal circuitry
enters low-power mode, consuming less than 1µA.
4
1
BYP
Bypass capacitor connection - to improve AC ripple rejection,
connect a 10nF capacitor to GND. This will also provide a soft
start function.
5
2, 3, 4
OUT
Output pin - should be decoupled with 2.2µF capacitor.
Input voltage pin - should be decoupled with 1µF or greater
capacitor.
Ground connection pin
Pin Configuration
SOT-23-5
(Top View)
OUT
BYP
BYP
OUT
OUT
OUT
1
8
7
2
2
2
1 5
2
3 4
1
IN
GND
EN
SC70JW-8
(Top View)
3
6
4
5
GND
EN
IN
IN
3236.2001.11.0.9
AAT3236
300mA CMOS High Performance LDO
Absolute Maximum Ratings
Symbol
(TA=25°C unless otherwise noted)
Description
VIN
IOUT
TJ
TLEAD
Input Voltage
DC Output Current
Operating Junction Temperature Range
Maximum Soldering Temperature (at leads, 10 sec)
Value
Units
6
PD/(VIN-VO)
-40 to 150
300
V
mA
°C
°C
Note: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. Functional operation at conditions other than the operating conditions specified is not implied. Only one Absolute Maximum rating should be applied at any one time.
Thermal Information
Symbol
Description
ΘJA
PD
Rating
Units
190
526
°C/W
mW
Rating
Units
(VOUT+0.3) to 5.5
-40 to +85
V
°C
1
Maximum Thermal Resistance (SOT23-5, SC70JW-8)
Maximum Power Dissipation1 (SOT23-5, SC70JW-8)
Note 1: Mounted on a demo board.
Recommended Operating Conditions
Symbol
Description
VIN
T
Input Voltage
Ambient Temperature Range
Electrical Characteristics (VIN=VOUT(NOM)+1V, IOUT=1mA, COUT = 2.2µF, CIN = 1µF, CBYP = 10nF,
TA= -40 to 85°C unless otherwise noted. For typical values TA=25°C)
Symbol
VOUT
Description
Conditions
Output Voltage Tolerance
IOUT = 1mA to 300mA
Min Typ Max
TA=25°C
TA=-40 to 85°C
IOUT
VDO
ISC
IQ
ISD
∆VOUT/
VOUT*∆VIN
∆VOUT(line)
Output Current
Dropout Voltage2
Short Circuit Current
Ground Current
Shutdown Current
Line Regulation
VOUT > 1.2V
IOUT = 300mA
VOUT < 0.4V
VIN = 5V, no load,EN = VIN
VIN = 5V, EN = 0V
VIN = VOUT + 1 to 5.5V
Dynamic Line Regulation
∆VOUT(load)
VEN(L)
VEN(H)
IEN
Dynamic Load Regulation
Enable Threshold Low
Enable Threshold High
Leakage Current Enable Pin
VIN=VOUT+1V to VOUT+2V,
IOUT=150mA, TR/TF =2µs
IOUT = 1mA to 150mA, TR<5µs
PSRR
TSD
THYS
eN
TC
Power Supply Rejection Ratio
Over Temp Shutdown Threshold
Over Temp Shutdown Hysteresis
Output Noise
Output Voltage Temp. Coeff.
-1.5
-2.5
300
1.5
2.5
300
600
100
500
150
1
0.07
mV
30
mV
V
V
µA
1.5
1
VEN=5V
1 kHz
10kHz
1MHz
Noise Power BW= 300Hz to 50KHz
%
%
mA
mV
mA
µA
µA
%/V
1
0.6
IOUT = 10mA, CBYP = 10nF
Units
70
50
47
150
10
45
22
dB
°C
°C
µVRMS/rtHz
ppm/°C
Note 2: VDO is defined as VIN - VOUT when VOUT is 98% of nominal.
3236.2001.11.0.9
3
AAT3236
300mA CMOS High Performance LDO
Typical Characteristics
Dropout Characteristics
Dropout Voltage vs. Temperature
3.1
IOUT=10mA
IOUT=0mA
IL=300mA
300
3.0
IOUT=50mA
250
200
150
IL=150mA
100
IL=100mA
50
Vout
Dropout Voltage (mV)
400
350
2.9
IOUT=100mA
IOUT=150mA
2.8
IOUT=300mA
IL=50mA
0
2.7
-40
-20
0
20
40
60
80
100
120
2.9
3.0
3.1
3.3
Vin
Temperature (°C)
Ground Current vs. Input Voltage
Ground Current vs. Temperature
105
120
VOUT=3.0V
100
IGND (µA)
100
Ignd (µA)
3.2
95
90
IOUT=0
80
IOUT=150mA
IOUT=300mA
IOUT=50mA
60
40
20
85
0
80
-50
0
50
100
2
150
3
Output Voltage vs. Temperature
Dropout Voltage vs. IOUT
3.014
350
300
3.013
85 C
250
Output Voltage
Dropout Voltage (mV)
5
VIN
Temperature (°C)
25 C
200
-40 C
150
100
3.012
3.011
3.01
3.009
50
3.008
0
3.007
0
50
100
150
200
Output Current (mA)
4
4
250
300
-50
0
50
100
150
Temperature (°C)
3236.2001.11.0.9
AAT3236
300mA CMOS High Performance LDO
On/Off Transient Response
No CBYP Capacitor
On/Off Transient Response
CBYP=10nF
EN (2v/div)
EN (2V/div)
150mA
VOUT (1v/div)
VOUT (1V/div)
10mA
10mA
150mA
300mA
300mA
100µs/div
5ms/div
6
3.10
1200
3.15
5
3.05
1000
3.10
4
3.00
800
3.05
3
2.95
600
3.00
2
2.90
400
2.95
1
2.85
200
0
2.80
2.90
VOUT
3.20
0
100 µS/div
5µs/div
Power Supply Rejection Ratio
vs. Frequency
Short Circuit Current
90
1
80
PSRR (dB)
1.2
Isc(A)
0.8
0.6
0.4
IOUT (mA)
Load Transient Response
VIN
VOUT
Line Transient Response
70
4.7µF
60
2.2µF
10µF
50
40
0.2
1.0µF
30
0
10
10ms/div
3236.2001.11.0.9
100
1k
10k
100k
1m
10m
Frequency (Hz)
5
AAT3236
300mA CMOS High Performance LDO
Noise Amplitude in nVrms/√Hz
(50nVrms/√Hz per DIV)
Output Self Noise
500
0
10
100
1k
10k
100k
1m
10m
Frequency (Hz)
6
3236.2001.11.0.9
AAT3236
300mA CMOS High Performance LDO
Functional Block Diagram
IN
OUT
Over-Current
Protection
Over-Temp
Protection
EN
BYP
Voltage
Reference
GND
Functional Description
The AAT3236 is intended for LDO regulator applications where output current load requirements
range from no load to 300mA. The AAT3236 is
capable of handling peak output currents up to
500mA. Refer to the Thermal Considerations discussion in the section for details on device operation at 500mA peak loads.
The advanced circuit design of the AAT3236 provides excellent input to output isolation, which
allows for good power supply ripple rejection characteristics. To optimize for very low output self
noise performance, a bypass capacitor pin has
been provided to decrease noise generated by the
internal voltage reference.
3236.2001.11.0.9
The LDO regulator output has been specifically
optimized to function with low cost, low ESR
ceramic capacitors. However, the design will allow
for operation over a wide range of capacitor types.
The device enable circuit is provided to shutdown
the LDO regulator for power conservation in portable
products. The enable circuit has an additional output capacitor discharge circuit to assure sharp application circuit turn off upon device shutdown.
This LDO regulator has complete short circuit and
thermal protection. The integral combination of
these two internal protection circuits give the
AAT3236 a comprehensive safety system during
extreme adverse operating conditions.
7
AAT3236
300mA CMOS High Performance LDO
Applications Information
Input Capacitor
Typically a 1µF or larger capacitor is recommended for CIN in most applications. A CIN capacitor is
not required for basic LDO regulator operation.
However, if the AAT3236 is physically located more
than 6 centimeters from an input power source, a
CIN capacitor will be needed for stable operation.
CIN should be located as close to the device VIN pin
as practically possible. CIN values greater than
1µF will offer superior input line transient response
and will assist in maximizing the highest possible
power supply ripple rejection.
Ceramic, tantalum or aluminum electrolytic capacitors may be selected for CIN. There is no specific
capacitor ESR requirement for CIN. However, for
300mA LDO regulator output operation, ceramic
capacitors are recommended for CIN due to their
inherent capability over tantalum capacitors to withstand input current surges from low impedance
sources such as batteries in portable devices.
Output Capacitor
For proper load voltage regulation and operational
stability, a capacitor is required between pins VOUT
and GND. The COUT capacitor connection to
the LDO regulator ground pin should be made as
direct as practically possible for maximum device
performance.
The AAT3236 has been specifically designed to
function with very low ESR ceramic capacitors.
Although the device is intended to operate with
these low ESR capacitors, it is stable over a very
wide range of capacitor ESR, thus it will also work
with higher ESR tantalum or aluminum electrolytic
capacitors.
However, for best performance,
ceramic capacitors are recommended.
Bypass Capacitor and Low Noise
Applications
A bypass capacitor pin is provided to enhance the
very low noise characteristics of the AAT3236 LDO
regulator. The bypass capacitor is not necessary for
operation of the AAT3236. However, for best device
performance, a small ceramic capacitor should be
placed between the Bypass pin (BYP) and the device
ground pin (GND). The value of CBYP may range
from 470pF to 10nF. For lowest noise and best possible power supply ripple rejection performance a
10nF capacitor should be used. To practically realize
the highest power supply ripple rejection and lowest
output noise performance, it is critical that the capacitor connection between the BYP pin and GND pin be
direct and PCB traces should be as short as possible. Refer to the PCB Layout Recommendations
section of this document for examples.
There is a relationship between the bypass capacitor value and the LDO regulator turn on time. In
applications where fast device turn on time is
desired, the value of CBYP should be reduced.
In applications where low noise performance
and/or ripple rejection are less of a concern, the
bypass capacitor may be omitted. The fastest
device turn on time will be realized when no bypass
capacitor is used.
DC leakage on this pin can affect the LDO regulator output noise and voltage regulation performance. For this reason, the use of a low leakage,
high quality ceramic (NPO or COG type) or film
capacitor is highly recommended.
Capacitor Characteristics
Typical output capacitor values for maximum output current conditions range from 1µF to 10µF.
Applications utilizing the exceptionally low output
noise and optimum power supply ripple rejection
characteristics of the AAT3236 should use 2.2µF or
greater for COUT. If desired, COUT may be
increased without limit.
Ceramic composition capacitors are highly recommended over all other types of capacitors for use
with the AAT3236. Ceramic capacitors offer many
advantages over their tantalum and aluminum electrolytic counterparts. A ceramic capacitor typically
has very low ESR, is lower cost, has a smaller PCB
footprint and is non-polarized. Line and load transient response of the LDO regulator is improved by
using low ESR ceramic capacitors. Since ceramic
capacitors are non-polarized, they are not prone to
incorrect connection damage.
In low output current applications where output
load is less then 10mA, the minimum value for
COUT can be as low as 0.47µF.
Equivalent Series Resistance (ESR): ESR is a very
important characteristic to consider when selecting a
capacitor. ESR is the internal series resistance asso-
8
3236.2001.11.0.9
AAT3236
300mA CMOS High Performance LDO
ciated with a capacitor, which includes lead resistance, internal connections, size and area, material
composition and ambient temperature. Typically
capacitor ESR is measured in milliohms for ceramic
capacitors and can range to more than several ohms
for tantalum or aluminum electrolytic capacitors.
Ceramic Capacitor Materials: Ceramic capacitors less than 0.1µF are typically made from NPO
or COG materials. NPO and COG materials are
typically tight tolerance very stable over temperature. Larger capacitor values are typically composed of X7R, X5R, Z5U and Y5V dielectric materials. Large ceramic capacitors, typically greater
then 2.2µF are often available in the low cost Y5V
and Z5U dielectrics. These two material types are
not recommended for use with LDO regulators
since the capacitor tolerance can vary more than
±50% over the operating temperature range of the
device. A 2.2µF Y5V capacitor could be reduced to
1µF over temperature, this could cause problems
for circuit operation. X7R and X5R dielectrics are
much more desirable. The temperature tolerance
of X7R dielectric is better than ±15%.
Capacitor area is another contributor to ESR.
Capacitors which are physically large in size will
have a lower ESR when compared to a smaller sized
capacitor of equivalent material and capacitance
value. These larger devices can improve circuit
transient response when compared to an equal
value capacitor in a smaller package size.
Consult capacitor vendor data sheets carefully
when selecting capacitors for LDO regulators.
Enable Function
The AAT3236 features an LDO regulator enable /
disable function. This pin (EN) is active high and is
compatible with CMOS logic. To assure the LDO
regulator will switch on, the EN turn on control level
must be greater than 2.0 volts. The LDO regulator
will go into the disable shutdown mode when the
voltage on the EN pin falls below 0.6 volts. If the
enable function is not needed in a specific application, it may be tied to VIN to keep the LDO regulator in a continuously on state.
When the LDO regulator is in the shutdown mode,
an internal 1.5kΩ resistor is connected between
VOUT and GND. This is intended to discharge COUT
when the LDO regulator is disabled. The internal
1.5kΩ has no adverse effect on device turn on time.
3236.2001.11.0.9
Short Circuit Protection
The AAT3236 contains an internal short circuit protection circuit that will trigger when the output load
current exceeds 750mA. Under short circuit conditions the output will be limited to 750mA until the
LDO regulator package power dissipation exceeds
the device thermal limit or the until the short circuit
condition is removed.
Thermal Protection
The AAT3236 has an internal thermal protection circuit which will turn on when the device die temperature exceeds 150°C. The internal thermal protection circuit will actively turn off the LDO regulator
output pass device to prevent the possibility of over
temperature damage. The LDO regulator output
will remain in a shutdown state until the internal die
temperature falls back below the 150°C trip point.
The combination and interaction between the short
circuit and thermal protection systems allow the
LDO regulator to withstand indefinite short circuit
conditions without sustaining permanent damage.
No-Load Stability
The AAT3236 is designed to maintain output voltage regulation and stability under operational noload conditions. This is an important characteristic
for applications where the output current may drop
to zero.
Reverse Output to Input Voltage
Conditions and Protection
Under normal operating conditions a parasitic
diode exists between the output and input of the
LDO regulator. The input voltage should always
remain greater than the output load voltage maintaining a reverse bias on the internal parasitic
diode. Conditions where VOUT might exceed VIN
should be avoided since this would forward bias
the internal parasitic diode and allow excessive
current flow into the VOUT pin possibly damaging
the LDO regulator.
In applications where there is a possibility of VOUT
exceeding VIN for brief amounts of time during normal operation, the use of a larger value CIN capacitor is highly recommended. A larger value of CIN
with respect to COUT will effect a slower CIN decay
rate during shutdown, thus preventing VOUT from
exceeding VIN. In applications where there is a
greater danger of VOUT exceeding VIN for extended
9
AAT3236
300mA CMOS High Performance LDO
periods of time, it is recommended to place a schottky diode across VIN to VOUT (connecting the cathode to VIN and anode to VOUT. The Schottky diode
forward voltage should be less than 0.45 volts.
ture were to increase, the internal die temperature
will increase. If the condition remained constant,
the LDO regulator thermal protection circuit will
activate.
Thermal Considerations and High
Output Current Applications
To figure what the maximum input voltage would be
for a given load current, refer to the following equation. This calculation accounts for the total power
dissipation of the LDO Regulator, including that
caused by ground current.
The AAT3236 is designed to deliver a continuous
output load current of 300mA under normal operations and can supply up to 500mA during circuit
start up conditions. This is desirable for circuit
applications where there might be a brief high in
rush current during a power on event.
The limiting characteristic for the maximum output
load current safe operating area is essentially
package power dissipation and the internal preset
thermal limit of the device. In order to obtain high
operating currents, careful device layout and circuit
operating conditions need to be taken into account.
The following discussions will assume the LDO regulator is mounted on a printed circuit board utilizing
the minimum recommended footprint as stated in
the layout considerations section of the document.
At any given ambient temperature (TA) the maximum package power dissipation can be determined by the following equation:
PD(MAX) = [TJ(MAX) - TA] / Θ JA
Constants for the AAT3236 are TJ(MAX), the maximum junction temperature for the device which is
125°C and ΘJA = 190°C/W, the package thermal
resistance. Typically, maximum conditions are calculated at the maximum operating temperature
where TA = 85°C, under normal ambient conditions
TA = 25°C. Given TA = 85°, the maximum package
power dissipation is 211mW. At TA = 25°C, the
maximum package power dissipation is 526mW
The maximum continuous output current for the
AAT3236 is a function of the package power dissipation and the input to output voltage drop across
the LDO regulator. Refer to the following simple
equation:
IOUT(MAX) < PD(MAX) / (VIN - VOUT)
For example, if VIN = 4.2V, VOUT = 3.3V and TA =
25°, IOUT(MAX) < 584mA. If the output load current
were to exceed 584mA or if the ambient tempera-
10
PD(MAX) = (VIN - VOUT)IOUT + (VIN x IGND)
This formula can be solved for VIN to determine the
maximum input voltage.
VIN(MAX) = (PD(MAX) + (VOUT x IOUT)) / (IOUT + IGND)
The following is an example for an AAT3236 set for
a 3.0 volt output:
From the discussion above, PD(MAX) was determined to equal 526mW at TA = 25°C°.
VOUT = 3.0 volts
IOUT = 500mA
IGND = 150uA
VIN(MAX)=(526mW+(3.0Vx500mA))/(500mA +150µA)
VIN(MAX) = 4.05V
Thus, the AAT3236 can sustain a constant 3V output at a 500mA load current as long as VIN is ≤
4.05V at an ambient temperature of 25°C.
Higher input to output voltage differentials can be
obtained with the AAT3236, while maintaining
device functions within the thermal safe operating
area. To accomplish this, the device thermal resistance must be reduced by increasing the heat sink
area or by operating the LDO regulator in a duty
cycled mode.
For example, an application requires VIN = 4.2V
while VOUT = 3.0V at a 500mA load and TA = 25°C.
VIN is greater then 4.05V, which is the maximum
safe continuous input level for VOUT = 3.0V at
500mA for TA = 25°C. To maintain this high input
voltage and output current level, the LDO regulator
must be operated in a duty cycled mode. Refer to
the following calculation for duty cycle operation:
PD(MAX) is assumed to be 526mW
IGND = 150µA
IOUT = 500mA
3236.2001.11.0.9
AAT3236
300mA CMOS High Performance LDO
High Peak Output Current Applications
VIN = 4.2 volts
VOUT = 3.0 volt
%DC = 100(PD(MAX)/((VIN-VOUT)IOUT+(VINxIGND))
%DC = 100(526mW/((4.2V-3.0V)500mA+(4.2Vx150µA))
%DC = 87.57%
For a 500mA output current and a 1.2 volt drop
across the AAT3236 at an ambient temperature of
25°C, the maximum on time duty cycle for the
device would be 87.57%.
The following family of curves show the safe operating area for duty cycled operation from ambient
room temperature to the maximum operating level.
Some applications require the LDO regulator to
operate at a continuous nominal level with short
duration high current peaks. The duty cycles for
both output current levels must be taken into
account. To do so, one would first need to calculate the power dissipation at a nominal continuous
level and then factor in the additional power dissipation due to the short duration high current peaks.
For example, a 3.3V system using a AAT3236IGV3.3-T1 operates at a continuous 100mA load current
level and has short 500mA current peaks. The current peak occurs for 378µs out of a 4.61ms period.
It will be assumed the input voltage is 4.2V.
Device Duty Cycle vs. VDROP
VOUT = 2.5V @ 25 degrees C
Device Duty Cycle vs. V DROP
VOUT = 2.5V @ 50 degrees C
3.5
200 mA
3
Voltage Drop (V)
Voltage Drop (V)
3.5
500 mA
2.5
2
400 mA
1.5
300 mA
1
0.5
0
0
10
20
30
40
50
60
70
80
90
100
Duty Cycle (%)
200 mA
3
100 mA
500 mA
2.5
2
400 mA
1.5
1
300 mA
0.5
0
0
10
20
30
40
50
60
70
80
90
100
Duty Cycle (%)
Device Duty Cycle vs. V DROP
VOUT = 2.5V @ 85 degrees C
Voltage Drop (V)
3.5
3
100 mA
2.5
200 mA
2
1.5
500 mA
1
400 mA
0.5
300 mA
0
0
10
20
30
40
50
60
70
80
90
100
Duty Cycle (%)
3236.2001.11.0.9
11
AAT3236
300mA CMOS High Performance LDO
First the current duty cycle in percent must be
calculated:
The power dissipation for 500mA load occurring for
8.2% of the duty cycle will be 37mW. Finally, the two
power dissipation levels can summed to determine
the total true power dissipation under the varied load.
% Peak Duty Cycle: X/100 = 378µs/4.61ms
% Peak Duty Cycle = 8.2%
PD(total) = PD(100mA) + PD(500mA)
PD(total) = 83.2mW + 37mW
PD(total) = 120.2mW
The LDO Regulator will be under the 100mA load
for 91.8% of the 4.61ms period and have 500mA
peaks occurring for 8.2% of the time. Next, the
continuous nominal power dissipation for the
100mA load should be determined and then multiplied by the duty cycle to conclude the actual
power dissipation over time.
The maximum power dissipation for the AAT3236
operating at an ambient temperature of 25°C is
526mW. The device in this example will have a
total power dissipation of 120.2mW. This is well
within the thermal limits for safe operation of the
device.
PD(MAX) = (VIN - VOUT)IOUT + (VIN x IGND)
PD(100mA) = (4.2V - 3.3V)100mA + (4.2V x 150µA)
PD(100mA) = 90.6mW
Printed Circuit Board Layout
Recommendations
PD(91.8%D/C) = %DC x PD(100mA)
PD(91.8%D/C) = 0.918 x 90.6mW
PD(91.8%D/C) = 83.2mW
In order to obtain the maximum performance from
the AAT3236 LDO regulator, very careful attention
must be considered in regard to the printed circuit
board (PCB) layout. If grounding connections are
not properly made, power supply ripple rejection,
low output self noise and transient response can be
compromised.
The power dissipation for 100mA load occurring for
91.8% of the duty cycle will be 83.2mW. Now the
power dissipation for the remaining 8.2% of the
duty cycle at the 500mA load can be calculated:
PD(MAX) = (VIN - VOUT)IOUT + (VIN x IGND)
PD(500mA) = (4.2V - 3.3V)500mA + (4.2V x 150µA)
PD(500mA) = 450.6mW
Figure 18 shows a common LDO regulator layout
scheme. The LDO Regulator, external capacitors
(CIN, COUT and CBYP) and the load circuit are all
connected to a common ground plane. This type of
layout will work in simple applications where good
power supply ripple rejection and low self noise are
not a design concern. For high performance applications, this method is not recommended.
PD(8.2%D/C) = %DC x PD(500mA)
PD(8.2%D/C) = 0.082 x 450.6mW
PD(8.2%D/C) = 37mW
VIN
ILOAD
IIN
VIN
LDO
Regulator
EN
DC INPUT
VOUT
BYP
GND
CIN
CBYP
IGND
IRIPPLE
IBYP + noise
COUT
RLOAD
CBYP
GND
LOOP
GND
RTRACE
RTRACE
RTRACE
RTRACE
ILOAD return + noise and ripple
Figure 18: Common LDO Regulator Layout with CBYP Ripple feedback loop
12
3236.2001.11.0.9
AAT3236
300mA CMOS High Performance LDO
The problem with the layout in Figure 18 is the
bypass capacitor and output capacitor share the
same ground path to the LDO regulator ground pin
along with the high current return path from the load
back to the power supply. The bypass capacitor
node is connected directly to the LDO regulator
internal reference, making this node very sensitive
to noise or ripple. The internal reference output is
fed into the error amplifier, thus any noise or ripple
from the bypass capacitor will be subsequently
amplified by the gain of the error amplifier. This
effect can increase noise seen on the LDO regulator
output as well as reduce the maximum possible
power supply ripple rejection. There is PCB trace
impedance between the bypass capacitor connection to ground and the LDO regulator ground connection. When the high load current returns through
this path, a small ripple voltage is created, feeding
into the CBYP loop.
Figure 19 shows the preferred method for the
bypass and output capacitor connections. For low
output noise and highest possible power supply
ripple rejection performance, it is critical to connect
the bypass and output capacitor directly to the LDO
regulator ground pin. This method will eliminate
any load noise or ripple current feedback through
the LDO regulator.
Evaluation Board Layout
The AAT3236 evaluation layout follows the recommend printed circuit board layout procedures and
can be used as an example for good application
layouts.
Note: Board layout shown is not to scale.
ILOAD
IIN
VIN
VIN
LDO
Regulator
EN
VOUT
BYP
GND
DC INPUT
CIN
IGND
CBYP
COUT
RLOAD
IBYP only
IRIPPLE
GND
RTRACE
RTRACE
RTRACE
RTRACE
ILOAD return + noise and ripple
Figure 19: Recommended LDO Regulator Layout
Figure 20: Evaluation board
component side layout
3236.2001.11.0.9
Figure 21: Evaluation board
solder side layout
Figure 22: Evaluation board
top side silk screen layout /
assembly drawing
13
AAT3236
300mA CMOS High Performance LDO
Ordering Information
14
Output Voltage
Package
2.5V
Marking
Part Number
Bulk
Tape and Reel
SOT-23-5
N/A
AAT3236IGV-2.5-T1
2.7V
SOT-23-5
N/A
AAT3236IGV-2.7-T1
2.8V
SOT-23-5
N/A
AAT3236IGV-2.8-T1
2.85V
SOT-23-5
N/A
AAT3236IGV-2.85-T1
3.0V
SOT-23-5
N/A
AAT3236IGV-3.0-T1
3.3V
SOT-23-5
N/A
AAT3236IGV-3.3-T1
3.5V
SOT-23-5
N/A
AAT3236IGV-3.5-T1
2.5V
SC70JW-8
N/A
AAT3236IJS-2.5-T1
2.7V
SC70JW-8
N/A
AAT3236IJS-2.7-T1
2.8V
SC70JW-8
N/A
AAT3236IJS-2.8-T1
2.85V
SC70JW-8
N/A
AAT3236IJS-2.85-T1
3.0V
SC70JW-8
N/A
AAT3236IJS-3.0-T1
3.3V
SC70JW-8
N/A
AAT3236IJS-3.3-T1
3.5V
SC70JW-8
N/A
AAT3236IJS-3.5-T1
3236.2001.11.0.9
AAT3236
300mA CMOS High Performance LDO
Package Information
SOT-23-5
e
Dim
S1
A
A1
A2
b
c
D
E
e
H
L
S
S1
Θ
H
E
D
A
A2
A1
c
b
S
L
Millimeters
Min
Max
1.00
1.30
0.00
0.10
0.70
0.90
0.35
0.50
0.10
0.25
2.70
3.10
1.40
1.80
1.90
2.60
3.00
0.37
0.45
0.55
0.85
1.05
1°
9°
Inches
Min
Max
0.039
0.051
0.000
0.004
0.028
0.035
0.014
0.020
0.004
0.010
0.106
0.122
0.055
0.071
0.075
0.102
0.118
0.015
0.018
0.022
0.033
0.041
1°
9°
Millimeters
Min
Max
2.10 BSC
1.75
2.00
0.23
0.40
1.10
0
0.10
0.70
1.00
2.00 BSC
0.50 BSC
0.15
0.30
0.10
0.20
0
8º
4º
10º
Inches
Min
Max
0.083 BSC
0.069
0.079
0.009
0.016
0.043
0.004
0.028
0.039
0.079 BSC
0.020 BSC
0.006
0.012
0.004
0.008
0
8º
4º
10º
SC70JW-8
e
e
e
Dim
E
b
D
0.048REF
c
A2 A
E
E1
L
A
A1
A2
D
e
b
c
Θ
Θ1
A1
Θ1
3236.2001.11.0.9
L
E1
Θ
15
AAT3236
300mA CMOS High Performance LDO
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Advanced Analogic Technologies, Inc.
1250 Oakmead Parkway, Suite 310, Sunnyvale, CA 94086
Phone (408) 524-9684
Fax (408) 524-9689
16
3236.2001.11.0.9
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