Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI MCU ADuC7122 Data Sheet FEATURES Software-triggered in-circuit reprogrammability On-chip peripherals UART, 2× I2C and SPI serial I/Os 32-pin GPIO port 4 general-purpose timers Wake-up and watchdog timers (WDT) Power supply monitor Vectored interrupt controller for FIQ and IRQ 8 priority levels for each interrupt type Interrupt on edge or level external pin inputs Power Specified for 3 V operation Active mode: 11 mA at 5 MHz, 40 mA at 41.78 MHz Packages and temperature range 7 mm × 7 mm 108-ball BGA Fully specified for −10°C to +95°C operation Tools Low cost QuickStart development system Full third-party support Analog I/O 13-external channel, 12-bit, 1 MSPS ADC 2 differential channels with programmable gain PGA (1 to 5) input range IOVDD power monitor channel On-chip temperature monitor 11 general-purpose inputs Fully differential and single-ended modes 0 V to VREF analog input range 12 × 12-bit voltage output DACs On-chip voltage reference: 1.2 V/2.5 V Buffered output reference sources for use with external circuits Microcontroller ARM7TDMI core, 16-bit/32-bit RISC architecture JTAG port supports code download and debug Clocking options Trimmed on-chip oscillator (±3%) External watch crystal External clock source up to 41.78 MHz 41.78 MHz PLL with programmable divider Memory 126 kB Flash/EE memory, 8 kB SRAM In-circuit download, JTAG-based debug APPLICATIONS Optical networking, industrial control, and automation systems Smart sensors and precision instrumentation BUF BUF BUF BUF BUF DAC DAC DAC DAC DAC DAC6 DAC7 1MSPS 12-BIT SAR ADC DAC BUF DAC9 DAC BUF DAC10 DAC BUF DAC11 PLA OSC PLL POR PWM WAKE-UP TIMER 3× GP TIMERS 8k SRAM (2k × 32-BIT) LDO WD TIMER 126k FLASH (63k × 16-BIT) ARM7 TDMI VIC TEMPERATURE IOVDD MON SENSOR JTAG GPIO CONTROL SPI IOVDD UART 12C × 2 BUF VREF_1.2 VREF_2.5 P0.0 TO P0.7 P1.0 TO P1.7 P2.0 TO P2.7 P3.0 TO P3.7 IOGND XTALI XTALO RST TDO TDI TCK TMS TRST 08755-001 ADuC7122 INTERNAL REFERENCE DAC8 BUF BUF DAC5 DAC ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 ADC7 ADC8 ADC9 ADC10 DAC4 DAC PGA DAC3 BUF PADC1 DAC2 DAC PGA DAC1 BUF PADC0 DAC0 DAC FUNCTIONAL BLOCK DIAGRAM AVDD 3.3V AGND Figure 1. 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Technical Support www.analog.com ADuC7122 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Other Analog Peripherals .............................................................. 43 Applications ....................................................................................... 1 DAC.............................................................................................. 43 Functional Block Diagram .............................................................. 1 LDO (Low dropout Regulator)................................................. 45 Revision History ............................................................................... 3 Oscillator and PLL—Power Control ............................................ 46 General Description ......................................................................... 4 External Crystal Selection ......................................................... 46 Specifications..................................................................................... 5 External Clock Selection ........................................................... 46 Timing Specifications .................................................................. 9 Power Control System ............................................................... 47 Absolute Maximum Ratings .......................................................... 14 MMRs and Keys ......................................................................... 48 ESD Caution ................................................................................ 14 Digital Peripherals .......................................................................... 49 Pin Configuration and Function Descriptions ........................... 15 PWM General Overview ........................................................... 49 Terminology .................................................................................... 19 PWM Convert Start Control .................................................... 51 ADC Specifications .................................................................... 19 General-Purpose I/O ..................................................................... 52 DAC Specifications..................................................................... 19 UART Serial Interface .................................................................... 54 Overview of the ARM7TDMI Core ............................................. 20 Baud Rate Generation ................................................................ 54 Thumb Mode (T)........................................................................ 20 UART Register Definition ......................................................... 54 Long Multiply (M) ...................................................................... 20 I C ..................................................................................................... 59 EmbeddedICE (I) ....................................................................... 20 Serial Clock Generation ............................................................ 59 Exceptions ................................................................................... 20 I2C Bus Addresses....................................................................... 59 ARM Registers ............................................................................ 20 I2C Registers ................................................................................ 60 Interrupt Latency ........................................................................ 21 I2C Common Registers .............................................................. 68 Memory Organization ................................................................... 22 Serial Peripheral Interface ............................................................. 69 Flash/EE Memory ....................................................................... 22 SPIMISO (Master In, Slave Out) Pin ....................................... 69 SRAM ........................................................................................... 22 SPIMOSI (Master Out, Slave In) Pin ....................................... 69 Memory Mapped Registers ....................................................... 22 SPICLK (Serial Clock I/O) Pin ................................................. 69 Complete MMR Listing ............................................................. 23 SPI Chip Select (SPICS Input) Pin ........................................... 69 ADC Circuit Overview .................................................................. 27 Configuring External Pins for SPI Functionality ................... 69 ADC Transfer Function ............................................................. 28 SPI Registers ................................................................................ 70 Typical Operation ....................................................................... 29 Programmable Logic Array (PLA) ............................................... 73 Temperature Sensor ................................................................... 30 Interrupt System ............................................................................. 76 Converter Operation .................................................................. 33 IRQ ............................................................................................... 77 Driving the Analog Inputs ........................................................ 34 Fast Interrupt Request (FIQ) .................................................... 77 Band Gap Reference ................................................................... 34 Timers .......................................................................................... 83 Power Supply Monitor ............................................................... 35 Hour:Minute:Second:1/128 Format......................................... 83 Nonvolatile Flash/EE Memory ..................................................... 36 Timer0—Lifetime Timer ........................................................... 84 Flash/EE Memory Overview..................................................... 36 Timer1—General-Purpose Timer ........................................... 85 Flash/EE Memory ....................................................................... 36 Timer2—Wake-Up Timer ......................................................... 87 Flash/EE Memory Security ....................................................... 37 Timer3—Watchdog Timer ........................................................ 89 Flash/EE Control Interface ........................................................ 37 Timer4—General-Purpose Timer ........................................... 91 Execution Time from SRAM and FLASH/EE ........................ 40 Hardware Design Considerations ................................................ 93 Reset and Remap ........................................................................ 41 Power Supplies ............................................................................ 93 2 Rev. A | Page 2 of 96 Data Sheet ADuC7122 Grounding and Board Layout Recommendations .................94 Outline Dimensions ........................................................................ 96 Clock Oscillator ...........................................................................95 Ordering Guide ........................................................................... 96 REVISION HISTORY 11/14—Rev. 0 to Rev. A Changed Accuracy from ±5 mV to ±30 mV; Table 1 ................... 6 Changes to Flash/EE Memory Section .........................................22 Changes to PGA and Input Buffer Section .................................28 Changes to Flash/EE Memory Section and Serial Downloading (In-Circuit Programming) Section ...............................................36 Changes to Flash/EE Memory Security Section .........................37 Changes to Table 57 and Table 58 .................................................40 Changes to I2C Section ...................................................................59 Changes to Table 101 ......................................................................60 Changes to Table 108 ......................................................................64 Changes to Table 109 ......................................................................65 Changes to Table 111 ......................................................................70 Added Hour:Minute:Second:1/128 Format Section ...................83 Changes to Table 168 ......................................................................89 Added Hardware Design Consideration Section ........................93 Changes to Ordering Guide ...........................................................96 4/10—Revision 0: Initial Version Rev. A | Page 3 of 96 ADuC7122 Data Sheet GENERAL DESCRIPTION The ADuC7122 is a fully integrated, 1 MSPS, 12-bit data acquisition system, incorporating high performance multichannel ADCs, 12 voltage output DACs, 16-bit/32-bit MCUs, and Flash/EE memory on a single chip. The ADC consists of up to 13 inputs. Four of these inputs can be configured as differential pairs with a programmable gain amplifier on their front end, providing a gain between 1 and 5. The ADC can operate in single-ended or differential input mode. The ADC input voltage is 0 V to VREF. A low drift band gap reference, temperature sensor, and supply voltage monitor complete the ADC peripheral set. The DAC output range is programmable to one of two voltage ranges. The DAC outputs have an enhanced feature of being able to retain their output voltage during a watchdog or software reset sequence. The device operates from an on-chip oscillator and a PLL, generating an internal high frequency clock of 41.78 MHz. This clock is routed through a programmable clock divider from which the MCU core clock operating frequency is generated. The microcontroller core is an ARM7TDMI®, 16-bit/32-bit RISC machine that offers up to 41 MIPS peak performance. There are 8 kB of SRAM and 126 kB of nonvolatile Flash/EE memory provided on chip. The ARM7TDMI core views all memory and registers as a single linear array. The ADuC7122 contains an advanced interrupt controller. The vectored interrupt controller (VIC) allows every interrupt to be assigned a priority level. It also supports nested interrupts to a maximum level of eight per IRQ and FIQ. When IRQ and FIQ interrupt sources are combined, a total of 16 nested interrupt levels are supported. On-chip factory firmware supports in-circuit download via the I2C serial interface port, and nonintrusive emulation is also supported via the JTAG interface. These features are incorporated into a low cost QuickStart™ development system supporting this MicroConverter® family. The part contains a 16-bit PWM with six output signals. For communication purposes, the part contains 2× I2C channels that can be individually configured for master or slave mode. An SPI interface supporting both master and slave modes is also provided. The part operates from 3.0 V to 3.6 V and is specified over a temperature range of −10°C to +95°C. The ADuC7122 is available in a 108-ball BGA package. Rev. A | Page 4 of 96 Data Sheet ADuC7122 SPECIFICATIONS AVDD = IOVDD = 3.0 V to 3.6 V, VREF = 2.5 V internal reference, fCORE = 41.78 MHz, TA = −10°C to +95°C, unless otherwise noted. Table 1. Parameter ADC CHANNEL SPECIFICATIONS ADC Power-Up Time DC Accuracy 1, 2 Resolution Integral Nonlinearity Min Full Scale Input Range Input Leakage at PADC0P4 Resolution Gain Error4 Gain Drift4 Offset4 Offset Drift4 PADC0P Compliant Range PADC1 INPUT Full Scale Input Range Input Leakage at PADC1P4 Resolution Gain Error4 Gain Drift4 Offset4 Offset Drift4 PADC1P Compliant Range Max 5 Unit Bits LSB ±0.6 ±2 ±0.5 1 +1.4/−0.99 LSB LSB ±2 ±1 ±2 ±1 ±5 LSB LSB LSB LSB ±5 69 −78 −75 −80 dB dB dB dB VCM 6 ± VREF/2 0 to VREF AVDD − 1.5 0.15 ±0.2 20 20 20 0.15 1000 2 11 3 30 0.1 Test Conditions/Comments Eight acquisition clocks and fADC/2 μs 12 Differential Nonlinearity 3, 4 DC Code Distribution ENDPOINT ERRORS 5 Offset Error Offset Error Match Gain Error Gain Error Match DYNAMIC PERFORMANCE Signal-to-Noise Ratio (SNR) Total Harmonic Distortion (THD) Peak Harmonic or Spurious Noise Channel-to-Channel Crosstalk ANALOG INPUT Input Voltage Ranges Differential Mode Single-Ended Mode Single-Ended Mode Leakage Current Input Capacitance Input Capacitance PADC0 INPUT Typ 1 50 6 60 AVDD − 1.2 V V V µA pF pF µA nA Bits % ppm/°C nA pA/°C V 2.5 V internal reference, not production tested for PADC0/PADC1 channels 2.5 V internal reference, gauranteed monotonic ADC input is a dc voltage Internally unbuffered channels fIN = 10 kHz sine wave, fSAMPLE = 1 MSPS internally unbuffered channels Includes distortion and noise components Measured on adjacent channels See Table 35 and Table 36 Buffer bypassed Buffer enabled During ADC acquisition buffer bypassed During ADC acquisition buffer enabled 28.3 kΩ resistor, PGA gain = 3; acquisition time = 6 µs, pseudo differential mode 0.1% accuracy, 5 ppm external resistor for I to V PGA offset not included 53.5 kΩ resistor, PGA gain = 3; acquisition time = 6 µs, pseudo differential mode 10.6 0.15 700 2 11 3 30 0.1 1 50 6 60 AVDD − 1.2 µA nA Bits % ppm/°C nA pA/°C V Rev. A | Page 5 of 96 0.1% accuracy, 5 ppm external resistor for I to V PGA offset not included ADuC7122 Parameter ON-CHIP VOLTAGE REFERENCE Output Voltage Accuracy 7 Reference Temperature Coefficient4 Power Supply Rejection Ratio Output Impedance Internal VREF Power-On Time EXTERNAL REFERENCE INPUT Input Voltage Range BUF_VREF1, BUF_VREF2 OUTPUTS Accuracy Reference Temperature Coefficient Load Current DAC CHANNEL SPECIFICATIONS DC Accuracy 8 Resolution Relative Accuracy Differential Nonlinearity Calculated Offset Error Actual Offset Error Gain Error 9 Gain Error Mismatch Settling Time 4 PSRR DC 1 kHz 10 kHz 100 kHz OFFSET DRIFT4 GAIN ERROR DRIFT4 SHORT-CIRCUIT CURRENT ANALOG OUTPUTS Output Range Data Sheet Min Typ Max 2.5 10 61 10 1 1.2 ±5 30 Unit V mV ppm/°C dB Ω ms AVDD V 1.2 mV µV/°C mA ±30 40 TA = 25°C TA = 25°C TA = 25°C RL = 5 kΩ, CL = 100 pF Buffered 12 ±2 ±0.2 ±2 9 ±0.15 0.1 10 ±1 ±0.8 Bits LSB LSB mV mV % % µs Guaranteed monotonic 2.5 V internal reference Measured at Code 0 % of full scale on DAC0 Buffered −59 −57 −47 −19 −61 10 10 20 0.1 VREF/AVDD − 0.1 dB dB dB dB µV/°C µV/°C mA V DAC AC CHARACTERISTICS Slew Rate Voltage Output Settling Time Digital-to-Analog Glitch Energy 2.49 10 ±20 V/µs µs nV-sec TEMPERATURE SENSOR 10 Voltage Output at 25°C Voltage TC Accuracy 707 −1.25 ±3 mV mV/°C °C 2.79 3.07 ±2.5 2.36 V V % V POWER SUPPLY MONITOR (PSM) IOVDD Trip Point Selection Power Supply Trip Point Accuracy POWER-ON RESET WATCHDOG TIMER (WDT) Timeout Period Test Conditions/Comments 0.47 µF from VREF to AGND 0 512 sec Rev. A | Page 6 of 96 Buffer on 1 LSB change at major carry (where maximum number of bits simultaneously change in the DACxDAT register) MCU in power-down or standby mode before measurement Two selectable trip points Of the selected nominal trip point voltage Data Sheet Parameter FLASH/EE MEMORY Endurance 11 Data Retention 12 DIGITAL INPUTS Logic 1 Input Current Logic 0 Input Current Input Capacitance LOGIC INPUTS4 VINL, Input Low Voltage4 VINH, Input High Voltage4 LOGIC OUTPUTS VOH, Output High Voltage VOL, Output Low Voltage 13 CRYSTAL INPUTS XTALI and XTALO Logic Inputs, XTALI Only VINL, Input Low Voltage VINH, Input High Voltage XTALI Input Capacitance XTALO Output Capacitance INTERNAL OSCILLATOR MCU CLOCK RATE From 32 kHz Internal Oscillator From 32 kHz External Crystal Using an External Clock START-UP TIME At Power-On From Pause/Nap Mode From Sleep Mode From Stop Mode PROGRAMMABLE LOGIC ARRAY (PLA) Pin Propagation Delay Element Propagation Delay POWER REQUIREMENTS 14, 15 Power Supply Voltage Range AVDD to AGND and IOVDD to IOGND Analog Power Supply Currents AVDD Current Digital Power Supply Current IOVDD Current in Normal Mode IOVDD Current in Pause Mode4 IOVDD Current in Sleep Mode4 Additional Power Supply Currents ADC DAC ADuC7122 Min Typ Max 10,000 20 Unit Cycles Years ±0.2 −40 10 ±1 −60 µA µA pF 0.8 V V Test Conditions/Comments TJ = 85°C All digital inputs excluding XTALI and XTALO VIH = VDD or VIH = 5 V VIL = 0 V; except TDI All logic inputs excluding XTALI 2.0 2.4 0.4 V V ±3 V V pF pF kHz % 41.78 kHz MHz MHz 1.1 1.7 20 20 32.768 326 41.78 0.05 70 24 3.06 1.58 1.7 ms ns µs ms ms 12 2.5 ns ns 3.0 3.6 All digital outputs excluding XTALO ISOURCE = 1.6 mA ISINK = 1.6 mA CD = 7 CD = 0 TA = 95°C Core clock = 41.78 MHz CD = 0 CD = 7 From input pin to output pin V 200 µA ADC in idle mode 7 11 30 25 100 mA mA mA mA µA Code executing from Flash/EE CD = 7 CD = 3 CD = 0 (41.78 MHz clock) CD = 0 (41.78 MHz clock) TA = 85°C mA µA At 1 MSPS Per DAC 2.7 250 40 Rev. A | Page 7 of 96 ADuC7122 Parameter ESD TESTS HBM Passed Up To FCIDM Passed Up To Data Sheet Min Typ Max Unit 4 0.5 kV kV Test Conditions/Comments 2.5 V reference, TA = 25°C All ADC channel specifications are guaranteed during normal MicroConverter core operation. Applies to all ADC input channels. Measured using the factory-set default values in the ADC offset register (ADCOF) and gain coefficient register (ADCGN); see the the Calibration section. 4 Not production tested but supported by design and/or characterization data on production release. 5 Measured using the factory-set default values in ADCOF and ADCGN with an external AD845 op amp as an input buffer stage, as shown in Figure 23. Based on external ADC system components, the user may need to execute a system calibration to remove external endpoint errors and achieve these specifications (see the ADC Circuit Overview section). 6 The input signal can be centered on any dc common-mode voltage (VCM) as long as this value is within the ADC voltage input range specified. 7 VREF calibration and trimming are performed with core operating in normal mode (CD = 0), ADC on, and all DACs on. VREF accuracy may vary under other operating conditions. 8 DAC linearity is calculated using a reduced code range of 100 to 3995. 9 DAC gain error is calculated using a reduced code range of 100 to internal 2.5 V VREF. 10 Die temperature. 11 Endurance is qualified as per JEDEC Standard 22 Method A117 and measured at −40°C, +25°C, +85°C, and +125°C. 12 Retention lifetime equivalent at junction temperature (TJ) = 85°C as per JEDEC Standard 22 Method A117. Retention lifetime derates with junction temperature. 13 Test carried out with a maximum of eight I/Os set to a low output level. 14 Power supply current consumption is measured in normal, pause, and sleep modes under the following conditions: normal mode with 3.6 V supply, pause mode with 3.6 V supply, and sleep mode with 3.6 V supply. 15 IOVDD power supply current decreases typically by 2 mA during a Flash/EE erase cycle. 1 2 3 Rev. A | Page 8 of 96 Data Sheet ADuC7122 TIMING SPECIFICATIONS Table 2. I2C Timing in Fast Mode (400 kHz) Parameter tL tH tSHD tDSU tDHD tRSU tPSU tBUF tR tF Description SCLx low pulse width SCLx high pulse width Start condition hold time Data setup time Data hold time Setup time for repeated start Stop condition setup time Bus-free time between a stop condition and a start condition Rise time for both SCLx and SDAx Fall time for both SCLx and SDAx Slave Typ Min 200 100 300 100 0 100 100 1.3 Max Master Typ Max 1360 1140 Min 740 400 800 300 300 200 Unit ns ns ns ns ns ns ns μs ns ns Table 3. I2C Timing in Standard Mode (100 kHz) Parameter tL tH tSHD tDSU tDHD tRSU tPSU tBUF tR tF Description SCLx low pulse width SCLx high pulse width Start condition hold time Data setup time Data hold time Setup time for repeated start Stop condition setup time Bus-free time between a stop condition and a start condition Rise time for both SCLx and SDAx Fall time for both SCLx and SDAx tBUF Slave Typ Min 4.7 4.0 4.0 250 0 4.7 4.0 4.7 Max Unit μs ns μs ns μs μs μs μs μs ns 3.45 1 300 tSUP tR MSB LSB tDSU tSHD P S tF tDHD 2–7 tR tRSU tH 1 SCLx MSB tDSU tDHD tPSU ACK 8 tL 9 tSUP 1 S(R) REPEATED START STOP START CONDITION CONDITION Figure 2. I2C-Compatible Interface Timing Rev. A | Page 9 of 96 tF 08755-002 SDAx ADuC7122 Data Sheet Table 4. SPI Master Mode Timing (SPICPH = 1) Parameter tSL tSH tDAV tDSU tDHD tDF tDR tSR tSF Min Typ (SPIDIV + 1) × tUCLK (SPIDIV + 1) × tUCLK Max 25 1 × tUCLK 2 × tUCLK 5 5 5 5 12.5 12.5 12.5 12.5 tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider. SCLOCK (POLARITY = 0) tSH tSL tSR tSF SCLOCK (POLARITY = 1) tDAV tDF MSB MOSI MISO tDR MSB IN BITS 6 TO 1 BITS 6 TO 1 tDSU tDHD Figure 3. SPI Master Mode Timing (SPICPH = 1) Rev. A | Page 10 of 96 LSB LSB IN 08755-003 1 Description SCLOCK low pulse width SCLOCK high pulse width Data output valid after SCLOCK edge Data input setup time before SCLOCK edge1 Data input hold time after SCLOCK edge Data output fall time Data output rise time SCLOCK rise time SCLOCK fall time Unit ns ns ns ns ns ns ns ns ns Data Sheet ADuC7122 Table 5. SPI Master Mode Timing (SPICPH = 0) Parameter tSL tSH tDAV tDOSU tDSU tDHD tDF tDR tSR tSF Min Typ (SPIDIV + 1) × tUCLK (SPIDIV + 1) × tUCLK Max Unit ns ns ns ns ns ns ns ns ns ns 25 75 1 × tUCLK 2 × tUCLK 5 5 5 5 12.5 12.5 12.5 12.5 tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider. SCLOCK (POLARITY = 0) tSH tSL tSR tSF SCLOCK (POLARITY = 1) tDAV tDOSU MSB MOSI MISO tDF MSB IN tDR BITS 6 TO 1 BITS 6 TO 1 LSB LSB IN 08755-004 1 Description SCLOCK low pulse width SCLOCK high pulse width Data output valid after SCLOCK edge Data output setup before SCLOCK edge Data input setup time before SCLOCK edge1 Data input hold time after SCLOCK edge Data output fall time Data output rise time SCLOCK rise time SCLOCK fall time tDSU tDHD Figure 4. SPI Master Mode Timing (SPICPH = 0) Rev. A | Page 11 of 96 ADuC7122 Data Sheet Table 6. SPI Slave Mode Timing (SPICPH = 1) Parameter tCS Description CS to SCLOCK edge tSL tSH tDAV tDSU tDHD tDF tDR tSR tSF tSFS SCLOCK low pulse width1 SCLOCK high pulse width1 Data output valid after SCLOCK edge Data input setup time before SCLOCK edge Data input hold time after SCLOCK edge Data output fall time Data output rise time SCLOCK rise time SCLOCK fall time CS high after SCLOCK edge 1 Min A A Max (SPIDIV + 1) × tUCLK (SPIDIV + 1) × tUCLK 25 1 × tUCLK 2 × tUCLK 5 5 5 5 12.5 12.5 12.5 12.5 0 E A Typ 200 E E A tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider. CS tSFS tCS SCLOCK (POLARITY = 0) tSH tSL tSR tSF SCLOCK (POLARITY = 1) tDAV tDF MSB MOSI MISO MSB IN tDR BITS 6 TO 1 BITS 6 TO 1 tDSU LSB LSB IN 08755-005 A tDHD Figure 5. SPI Slave Mode Timing (SPICPH = 1) Rev. A | Page 12 of 96 Unit ns ns ns ns ns ns ns ns ns ns ns Data Sheet ADuC7122 Table 7. SPI Slave Mode Timing (SPICPH = 0) Parameter tCS Description CS to SCLOCK edge tSL tSH tDAV tDSU tDHD tDF tDR tSR tSF tDOCS tSFS SCLOCK low pulse width1 SCLOCK high pulse width1 Data output valid after SCLOCK edge Data input setup time before SCLOCK edge1 Data input hold time after SCLOCK edge1 Data output fall time Data output rise time SCLOCK rise time SCLOCK fall time Data output valid after CS edge CS high after SCLOCK edge 1 E Min Typ Max A 25 1 × tUCLK 2 × tUCLK 5 5 5 5 12.5 12.5 12.5 12.5 25 E A ns ns ns ns ns ns ns ns ns ns ns ns (SPIDIV + 1) × tUCLK (SPIDIV + 1) × tUCLK A 0 E A Unit 200 E A A tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider. CS tSFS tCS SCLOCK (POLARITY = 0) tSH tSL tSR tSF SCLOCK (POLARITY = 1) tDAV tDOCS tDF MSB MOSI MISO MSB IN tDR BITS 6 TO 1 BITS 6 TO 1 LSB LSB IN 08755-006 A tDSU tDHD Figure 6. SPI Slave Mode Timing (SPICPH = 0) Rev. A | Page 13 of 96 ADuC7122 Data Sheet ABSOLUTE MAXIMUM RATINGS 2B AGND = REFGND = DACGND = GNDREF, TA = 25°C, unless otherwise noted. Table 8. Parameter AVDD to IOVDD AGND to DGND IOVDD to IOGND, AVDD to AGND Digital Input Voltage to IOGND Digital Output Voltage to IOGND VREF_2.5 and VREF_1.2 to AGND Analog Inputs to AGND Analog Outputs to AGND Operating Temperature Range Storage Temperature Range Junction Temperature θJA Thermal Impedance 108-Ball CSP_BGA Peak Solder Reflow Temperature SnPb Assemblies (10 sec to 30 sec) RoHS-Compliant Assemblies (20 sec to 40 sec) Rating −0.3 V to +0.3 V −0.3 V to +0.3 V −0.3 V to +6 V −0.3 V to +5.3 V −0.3 V to IOVDD + 0.3 V −0.3 V to AVDD + 0.3 V −0.3 V to AVDD + 0.3 V −0.3 V to AVDD + 0.3 V −10°C to +95°C −65°C to +150°C 150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating can be applied at any one time. ESD CAUTION 26B 40°C/W 240°C 260°C Rev. A | Page 14 of 96 Data Sheet ADuC7122 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 3B 1 2 3 4 5 6 7 8 9 10 11 12 A A B B C C D D E ADuC7122 F G TOP VIEW G H H J J K K L L M M 1 2 3 4 5 6 7 8 9 10 11 12 08755-007 E F Figure 7. Pin Configuration Table 9. Pin Function Descriptions Pin No. C12 D11 Mnemonic RST P0.0/SCL1/PLAI[5] Type 1 I I/O E11 P0.1/SDA1/PLAI[4] I/O C3 P0.2/SPICLK/ADCBusy/PLAO[13] I/O D3 P0.3/SPIMISO/PLAO[12]/SYNC I/O E3 P0.4/SPIMOSI/PLAI[11]/TRIP I/O F3 P0.5/SPICS/PLAI[10]/CONVST I/O E A E A 19F Description Reset Input (Active Low). General-Purpose Input and Output Port 0.0 (P0.0). I2C Interface SCLOCK for I2C0 (SCL1). Input to PLA Element 5 (PLAI[5]). General-Purpose Input and Output Port 0.1 (P0.1). I2C Interface SDATA for I2C0 (SDA1). Input to PLA Element 4 (PLAI[4]). General-Purpose Input and Output Port 0.2 (P0.2). SPI Clock (SPICLK). Status of the ADC (ADCBusy). Output of PLA Element 13 (PLAO[13]). General-Purpose Input and Output Port 0.3 (P0.3). SPI Master Input, Slave Output (SPIMISO). Output of PLA Element 12 (PLAO[12]). Input to Synchronously Reset PWM Counters Using an External Source (SYNC). General-Purpose Input and Output Port 0.4 (P0.4). SPI Master Out, Slave Input (SPIMOSI). Input to PLA Element 11 (PLAI[11]). Input that Allows the PWM Trip Interrupt to Be Triggered (TRIP). General-Purpose Input and Output Port 0.5 (P0.5). SPI Slave Select Input (SPICS). Input to PLA Element 10 (PLAI[10]). Initiates ADC Conversions Using PLA or Timer Output (CONVST). General-Purpose Input and Output Port 0.6 (P0.6). Power-On Reset Output (MRST). Input to PLA Element 2 (PLAI[2]) General-Purpose Input and Output Port 0.7 (P0.7). JTAG Test Port Input, Test Reset (TRST). Debug and download access. Input to PLA Element 3 (PLAI[3]). General-Purpose Input and Output Port 1.0 (P1.0). Serial Input, Receive Data (RxD), UART (SIN) I2C Interface SCLOCK for I2C1 (SCL2). Input to PLA Element 7 (PLAI[7]). General-Purpose Input and Output Port 1.1 (P1.1). Serial Output, Transmit Data (TxD), UART (SOUT) I2C Interface SDATA for I2C1 (SDA2). Input to PLA Element 6 (PLAI[6]). E A E A G3 P0.6/MRST/PLAI[2] E A A I/O E A G10 P0.7/TRST/PLAI[3] E A A I/O A E A C2 P1.0/SIN/SCL2/PLAI[7] I/O D2 P1.1/SOUT/SDA2/PLAI[6] I/O Rev. A | Page 15 of 96 A A ADuC7122 Data Sheet Pin No. H3 Mnemonic P1.4/PWM1/PLAI[8]/ECLK/XCLK Type 1 I/O J3 P1.5/PWM2/PLAI[9] I/O B3 P1.6/PLAO[5] I/O B2 P1.7/PLAO[4] I/O F11 P2.0/IRQ0/PLAI[13] I/O G11 P2.1/IRQ1/PLAI[12] I/O H11 P2.2/PLAI[1] I/O J11 P2.3/IRQ2/PLAI[14] I/O H10 P2.4/PWM5/PLAO[7] I/O J10 P2.5/PWM6/PLAO[6] I/O C1 P2.6/IRQ3/PLAI[15] I/O C9 P2.7/PLAI[0] I/O C4 P3.0/PLAO[0] I/O C11 P3.1/PLAO[1] I/O D1 P3.2/IRQ4/PWM3/PLAO[2] I/O E1 P3.3/IRQ5/PWM4/PLAO[3] I/O E2 P3.4/PLAO[8] I/O F2 P3.5/PLAO[9] I/O D12 P3.6/PLAO[10] I/O 19F Description General-Purpose Input and Output Port 1.4 (P1.4). PWM1 Output (PWM1). Input to PLA Element 8 (PLAI[8]). Base System Clock Output (ECLK). Base System Clock Input (XCLK). General-Purpose Input and Output Port 1.5 (P1.5). PWM2 Output (PWM2). Input to PLA Element 9 (PLAI[9]). General-Purpose Input and Output Port 1.6 (P1.6). Output of PLA Element 5 (PLAO[5]). General-Purpose Input and Output Port 1.7 (P1.7). Output of PLA Element 4 (PLAO[4]). General-Purpose Input and Output Port 2.0 (P2.0). External Interrupt Request 0 (IRQ0). Input to PLA Element 13 (PLAI[13]). General-Purpose Input and Output Port 2.1 (P2.1). External Interrupt Request 1 (IRQ1). Input to PLA Element 12 (PLAI[12]). General-Purpose Input and Output Port 2.2 (P2.2). Input to PLA Element 1 (PLAI[1]). General-Purpose Input and Output Port 2.3 (P2.3). External Interrupt Request 2 (IRQ2). Input to PLA Element 14 (PLAI[14]). General-Purpose Input and Output Port 2.4 (P2.4). PWM5 Output (PWM5). Output of PLA Element 7 (PLAO[7]). General-Purpose Input and Output Port 2.5 (P2.5). PWM6 Output (PWM6). Output of PLA Element 6 (PLAO[6]). General-Purpose Input and Output Port 2.6 (P2.6). External Interrupt Request 3 (IRQ3). Input to PLA Element 15 (PLAI[15]). General-Purpose Input and Output Port 2.7 (P2.7). Input to PLA Element 0 (PLAI[0]). General-Purpose Input and Output Port 3.0 (P3.0). Output of PLA Element 0 (PLAO[0]). General-Purpose Input and Output Port 3.1 (P3.1). Output of PLA Element 1 (PLAO[1]). General-Purpose Input and Output Port 3.2 (P3.2). External Interrupt Request 4 (IRQ4). PWM3 Output (PWM3). Output of PLA Element 2 (PLAO[2]). General-Purpose Input and Output Port 3.3 (P3.3). External Interrupt Request 5 (IRQ5). PWM4 Output (PWM4). Output of PLA Element 3 (PLAO[3]). General-Purpose Input and Output Port 3.4 (P3.4). Output of PLA Element 8 (PLAO[8]). General-Purpose Input and Output Port 3.5 (P3.5). Output of PLA Element 9 (PLAO[9]). General-Purpose Input and Output Port 3.6 (P3.6). Output of PLA Element 10 (PLAO[10]). Rev. A | Page 16 of 96 Data Sheet Pin No. E12 ADuC7122 Mnemonic P3.7/BM/PLAO[11] E A A Type 1 I/O 19F Description General-Purpose Input and Output Port 3.7 (P3.7). Boot Mode (BM). If BM is low and Address 0x00014 of Flash is 0xFFFFFFFF, then the part enters I2C download after the next rest sequence. Output of PLA Element 11 (PLAO[11]). 2.5 V Reference Output, External 2.5 V Reference Input. Can be used to drive the anode of a photo diode 1.2 V Reference Output, External 1.2 V Reference Input. Cannot be used to source current externally. No Connect. Buffered 2.5 V Bias. Maximum load = 1.2 mA. Buffered 2.5 V Bias. Maximum load = 1.2 mA. PADC0 Positive Input Channel. PGA-based ADC input channel. PADC0 Negative Input Channel. PGA-based ADC input channel. PADC1 Positive Input Channel. PGA-based ADC input channel. PADC1 Negative Input Channel. PGA-based ADC input channel. Single-Ended or Differential Analog Input 0. Single-Ended or Differential Analog Input 1. Single-Ended or Differential Analog Input 2. Single-Ended or Differential Analog Input 3. Single-Ended or Differential Analog Input 4. Single-Ended or Differential Analog Input 5. Single-Ended or Differential Analog Input 6. Single-Ended or Differential Analog Input 7. Single-Ended or Differential Analog Input 8. Single-Ended or Differential Analog Input 9. Single-Ended or Differential Analog Input 10. Common Mode for Pseudo Differential Input (AINCM). 12-Bit DAC Output. 12-Bit DAC Output. 12-Bit DAC Output. 12-Bit DAC Output. 12-Bit DAC Output. 12-Bit DAC Output. 12-Bit DAC Output. 12-Bit DAC Output. 12-Bit DAC Output. 12-Bit DAC Output. 12-Bit DAC Output. 12-Bit DAC Output. No Connect. No Connect. No Connect. No Connect. No Connect. No Connect. No Connect. No Connect. No Connect. No Connect. No Connect. No Connect. No Connect. No Connect. No Connect. E A L8 VREF_2.5 AI/O L5 VREF_1.2 AI/O B8 K6 K7 L6 M5 L7 M8 K5 K4 M4 L4 K3 M3 M10 M9 L9 K9 K8 NC BUF_VREF1 BUF_VREF2 PADC0P PADC0N PADC1P PADC1N ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 ADC7 ADC8 ADC9 ADC10/AINCM NC AO AO AI AI AI AI AI AI AI AI AI AI AI AI AI AI AI K1 K2 J2 L2 M2 L3 M11 L11 L10 K10 K11 K12 B5 C6 A6 A8 A7 C8 A5 C5 B4 A4 A1 A3 A2 B1 A12 DAC0 DAC1 DAC2 DAC3 DAC4 DAC5 DAC6 DAC7 DAC8 DAC9 DAC10 DAC11 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC AO AO AO AO AO AO AO AO AO AO AO AO NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC E A A A Rev. A | Page 17 of 96 ADuC7122 Data Sheet Pin No. A9 A11 A10 B12 B11 B10 B9 M1 M6 L1 M7 M12 B6 L12 C7 B7 Mnemonic NC NC NC NC NC AGND AGND AGND AGND AVDD AVDD AGND AGND AVDD NC REG_PWR Type 1 NC NC NC NC NC S S S S S S S S S NC S G1 LVDD S G12 LVDD S F1 F12 H1 J1 H12 J12 G2 DGND DGND IOVDD IOGND IOVDD IOGND XTALO S S S S S S DO H2 XTALI DI D10 TDO/P1.3/PLAO[14] DO C10 TDI/P1.2/PLAO[15] DI F10 E10 TCK TMS DI DI 1 19F Description No Connect. No Connect. No Connect. No Connect. No Connect. Analog Ground. Analog Ground. Analog Ground. Analog Ground. Analog Supply (3.3 V). Analog Supply (3.3 V). Analog Ground. Analog Ground. Analog Supply (3.3 V). No Connect. Output of 2.5 V On-Chip Regulator. A 470 nF capacitor to DGND must be connected to this pin. Output of 2.6 V On-Chip LDO Regulator. A 470 nF capacitor to DGND must be connected to this pin. Output of 2.6 V On-Chip LDO Regulator. A 470 nF capacitor to DGND must be connected to this pin. Digital ground. Digital ground. 3.3 V GPIO Supply. 3.3 V GPIO Ground. 3.3 V GPIO Supply. 3.3 V GPIO Ground. Output from the Crystal Oscillator Inverter. If an external crystal is not being used, this pin can be left unconnected. Input to the Crystal Oscillator Inverter and Input to the Internal Clock Generator Circuits. If an external crystal is not being used, this pin should be connected to the DGND system ground. JTAG Test Port Output, Test Data Out (TDO). Debug and download access. General-Purpose Input and Output Port 1.3 (P1.3). Output of PLA Element 14 (PLAO[14]). This pin should not be used as a GPIO when debugging via the JTAG interface. JTAG Test Port Input, Test Data In (TDI). Debug and download access. General-Purpose Input and Output Port 1.2 (P1.2). Output of PLA Element 15 (PLAO[15]). This pin should not be used as a GPIO when debugging via the JTAG interface. JTAG Test Port Input, Test Clock. Debug and download access. JTAG Test Port Input, Test Mode Select. Debug and download access. I = input, I/O = input/output, AI/O = analog input/output, NC = no connect, AO = analog output, AI = analog input, DI = digital input, DO = digital output, S = supply. Rev. A | Page 18 of 96 Data Sheet ADuC7122 TERMINOLOGY 4B ADC SPECIFICATIONS 27B Integral Nonlinearity (INL) The maximum deviation of any code from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, a point ½ LSB below the first code transition, and full scale, a point ½ LSB above the last code transition. The ratio is dependent upon the number of quantization levels in the digitization process; the more levels there are, the smaller the quantization noise becomes. The theoretical signal-to-(noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by Signal to (Noise + Distortion) = (6.02 N + 1.76) dB Thus, for a 12-bit converter, this is 74 dB. Differential Nonlinearity (DNL) The difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Total Harmonic Distortion The ratio of the rms sum of the harmonics to the fundamental. DAC SPECIFICATIONS Offset Error The deviation of the first code transition (0000…000) to (0000…001) from the ideal, that is, ½ LSB. 28B Relative Accuracy Otherwise known as endpoint linearity, relative accuracy is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting for zero error and full-scale error. Gain Error The deviation of the last code transition from the ideal AIN voltage (full scale − 1.5 LSB) after the offset error has been adjusted out. Signal-to-(Noise + Distortion) Ratio The measured ratio of signal to (noise + distortion) at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the rms sum of all nonfundamental signals up to half the sampling frequency (fS/2), excluding dc. Voltage Output Settling Time The amount of time it takes the output to settle to within a 1 LSB level for a full-scale input change. Rev. A | Page 19 of 96 ADuC7122 Data Sheet OVERVIEW OF THE ARM7TDMI CORE The ARM7® core is a 32-bit reduced instruction set computer (RISC). It uses a single 32-bit bus for instruction and data. The length of the data can be eight bits, 16 bits, or 32 bits. The length of the instruction word is 32 bits. The ARM7TDMI is an ARM7 core with four additional features: T support for the thumb (16-bit) instruction set D support for debugging M support for long multiplications I includes the EmbeddedICE module to support embedded system debugging THUMB MODE (T) An ARM instruction is 32 bits long. The ARM7TDMI processor supports a second instruction set that has been compressed into 16 bits, called the thumb instruction set. Faster execution from 16-bit memory and greater code density can usually be achieved by using the thumb instruction set instead of the ARM instruction set, which makes the ARM7TDMI core particularly suitable for embedded applications. However, the thumb mode has two limitations: Thumb code typically requires more instructions for the same job. As a result, ARM code is usually best for maximizing the performance of time-critical code. The thumb instruction set does not include some of the instructions needed for exception handling, which automatically switches the core to ARM code for exception handling. See the ARM7TDMI user guide for details on the core architecture, the programming model, and both the ARM and ARM thumb instruction sets. LONG MULTIPLY (M) The ARM7TDMI instruction set includes four extra instructions that perform 32-bit by 32-bit multiplication with a 64-bit result, and 32-bit by 32-bit multiplication-accumulation (MAC) with a 64-bit result. These results are achieved in fewer cycles than required on a standard ARM7 core. ARM supports five types of exceptions and a privileged processing mode for each type. The five types of exceptions are: Normal interrupt or IRQ. This is provided to service general-purpose interrupt handling of internal and external events. Fast interrupt or FIQ. This is provided to service data transfers or communication channels with low latency. FIQ has priority over IRQ. Memory abort. Attempted execution of an undefined instruction. Software interrupt instruction (SWI). This can be used to make a call to an operating system. Typically, the programmer defines an interrupt as IRQ, but for a higher priority interrupt, that is, faster response time, the programmer can define the interrupt as FIQ. ARM REGISTERS ARM7TDMI has a total of 37 registers: 31 general-purpose registers and six status registers. Each operating mode has dedicated banked registers. When writing user-level programs, 15 general-purpose, 32-bit registers (R0 to R14), the program counter (R15) and the current program status register (CPSR) are usable. The remaining registers are only used for system-level programming and exception handling. When an exception occurs, some of the standard registers are replaced with registers specific to the exception mode. All exception modes have replacement banked registers for the stack pointer (R13) and the link register (R14), as represented in Figure 8. The fast interrupt mode has more registers (R8 to R12) for fast interrupt processing. This means the interrupt processing can begin without the need to save or restore these registers, and thus save critical time in the interrupt handling process. R0 USABLE IN USER MODE R1 SYSTEM MODES ONLY R2 R3 R4 EmbeddedICE (I) R5 EmbeddedICE provides integrated on-chip support for the core. The EmbeddedICE module contains the breakpoint and watchpoint registers that allow code to be halted for debugging purposes. These registers are controlled through the JTAG test port. R7 R6 R8 R9 R10 R11 R12 When a breakpoint or watchpoint is encountered, the processor halts and enters a debug state. Once in a debug state, the processor registers can be inspected as well as the Flash/EE, SRAM, and memory mapped registers. R13 R14 R8_FIQ R9_FIQ R10_FIQ R11_FIQ R12_FIQ R13_FIQ R14_FIQ R13_SVC R14_SVC R13_ABT R14_ABT R13_IRQ R14_IRQ R13_UND R14_UND R15 (PC) CPSR USER MODE SPSR_FIQ FIQ MODE SPSR_SVC SVC MODE SPSR_ABT ABORT MODE SPSR_IRQ IRQ MODE Figure 8. Register Organization Rev. A | Page 20 of 96 SPSR_UND UNDEFINED MODE 08755-008 EXCEPTIONS Data Sheet ADuC7122 More information relative to the programmer’s model and the ARM7TDMI core architecture can be found in the following materials from ARM: • • DDI 0029G, ARM7TDMI Technical Reference Manual DDI 0100, ARM Architecture Reference Manual INTERRUPT LATENCY 34B The worst-case latency for a fast interrupt request (FIQ) consists of the following: • • • • The longest time the request can take to pass through the synchronizer The time for the longest instruction to complete (the longest instruction is an LDM) that loads all the registers including the PC The time for the data abort entry The time for FIQ entry At the end of this time, the ARM7TDMI executes the instruction at 0x1C (FIQ interrupt vector address). The maximum total time is 50 processor cycles, which is just under 1.2 µs in a system using a continuous 41.78 MHz processor clock. The maximum interrupt request (IRQ) latency calculation is similar but must allow for the fact that FIQ has higher priority and can delay entry into the IRQ handling routine for an arbitrary length of time. This time can be reduced to 42 cycles if the LDM command is not used. Some compilers have an option to compile without using this command. Another option is to run the part in thumb mode where the time is reduced to 22 cycles. The minimum latency for FIQ or IRQ interrupts is a total of five cycles, which consist of the shortest time the request can take through the synchronizer, plus the time to enter the exception mode. Note that the ARM7TDMI always runs in ARM (32-bit) mode when in privileged mode, for example, when executing interrupt service routines. Rev. A | Page 21 of 96 ADuC7122 Data Sheet MEMORY ORGANIZATION 6B The ADuC7122 incorporates three separate blocks of memory: 8 kB of SRAM and two 64 kB of on-chip Flash/EE memory. There are 126 kB of on-chip Flash/EE memory available to the user, and the remaining 2 kB are reserved for the factoryconfigured boot page. These two blocks are mapped as shown in Figure 9. Note that by default, after a reset, the Flash/EE memory is mirrored at Address 0x00000000. It is possible to remap the SRAM at Address 0x00000000 by clearing Bit 0 of the REMAP MMR. This remap function is described in more detail in the Flash/EE Memory section. FLASH/EE MEMORY 35B The 128 kB of Flash/EE are organized as two banks of 32k × 16 bits. Block 0 starts at Address 0x90000 and finishes at Address 0x9F700. In this block, 31k × 16 bits is user space and 1k × 16 bits are reserved for the factory-configured boot page. The page size of this Flash/EE memory is 512 bytes. Block 1 starts at Address 0x80000 and finishes at Address 0x90000. In this block 64 kB block is arranged in 32k × 16 bits, all of which is available as user space. The 126 kB of Flash/EE are available to the user as code and nonvolatile data memory. There is no distinction between data and program because ARM code shares the same space. The real width of the Flash/EE memory is 16 bits, meaning that in ARM mode (32-bit instruction), two accesses to the Flash/EE are necessary for each instruction fetch. Therefore, it is recommended that Thumb mode be used when executing from Flash/EE memory for optimum access speed. The maximum access speed for the Flash/EE memory is 41.78 MHz in Thumb mode and 20.89 MHz in full ARM mode (see the Execution Time from SRAM and FLASH/EE section). 0xFFFFFFFF MMRs 0xFFFF0000 RESERVED 0x0009F800 FLASH/EE 0x00080000 RESERVED 0x00041FFF SRAM 0x00040000 SRAM RESERVED 36B 0x0001FFFF 0x00000000 The 8 kB of SRAM are available to the user, organized as 2k × 32 bits, that is, 2k words. ARM code can run directly from SRAM at 41.78 MHz, given that the SRAM array is configured as a 32-bit wide memory array (see the Execution Time from SRAM and FLASH/EE section). 08755-009 REMAPPABLE MEMORY SPACE (FLASH/EE OR SRAM) Figure 9. Physical Memory Map Memory Access MEMORY MAPPED REGISTERS 85B The ARM7 core sees memory as a linear array of 232 byte locations, where the different blocks of memory are mapped as outlined in Figure 9. The ADuC7122 memory organization is configured in little endian format: the least significant byte is located in the lowest byte address and the most significant byte in the highest byte address. BIT 31 BIT 0 BYTE 2 . . . B 7 3 BYTE 1 . . . BYTE 0 . . . A 9 8 6 5 4 0x00000004 2 1 0 0x00000000 0xFFFFFFFF 32 BITS Figure 10. Little Endian Format 08755-010 BYTE 3 . . . 37B The memory mapped register (MMR) space is mapped into the upper two pages of the memory array and accessed by indirect addressing through the ARM7 banked registers. The MMR space provides an interface between the CPU and all on-chip peripherals. All registers except the core registers reside in the MMR area. All shaded locations shown in Figure 11 are unoccupied or reserved locations and should not be accessed by user software. Table 10 to Table 26 show a full MMR memory map. The access time reading or writing a MMR depends on the advanced microcontroller bus architecture (AMBA) bus used to access the peripheral. The processor has two AMBA buses: advanced high performance bus (AHB) used for system modules and advanced peripheral bus (APB) used for lower performance peripheral. Access to the AHB is one cycle, and access to the APB is two cycles. All peripherals on the ADuC7122 are on the APB except the Flash/EE memory and the GPIOs. Rev. A | Page 22 of 96 Data Sheet ADuC7122 0xFFFF082D Table 10. IRQ Base Address = 0xFFFF0000 UART 0xFFFF0800 0xFFFF0F89 0xFFFF05DF PWM DAC 0xFFFF0F80 0xFFFF0580 0xFFFF0EA3 0xFFFF0521 ADC 0xFFFF0E80 0xFFFF0500 0xFFFF0480 0xFFFF0441 0xFFFF0440 0xFFFF0419 0xFFFF0404 BAND GAP REFERENCE POWER SUPPLY MONITOR PLL AND OSCILLATOR CONTROL 0xFFFF0E23 0xFFFF0E00 FLASH CONTROL INTERFACE 0 0xFFFF0D5F GPIO 0xFFFF0D00 0xFFFF0B53 PLA 0xFFFF0B00 0xFFFF0A11 0xFFFF0393 SPI TIMER 0xFFFF0300 0xFFFF0A00 0xFFFF0234 0xFFFF094C 0xFFFF0220 0xFFFF013C 0xFFFF0000 REMAP AND SYSTEM CONTROL INTERRUPT CONTROLLER I2C1 0xFFFF0900 0xFFFF08CC I2C0 0xFFFF0880 08755-011 0xFFFF0480 FLASH CONTROL INTERFACE 1 Figure 11. Memory Mapped Registers Address 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x001C 0x0020 0x0024 0x0028 0x002C 0x0030 0x0034 0x0038 0x003C 0x0100 0x0104 0x0108 0x010C 0x011C 0x013C Name IRQSTA IRQSIG IRQEN IRQCLR SWICFG IRQBASE IRQVEC IRQP0 IRQP1 IRQP2 IRQP3 IRQCONN IRQCONE IRQCLRE IRQSTAN FIQSTA FIQSIG FIQEN FIQCLR FIQVEC FIQSTAN Byte 4 4 4 4 4 4 4 4 4 4 4 1 1 1 1 4 4 4 4 4 1 Access Type R R R/W W W R/W R R/W R/W R/W R/W R/W R/W W R/W R R R/W W R R/W Cycle 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 COMPLETE MMR LISTING Note that the access type column in Table 10 to Table 26 corresponds to the access time reading or writing an MMR. It depends on the AMBA bus used to access the peripheral. The processor has two AMBA buses: the AHB (advanced high performance bus) used for system modules and the APB (advanced peripheral bus) used for lower performance peripherals. Table 11. System Control Base Address = 0xFFFF0200 Address 0x0220 0x0230 0x0234 0x0248 0x024C 0x0250 Rev. A | Page 23 of 96 Name REMAP RSTSTA RSTCLR RSTKEY1 RSTCFG RSTKEY2 Byte 1 1 1 1 1 1 Access Type R/W R W W R/W W Cycle 1 1 1 N/A 0x00 N/A ADuC7122 Data Sheet Table 12. Timer Base Address = 0xFFFF0300 Address 0x0300 0x0304 0x0308 0x030C 0x0310 0x0314 0x0320 0x0324 0x0328 0x032C 0x0330 0x0340 0x0344 0x0348 0x034C 0x0360 0x0364 0x0368 0x036C 0x0380 0x0384 0x0388 0x038C 0x0390 Name T0LD T0VAL0 T0VAL1 T0CON T0CLRI T0CAP T1LD T1VAL T1CON T1CLRI T1CAP T2LD T2VAL T2CON T2CLRI T3LD T3VAL T3CON T3CLRI T4LD T4VAL T4CON T4CLRI T4CAP Byte 2 2 4 4 1 2 4 4 4 1 4 4 4 4 1 2 2 2 1 4 4 4 1 4 Access Type R/W R R R/W W R R/W R R/W W R R/W R R/W W R/W R R/W W R/W R R/W W R Table 16. ADC Base Address = 0xFFFF0500 Cycle 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Table 13. PLL Base Address = 0xFFFF0400 Address 0x0404 0x0408 0x040C 0x0410 0x0414 0x0418 Name POWKEY1 POWCON POWKEY2 PLLKEY1 PLLCON PLLKEY2 Byte 2 1 2 2 1 2 Access Type W R/W W W R/W W Cycle 2 2 2 2 2 2 Address 0x0500 0x0504 0x0508 0x050C 0x0510 0x0514 0x0520 Name PSMCON Byte 2 Access Type R/W Address 0x0580 0x0584 0x0588 0x058C 0x0590 0x0594 0x0598 0x059C 0x05A0 0x05A4 0x05A8 0x05AC 0x05B0 0x05B4 0x05B8 0x05BC 0x05C0 0x05C4 0x05C8 0x05CC 0x05D0 0x05D4 0x05D8 0x05DC Cycle 2 Table 15. Reference Base Address = 0xFFFF0480 Address 0x0480 Name REFCON Byte 1 Access Type R/W Byte 4 1 1 1 4 1 2 Access Type R/W R/W R/W R R W R/W Cycle 2 2 2 2 2 2 2 Table 17. DAC Base Address = 0xFFFF0580 Table 14. PSM Base Address = 0xFFFF0440 Address 0x0440 Name ADCCON ADCCP ADCCN ADCSTA ADCDAT ADCRST PGA_GN Cycle 2 Rev. A | Page 24 of 96 Name DAC0CON DAC0DAT DAC1CON DAC1DAT DAC2CON DAC2DAT DAC3CON DAC3DAT DAC4CON DAC4DAT DAC5CON DAC5DAT DAC6CON DAC6DAT DAC7CON DAC7DAT DAC8CON DAC8DAT DAC9CON DAC9DAT DAC10CON DAC10DAT DAC11CON DAC11DAT Byte 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 Access Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Cycle 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Data Sheet ADuC7122 Table 20. I2C1 Base Address = 0xFFFF0900 Table 18. UART0 Base Address = 0xFFFF0800 Address 0x0800 0x0800 0x0800 0x0804 0x0804 0x0808 0x080C 0x0810 0x0814 0x0818 0x081C 0x0820 0x0824 0x0828 0x082C Name COMTX COMRX COMDIV0 COMIEN0 COMDIV1 COMIID0 COMCON0 COMCON1 COMSTA0 COMSTA1 COMSCR COMIEN1 COMIID1 COMADR COMDIV2 Byte 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 Access Type W R R/W R/W R/W R R/W R/W R R R/W R/W R R/W R/W Cycle 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Table 19. I2C0 Base Address = 0xFFFF0880 Address 0x0880 0x0884 0x0888 0x088C 0x0890 0x0894 0x0898 0x089C 0x08A0 0x08A4 0x08A8 0x08AC 0x08B0 0x08B4 0x08B8 0x08BC 0x08C0 0x08C4 0x08C8 0x08CC Name I2C0MCTL I2C0MSTA I2C0MRX I2C0MTX I2C0MCNT0 I2C0MCNT1 I2C0ADR0 I2C0ADR1 I2C0SBYTE I2C0DIV I2C0SCTL I2C0SSTA I2C0SRX I2C0STX I2C0ALT I2C0ID0 I2C0ID1 I2C0ID2 I2C0ID3 I2C0FSTA Byte 2 2 1 2 2 1 1 1 1 2 2 2 1 1 1 1 1 1 1 1 Access Type R/W R R R/W R/W R R/W R/W R/W R/W R/W R R R/W R/W R/W R/W R/W R/W R/W Cycle 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Address 0x0900 0x0904 0x0908 0x090C 0x0910 0x0914 0x0918 0x091C 0x0920 0x0924 0x0928 0x092C 0x0930 0x0934 0x0938 0x093C 0x0940 0x0944 0x0948 0x094C Name I2C1MCTL I2C1MSTA I2C1MRX I2C1MTX I2C1MCNT0 I2C1MCNT1 I2C1ADR0 I2C1ADR1 I2C1SBYTE I2C1DIV I2C1SCTL I2C1SSTA I2C1SRX I2C1STX I2C1ALT I2C1ID0 I2C1ID1 I2C1ID2 I2C1ID3 I2C1FSTA Byte 2 2 1 2 2 1 1 1 1 2 2 2 1 1 1 1 1 1 1 1 Access Type R/W R R R/W R/W R R/W R/W R/W R/W R/W R R R/W R/W R/W R/W R/W R/W R/W Cycle 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Table 21. SPI Base Address = 0xFFFF0A00 Address 0x0A00 0x0A04 0x0A08 0x0A0C 0x0A10 Rev. A | Page 25 of 96 Name SPISTA SPIRX SPITX SPIDIV SPICON Byte 1 1 1 1 2 Access Type R R W R/W R/W Cycle 2 2 2 2 2 ADuC7122 Data Sheet Table 22. PLA Base Address = 0xFFFF0B00 Address 0x0B00 0x0B04 0x0B08 0x0B0C 0x0B10 0x0B14 0x0B18 0x0B1C 0x0B20 0x0B24 0x0B28 0x0B2C 0x0B30 0x0B34 0x0B38 0x0B3C 0x0B40 0x0B44 0x0B48 0x0B4C 0x0B50 Name PLAELM0 PLAELM1 PLAELM2 PLAELM3 PLAELM4 PLAELM5 PLAELM6 PLAELM7 PLAELM8 PLAELM9 PLAELM10 PLAELM11 PLAELM12 PLAELM13 PLAELM14 PLAELM15 PLACLK PLAIRQ PLAADC PLADIN PLADOUT Byte 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 4 4 4 4 Access Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R Cycle 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Table 23. GPIO Base Address = 0xFFFF0D00 Address 0x0D00 0x0D04 0x0D08 0x0D0C 0x0D20 0x0D24 0x0D28 0x0D2C 0x0D30 0x0D34 0x0D38 0x0D3C 0x0D40 0x0D44 0x0D48 0x0D4C 0x0D50 0x0D54 0x0D58 0x0D5C 0x0D70 0x0D74 0x0D78 Name GP0CON GP1CON GP2CON GP3CON GP0DAT GP0SET GP0CLR GP0PAR GP1DAT GP1SET GP1CLR GP1PAR GP2DAT GP2SET GP2CLR GP2PAR GP3DAT GP3SET GP3CLR GP3PAR GP1OCE GP2OCE GP3OCE Byte 4 4 4 4 4 1 1 4 4 1 1 4 4 1 1 4 4 1 1 4 1 1 1 Access Type R/W R/W R/W R/W R/W W W R/W R/W W W R/W R/W W W R/W R/W W W R/W W W W Cycle 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Table 24. Flash/EE Block 0 Base Address = 0xFFFF0E00 Address 0x0E00 0x0E04 0x0E08 0x0E0C 0x0E10 0x0E18 0x0E1C 0x0E20 Name FEE0STA FEE0MOD FEE0CON FEE0DAT FEE0ADR FEE0SGN FEE0PRO FEE0HID Byte 1 1 1 2 2 3 4 4 Access Type R R/W R/W R/W R/W R R/W R/W Cycle 1 1 1 1 1 1 1 1 Table 25. Flash/EE Block 1 Base Address = 0xFFFF0E80 Address 0x0E80 0x0E84 0x0E88 0x0E8C 0x0E90 0x0E98 0x0E9C 0x0EA0 Name FEE1STA FEE1MOD FEE1CON FEE1DAT FEE1ADR FEE1SGN FEE1PRO FEE1HID Byte 1 1 1 2 2 3 4 4 Access Type R R/W R/W R/W R/W R R/W R/W Cycle 1 1 1 1 1 1 1 1 Table 26. PWM Base Address= 0xFFFF0F80 Address 0x0F80 0x0F84 0x0F88 0x0F8C 0x0F90 0x0F94 0x0F98 0x0F9C 0x0FA0 0x0FA4 0x0FA8 0x0FAC 0x0FB0 0x0FB4 0x0FB8 Rev. A | Page 26 of 96 Name PWMCON1 PWM1COM1 PWM1COM2 PWM1COM3 PWM1LEN PWM2COM1 PWM2COM2 PWM2COM3 PWM2LEN PWM3COM1 PWM3COM2 PWM3COM3 PWM3LEN PWMCON2 PWMICLR Byte 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Access Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W W Cycle 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Data Sheet ADuC7122 ADC CIRCUIT OVERVIEW 7B The analog-to-digital converter (ADC) incorporates a fast, multichannel, 12-bit ADC. It can operate from 3.0 V to 3.6 V supplies and is capable of providing a throughput of up to 1 MSPS when the clock source is 41.78 MHz. This block provides the user with a multichannel multiplexer, differential track-andhold, on-chip reference, and ADC. The ADC consists of a 12-bit successive approximation converter based around two capacitor DACs. Depending on the input signal configuration, the ADC can operate in one of the following three modes: • • • Fully differential mode for small and balanced signals Single-ended mode for any single-ended signals Pseudo differential mode for any single-ended signals, taking advantage of the common-mode rejection offered by the pseudo differential input The converter accepts an analog input range of 0 to VREF when operating in single-ended mode or pseudo differential mode. In fully differential mode, the input signal must be balanced around a common-mode voltage, VCM, in the range 0 V to AVDD, and with maximum amplitude of 2 VREF (see Figure 12). AVDD VCM VCM Single or continuous conversion modes can be initiated in software. An external CONVST pin, an output generated from the on-chip PLA, or a Timer0 or Timer1 overflow can also be used to generate a repetitive trigger for ADC conversions. E A A voltage output from an on-chip band gap reference proportional to absolute temperature can also be routed through the front-end ADC multiplexer, effectively an additional ADC channel input. This facilitates an internal temperature sensor channel, measuring die temperature to an accuracy of ±3°C. For the ADuC7122, a number of modifications have been made to the ADC input structure that appears in the ADuC702x family. The PADC0 and PADC1 inputs connect to a PGA in pseudo differential mode and allow for selectable gains from 1 to 5 with 32 steps. The remaining ADC channels can be configured as single, differential, or pseudo differential. A buffer is provided before the ADC for measuring internal channels. 08755-012 2VREF A If the signal has not been deasserted by the time the ADC conversion is complete, a second conversion begins automatically. 2VREF VCM 0 2VREF A high precision, low drift, and factory-calibrated 2.5 V reference is provided on chip. An external reference can also be connected as described in the Band Gap Reference section. Figure 12. Examples of Balanced Signals for Fully Differential Mode Rev. A | Page 27 of 96 ADuC7122 Data Sheet SIGN BIT 0 1111 1111 1110 ADC TRANSFER FUNCTION Pseudo Differential and Single-Ended Modes 0 1111 1111 1100 1 LSB = FS/4096 or 2.5 V/4096 = 0.61 mV or 610 μV when VREF = 2.5 V 0 0000 0000 0001 0 0000 0000 0000 1 1111 1111 1110 1 0000 0000 0100 The ideal code transitions occur midway between successive integer LSB values (that is, 1/2 LSB, 3/2 LSBs, 5/2 LSBs, …, FS – 3/2 LSBs). The ideal input/output transfer characteristic is shown in Figure 13. 1 0000 0000 0000 0LSB +VREF – 1LSB –VREF + 1LSB VOLTAGE INPUT (VIN+ – VIN–) 08755-014 1 0000 0000 0010 Figure 14. ADC Transfer Function in Differential Mode ADC Input Channels 1111 1111 1111 The ADuC7122 provides 11 fixed gain ADC input pins. Each of these pins can be separately configured as a differential input pair, single-ended input, or positive side pseudo differential input (the negative side must be the AINCM channel). The buffer and ADC are configured independently from input channel selection. Note that the input range of the ADC input buffer is from 0.15 V to AVDD − 0.15 V. If the input signal range exceeds this range, the input buffer must be bypassed. 1111 1111 1110 1111 1111 1101 OUTPUT CODE 2 × VREF 4096 0 1111 1111 1010 OUTPUT CODE In pseudo differential or single-ended mode, the input range is 0 V to VREF. The output coding is straight binary in pseudo differential and single-ended modes with 1LSB = 1111 1111 1100 1LSB = FS 4096 0000 0000 0011 0000 0000 0010 0000 0000 0000 0V 1LSB +FS – 1LSB VOLTAGE INPUT 08755-013 0000 0000 0001 Figure 13. ADC Transfer Function in Pseudo Differential Mode or Single-Ended Mode Fully Differential Mode The amplitude of the differential signal is the difference between the signals applied to the VIN+ and VIN− inputs (that is, VIN+ − VIN−) of the currently enabled differential channel. The maximum amplitude of the differential signal is, therefore, −VREF to +VREF p-p (2 × VREF). This is regardless of the common mode (CM). The common mode is the average of the two signals (VIN+ + VIN−)/2, and is, therefore, the voltage that the two inputs are centered on. This results in the span of each input being CM ± VREF/2. This voltage must be set up externally, and its range varies with VREF (see the Driving the Analog Inputs section). The output coding is twos complement in fully differential mode with 1 LSB = 2 VREF/4096 or 2 × 2.5 V/4096 = 1.22 mV when VREF = 2.5 V. The output result is ±11 bits, but this is shifted by one to the right, which allows the result in ADCDAT to be declared as a signed integer when writing C code. The designed code transitions occur midway between successive integer LSB values (that is, 1/2 LSB, 3/2 LSBs, 5/2 LSBs, …, FS − 3/2 LSBs). The ideal input/output transfer characteristic is shown in Figure 14. The ADC mux can be configured to select an internal channel like IOVDD_MON or the temperature sensor. When converting on an internal channel, the input buffer must be enabled. In addition, an on-chip diode can be selected to provide chip temperature monitoring. The ADC can also select VREF and AGND as the input for calibration purposes. PGA and Input Buffer The ADuC7122 contains two programmable gain channels that operate in pseudo differential mode. The PGA is a one-stage positive gain amplifier that is able to accept an input from 0.1 V to AVDD − 1.2 V. The PGA output can swing up to 2.5 V. The PGA is designed to handle 10 mV minimum input. The gain of the PGA is from 1 to 5 with 32 linear steps. The PGA cannot be bypassed for the PADC0 and PADC1 channels. The PGAs use a PMOS input to minimize nonlinearity and noise. The input level for PGA is limited from AVDD − 1.2 V to 0.1 V to make sure the amplifiers are not saturated. The input buffer is a rail-to-rail buffer. It can accept signals from 0.15 V to AVDD − 0.15 V. Each of the input buffers can be bypassed independently. To minimize noise, the PADC input buffer can be bypassed. PADCxN is driven by a buffer to 0.15 V to keep the PGA from saturation when the input current drops to 0. The buffer can be disabled by setting ADCCON[14] so that the PADCxN can be connected to GND as well. The PADCx channels are only specified to operate in pseudo differential mode and this assumes the negative input is close to ground. Rev. A | Page 28 of 96 Data Sheet ADuC7122 Current Consumption All the controls are independently set through register bits to give maximum flexibility to the user. Typically, users must set the following: 1. 2. 3. 4. The ADC in standby mode, that is, powered up but not converting, typically consumes 640 μA. The internal reference adds 140 μA. During conversion, the extra current is 0.3 μA, multiplied by the sampling frequency (in kHz). Select PADCxP and PADCxN in the ADCP and ADCCN registers. Optionally bypass the ADC input buffer in ADCCON[15:14]. Set the proper gain value for the PGA. Set the ADC to pseudo differential mode and start the conversion. Timing TYPICAL OPERATION Once configured via the ADC control and channel selection registers, the ADC converts the analog input and provides a 12-bit result in the ADCDAT register. The top four bits are the sign bits, and the 12-bit result is placed from Bit 16 to Bit 27, as shown in Figure 15. Note that in fully differential mode, the result is represented in twos complement format, and in pseudo differential and single-ended mode, the result is represented in straight binary format. SIGN BITS 27 16 15 12-BIT ADC RESULT ACQ BIT TRIAL WRITE ADC CLOCK 0 08755-015 31 Figure 16 gives details of the ADC timing. Users control the ADC clock speed and the number of acquisition clock in the ADCCON MMR. By default, the acquisition time is eight clocks and the clock divider is two. The number of extra clocks (such as bit trial or write) is set to 19, giving a sampling rate of 774 kSPS. For conversion on the temperature sensor, the ADC acquisition time is automatically set to 16 clocks and the ADC clock divider is set to 32. When using multiple channels, including the temperature sensor, the timing settings revert back to the userdefined settings after reading the temperature sensor channel. Figure 15. ADC Result Format CONVST ADCBUSY Calibration DATA ADCDAT For system offset error correction, the ADC channel input stage must be tied to AGND. A continuous software ADC conversion loop must be implemented by modifying the value in ADCOF until the ADC result (ADCDAT) reads Code 0 to Code 1. If the ADCDAT value is greater than 1, ADCOF should be decremented until ADCDAT reads Code 0 to Code 1. Offset error correction is performed digitally and has a resolution of 0.25 LSB and a range of ±3.125% of VREF. For system gain error correction, the ADC channel input stage must be tied to VREF. A continuous software ADC conversion loop must be implemented to modify the value in ADCGN until ADCDAT reads Code 4094 to Code 4095. If the ADCDAT value is less than 4094, ADCGN should be incremented until ADCDAT reads Code 4094 to Code 4095. Similar to the offset calibration, the gain calibration resolution is 0.25 LSB with a range of ±3% of VREF. Rev. A | Page 29 of 96 ADCSTA = 0 ADCSTA = 1 ADC INTERRUPT Figure 16. ADC Timing 08755-016 By default, the factory-set values written to the ADC offset (ADCOF) and gain coefficient registers (ADCGN) yield optimum performance in terms of end-point errors and linearity for standalone operation of the part (see the General Description section). If system calibration is required, it is possible to modify the default offset and gain coefficients to improve end-point errors, but note that any modification to the factory-set ADCOF and ADCGN values can degrade ADC linearity performance. ADuC7122 Data Sheet TEMPERATURE SENSOR ADC MMRs Interface The ADuC7122 provides a voltage output from an on-chip band gap reference proportional to absolute temperature. This voltage output can also be routed through the front-end ADC multiplexer (effectively, an additional ADC channel input), facilitating an internal temperature sensor channel that measures die temperature. The ADC is controlled and configured via a number of MMRs (see Table 27) that are described in detail in Table 28 to Table 34. 1200 ADCDAT (dB) The internal temperature sensor is not designed for use as an absolute ambient temperature calculator. It is intended for use as an approximate indicator of the temperature of the ADuC7122 die. 1250 The typical temperature coefficient is −1.25 mV/°C. 1150 1100 1000 –20 08755-017 1050 0 20 40 60 80 100 TEMPERATURE (°C) Figure 17. ADC Output vs. Temperature Table 27. ADC MMRs Name ADCCON ADCCP ADCCN ADCSTA ADCDAT ADCRST PGA_GN Description ADC control register. Allows the programmer to enable the ADC peripheral to select the mode of operation of the ADC (either single-ended, pseudo differential, or fully differential mode) and to select the conversion type (see Table 28). ADC positive channel selection register. ADC negative channel selection register. ADC status register. Indicates when an ADC conversion result is ready. The ADCSTA register contains only one bit, ADCREADY (Bit 0), representing the status of the ADC. This bit is set at the end of an ADC conversion generating an ADC interrupt. It is cleared automatically by reading the ADCDAT MMR. When the ADC is performing a conversion, the status of the ADC can be read externally via the ADCBusy pin. This pin is high during a conversion. When the conversion is finished, ADCBusy goes back low. This information is available on P0.2 (see the General-Purpose I/O section) if enabled in the GP0CON register. ADC data result register. Holds the 12-bit ADC result, as shown Table 32. ADC reset register. Resets all the ADC registers to their default value. Gain of PADC0 and PADC1. Rev. A | Page 30 of 96 Data Sheet ADuC7122 Table 28. ADCCON MMR Bit Designations (Address = 0xFFFF0500, Default Value = 0x00000A00) Bit 31:16 15 Value 000 Description These bits are reserved. Positive ADC buffer bypass. Set to 0 by the user to enable the positive ADC buffer. Set to 1 by the user to bypass the positive ADC buffer. Negative ADC buffer bypass. Set to 0 by the user to enable the negative ADC buffer. Set to 1 by the user to bypass the negative ADC buffer. ADC clock speed (fADC = fCORE, conversion = 19 ADC clocks + acquisition time). fADC/1. This divider is provided to obtain 1 MSPS ADC with an external clock <41.78 MHz. fADC/2 (default value). fADC/4. fADC/8. fADC/16. fADC/32. ADC acquisition time (number of ADC clocks). 2 clocks. 4 clocks. 8 clocks (default value). 16 clocks. 32 clocks. 64 clocks. Enable conversion. Set by user to 1 to enable conversion mode. Cleared by user to 0 to disable conversion mode. Reserved. This bit should be set to 0 by the user. ADC power control. Set by user to 1 to place the ADC in normal mode. The ADC must be powered up for at least 5 μs before it converts correctly. Cleared by user to 0 to place the ADC in power-down mode. Conversion mode. Single-ended mode. Differential mode. Pseudo differential mode. Reserved. Conversion type. Enable CONVST pin as a conversion input. 001 010 011 100 101 110 Other Enable Timer1 as a conversion input. Enable Timer0 as a conversion input. Single software conversion. Automatically set to 000 after conversion. Continuous software conversion. PLA conversion. Reserved Reserved. 0 1 14 0 1 13:11 000 001 010 011 100 101 10:8 000 001 010 011 100 101 7 1 0 6 5 1 0 4:3 00 01 10 11 2:0 E A Rev. A | Page 31 of 96 ADuC7122 Data Sheet Table 29. ADCCP MMR Bit Designations (Address = 0xFFFF0504, Default Value = 0x00) Table 30. ADCCN MMR Bit Designations (Address = 0xFFFF0508, Default Value = 0x00) Bit 7:5 4:0 Bit 7:5 4:0 Value 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 Others Description Reserved Positive channel selection bits PADC0P PADC1P ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 ADC7 ADC8 ADC9 ADC10/AINCM Temperature sensor Reserved Reserved Reserved Reserved Reserved IOVDD_MON Reserved Reserved VREF AGND Reserved Value 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 Others Description Reserved Negative channel selection bits PADC0N PADC1N ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 ADC7 ADC8 ADC9 ADC10/AINCM Reserved AGND Reserved IOGND Reserved Table 31. ADCSTA MMR Bit Designations (Address = 0xFFFF050C, Default Value = 0x00) Bit 0 Value 1 0 0 Description Indicates that an ADC conversion is complete. It is set automatically when an ADC conversion completes. Automatically cleared by reading the ADCDAT MMR. Table 32. ADCDAT MMR Bit Designations (Address = 0xFFFF0510, Default Value = 0x00000000) Bit 27:16 Value Description Holds the ADC result (see Figure 15). Table 33. ADCRST MMR Bit Designations (Address = 0xFFFF0514, Default Value = 0x00) Bit 0 Value 1 Description Set to 1 by the user to reset all the ADC registers to their default values. Table 34. PGA_GN MMR Bit Designations (Address = 0xFFFF0520, Default Value = 0x0000) Bit 15:12 11:6 5:0 Value Description Reserved. Set to 0. Gain of PGA for PADC0 (PGA_PADC0_GN) = 1 + 4 × (PGA_ADC0_GN/32) Gain of PGA for PADC1 (PGA_PADC1_GN) = 1 + 4 × (PGA_ADC1_GN/32) Note that PGA_PADC0_GN and PGA_PADC1_GN must be ≤32. Rev. A | Page 32 of 96 Data Sheet ADuC7122 CONVERTER OPERATION Pseudo Differential Mode The ADC incorporates a successive approximation (SAR) architecture involving a charge-sampled input stage. This architecture is described for the three different modes of operation: differential mode, pseudo differential mode, and single-ended mode. In pseudo differential mode, Channel− is linked to the VIN− input of the ADuC7122, and SW2 switches between A (Channel−) and B (VREF). The VIN− input must be connected to ground or a low voltage. The input signal on VIN+ can then vary from VIN− to VREF + VIN−. Note that VIN− must be selected so that VREF + VIN− does not exceed AVDD. In pseudo differential mode, only AINCM or PADCxN should be enabled for the VIN− channel. The ADCCN register is used to set Channel− to AINCM or PADCxN, and the Channel+ can be selected using the ADCCP register. The ADuC7122 contains a successive approximation ADC based on two capacitive DACs. Figure 18 and Figure 19 show simplified schematics of the ADC in acquisition and conversion phase, respectively. The ADC comprises control logic, a SAR, and two capacitive DACs. In Figure 18 (the acquisition phase), SW3 is closed and SW1 and SW2 are in Position A. The comparator is held in a balanced condition, and the sampling capacitor arrays acquire the differential signal on the input. CAPACITIVE DAC A SW1 MUX A ADC9 B CS CHANNEL– A SW2 CS SW3 CAPACITIVE DAC 08755-018 VREF Figure 18. ADC Acquisition Phase When the ADC starts a conversion (see Figure 19), SW3 opens and SW1 and SW2 move to Position B, causing the comparator to become unbalanced. Both inputs are disconnected when the conversion begins. The control logic and the charge redistribution DACs are used to add and subtract fixed amounts of charge from the sampling capacitor arrays to bring the comparator back into a balanced condition. When the comparator is rebalanced, the conversion is complete. The control logic generates the ADC output code. The output impedances of the sources driving the VIN+ and VIN− inputs must be matched; otherwise, the two inputs have different settling times, resulting in errors. The input channel configuration for differential mode is set using the ADCCP and ADCCN registers. CS CS SW3 ADC10 Figure 19. ADC Conversion Phase COMPARATOR CS SW3 CONTROL LOGIC CHANNEL– CAPACITIVE DAC Figure 21. ADC in Single-Ended Mode Analog Input Structure Figure 22 shows the equivalent circuit of the analog input structure of the ADC. The four diodes provide ESD protection for the analog inputs. Care must be taken to ensure that the analog input signals never exceed the supply rails by more than 300 mV. Voltage in excess of 300 mV can cause these diodes to become forward biased and start conducting into the substrate. These diodes can conduct up to 10 mA without causing irreversible damage to the part. CONTROL LOGIC CAPACITIVE DAC CS A SW1 B VREF B MUX 08755-019 ADC10 CHANNEL– A SW2 CHANNEL+ ADC0 COMPARATOR A SW1 MUX In single-ended mode, SW2 is always connected internally to ground. The VIN− input can be floating. The input signal range on VIN+ is 0 V to VREF. The ADuC7122 has 11 fixed gain ADC channels and two programmable gain ADC channels, which are enabled using the ADCCP register. CAPACITIVE DAC CAPACITIVE DAC B CAPACITIVE DAC CHANNEL– Single-Ended Mode B CHANNEL+ CONTROL LOGIC Figure 20. ADC in Pseudo Differential Mode CONTROL LOGIC ADC10 ADC0 SW3 VREF VIN– COMPARATOR A SW1 MUX CS 08755-021 CHANNEL+ ADC0 SW2 B PADCxP CAPACITIVE DAC COMPARATOR CS B CHANNEL+ ADC0 08755-020 Differential Mode The C1 capacitors in Figure 22 are typically 4 pF and can be primarily attributed to pin capacitance. The resistors are lumped components made up of the on resistance of the switches. The value of these resistors is typically about 100 Ω. The C2 capacitors are the ADC sampling capacitors and have a capacitance of 16 pF typical. Rev. A | Page 33 of 96 ADuC7122 Data Sheet AVDD D C1 DRIVING THE ANALOG INPUTS Internal or external reference can be used for the ADC. In differential mode of operation, there are restrictions on the common-mode input signal (VCM) that are dependent on reference value and supply voltage used to ensure that the signal remains within the supply rails. R1 C2 D AVDD D D Table 35. VCM Ranges 08755-022 C1 Table 35 gives some calculated VCM minimum and VCM maximum values under various AVDD and VREF conditions. R1 C2 Figure 22. Equivalent Analog Input Circuit Conversion Phase: Switches Open, Track Phase: Switches Closed For ac applications, removing high frequency components from the analog input signal is recommended through the use of an RC low-pass filter on the relevant analog input pins. In applications where harmonic distortion and signal-to-noise ratio are critical, the analog input should be driven from a low impedance source. Large source impedances significantly affect the ac performance of the ADC and can necessitate the use of an input buffer amplifier. The choice of the op amp is a function of the particular application. Figure 23 and Figure 24 give an example of an ADC front end. 08755-023 ADC0 0.01µF Figure 23. Buffering Single-Ended/Pseudo Differential Input VCM Min 1.25 V 1.024 V 0.75 V VCM Max 2.05 V 2.276 V 2.55 V Peak-to-Peak Signal 2.5 V 2.048 V 1.25 V 3.0 V 2.5 V 2.048 V 1.25 V 1.25 V 1.024 V 0.75 V 1.75 V 1.976 V 2.25 V 2.5 V 2.048 V 1.25 V BAND GAP REFERENCE The ADuC7122 provides an on-chip band gap reference of 2.5 V that can be used for the ADC and for the DAC. This 2.5 V reference is generated from a 1.2 V reference. The band gap reference also connects through buffers to the BUF_VREF1 and the BUF_VREF2 pins, which can be used as a reference for other circuits in the system. A minimum of 0.1 μF capacitor should be connected to these pins to damp noise. ADuC7122 ADC0 The band gap reference interface consists of an 8-bit REFCON MMR, described in Table 36. It is recommended to enable REFCON Bit 0 and Bit 1 when performing an ADC or DAC conversion that uses the internal reference. 08755-024 VREF ADC1 VREF 2.5 V 2.048 V 1.25 V This internal reference also appears on the VREF_1.2 and VREF_2.5 pins. When using the internal reference, a 470 nF capacitor must be connected between VREF_1.2 and AGND and a 470 nF capacitor between VREF_2.5 pin and AGND to ensure stability and fast response during ADC conversions. ADuC7122 10Ω AVDD 3.3 V Figure 24. Buffering Differential Inputs When no amplifier is used to drive the analog input, the source impedance should be limited to values lower than 1 kΩ. The maximum source impedance depends on the amount of total harmonic distortion (THD) that can be tolerated. The THD increases as the source impedance increases and the performance degrades. An external reference can be used for an ADC conversion. To perform an ADC conversion with an external 2.5 V reference, clear REFCON[1] and apply the external reference to the VREF_2.5 pin. To apply an external 1.2 V reference, clear REFCON[0] and apply the external reference to the VREF_1.2 pin. Note that when applying an external reference to the VREF_1.2 pin, this internally influences the 2.5 V reference as the 2.5 V reference is generated from the 1.2 V reference. Rev. A | Page 34 of 96 Data Sheet ADuC7122 POWER SUPPLY MONITOR The power supply monitor on the ADuC7122 indicates when the IOVDD supply pin drops below one of two supply trip points. The monitor function is controlled via the PSMCON register. If enabled in the IRQEN or FIQEN register, the monitor interrupts the core using the PSMI bit in the PSMCON MMR. This bit is cleared immediately when CMP goes high. Note that if the interrupt generated is exited before CMP goes high (IOVDD is above the trip point), no further interrupts are generated until CMP returns high. The user should ensure that code execution remains within the ISR until CMP returns high. This monitor function allows the user to save working registers to avoid possible data loss due to the low supply or brownout conditions. It also ensures that normal code execution does not resume until a safe supply level has been established. to convert the voltage available at the input of the power supply monitor comparator. When measuring an internal channel, the internal buffer must be enabled. The internal buffer should be enabled to isolate from external interference when sampling any of the internal channels. Before measuring this voltage, the following sequence is required: 1. 2. 3. 4. Measure VREF using the ADC. Set ADCCP = IOVDD_MON channel. Set a typical delay of 60 µs. Perform ADC conversion on the IOVDD_MON channel (use an ADCCON value of 0x2AA3 for optimum results). The delay between the ADC mux select switching and the initiation of the conversion is required to allow the voltage on the ADC sampling capacitor to settle to the divided down supply voltage. When the ADC channel selection bits are configured to IOVDD_MON (ADCCP[4:0] = 10011), this permits the ADC Table 36. REFCON MMR Bit Designations (Address = 0xFFFF0480, Default Value = 0x01) Bit 7:1 2 1 0 Description Reserved. Reserved. Always set to 1. This bit outputs the buffered version of the internal 2.5 V reference onto BUF_VREF1 and BUF_VREF2. To disable this buffer, the user must disable the internal reference by clearing REFCON = 0x00. Internal 2.5 V reference output enable. Set by the user to connect the internal 2.5 V reference to the VREF_2.5 pin. Cleared by the user to disconnect the reference from the VREF_2.5 pin. This pin should also be cleared to connect an external reference source to the VREF_2.5 pin. Internal 1.2 V reference output enable. Set by the user to connect the internal 1.2 V reference to the VREF_1.2 pin. Cleared by the user to disconnect the reference from the VREF_1.2 pin. Table 37. PSMCON MMR Bit Designations (Address = 0xFFFF0440, Default Value = 0x08 or 0x00 (Dependent on Device Supply Level) Bit 7:4 3 Name Reserved CMP 2 TP 1 PSMEN 0 PSMI Description Reserved bits. Clear to 0. Comparator bit. This is a read-only bit that directly reflects the state of the comparator. Read 1 indicates the IOVDD supply is above its selected trip point or the PSM is in power-down mode. Read 0 indicates the IOVDD supply is below its selected trip point. This bit should be set before leaving the interrupt service routine. Trip point selection bit. 0 = 2.79 V 1 = 3.07 V Power supply monitor enable bit. Set to 1 by the user to enable the power supply monitor circuit. Cleared to 0 by the user to disable the power supply monitor circuit. Power supply monitor interrupt bit. This bit is set high by the ADuC7122 if CMP is low, indicating low I/O supply. The PSMI bit can be used to interrupt the processor. When CMP returns high, the PSMI bit can be cleared by writing a 1 to this location. A write of 0 has no effect. There is no timeout delay. PSMI can be cleared immediately when CMP goes high. Rev. A | Page 35 of 96 ADuC7122 Data Sheet NONVOLATILE FLASH/EE MEMORY As indicated in the General Description section, the Flash/EE memory endurance qualification is carried out in accordance with JEDEC Retention Lifetime Specification A117 over the industrial temperature range of –10° to +95°C. The results allow the specification of a minimum endurance figure over a varying supply across the industrial temperature range for 10,000 cycles. FLASH/EE MEMORY OVERVIEW The ADuC7122 incorporates Flash/EE memory technology on-chip to provide the user with nonvolatile, in-circuit reprogrammable memory space. FLASH/EE MEMORY The ADuC7122 contains two 64 kB arrays of Flash/EE memory. In Flash Block 0, the bottom 62 kB are available to the user and the top 2 kB of this Flash/EE program memory array contain permanently embedded firmware, allowing in-circuit serial download. The 2 kB of embedded firmware also contain a power-on configuration routine that downloads factorycalibrated coefficients to the various calibrated peripherals (band gap references and so on). This 2 kB embedded firmware is hidden from user code. It is not possible for the user to read, write, or erase this page. In Flash Block 1, all 64 kB of Flash/EE memory are available to the user. 600 450 300 150 The 126 kB of Flash/EE memory can be programmed in-circuit, using the serial download mode or the JTAG mode provided. 0 08755-026 Overall, Flash/EE memory represents a step closer to the ideal memory device that includes no volatility, in-circuit programmability, high density, and low cost. Incorporated in the ADuC7122, Flash/EE memory technology allows the user to update program code space in-circuit, without the need to replace one-time programmable (OTP) devices at remote operating nodes. Retention quantifies the ability of the Flash/EE memory to retain its programmed data over time. The parts are qualified in accordance with the formal JEDEC Retention Lifetime Specification (A117) at a specific junction temperature (TJ = 85°C). As part of this qualification procedure, the Flash/EE memory is cycled to its specified endurance limit, described previously, before data retention is characterized. This means that the Flash/EE memory is guaranteed to retain its data for its fully specified retention lifetime every time the Flash/EE memory is reprogrammed. Note, too, that retention lifetime, based on activation energy of 0.6 eV, derates with TJ, as shown in Figure 25. RETENTION (Years) Like EEPROM, Flash memory can be programmed in-system at a byte level, although it must first be erased. The erase is performed in page blocks. As a result, Flash memory is often and more correctly referred to as Flash/EE memory. 30 40 55 Flash/EE Memory Reliability The Flash/EE memory arrays on the ADuC7122 is fully qualified for two key Flash/EE memory characteristics: Flash/EE memory cycling endurance and Flash/EE memory data retention. 85 100 125 135 150 Figure 25. Flash/EE Memory Data Retention Serial Downloading (In-Circuit Programming) Endurance quantifies the ability of the Flash/EE memory to be cycled through many program, read, and erase cycles. A single endurance cycle is composed of four independent, sequential events: 1. 2. 3. 4. 70 JUNCTION TEMPERATURE (°C) The ADuC7122 facilitates code download via the I2C serial port. The ADuC7122 enters serial download mode after a reset or power cycle if the BM pin is pulled low through an external 1 kΩ resistor. This is combined with the state of Address 0x00014 in Flash. If this address is 0xFFFFFFFF and the BM pin is pulled low, the part enters download mode; if this address contains any other value, user code is executed. When in serial download mode, the user can download code to the full 126 kB of Flash/EE memory while the device is in-circuit in its target application hardware. A PC executable serial download and hardware dongle are provided as part of the development system for serial downloads via the I2C port. The I2C maximum allowed baud rate is 100 kHz for the I2C downloader. E A E A Initial page erase sequence Read/verify a single Flash/EE sequence Byte program memory sequence Second read/verify endurance cycle sequence In reliability qualification, three separate page blocks from each Flash/EE memory block is tested. An entire Flash/EE page at the top, middle, and bottom of each Flash/EE memory block is cycled 10,000 times from 0x0000 to 0xFFFF. A JTAG Access 10B The JTAG protocol uses the on-chip JTAG interface to facilitate code download and debug. Rev. A | Page 36 of 96 Data Sheet ADuC7122 FLASH/EE MEMORY SECURITY The sequence to write the key is shown in the following example; this protects writing Page 4 to Page 7 of the Flash/EE memory: 48B The 126 kB of Flash/EE memory available to the user can be read and write protected. Bit 31 of the FEE0PRO/FEE0HID MMR protects the 62 kB of Block 0 from being read through JTAG or the serial downloader. The other 31 bits of this register protect writing to the Flash/EE memory; each bit protects four pages, that is, 2 kB. Write protection is activated for all access types. FEE1PRO and FEE1HID, similarly, protect Flash Block 1. Bit 31 of the FEE1PRO/FEE1HID MMR protects the 64 kB of Block 1 from being read through JTAG. Bit 30 protects writing to the top 8 pages of Block 1. The other 30 bits of this register protect writing to the Flash/EE memory; each bit protects four pages, that is, 2 kB. FEE0PRO=0xFFFFFFFD; FEE0MOD=0x48; FEE0ADR=0x1234; FEE0DAT=0x5678; FEE0CON= 0x0C; //Protect pages 4 to 7 //Write key enable //16 bit key value //16 bit key value // Write key command The same sequence should be followed to protect the part permanently with FEExADR = 0xDEAD and FEExDAT = 0xDEADDEAD. FLASH/EE CONTROL INTERFACE 49B Table 38. FEE0DAT Register Three Levels of Protection Name FEE0DAT Protection can be set and removed by writing directly into FEExHID MMR. This protection does not remain after reset. FEE0DAT is a 16-bit data register. 10B Protection can be set by writing into FEExPRO MMR. It takes effect only after a save protection command (0x0C) and a reset. The FEExPRO MMR is protected by a key to avoid direct access. The key is saved once and must be entered again to modify FEExPRO. A mass erase sets the key back to 0xFFFF but also erases all the user code. The Flash/EE memory can be permanently protected by using the FEExPRO MMR and a particular value of the 0xDEADDEAD key. Entering the key again to modify the FEExPRO register is not allowed. Sequence to Write the Key 102B 1. 2. 3. 4. 5. Write the bit in FEExPRO corresponding to the page to be protected. Enable key protection by setting Bit 6 of FEExMOD (Bit 5 must equal 0). Write a 32-bit key in FEExADR, FEExDAT. Run the write key command 0×0C in FEExCON; wait for the read to be successful by monitoring FEExSTA. Reset the part. To remove or modify the protection, the same sequence is used with a modified value of FEExPRO. If the key chosen is the value 0xDEADDEAD, then the memory protection cannot be removed. Only a mass erase unprotects the part; however, it also erases all user code. Address 0xFFFF0E0C Default Value 0xXXXX Access R/W Table 39. FEE0ADR Register Name FEE0ADR Address 0xFFFF0E10 Default Value 0x0000 Access R/W FEE0ADR is a 16-bit address register. Table 40. FEE0SGN Register Name FEE0SGN Address 0xFFFF0E18 Default Value 0xFFFFFF Access R FEE0SGN is a 24-bit code signature. Table 41. FEE0PRO Register Name FEE0PRO Address 0xFFFF0E1C Default Value 0x00000000 Access R/W FEE0PRO provides protection following a subsequent reset. It requires a software key (see Table 57). As stated previously, each bit from 30 to 0 of the FEExPRO register protects a 2 kB block of memory; that is, setting Bit 0 low protects Page 0 to Page 3, and setting Bit 2 low protects Page 8 to Page 11. Table 42. FEE0HID Register Name FEE0HID Address 0xFFFF0E20 Default Value 0xFFFFFFFF Access R/W FEE0HID provides immediate protection. It does not require any software keys (see Table 57). Command Sequence for Executing a Mass Erase 103B FEE0DAT = 0x3CFF; FEE0ADR = 0xFFC3; FEE0MOD = FEE0MOD|0x8; //Erase key enable FEE0CON = 0x06; //Mass erase command Rev. A | Page 37 of 96 ADuC7122 Data Sheet Table 43. FEE1DAT Register Name FEE1DAT Address 0xFFFF0E8C Default Value 0xXXXX Access R/W Table 44. FEE1ADR Register Address 0xFFFF0E90 Default Value 0x0000 Access R/W FEE1ADR is a 16-bit address register. Address 0xFFFF0E98 Address 0xFFFF0E00 Name FEE1STA Address 0xFFFF0E80 Default Value 0xFFFFFF Access R Name FEE0MOD Address 0xFFFF0E04 Table 51. FEE1MOD Register Table 46. FEE1PRO Register Name FEE1MOD Address 0xFFFF0E9C Default Value 0x00000000 Access R/W Address 0xFFFF0E84 Name FEE0CON Table 47. FEE1HID Register Table 53. FEE1CON Register Address 0xFFFF0EA0 Default Value 0x0000 Access R Default Value 0x80 Access R/W Default Value 0x80 Access R/W Default Value 0x0000 Access R/W Default Value 0x0000 Access R/W Table 52. FEE0CON Register FEE1PRO provides protection following a subsequent reset. It requires a software key (see Table 58). Name FEE1HID Access R Table 49. FEE1STA Register FEE1SGN is a 24-bit code signature. Name FEE1PRO Default Value 0x0000 Table 50. FEE0MOD Register Table 45. FEE1SGN Register Name FEE1SGN Table 48. FEE0STA Register Name FEE0STA FEE1DAT is a 16-bit data register. Name FEE1ADR FEE1HID provides immediate protection MMR. It does not require any software keys (see Table 58). Default Value 0xFFFFFFFF Access R/W Name FEE1CON Rev. A | Page 38 of 96 Address 0xFFFF0E08 Address 0xFFFF0E88 Data Sheet ADuC7122 Table 54. FEExSTA MMR Bit Designations Bit 15:6 5 4 3 Description Reserved. Reserved. Reserved. Flash/EE interrupt status bit. Set automatically when an interrupt occurs, that is, when a command is complete and the Flash/EE interrupt enable bit in the FEExMOD register is set. Cleared when reading the FEExSTA register. Flash/EE controller busy. Set automatically when the controller is busy. Cleared automatically when the controller is not busy. Command fail. Set automatically when a command completes unsuccessfully. Cleared automatically when reading the FEExSTA register. Command complete. Set by ADuC7122 when a command is complete. Cleared automatically when reading the FEExSTA register. 2 1 0 Table 55. FEExMOD MMR Bit Designations Bit 7:5 4 Description Reserved. Always set these bits to 0 except when writing Flash memory control keys. Flash/EE interrupt enable. Set by the user to enable the Flash/EE interrupt. The interrupt occurs when a command is complete. Cleared by user to disable the Flash/EE interrupt. Erase/write command protection. Set by the user to enable the erase and write commands. Cleared to protect the Flash/EE memory against erase/write command. Reserved. Should always be set to 0 by the user. Flash/EE wait states. Both Flash/EE blocks must have the same wait state value for any change to take effect. 3 2 1:0 Table 56. Command Codes in FEExCON Code 0x00 1 0x011 0x021 0x031 Command Null Single read Single write Erase/write 0x041 Single verify 0x051 0x061 Single erase Mass erase 0x07 0x08 0x09 0x0A 0x0B 0x0C Reserved Reserved Reserved Reserved Signature Protect 0x0D 0x0E 0x0F Reserved Reserved Ping 20F 1 Description Idle state. Load FEExDAT with the 16-bit data indexed by FEExADR. Write FEExDAT at the address pointed by FEExADR. This operation takes 50 µs. Erase the page indexed by FEExADR and write FEExDAT at the location pointed by FEExADR. This operation takes 20 ms. Compare the contents of the location pointed by FEExADR to the data in FEExDAT. The result of the comparison is returned in FEExSTA Bit 1. Erase the page indexed by FEExADR. Erase user space. The 2 kB of kernel are protected in Block 0. This operation takes 2.48 sec. To prevent accidental execution, a command sequence is required to execute this instruction. Reserved. Reserved. Reserved. Reserved. Gives a signature of the 64 kB of Flash/EE in the 24-bit FEExSIGN MMR. This operation takes 32,778 clock cycles. This command can be run only once. The value of FEExPRO is saved and can be removed only with a mass erase (0x06) or with the key. Reserved. Reserved. No operation, interrupt generated. The FEExCON register always reads 0x07 immediately after execution of any of these commands. Rev. A | Page 39 of 96 ADuC7122 Data Sheet Table 57. FEE0PRO and FEE0HID MMR Bit Designations Bit 31 30:0 Description Read protection. Cleared by the user to protect Block 0. Set by the user to allow reading of Block 0. Write protection for Page 123 to Page 0. Each bit protects a group of 4 pages. Cleared by the user to protect the pages when writing to flash. Thus preventing an accidental write to specific pages in flash Set by the user to allow writing the pages. Table 58. FEE1PRO and FEE1HID MMR Bit Designations Bit 31 30 29:0 Description Read protection. Cleared by the user to protect Block 1. Set by the user to allow reading of Block 1. Write protection for Page 127 to Page 120. Cleared by the user to protect the pages when writing to flash. Thus preventing an accidental write to specific pages in flash. Set by the user to allow writing the pages. Write protection for Page 119 to Page 0. Each bit protects a group of 4 pages. Cleared by the user to protect the pages when writing to flash. Thus preventing an accidental write to specific pages in flash Set by the user to allow writing the pages. EXECUTION TIME FROM SRAM AND FLASH/EE 50B This section describes SRAM and Flash/EE access times during execution of applications where execution time is critical. Execution from SRAM 104B Fetching instructions from SRAM takes one clock cycle because the access time of the SRAM is 2 ns and a clock cycle is 22 ns minimum. However, if the instruction involves reading or writing data to memory, one extra cycle must be added if the data is in SRAM (or three cycles if the data is in Flash/EE), one cycle to execute the instruction and two cycles to obtain the 32-bit data from Flash/EE. A control flow instruction, such as a branch instruction, takes one cycle to fetch, but it also takes two cycles to fill the pipeline with the new instructions. Execution from Flash/EE Timing is identical in both modes when executing instructions that involve using Flash/EE for data memory. If the instruction to be executed is a control flow instruction, an extra cycle is needed to decode the new address of the program counter and then four cycles are needed to fill the pipeline. A data processing instruction involving only core registers does not require any extra clock cycles, but if it involves data in Flash/EE, an extra clock cycle is needed to decode the address of the data and two cycles to obtain the 32-bit data from Flash/EE. An extra cycle must also be added before fetching another instruction. Data transfer instructions are more complex and are summarized in Table 59. Table 59. Execution Cycles in ARM/Thumb Mode Fetch Cycles 2/1 2/1 2/1 2/1 2/1 2/1 Dead Time 1 1 N 1 1 N Because the Flash/EE width is 16 bits and access time for 16-bit words is 23 ns, execution from Flash/EE cannot be completed in one cycle (contrary to a SRAM fetch, which can be completed in a single cycle when CD bits = 0). Dependent on the instruction, some dead times may be required before accessing data for any value of CD bits. In ARM mode, where instructions are 32 bits, two cycles are needed to fetch any instruction when CD = 0. In Thumb mode, where instructions are 16 bits, one cycle is needed to fetch any instruction. With 1 < N ≤ 16, N is the number of bytes of data to load or store in the multiple load/store instruction. The SWAP instruction combines an LD and STR instruction with only one fetch, giving a total of eight cycles plus 40 µs. Rev. A | Page 40 of 96 Data Access 2 1 2×N 2 × 20 µs 20 µs 2 × N × 20 µs Dead Time 1 1 N 1 1 N Instructions LD LDH LDM/PUSH STR STRH STRM/POP 105B Data Sheet ADuC7122 Remap Operation RESET AND REMAP 106B 51B When a reset occurs on the ADuC7122, execution starts automatically in factory-programmed internal configuration code. This kernel is hidden and cannot be accessed by user code. If the ADuC7122 is in normal mode (the BM pin is high), it executes the power-on configuration routine of the kernel and then jumps to the reset vector Address 0x00000000 to execute the reset exception routine of the user. Because the Flash/EE is mirrored at the bottom of the memory array at reset, the reset interrupt routine must always be written in Flash/EE. The ARM exception vectors are all situated at the bottom of the memory array, from Address 0x00000000 to Address 0x00000020, as shown in Figure 26. E 0xFFFFFFFF KERNEL A 0x0009F800 FLASH/EE INTERRUPT SERVICE ROUTINES 0x00080000 INTERRUPT SERVICE ROUTINES 0x00040000 The memory remap from Flash/EE is configured by setting Bit 0 of the REMAP register. Precautions must be taken to execute this command from Flash/EE, above Address 0x00080020, and not from the bottom of the array because this is replaced by the SRAM. 0x00041FFF SRAM 0x00000020 0x00000000 0x00000000 08755-027 MIRROR SPACE ARM EXCEPTION VECTOR ADDRESSES A Figure 26. Remap for Exception Execution By default and after any reset, the Flash/EE is mirrored at the bottom of the memory array. The remap function allows the programmer to mirror the SRAM at the bottom of the memory array, facilitating execution of exception routines from SRAM instead of from Flash/EE. This means exceptions are executed twice as fast, with the exception being executed in ARM mode (32 bits), and the SRAM being 32 bits wide instead of a 16-bit wide Flash/EE memory. This operation is reversible: the Flash/EE can be remapped at Address 0x00000000 by clearing Bit 0 of the REMAP MMR. Precaution must again be taken to execute the remap function from outside the mirrored area. Any kind of reset remaps the Flash/EE memory at the bottom of the array. Reset Operation 107B There are four types of reset: external reset, power-on reset, watchdog expiration, and software force reset. The RSTSTA register indicates the source of the last reset and RSTCLR clears the RSTSTA register. These registers can be used during a reset exception service routine to identify the source of the reset. If RSTSTA is null, the reset was external. Note that when clearing RSTSTA, all bits that are currently 1 must be cleared. Otherwise, a reset event occurs. The RSTCFG register allows different peripherals to retain their state after a watchdog or software reset. Table 60. REMAP MMR Bit Designations (Address = 0xFFFF0220, Default Value = 0x00) Bit 0 Name Remap Description Remap bit. Set by the user to remap the SRAM to Address 0x00000000. Cleared automatically after reset to remap the Flash/EE memory to Address 0x00000000. Table 61. RSTSTA MMR Bit Designations (Address = 0xFFFF0230, Default Value = 0x0X) Bit 7:3 2 1 0 Description Reserved. Software reset. Set by the user to force a software reset. Cleared by setting the corresponding bit in RSTCLR. Watchdog timeout. Set automatically when a watchdog timeout occurs. Cleared by setting the corresponding bit in RSTCLR. Power-on reset. Set automatically when a power-on reset occurs. Cleared by setting the corresponding bit in RSTCLR. Rev. A | Page 41 of 96 ADuC7122 Data Sheet RSTCFG Register RSTKEY1 Register 108B 109B Name: RSTCFG Name: RSTKEY1 Address: 0xFFFF024C Address: 0xFFFF0248 Default value: 0x00 Default Value: N/A Access: Read/write Access Write RSTKEY2 Register Table 62. RSTCFG MMR Bit Designations Bit 7 to 3 2 1 0 10B Description Reserved. Always set to 0. This bit is set to 1 to configure the DAC outputs to retain their state after a watchdog or software reset. This bit is cleared for the DAC pins and registers to return to their default state. Reserved. Always set to 0. This bit is set to 1 to configure the GPIO pins to retain their state after a watchdog or software reset. This bit is cleared for the GPIO pins and registers to return to their default state. Name: RSTKEY2 Address: 0xFFFF0250 Default Value: N/A Access: Write Table 63. RSTCFG Write Sequence Name RSTKEY1 RSTCFG RSTKEY2 Rev. A | Page 42 of 96 Code 0x76 User value 0xB1 Data Sheet ADuC7122 OTHER ANALOG PERIPHERALS 9B MMRs Interface DAC 1B 52B Each DAC is independently configurable through a control register and a data register. These two registers are identical for the 12 DACs. DACxCON and DACxDAT (see Table 64 to Table 67) are described in detail in this section. The ADuC7122 incorporates 12 buffered, 12-bit voltage output string DACs on chip. Each DAC has a rail-to-rail voltage output buffer capable of driving 5 kΩ/100 pF. Each DAC has two selectable ranges: 0 V to VREF (internal band gap 2.5 V reference) and 0 V to AVDD. The maximum signal range is 0 V to AVDD. AVDD AVDD VREF VREF DAC_REBUF DAC_REBUF SW_A0 SW_A12 SW_B0 SW_B11 STRING DAC STRING DAC SW_C0 SW_C11 SW_D0 SW_D11 DAC0 DAC11 DAC_BUF 08755-028 DAC_BUF Figure 27. DAC Configuration SW_B HCLK 12 DATA_REG SW_C STRING DAC TIMER1 DACx 08755-029 DAC_BUF Figure 28. DAC User Functionality Table 64. DACxCON Registers Name DAC0CON DAC1CON DAC2CON DAC3CON DAC4CON DAC5CON DAC6CON DAC7CON DAC8CON DAC9CON DAC10CON DAC11CON Address 0xFFFF0580 0xFFFF0588 0xFFFF0590 0xFFFF0598 0xFFFF05A0 0xFFFF05A8 0xFFFF05B0 0xFFFF05B8 0xFFFF05C0 0xFFFF05C8 0xFFFF05D0 0xFFFF05D8 Default Value 0x100 0x100 0x100 0x100 0x100 0x100 0x100 0x100 0x100 0x100 0x100 0x100 Rev. A | Page 43 of 96 Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W ADuC7122 Data Sheet Table 65. DACxCON MMR Bit Designations Bit 15:9 8 Value 0 1 Name 7 6 0 0 BYP 5 0 DACCLK 4 0 DACCLR 3 2 1:0 0 0 DACPD DACRNx 00 01 10 11 Description Reserved. DAC power-down. Set by user to set DACOUTx to tri-state mode. Reserved. DAC bypass bit. Set this bit to bypass the DAC buffer. Cleared to buffer the DAC output. DAC update rate. Set by the user to update the DAC using Timer1. Cleared by the user to update the DAC using HCLK (core clock). DAC clear bit. Set by the user to enable normal DAC operation. Cleared by the user to reset data register of the DAC to 0. Reserved. Reserved. Always clear to 0. DAC range bits. VREF/AGND. Reserved. Reserved. AVDD/AGND. Table 66. DACxDAT Registers Name DAC0DAT DAC1DAT DAC2DAT DAC3DAT DAC4DAT DAC5DAT DAC6DAT DAC7DAT DAC8DAT DAC9DAT DAC10DAT DAC11DAT Address 0xFFFF0584 0xFFFF058C 0xFFFF0594 0xFFFF059C 0xFFFF05A4 0xFFFF05AC 0xFFFF05B4 0xFFFF05BC 0xFFFF05C4 0xFFFF05CC 0xFFFF05D4 0xFFFF05DC Default Value 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 Table 67. DACxDAT MMR Bit Designations Bit 31:28 27:16 15:12 11:0 Description Reserved. 12-bit data for DACx. Reserved. Reserved. Rev. A | Page 44 of 96 Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Data Sheet ADuC7122 Using the DACs AVDD The on-chip DAC architecture consists of a resistor string DAC followed by an output buffer amplifier. The functional equivalent is shown in Figure 29. AVDD – 100mV AVDD VREF R R 0x00000000 0x0FFF0000 08755-031 100mV DAC0 R Figure 30. Endpoint Nonlinearities Due to Amplifier Saturation R 08755-030 R Figure 29. DAC Structure As illustrated in Figure 29, the reference source for each DAC is user-selectable in software. It can be either AVDD or VREF. In 0 Vto-AVDD mode, the DAC output transfer function spans from 0 V to the voltage at the AVDD pin. In 0 V-to-VREF mode, the DAC output transfer function spans from 0 V to the internal 2.5 V reference, VREF. The DAC output buffer amplifier features a true, rail-to-rail output stage implementation. This means that when unloaded, each output is capable of swinging to within less than 5 mV of both AVDD and ground. Moreover, the DAC linearity specification (when driving a 5 kΩ resistive load to ground) is guaranteed through the full transfer function except Code 0 to Code 100, and, in 0 V-to-AVDD mode only, Code 3995 to Code 4095. Linearity degradation near ground and AVDD is caused by saturation of the output amplifier, and a general representation of its effects (neglecting offset and gain error) is illustrated in Figure 30. The dotted line in Figure 30 indicates the ideal transfer function, and the solid line represents what the transfer function may look like with endpoint nonlinearities due to saturation of the output amplifier. Note that Figure 30 represents a transfer function in 0-to-AVDD mode only. In 0 V-to-VREF mode (with VREF < AVDD), the lower nonlinearity is similar. However, the upper portion of the transfer function follows the ideal line right to the end (VREF in this case, not AVDD), showing no signs of endpoint linearity errors. The endpoint nonlinearities conceptually illustrated in Figure 30 become worse as a function of output loading. The ADuC7122 data sheet specifications assume a 5 kΩ resistive load to ground at the DAC output. As the output is forced to source or sink more current, the nonlinear regions at the top or bottom (respectively) of Figure 30 become larger. With larger current demands, this can significantly limit output voltage swing. The DAC can be configured to retain its output voltage after a watchdog or software reset by writing to the RSTCFG register. LDO (LOW DROPOUT REGULATOR) The ADuC7122 contains an integrated LDO that generates the core supply voltage (LVDD) of approximately 2.6 V from the IOVDD supply. Because the LDO is driven from IOVDD, the IOVDD supply voltage needs to be greater than 2.7 V. An external compensation capacitor (CT) of 0.47 μF with low equivalent series resistance (ESR) must be placed very close to the LVDD pin. This capacitor also acts as a storage of charge and supplies an instantaneous charge required by the core, particularly at the positive edge of the core clock (HCLK). The LVDD voltage generated by the LDO is solely for providing a supply for the ADuC7122. Therefore, users should not use the LVDD pin as the power supply pin for any other chip. Also, the IOVDD pin should have excellent power supply decoupling to help improve line regulation performance of the LDO. The LVDD pin has no reverse battery, current limit, or thermal shutdown protection; therefore, it is essential that users of the ADuC7122 do not short this pin to ground at anytime during normal operation or during board manufacture. Rev. A | Page 45 of 96 ADuC7122 Data Sheet OSCILLATOR AND PLL—POWER CONTROL 10B Example Source Code The ADuC7122 integrates a 32.768 kHz oscillator, a clock divider, and a PLL. The PLL locks onto a multiple (1275) of the internal oscillator to provide a stable 41.78 MHz clock for the system. The core can operate at this frequency or at binary submultiples of it to allow power saving. The default core clock is the PLL clock divided by 8 (CD = 3) or 5.2 MHz. The core clock frequency can be output on the ECLK pin as described in Figure 31. Note that when the ECLK pin is used to output the core clock, the output signal is not buffered and is not suitable for use as a clock source to an external device without an external buffer. 13B T2LD = 5; T2CON = 0x480; while ((T2VAL == t2val_old) || (T2VAL > 3)) //ensures timer value loaded IRQEN = 0x10; //enable T2 interrupt A power-down mode is available on the ADuC7122. PLLKEY1 = 0xAA; PLLCON = 0x01; PLLKEY2 = 0x55; POWKEY1 = 0x01; POWCON = 0x27; // Set Core into Nap mode POWKEY2 = 0xF4; The operating mode, clocking mode, and programmable clock divider are controlled via two MMRs, PLLCON (see Table 75) and POWCON (see Table 76). PLLCON controls the operating mode of the clock system, and POWCON controls the core clock frequency and the power-down mode. WATCHDOG TIMER INT. 32kHz1 OSCILLATOR XTALO In noisy environments, noise can couple to the external crystal pins, and PLL may lose lock momentarily. A PLL interrupt is provided in the interrupt controller. The core clock is immediately halted, and this interrupt is serviced only when the lock is restored. CRYSTAL OSCILLATOR XTALI In case of crystal loss, the watchdog timer should be used. During initialization, a test on the RSTSTA can determine if the reset came from the watchdog timer. TIMERS AT POWER-UP EXTERNAL CLOCK SELECTION OCLK 32.768kHz PLL 5B 41.78MHz To switch to an external clock on P1.4, configure P1.4 in Mode 2. The external clock can be up to 41.78 MHz, providing the tolerance is 1%. XCLK2 MDCLK UCLK I2C ANALOG PERIPHERALS Example Source Code 14B CD T2LD = 5; TCON = 0x480; HCLK ECLK3 NOTES 1. 32.768kHz ± 3%. 2. TO USE THE SECONDARY FUNCTION OF P1.4 AS XCLK, PLLCON BITS[1:0] MUST EQUAL 11. 3. WHEN THE SECONDARY FUNCTION FOR P1.4 IS SET TO 2 (THAT IS, GP1CON[17:16] = 10), THE ECLK FUNCTION IS SELECTED BY DEFAULT. while ((T2VAL == t2val_old) || (T2VAL > 3)) //ensures timer value loaded IRQEN = 0x10; //enable T2 interrupt 08755-032 CORE /2CD Figure 31. Clocking System EXTERNAL CRYSTAL SELECTION POWKEY1 = 0x01; POWCON = 0x27; // Set Core into Nap mode POWKEY2 = 0xF4; 54B To switch to an external crystal, use the following procedure: 1. 2. 3. 4. PLLKEY1 = 0xAA; PLLCON = 0x03; //Select external clock PLLKEY2 = 0x55; Enable the Timer2 interrupt and configure it for a timeout period of >120 µs. Follow the write sequence to the PLLCON register, setting the MDCLK bits to 01 and clearing the OSEL bit. Force the part into nap mode by following the correct write sequence to the POWCON register. When the part is interrupted from nap mode by the Timer2 interrupt source, the clock source has switched to the external clock. Rev. A | Page 46 of 96 Data Sheet ADuC7122 POWER CONTROL SYSTEM 56B A choice of operating modes is available on the ADuC7122. Table 68 describes which blocks of the ADuC7122 are powered on in the different modes and indicates the power-up time. Table 69 gives some typical values of the total current consumption (analog and digital supply currents) in the different modes, depending on the clock divider bits when the ADC is turned off. Note that these values also include current consumption of the regulator and other parts on the test board on which these values were measured. Table 68. Operating Modes Mode Active Pause Nap Sleep Stop Core On Peripherals On On PLL On On On XTAL/Timer2/Timer3 On On On On XIRQ On On On On On Start-Up/Power-On Time 130 ms at CD = 0 24 ns at CD = 0; 3.06 µs at CD = 7 24 ns at CD = 0; 3.06 µs at CD = 7 1.58 ms 1.7 ms Table 69. Typical Current Consumption at 25°C PC[2:0] 000 001 010 011 100 Mode Active Pause Nap Sleep Stop CD = 0 30 22.7 3.8 0.25 0.25 CD = 1 21.2 13.3 3.8 0.25 0.25 CD = 2 13.8 8.5 3.8 0.25 0.25 CD = 3 11 6.1 3.8 0.25 0.25 Rev. A | Page 47 of 96 CD = 4 8.1 4.9 3.8 0.25 0.25 CD = 5 7.2 4.3 3.8 0.25 0.25 CD = 6 6.7 4 3.8 0.25 0.25 CD = 7 6.45 3.85 3.8 0.25 0.25 ADuC7122 Data Sheet MMRS AND KEYS 57B To prevent accidental programming, a certain sequence must be followed when writing in the PLLCON and POWCON registers (see Table 74). Table 75. PLLCON MMR Bit Designations Bit 7:6 5 Address 0xFFFF0410 0xFFFF0418 Default Value 0x0000 0x0000 Access W W Address 0xFFFF0414 Default Value 0x21 4:2 1:0 Address 0xFFFF0404 0xFFFF040C Address 0xFFFF0408 Default Value 0x0000 0x0000 Access W W Default Value 0x03 Access R/W Table 74. PLLCON and POWCON Write Sequence PLLCON PLLKEY1 = 0xAA PLLCON = 0x01 PLLKEY2 = 0x55 Description Reserved. 32 kHz PLL input selection. Set by the user to use the internal 32 kHz oscillator. Set by default. Cleared by the user to use the external 32 kHz crystal. Reserved. Clocking modes. Reserved. PLL. default configuration. Reserved. External clock on P1.4 pin. Table 76. POWCON MMR Bit Designations Bit 7 6:4 POWCON POWKEY1 = 0x01 POWCON = user value POWKEY2 = 0xF4 Value Name PC 000 001 010 011 Table 73. POWCON Register Name POWCON MDCLK 00 01 10 11 Access R/W Table 72. POWKEYx Register Name POWKEY1 POWKEY2 OSEL 0 Table 71. PLLCON Register Name PLLCON Name 1 Table 70. PLLKEYx Register Name PLLKEY1 PLLKEY2 Value 100 Others 3 2:0 RSVD CD 000 001 010 011 100 101 110 111 Rev. A | Page 48 of 96 Description Reserved. Operating modes. Active mode. Pause mode. Nap. Sleep mode. IRQ0 to IRQ3 and Timer2 can wake up the ADuC7122. Stop mode. Reserved. Reserved. CPU clock divider bits. 41.779200 MHz. 20.889600 MHz. 10.444800 MHz. 5.222400 MHz. 2.611200 MHz. 1.305600 MHz. 654.800 kHz. 326.400 kHz. Data Sheet ADuC7122 DIGITAL PERIPHERALS PWM GENERAL OVERVIEW HIGH SIDE (PWM1) The ADuC7122 integrates a 6-channel PWM interface. The PWM outputs can be configured to drive an H-bridge or can be used as standard PWM outputs. On power-up, the PWM outputs default to H-bridge mode. This ensures that the H-bridge controlled motor is turned off by default. In standard PWM mode, the outputs are arranged as three pairs of PWM pins. Users have control over the period of each pair of outputs and over the duty cycle of each individual output. LOW SIDE (PWM2) PWM1COM3 PWM1COM2 Table 77. PWM MMRs Function PWM control Compare Register 1 for PWM Output 1 and Output 2 Compare Register 2 for PWM Output 1 and Output 2 Compare Register 3 for PWM Output 1 and Output 2 Frequency control for PWM Output 1 and Output 2 Compare Register 1 for PWM Output 3 and Output 4 Compare Register 2 for PWM Output 3 and Output 4 Compare Register 3 for PWM Output 3 and Output 4 Frequency control for PWM Output 3 and Output 4 Compare Register 1 for PWM Output 5 and Output 6 Compare Register 2 for PWM Output 5 and Output 6 Compare Register 3 for PWM Output 5 and Output 6 Frequency control for PWM Output 5 and Output 6 PWM convert start control PWM interrupt clear In all modes, the PWMxCOMx MMRs control the point at which the PWM outputs change state. An example of the first pair of PWM outputs (PWM1 and PWM2) is shown in Figure 32. 08755-033 Name PWMCON1 PWM1COM1 PWM1COM2 PWM1COM3 PWM1LEN PWM2COM1 PWM2COM2 PWM2COM3 PWM2LEN PWM3COM1 PWM3COM2 PWM3COM3 PWM3LEN PWMCON2 PWMICLR PWM1COM1 PWM1LEN Figure 32. PWM Timing The PWM clock is selectable via PWMCON1 with UCLK divided by one of the following values: 2, 4, 8, 16, 32, 64, 128, or 256. The length of a PWM period is defined by PWMxLEN. The PWM waveforms are set by the count value of the 16-bit timer and the compare registers contents, as shown in the PWM1 and PWM2 waveforms in Figure 32. The low-side waveform, PWM2, goes high when the timer count reaches PWM1LEN, and it goes low when the timer count reaches the value held in PWM1COM3 or when the high-side waveform PWM1 goes low. The high-side waveform, PWM1, goes high when the timer count reaches the value held in PWM1COM1, and it goes low when the timer count reaches the value held in PWM1COM2. In H-bridge mode, HMODE = 1 and Table 78 determine the PWM outputs. Table 78. PWMCON1 MMR Bit Designations (Address = 0xFFFF0F80, Default Value = 0x0012) Bit 15 14 Name Reserved SYNC 13 PWM6INV 12 PWM4NV 11 PWM2INV 10 PWMTRIP 9 ENA Description This bit is reserved. Enables PWM synchronization. Set to 1 by the user so that all PWM counters are reset on the next clock edge after the detection of a high-to-low transition on the SYNC pin. Cleared by the user to ignore transitions on the SYNC pin. Set to 1 by the user to invert PWM6. Cleared by the user to use PWM6 in normal mode. Set to 1 by the user to invert PWM4. Cleared by the user to use PWM4 in normal mode. Set to 1 by the user to invert PWM2. Cleared by the user to use PWM2 in normal mode. Set to 1 by the user to enable PWM trip interrupt. When the PWMTRIP input is low, the PWMEN bit is cleared and an interrupt is generated. Cleared by the user to disable the PWMTRIP interrupt. If HOFF = 0 and HMODE = 1. Set to 1 by the user to enable PWM outputs. Cleared by the user to disable PWM outputs. If HOFF = 1 and HMODE = 1, see Table 79. If not in H-Bridge mode, this bit has no effect. Rev. A | Page 49 of 96 ADuC7122 Bit 8:6 Name PWMCP[2:0] 5 POINV 4 HOFF 3 LCOMP 2 DIR 1 HMODE 0 PWMEN Data Sheet Description PWM clock prescaler bits. Sets the UCLK divider. 000 = UCLK/2. 001 = UCLK/4. 010 = UCLK/8. 011 = UCLK/16. 100 = UCLK/32. 101 = UCLK/64. 110 = UCLK/128. 111 = UCLK/256. Set to 1 by the user to invert all PWM outputs. Cleared by the user to use PWM outputs as normal. High-side off. Set to 1 by the user to force PWM1 and PWM3 outputs high. This also forces PWM2 and PWM4 low. Cleared by the user to use the PWM outputs as normal. Load compare registers. Set to 1 by the user to load the internal compare registers with the values in PWMxCOMx on the next transition of the PWM timer from 0x00 to 0x01. Cleared by the user to use the values previously stored in the internal compare registers. Direction control. Set to 1 by the user to enable PWM1 and PWM2 as the output signals while PWM3 and PWM4 are held low. Cleared by the user to enable PWM3 and PWM4 as the output signals while PWM1 and PWM2 are held low. Enables H-bridge mode. Set to 1 by the user to enable H-Bridge mode and Bit 1 to Bit 5 of PWMCON1. Cleared by the user to operate the PWMs in standard mode. Set to 1 by the user to enable all PWM outputs. Cleared by the user to disable all PWM outputs. Rev. A | Page 50 of 96 Data Sheet ADuC7122 Table 79. PWM Output Selection1 1 DIR X X 0 1 0 1 PWM1 1 1 0 HS HS 1 PWM Outputs PWM2 PWM3 1 1 0 1 0 HS LS 0 LS 1 1 HS PWM4 1 0 LS 0 1 LS Table 81. PWMCON2 MMR Bit Designations (Address = 0xFFFF0FB4, Default Value = 0x00) Bit 7 Value Name CSEN 1 0 3:0 CSD3 X = don’t care, HS = high side, LS = low side. 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 On power-up, PWMCON1 defaults to 0x12 (HOFF = 1 and HMODE = 1). All GPIO pins associated with the PWM are configured in PWM mode by default (see Table 80). Table 80. Compare Registers Name PWM1COM1 PWM1COM2 PWM1COM3 PWM2COM1 PWM2COM2 PWM2COM3 PWM3COM1 PWM3COM2 PWM3COM3 Address 0xFFFF0F84 0xFFFF0F88 0xFFFF0F8C 0xFFFF0F94 0xFFFF0F98 0xFFFF0F9C 0xFFFF0FA4 0xFFFF0FA8 0xFFFF0FAC Default Value 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 Access R/W R/W R/W R/W R/W R/W R/W R/W R/W The PWM trip interrupt can be cleared by writing any value to the PWMICLR MMR. Note that when using the PWM trip interrupt, users should make sure that the PWM interrupt has been cleared before exiting the ISR. This prevents generation of multiple interrupts. PWM CONVERT START CONTROL 59B The PWM can be configured to generate an ADC convert start signal after the active low-side signal goes high. There is a programmable delay between when the low-side signal goes high and the convert start signal is generated. Description Convert start enable. Set to 1 by the user to enable the PWM to generate a convert start signal. Cleared by the user to disable the PWM convert start signal. Convert start delay. Delays the convert start signal by a number of clock pulses. 4 clock pulses. 8 clock pulses. 12 clock pulses. 16 clock pulses. 20 clock pulses. 24 clock pulses. 28 clock pulses. 32 clock pulses. 36 clock pulses. 40 clock pulses. 44 clock pulses. 48 clock pulses. 52 clock pulses. 56 clock pulses. 60 clock pulses. 64 clock pulses. When calculating the time from the convert start delay to the start of an ADC conversion, the user needs to take account of internal delays. The example in Figure 33 shows the case for a delay of four clocks. One additional clock is required to pass the convert start signal to the ADC logic. When the ADC logic receives the convert start signal, an ADC conversion begins on the next ADC clock edge (see Figure 33). UCLK/ADC_CLOCK This is controlled via the PWMCON2 MMR. If the delay selected is higher than the width of the PWM pulse, the interrupt remains low. LOW SIDE COUNT PWM SIGNAL TO CONVST 08755-034 PWMCON1 MMR ENA HOFF POINV 0 0 X X 1 X 1 0 0 1 0 0 1 0 1 1 0 1 SIGNAL PASSED TO ADC LOGIC Figure 33. ADC Conversion Rev. A | Page 51 of 96 ADuC7122 Data Sheet GENERAL-PURPOSE I/O 12B The ADuC7122 provides 32 general-purpose, bidirectional I/O (GPIO) pins. All I/O pins are 5 V tolerant, meaning that the GPIOs support an input voltage of 5 V. In general, many of the GPIO pins have multiple functions (see Table 84). By default, the GPIO pins are configured in GPIO mode. Table 84. GPIO Pin Function Designations1 Port 0 All GPIO pins have an internal pull-up resistor (of about 100 kΩ), and their drive capability is 1.6 mA. Note that a maximum of 20 GPIOs can drive 1.6 mA at the same time. The 32 GPIOs are grouped in four ports: Port 0 to Port 3. Each port is controlled by four or five MMRs, with x representing the port number. Table 82. GPxCON Register Name GP0CON GP1CON GP2CON GP3CON Address 0xFFFF0D00 0xFFFF0D04 0xFFFF0D08 0xFFFF0D0C Default Value 0x00000000 0x00000000 0x00000000 0x11111111 Access R/W R/W R/W R/W The input level of any GPIO can be read at any time in the GPxDAT MMR, even when the pin is configured in a mode other than GPIO. The PLA input is always active. 12 2 When the ADuC7122 parts enter a power-saving mode, the GPIO pins retain their state. GPxCON is the Port x control register, and it selects the function of each pin of Port x, as described in Table 84. Table 83. GPxCON MMR Bit Designations Bit 31:30 29:28 27:26 25:24 23:22 21:20 19:18 17:16 15:14 13:12 11:10 9:8 7:6 5:4 3:2 1:0 Description Reserved Select function of Px.7 pin Reserved Select function of Px.6 pin Reserved Select function of Px.5 pin Reserved Select function of Px.4 pin Reserved Select function of Px.3 pin Reserved Select function of Px.2 pin Reserved Select function of Px.1 pin Reserved Select function of Px.0 pin 3 Pin P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0 P1.1 P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7/BM E A 1 2 Configuration (see GPxCON) 00 01 10 11 GPIO SCL1 N/A PLAI[5] GPIO SDA1 PLAI[4] N/A GPIO SPICLK ADCBUSY PLAO[13] GPIO SPIMISO SYNC PLAO[12] GPIO SPIMOSI TRIP PLAI[11] GPIO PLAI[10] CONVST SPICS GPIO N/A PLAI[2] MRST GPIO TRST N/A PLAI[3] GPIO SIN SCL2 PLAI[7] GPIO SOUT SDA2 PLAI[6] GPIO PWM1 ECLK/XCLK PLAI[8] GPIO PWM2 N/A PLAI[9] GPIO N/A N/A PLAO[5] GPIO N/A N/A PLAO[4] GPIO/IRQ0 N/A N/A PLAI[13] GPIO/IRQ1 N/A N/A PLAI[12] GPIO N/A N/A PLAI[1] GPIO/IRQ2 N/A N/A PLAI[14] GPIO PWM5 N/A PLAO[7] GPIO PWM6 N/A PLAO[6] GPIO/IRQ3 N/A N/A PLAI[15] GPIO N/A N/A PLAI[0] GPIO N/A N/A PLAO[0] GPIO N/A N/A PLAO[1] GPIO/IRQ4 PWM3 N/A PLAO[2] GPIO/IRQ5 PWM4 N/A PLAO[3] GPIO N/A N/A PLAO[8] GPIO N/A N/A PLAO[9] GPIO N/A N/A PLAO[10] GPIO N/A N/A PLAO[11] E A A N/A means no secondary function exists. Never attempt a write to P1.2 or P1.3. Rev. A | Page 52 of 96 E A E Data Sheet ADuC7122 Table 85. GPxPAR Register Name GP0PAR GP1PAR GP2PAR GP3PAR Address 0xFFFF0D2C 0xFFFF0D3C 0xFFFF0D4C 0xFFFF0D5C Table 90. GPxSET MMR Bit Designations Default Value 0x20000000 0x00000000 0x00000000 0x00222222 Access R/W R/W R/W R/W Bit 31: 24 23:16 Description Reserved. Data Port x set bit. Set to 1 by the user to set bit on Port x; also sets the corresponding bit in the GPxDAT MMR. Cleared to 0 by the user; does not affect the data output. Reserved. GPxPAR programs the parameters for Port 0, Port 1, Port 2, and Port 3. Note that the GPxDAT MMR must always be written after changing the GPxPAR MMR. 15: 0 Table 86. GPxPAR MMR Bit Designations Table 91. GPxCLR Register Bit 31:29 28 27:25 24 23:21 20 19:17 16 15:13 12 11:9 8 7:5 4 3:1 0 Name GP0CLR GP1CLR GP2CLR GP3CLR Description Reserved Pull-up disable Px.7 pin Reserved Pull-up disable Px.6 pin Reserved Pull-up disable Px.5 pin Reserved Pull-up disable Px.4 pin Reserved Pull-up disable Px.3 pin Reserved Pull-up disable Px.2 pin Reserved Pull-up disable Px.1 pin Reserved Pull-up disable Px.0 pin Address 0xFFFF0D20 0xFFFF0D30 0xFFFF0D40 0xFFFF0D50 Default Value 0x000000XX 0x000000XX 0x000000XX 0x000000XX Bit 31:24 23:16 15:0 Access R/W R/W R/W R/W Description Direction of the data. Set to 1 by the user to configure the GPIO pin as an output. Cleared to 0 by user to configure the GPIO pin as an input. Port x data output. Reflect the state of Port x pins at reset (read only). Port x data input (read only). Address 0xFFFF0D24 0xFFFF0D34 0xFFFF0D44 0xFFFF0D54 Default Value 0x000000XX 0x000000XX 0x000000XX 0x000000XX Description Reserved. Data Port x clear bit. Set to 1 by the user to clear bit on Port x; also clears the corresponding bit in the GPxDAT MMR. Cleared to 0 by the user; does not affect the data output. Reserved. Table 93. GPxOCE MMR Bit Designations Bit 31:8 7 6 5 4 3 2 Table 89. GPxSET Register Name GP0SET GP1SET GP2SET GP3SET Access W W W W Open-collector functionality is available on the following GPIO pins: P1.7, P1.6, P2.x, and P3.x. Open-collector functionality can be configured using GP1OCE[7:6], GP2OCE[7:0], and GP3OCE[7:0]. Table 88. GPxDAT MMR Bit Designations 23:16 15:8 7:0 Default Value 0x000000XX 0x000000XX 0x000000XX 0x000000XX Table 92. GPxCLR MMR Bit Designations GPxDAT is a Port x configuration and data register. It configures the direction of the GPIO pins of Port x, sets the output value for the pins configured as outputs, and receives and stores the input value of the pins configured as inputs. Bit 31:24 Address 0xFFFF0D28 0xFFFF0D38 0xFFFF0D48 0xFFFF0D58 GPxCLR is a data clear Port x register. Table 87. GPxDAT Register Name GP0DAT GP1DAT GP2DAT GP3DAT GPxSET is a data set Port x register. Access W W W W 1 0 Rev. A | Page 53 of 96 Description Reserved. GPIO Px.7 open-collector enable Set to 1 by the user to enable open-collector Set to 0 by the user to disable open collector GPIO Px.6 open-collector enable Set to 1 by the user to enable open-collector Set to 0 by the user to disable open-collector GPIO Px.5 open-collector enable Set to 1 by the user to enable open-collector Set to 0 by the user to disable open-collector GPIO Px.4 open-collector enable Set to 1 by the user to enable open-collector Set to 0 by the user to disable open-collector GPIO Px.3 open-collector enable Set to 1 by the user to enable open-collector Set to 0 by the user to disable open-collector GPIO Px.2 open-collector enable Set to 1 by the user to enable open-collector Set to 0 by the user to disable open-collector GPIO Px.1 open-collector enable Set to 1 by the user to enable open-collector Set to 0 by the user to disable open-collector GPIO Px.0 open-collector enable Set to 1 by the user to enable open-collector Set to 0 by the user to disable open-collector ADuC7122 Data Sheet UART SERIAL INTERFACE 13B The ADuC7122 features a 16450-compatible UART. The UART is a full-duplex, universal, asynchronous receiver/transmitter. A UART performs serial-to-parallel conversion on data characters received from a peripheral device, and parallel-to-serial conversion on data characters received from the ARM7TDMI. The UART features a fractional divider that facilitates high accuracy baud rate generation and a network addressable mode. The UART functionality is available on the P1.0 and P1.1 pins of the ADuC7122. The serial communication adopts an asynchronous protocol that supports various word length, stop bits, and parity generation options selectable in the configuration register. Calculation of the baud rate using fractional divider is as follows: Baud Rate = M+ BAUD RATE GENERATION Normal 450 UART Baud Rate Generation 16 × DL × 2 × ( M + N ) 2048 41.78 MHz N = 2048 Baud Rate × 16 × DL × 2 For example, generation of 19,200 baud 60B The ADuC7122 features two methods of generating the UART baud rate: normal 450 UART baud rate generation and ADuC7122 fractional divider. 41.78 MHz M+ 41.78 MHz N = 2048 19,200 × 16 × 67 × 2 M+ N = 1.015 2048 where: M = 1. N = 0.015 × 2048 = 30. 15B The baud rate is a divided version of the core clock using the value in COMDIV0 and COMDIV1 MMRs (16-bit value, DL). The standard baud rate generator formula is Baud rate = 41.78 MHz (1) 16 × 2 × DL Baud Rate = 41.78 MHz 30 16 × 67 × 2 × 1 + 2048 where Baud Rate = 19,219 bps. UART REGISTER DEFINITION Table 94 lists common baud rate values. The UART interface consists of the following ten registers: Table 94. Baud Rate Using the Standard Baud Rate Generator COMTX: 8-bit transmit register COMRX: 8-bit receive register COMDIV0: divisor latch (low byte) COMDIV1: divisor latch (high byte) COMCON0: line control register COMCON1: line control register COMSTA0: line status register COMIEN0: interrupt enable register COMIID0: interrupt identification register COMDIV2: 16-bit fractional baud divide register Baud Rate 9600 19,200 115,200 DL 0x88 0x44 0x0B Actual Baud Rate 9600 19,200 118,691 % Error 0% 0% 3% ADuC7122 Fractional Divider The fractional divider combined with the normal baud rate generator allows the generating of a wider range of more accurate baud rates. /2 FBEN /16DL UART /(M + N/2048) 08755-035 CORE CLOCK COMTX, COMRX, and COMDIV0 share the same address location. COMTX, COMRX, and COMIEN0 can be accessed when Bit 7 in the COMCON0 register is cleared. COMDIVx can be accessed when Bit 7 of COMCON0 is set Figure 34. Baud Rate Generation Options Rev. A | Page 54 of 96 (2) Data Sheet ADuC7122 UART TX Register UART Divisor Latch Register 1 Write to this 8-bit register to transmit data using the UART. Name: COMTX This 8-bit register contains the most significant byte of the divisor latch that controls the baud rate at which the UART operates. Address: 0xFFFF0800 Name: COMDIV1 Access: Write only Address: 0xFFFF0804 UART RX Register Default Value: 0x00 This 8-bit register is read from to receive data transmitted using the UART. Access: Read/write Name: COMRX UART Control Register 0 Address: 0xFFFF0800 This 8-bit register controls the operation of the UART in conjunction with COMCON1. Default Value: 0x00 Name: COMCON0 Access: Read only Address: 0xFFFF080C UART Divisor Latch Register 0 Default Value: 0x00 This 8-bit register contains the least significant byte of the divisor latch that controls the baud rate at which the UART operates. Access: Read/write Name: COMDIV0 Address: 0xFFFF0800 Default Value: 0x00 Access: Read/write Rev. A | Page 55 of 96 ADuC7122 Data Sheet Table 95. COMCON0 MMR Bit Designations Bit 7 Name DLAB 6 BRK 5 SP 4 EPS 3 PEN 2 STOP 1 to 0 WLS Description Divisor latch access. Set by the user to enable access to COMDIV0 and COMDIV1 registers. Cleared by the user to disable access to COMDIV0 and COMDIV1 and enable access to COMRX, COMTX, and COMIEN0. Set break. Set by the user to force TxD to 0. Cleared to operate in normal mode. Stick parity. Set by the user to force parity to defined values. 1 if EPS = 1 and PEN = 1. 0 if EPS = 0 and PEN = 1. Even parity select bit. Set for even parity. Cleared for odd parity. Parity enable bit. Set by the user to transmit and check the parity bit. Cleared by the user for no parity transmission or checking. Stop bit. Set by the user to transmit 1.5 stop bits if the word length is 5 bits, or 2 stop bits if the word length is 6, 7, or 8 bits. The receiver checks the first stop bit only, regardless of the number of stop bits selected. Cleared by the user to generate one stop bit in the transmitted data. Word length select. 00 = 5 bits. 01 = 6 bits. 10 = 7 bits. 11 = 8 bits. UART Control Register 1 This 8-bit register controls the operation of the UART in conjunction with COMCON0. Name: COMCON1 Address: 0xFFFF0810 Default Value: 0x00 Access: Read/write Table 96. COMCON1 MMR Bit Designations Bit 7:5 4 Name Loopback 3:2 1 RTS 0 DTR Rev. A | Page 56 of 96 Description Reserved bits. Not used. Set by the user to enable loopback mode. In loopback mode, the TxD is forced high. Reserved bits. Not used. Request to send. Set by the user to force the RTS output to 0. Cleared by the user to force the RTS output to 1. Data terminal ready. Set by the user to force the DTR output to 0. Cleared by the user to force the DTR output to 1. Data Sheet ADuC7122 UART Status Register 0 Name: COMSTA0 Address: 0xFFFF0814 Default Value: 0x60 Access: Read only Function: This 8-bit read-only register reflects the current status on the UART. Table 97. COMSTA0 MMR Bit Designations Bit 7 6 Name 5 THRE 4 BI 3 FE 2 PE 1 OE 0 DR TEMT Description Reserved. COMTX and shift register empty status bit. Set automatically if COMTX and the shift register are empty. This bit indicates that the data has been transmitted, that is, no more data is present in the shift register. Cleared automatically when writing to COMTX. COMTX empty status bit. Set automatically if COMTX is empty. COMTX can be written as soon as this bit is set, the previous data might not have been transmitted yet and can still be present in the shift register. Cleared automatically when writing to COMTX. Break indicator. Set when SIN is held low for more than the maximum word length. Cleared automatically. Framing error. Set when the stop bit is invalid. Cleared automatically. Parity error. Set when a parity error occurs. Cleared automatically. Overrun error. Set automatically if data are overwritten before being read. Cleared automatically. Data ready. Set automatically when COMRX is full. Cleared by reading COMRX. Rev. A | Page 57 of 96 ADuC7122 Data Sheet UART Interrupt Enable Register 0 Table 99. COMIID0 MMR Bit Designations Name: COMIEN0 Address: 0xFFFF0804 Default Value: 0x00 Bits[2:1] Status Bits 00 11 Bit 0 NINT 1 0 Access: Read/write Function: The 8-bit register enables and disables the individual UART interrupt sources. 10 0 2 Table 98. COMIEN0 MMR Bit Designations 01 0 3 Bit 7:4 3 00 0 4 2 1 0 Name EDSSI ELSI ETBEI ERBFI Description Reserved. Not used. Modem status interrupt enable bit. Set by the user to enable generation of an interrupt if any of COMSTA0[3:1] are set. Cleared by the user. RxD status interrupt enable bit. Set by the user to enable generation of an interrupt if any of the COMSTA0[3:1] register bits are set. Cleared by the user. Enable transmit buffer empty interrupt. Set by the user to enable an interrupt when the buffer is empty during a transmission, that is, when COMSTA[5] is set. Cleared by the user. Enable receive buffer full interrupt. Set by the user to enable an interrupt when the buffer is full during a reception. Cleared by the user. COMIID0 Address: 0xFFFF0808 Default Value: 0x01 Access: Read only Function: This 8-bit register reflects the source of the UART interrupt. 1 Definition No interrupt Receive line status interrupt Receive buffer full interrupt Transmit buffer empty interrupt Modem status interrupt Clearing Operation Read COMSTA0 Read COMRX Write data to COMTX or read COMIID0 Read COMSTA1 register UART Fractional Divider Register This 16-bit register controls the operation of the fractional divider for the ADuC7122. Name: COMDIV2 Address: 0xFFFF082C Default Value: 0x0000 Access: Read/write Table 100. COMDIV2 MMR Bit Designations Bit 15 Name FBEN 14:13 12:11 FBM[1:0] 10:0 FBN[10:0] UART Interrupt Identification Register 0 Name: Priority Rev. A | Page 58 of 96 Description Fractional baud rate generator enable bit. Set by the user to enable the fractional baud rate generator. Cleared by the user to generate the baud rate using the standard 450 UART baud rate generator. Reserved. M. If FBM = 0, M = 4. See Equation 2 for the calculation of the baud rate using a fractional divider and Table 94 for common baud rate values. N. See Equation 2 for the calculation of the baud rate using a fractional divider and Table 94 for common baud rate values. Data Sheet ADuC7122 I2C The ADuC7122 incorporates two I2C peripherals that can be separately configured as a fully I2C-compatible I2C bus master device or as a fully I2C bus-compatible slave device. Because both peripherals are identical, only one is explained here. The two pins used for data transfer, SDA and SCL, are configured in a wire-AND’ed format that allows arbitration in a multimaster system. These pins require external pull-up resistors. Typical pull-up values are between 4.7 kΩ and 10 kΩ. The I2C bus peripheral address in the I2C bus system is programmed by the user. This ID can be modified any time a transfer is not in progress. The user can configure the interface to respond to four slave addresses. The transfer sequence of an I2C system consists of a master device initiating a transfer by generating a start condition while the bus is idle. The master transmits the slave device address and the direction of the data transfer (read or write) during the initial address transfer. If the master does not lose arbitration and the slave acknowledges the last byte, the data transfer is initiated. This continues until the master issues a stop condition, and the bus becomes idle. The I2C peripheral can only be configured as a master or slave at any given time. The same I2C channel cannot simultaneously support master and slave modes. The I2C interface on the ADuC7122 includes the following features: • • • • • • • • Configuring External Pins for I2C Functionality The I2C pins of the ADuC7122 device are P0.0 and P0.1 for I2C0, and P1.0 and P1.1 for I2C1. P0.0 and P1.0 are the I2C clock signals, and P0.1 and P1.1 are the I2C data signals. For instance, to configure the I2C0 pins (SCL1, SDA1), Bit 0 and Bit 4 of the GP0CON register must be set to 1 to enable I2C mode. Alternatively, to configure the I2C1 pins (SCL2, SDA2), Bit 1 and Bit 5 of the GP1CON register must be set to 1 to enable I2C mode. SERIAL CLOCK GENERATION The I2C master in the system generates the serial clock for a transfer. The master channel can be configured to operate in fast mode (400 kHz) or standard mode (100 kHz). The bit rate is defined in the I2CxDIV MMR as follows: f SERIAL CLOCK = fUCLK (2 + DIVH ) + (2 + DIVL) where: fUCLK is the clock before the clock divider. DIVH is the high period of the clock. DIVL is the low period of the clock. Thus, for 100 kHz operation, DIVH = DIVL = 0xCF and for 400 kHz, Support for repeated start conditions. In master mode, the ADuC7122 can be programmed to generate a repeated start. In slave mode, the ADuC7122 recognizes repeated start conditions. In master and slave mode, the part recognizes both 7-bit and 10-bit bus addresses. In I2C master mode, the ADuC7122 supports continuous reads from a single slave up to 512 bytes in a single transfer sequence. Clock stretching can be enabled by other devices on the bus without causing any issues with the ADuC7122. However, the ADuC7122 cannot enable clock stretching. In slave mode, the ADuC7122 can be programmed to return a NACK (no acknowledge). This allows the validiation of checksum bytes at the end of I2C transfers. Bus arbitration in master mode is supported. Internal and external loopback modes are supported for I2C hardware testing. In loopback mode. The transmit and receive circuits in both master and slave mode contain 2-byte FIFOs. Status bits are available to the user to control these FIFOs. DIVH = 0x28, DIVL = 0x3C The I2CxDIV register corresponds to DIVH:DIVL. I2C BUS ADDRESSES Slave Mode In slave mode, the I2CxID0, I2CxID1, I2CxID2, and I2xCID3 registers contain the device IDs. The device compares the four I2CxIDx registers to the address byte received from the bus Master. To be correctly addressed, the seven MSBs of either ID register must be identical to that of the seven MSBs of the first received address byte. The LSB of the ID registers (the transfer direction bit) is ignored in the process of address recognition. The ADuC7122 also supports 10-bit addressing mode. When Bit 1 of I2CxSCTL (ADR10EN bit) is set to 1, then one 10-bit address is supported in slave mode and is stored in the I2CxID0 and I2CxID1 registers. The 10-bit address is derived as follows: I2CxID0[0] is the read/write bit and is not part of the I2C address. I2CxID0[7:1] = Address Bits[6:0]. I2CxID1[2:0] = Address Bits[9:7]. I2CxID1[7:3] must be set to 11110b. Rev. A | Page 59 of 96 ADuC7122 Data Sheet Master Mode I2C REGISTERS In master mode, the I2CADR0 register is programmed with the I2C address of the device. The I2C peripheral interface consists of a number of MMRs. These are described in the following section. In 7-bit address mode, I2CADR0[7:1] are set to the device address. I2CADR0[0] is the read/write bit. I2C Master Registers I2C Master Control Register In 10-bit address mode, the 10-bit address is created as follows: Name: I2C0MCTL, I2C1MCTL Address: 0xFFFF0880, 0xFFFF0900 I2CADR1[7:0] = Address Bits[7:0]. Default Value: 0x0000, 0x0000 I2CADR0[0] is the read/write bit. Access: Read/write Function: This 16-bit MMR configures I2C peripheral in master mode. I2CADR0[7:3] must be set to 11110b. I2CADR0[2:1] = Address Bits[9:8]. Table 101. I2CxMCTL MMR Bit Designations Bit 15:9 8 Name 7 I2CNACKENI 6 I2CALENI 5 I2CMTENI 4 I2CMRENI 3 2 I2CILEN 1 I2CBD 0 I2CMEN I2CMCENI Description Reserved. These bits are reserved and should not be written to. I2C transmission complete interrupt enable bit. Set this bit to enable an interrupt on detecting a stop condition on the I2C bus. Clear this bit to disable the interrupt source. I2C NACK received interrupt enable bit. Set this bit to enable interrupts when the I2C master receives a NACK. Clear this bit to disable the interrupt source. I2C arbitration lost interrupt enable bit. Set this bit to enable interrupts when the I2C master has lost in trying to gain control of the I2C bus. Clear this bit to disable the interrupt source. I2C transmit interrupt enable bit. Set this bit to enable interrupts when the I2C master has transmitted a byte. Clear this bit to disable the interrupt source. I2C receive interrupt enable bit. Set this bit to enable interrupts when the I2C master receives data. Cleared by user to disable interrupts when the I2C master is receiving data. Reserved. A value of 0 should be written to this bit. I2C internal loopback enable. Set this bit to enable loopback test mode. In this mode, the SCL and SDA signals are connected internally to their respective input signals. Cleared by user to disable loopback mode. I2C master backoff disable bit. Set this bit to allow the device to compete for control of the bus even if another device is currently driving a start condition. Clear this bit to back off (wait) until the I2C bus becomes free. I2C master enable bit. Set by user to enable I2C master mode. Cleared disable I2C master mode. Rev. A | Page 60 of 96 Data Sheet ADuC7122 I2C Master Status Register Name: I2C0MSTA , I2C1MSTA Address: 0xFFFF0884, 0xFFFF0904 Default Value: 0x0000, 0x0000 Access: Read Function: This 16-bit MMR is I2C status register in master mode. Table 102 I2CxMSTA MMR Bit Designations Bit 15:11 10 Name 9 I2CMRxFO 8 I2CMTC 7 I2CMNA 6 I2CMBUSY 5 I2CAL 4 I2CMNA 3 I2CMRXQ 2 I2CMTXQ 1:0 I2CMTFSTA I2CBBUSY Description Reserved. These bits are reserved. I2C bus busy status bit. This bit is set to 1 when a start condition is detected on the I2C bus. This bit is cleared when a stop condition is detected on the bus. Master Rx FIFO overflow. This bit is set to 1 when a byte is written to the Rx FIFO and it is already full. This bit is cleared in all other conditions. I2C transmission complete status bit. This bit is set to 1 when a transmission is complete between the master and the slave it was communicating with. If the I2CMCENI bit in I2CxMCTL is set, an interrupt is generated when this bit is set. Clear this bit to disable the interrupt source. I2C master NACK data bit. This bit is set to 1 when a NACK condition is received by the master in response to a data write transfer. If the I2CNACKENI bit in I2CxMCTL is set, an interrupt is generated when this bit is set. This bit is cleared in all other conditions. I2C master busy status bit Set to 1 when the master is busy processing a transaction. Cleared if the master is ready or if another Master device has control of the bus. I2C arbitration lost status bit. This bit is set to 1 when the I2C master has lost in trying to gain control of the I2C bus. If the I2CALENI bit in I2CxMCTL is set, an interrupt is generated when this bit is set. This bit is cleared in all other conditions. I2C master NACK address bit. This bit is set to 1 when a NACK condition is received by the master from an I2C slave address. If the I2CNACKENI bit in I2CxMCTL is set, an interrupt is generated when this bit is set. This bit is cleared in all other conditions. I2C master receive request bit. This bit is set to 1 when data enters the Rx FIFO. If the I2CMRENI in I2CxMCTL is set, an interrupt is generated. This bit is cleared in all other conditions. I2C master transmit request bit. This bit goes high if the Tx FIFO is empty or only contains one byte and the master has transmitted an address and a write. If the I2CMTENI bit in I2CxMCTL is set, an interrupt is generated when this bit is set. This bit is cleared in all other conditions. I2C master Tx FIFO status bits. 00 = I2C master Tx FIFO empty. 01 = one byte in master Tx FIFO. 10 = one byte in master Tx FIFO. 11 = I2C master Tx FIFO full. Rev. A | Page 61 of 96 ADuC7122 Data Sheet I2C Master Receive Register I2C Master Read Count Register Name: I2C0MRX, I2C1MRX Name: I2C0MCNT0, I2C1MCNT0 Address: 0xFFFF0888, 0xFFFF0908 Address: 0xFFFF0890, 0xFFFF0910 Default Value: 0x00, 0x00 Default Value: 0x0000, 0x0000 Access: Read only Access: Read/write Function: This 8-bit MMR is the I2C master receive register. Function: This 16-bit MMR holds the required number of bytes when the master begins a read sequence from a slave device. I2C Master Transmit Register Name: I2C0MTX, I2C1MTX Address: 0xFFFF088C, 0xFFFF090C Default Value: 0x00, 0x00 Access: Read/write Function: This 8-bit MMR is the I2C master transmit register. I2C Master Current Read Count Register Name: I2C0MCNT1, I2C1MCNT1 Address: 0xFFFF0894, 0xFFFF0914 Default Value: 0x00, 0x00 Access: Read Function: This 8-bit MMR holds the number of bytes received so far during a read sequence with a slave device. Table 103. I2CxMCNT0 MMR Bit Descriptions (Address = 0xFFFF0890, 0xFFFF0910, Default Value = 0x0000) Bit 15:9 8 Name 7:0 I2CRCNT I2CRECNT Description Reserved. Set this bit if greater than 256 bytes are required from the slave. Clear this bit when reading 256 bytes or less. These eight bits hold the number of bytes required during a slave read sequence, minus 1. If only a single byte is required, these bits should be set to 0. Rev. A | Page 62 of 96 Data Sheet ADuC7122 I2C Address 0 Register I2C Master Clock Control Register Name: I2C0ADR0, I2C1ADR0 Name: I2C0DIV, I2C1DIV Address: 0xFFFF0898, 0xFFFF0918 Address: 0xFFFF08A4, 0xFFFF0924 Default Value: 0x00, 0x00 Default Value: 0x1F1F, 0x1F1F Access: Read/write Access: Read/write Function: This 8-bit MMR holds the 7-bit slave address + the read/write bit when the master begins communicating with a slave. Function: This MMR controls the frequency of the I2C clock generated by the master on to the SCL pin. For further details, see the I2C section. I2C Address 1 Register Name: I2C0ADR1, I2C1ADR1 Address: I2C Start Byte Register Name: I2C0SBYTE, I2C1SBYTE 0xFFFF089C, 0xFFFF091C Address: 0xFFFF08A0, 0xFFFF0920 Default Value: 0x00, 0x00 Default Value: 0x00, 0x00 Access: Read/write Access: Read/write Function: This 8-bit MMR is used in 10-bit addressing mode only. This register contains the least significant byte of the address. Function: This MMR can be used to generate a start byte at the start of a transaction. To generate a start byte followed by a normal address, first write to I2CxSBYTE, then write to the address register (I2CxADRx). This drives the byte written in I2CxSBYTE onto the bus followed by a repeated start. This register can be used to drive any byte onto the I2C bus followed by a repeated start (not a start byte only, for example, 00000001). Table 104. I2CxADR0 MMR in 7-Bit Address Mode (Address = 0xFFFF0898, 0xFFFF0918, Default Value = 0x00) Bit 7:1 0 Name I2CADR R/W Description These bits contain the 7-bit address of the required slave device. Bit 0 is the read/write bit. When this bit = 1, a read sequence is requested. When this bit = 0, a write sequence is requested. Table 105. I2CxADR0 MMR in 10-Bit Address Mode Bit 7:3 2:1 0 Name I2CMADR R/W Description These bits must be set to [11110b] in 10-bit address mode. These bits contain ADDR[9:8] in 10-bit addressing mode. Read/write bit. When this bit = 1, a read sequence is requested. When this bit = 0, a write sequence is requested. Table 106. I2CxADR1 MMR in 10-Bit Address Mode Bit 7:0 Name I2CLADR Description These bits contain ADDR[7:0] in 10-bit addressing mode. Table 107. I2CxDIV MMR Bit 15:8 7:0 Name DIVH DIVL Description These bits control the duration of the high period of SCLx. These bits control the duration of the low period of SCLx. Rev. A | Page 63 of 96 ADuC7122 Data Sheet I2C Slave Registers I2C Slave Control Register Name: I2C0SCTL, I2C1SCTL Address: 0xFFFF08A8, 0xFFFF0928 Default Value: 0x0000, 0x000 Access: Read/write Function: This 16-bit MMR configures the I2C peripheral in slave mode. Table 108. I2CxSCTL MMR Bit Designations Bit 15:11 10 Name 9 I2CSRXENI 8 I2CSSENI 7 I2CNACKEN 6 5 I2CSETEN 4 I2CGCCLR 3 I2CHGCEN 2 I2CGCEN I2CSTXENI Description Reserved bits. Slave transmit interrupt enable bit. Set this bit to enable an interrupt after a slave transmits a byte. Clear this interrupt source. Slave receive interrupt enable bit. Set this bit to enable an interrupt after the slave receives data. Clear this interrupt source. I2C stop condition detected interrupt enable bit. Set this bit to enable an interrupt on detecting a stop condition on the I2C bus. Clear this interrupt source. I2C NACK enable bit. Set this bit to NACK the next byte in the transmission sequence. Clear this bit to let the hardware control the ACK/NACK sequence. Reserved. A value of 0 should be written to this bit. I2C early transmit interrupt enable bit. Setting this bit enables a transmit request interrupt just after the positive edge of SCLx during the read bit transmission. Clear this bit to enable a transmit request interrupt just after the negative edge of SCLx during the read bit transmission. I2C general call status and ID clear bit. Writing a 1 to this bit clears the general call status (I2CGC) and ID (I2CGCID[1:0]) bits in the I2CxSSTA register. Clear this bit at all other times. I2C hardware general call enable. Hardware general call enable. When this bit and Bit 2 are set, and having received a general call (Address 0x00) and a data byte, the device checks the contents of I2CxALT against the receive register. If the contents match, the device has received a hardware general call. This method is used if a device needs urgent attention from a master device without knowing which master it needs to turn to. This is a broadcast message to all master devices on the bus. The ADuC7122 watches for these addresses. The device that requires attention embeds its own address into the message. All masters listen, and the one that can handle the device contacts its slave and acts appropriately. The LSB of the I2CxALT register should always be written to 1, as per the I2C January 2000 bus specification. Set this bit and I2CGCEN to enable hardware general call recognition in slave mode. Clear this bit to disable recognition of hardware general call commands. I2C general call enable. Set this bit to enable the slave device to acknowledge an I2C general call, Address 0x00 (write). The device then recognizes a data bit. If it receives a 0x06 (reset and write programmable part of the slave address by hardware) as the data byte, the I2C interface resets as per the I2C January 2000 bus specification. This command can be used to reset an entire I2C system. If it receives a 0x04 (write programmable part of the slave address by hardware) as the data byte, the general call interrupt status bit sets on any general call. The user must take corrective action by reprogramming the device address. Set this bit to allow the slave ACK I2C general call commands. Clear to disable recognition of general call commands. Rev. A | Page 64 of 96 Data Sheet Bit 1 Name ADR10EN 0 I2CSEN ADuC7122 Description I2C 10-bit address mode. Set to 1 to enable 10-bit address mode. Clear to 0 to enable normal address mode. I2C slave enable bit. Set by the user to enable I2C slave mode. Clear to disable I2C slave mode. I2C Slave Status Registers Name: I2C0SSTA, I2C1SSTA Address: 0xFFFF08AC, 0xFFFF092C Default Value: 0x0000, 0x0000 Access: Read only Function: This 16-bit MMR is the I2C status register in slave mode. Table 109. I2CxSSTA MMR Bit Designations Bit 15 14 Name 13 I2CREPS 12-11 I2CID[1:0] 10 I2CSS 9:8 I2CGCID[1:0] 7 I2CGC 6 I2CSBUSY 5 I2CSNA I2CSTA Description Reserved bit. This bit is set to 1 if a start condition followed by a matching address is detected. It is also set if a start byte (0x01) is received, or if general calls are enabled and a general call code of 0x00 is received. This bit is cleared upon receiving a stop condition. This bit is set to 1 if a repeated start condition is detected. This bit is cleared on receiving a stop condition. A read of the I2CxSSTA register also clears this bit. I2C address matching register. These bits indicate which I2CxIDx register matches the received address. 00 = received address matches I2CxID0. 01 = received address matches I2CxID1. 10 = received address matches I2CxID2. 11 = received address matches I2CxID3. I2C stop condition after start detected bit. This bit is set to 1 when a stop condition is detected after a previous start and matching address. When the I2CSSENI bit in I2CxSCTL is set, an interrupt is generated. This bit is cleared by reading this register. I2C general call ID bits. 00 = no general call received. 01 = general call reset and program address. 10 = general program address. 11 = general call matching alternative ID. Note that these bits are not cleared by a general call reset command. Clear these bits by writing a 1 to the I2CGCCLR bit in I2CxSCTL. I2C general call status bit. This bit is set to 1 if the slave receives a general call command of any type. If the command received is a reset command, then all registers return to their default state. If the command received is a hardware general call, the Rx FIFO holds the second byte of the command and this can be compared with the I2CxALT register. Clear this bit by writing a 1 to the I2CGCCLR bit in I2CxSCTL. I2C slave busy status bit. Set to 1 when the slave receives a start condition. Cleared by hardware if the received address does not match any of the I2CxIDx registers, if the slave device receives a stop condition, or if a repeated start address does not match any of the I2CxIDx registers. I2C slave NACK data bit. This bit is set to 1 when the slave responds to a bus address with a NACK. This bit is asserted if NACK is returned because there is no data in the Tx FIFO or if the I2CNACKEN bit is set in the I2CxSCTL register. This bit is cleared in all other conditions. Rev. A | Page 65 of 96 ADuC7122 Bit 4 Name I2CSRxFO 3 I2CSRXQ 2 I2CSTXQ 1 I2CSTFE 0 I2CETSTA Data Sheet Description Slave Rx FIFO overflow. This bit is set to 1 when a byte is written to the Rx FIFO when it is already full. This bit is cleared in all other conditions. I2C slave receive request bit. This bit is set to 1 when the slave Rx FIFO is not empty. This bit causes an interrupt to occur if the I2CSRXENI bit in I2CxSCTL is set. The Rx FIFO must be read or flushed to clear this bit. I2C slave transmit request bit. This bit is set to 1 when the slave receives a matching address followed by a read. If the I2CSETEN bit in I2CxSCTL = 0, this bit goes high just after the negative edge of SCL during the read bit transmission. If the I2CSETEN bit in I2CxSCTL = 1, this bit goes high just after the positive edge of SCL during the read bit transmission. This bit causes an interrupt to occur if the I2CSTXENI bit in I2CxSCTL is set. This bit is cleared in all other conditions. I2C slave FIFO underflow status bit. This bit goes high if the Tx FIFO is empty when a master requests data from the slave. This bit is asserted at the rising edge of SCL during the read bit. This bit is cleared in all other conditions. I2C slave early transmit FIFO status bit. If the I2CSETEN bit in I2CxSCTL = 0, this bit goes high if the slave Tx FIFO is empty. If the I2CSETEN bit in I2CxSCTL = 1, this bit goes high just after the positive edge of SCL during the write bit transmission. This bit asserts once only for a transfer. This bit is cleared after being read. Rev. A | Page 66 of 96 Data Sheet ADuC7122 I2C Slave Receive Registers I2C Slave Device ID Registers Name: I2C0SRX, I2C1SRX Name: I2C0IDx, I2C1IDx Address: 0xFFFF08B0, 0xFFFF0930 Addresses: 0xFFFF093C = I2C1ID0 Default Value: 0x00 0xFFFF08BC = I2C0ID0 Access: Read 0xFFFF0940 = I2C1ID1 Function: This 8-bit MMR is the I2C slave receive register. 0xFFFF08C0 = I2C0ID1 0xFFFF0944 = I2C1ID2 I2C Slave Transmit Registers 0xFFFF08C4 = I2C0ID2 Name: I2C0STX, I2C1STX 0xFFFF0948 = I2C1ID3 Address: 0xFFFF08B4, 0xFFFF0934 0xFFFF08C8 = I2C0ID3 Default Value: 0x00 Default Value: 0x00 Access: Read/write Access: Read/write Function: This 8-bit MMR is the I2C slave transmit register. Function: These 8-bit MMRs are programmed with I2C bus IDs of the slave. See the I2C Bus Addresses section for further details. I2C Hardware General Call Recognition Registers Name: I2C0ALT, I2C1ALT Address: 0xFFFF08B8, 0xFFFF0938 Default Value: 0x00 Access: Read/write Function: This 8-bit MMR is used with hardware general calls when I2CxSCTL Bit 3 is set to 1. This register is used in cases where a master is unable to generate an address for a slave, and instead, the slave must generate the address for the master. Rev. A | Page 67 of 96 ADuC7122 Data Sheet I2C COMMON REGISTERS I2C FIFO Status Register Name: I2C0FSTA, I2C1FSTA Address: 0xFFFF08CC, 0xFFFF094C Default Value: 0x0000 Access: Read/write Function: These 16-bit MMRs contain the status of the Rx/Tx FIFOs in both master and slave modes. Table 110. I2CxFSTA MMR Bit Designations Bit 15:10 9 8 7:6 Name 5:4 I2CMTXSTA 3:2 I2CSRXSTA 1:0 I2CSTXSTA I2CFMTX I2CFSTX I2CMRXSTA Description Reserved bits. Set this bit to 1 to flush the master Tx FIFO. Set this bit to 1 to flush the slave Tx FIFO. I2C master receive FIFO status bits. 00 = FIFO empty. 01 = byte written to FIFO. 10 = 1 byte in FIFO. 11 = FIFO full. I2C master transmit FIFO status bits. 00 = FIFO empty. 01 = byte written to FIFO. 10 = 1 byte in FIFO. 11 = FIFO full. I2C slave receive FIFO status bits. 00 = FIFO empty. 01 = byte written to FIFO. 10 = 1 byte in FIFO. 11 = FIFO full. I2C slave transmit FIFO status bits. 00 = FIFO empty. 01 = byte written to FIFO. 10 = 1 byte in FIFO. 11 = FIFO full. Rev. A | Page 68 of 96 Data Sheet ADuC7122 SERIAL PERIPHERAL INTERFACE The ADuC7122 integrates a complete hardware serial peripheral interface (SPI) on chip. SPI is an industry standard, synchronous serial interface that allows eight bits of data to be synchronously transmitted and simultaneously received, that is, full duplex up to a maximum bit rate of 20 Mb. SPI CHIP SELECT (SPICS INPUT) PIN E 69B A In SPI slave mode, a transfer is initiated by the assertion of SPICS, which is an active low input signal. The SPI port then transmits and receives 8-bit data until the transfer is concluded by deassertion of SPICS. In slave mode, SPICS is always an input. E A A E A The SPI port can be configured for master or slave operation and typically consists of four pins: SPIMISO, SPIMOSI, SPICLK, and SPICS. A SPIMISO (MASTER IN, SLAVE OUT) PIN The SPIMOSI pin is configured as an output line in master mode and an input line in slave mode. The SPIMOSI line on the master (data out) should be connected to the SPIMOSI line in the slave device (data in). The data is transferred as byte wide (8-bit) serial data, MSB first. SPICLK (SERIAL CLOCK I/O) PIN 68B A 70B The SPI pins of the ADuC7122 device are P0.2 to P0.5. P0.5 is the slave chip select pin. In slave mode, this pin is an input and must be driven low by the master. In master mode, this pin is an output and goes low at the beginning of a transfer and high at the end of a transfer. P0.2 is the SPICLK pin. P0.3 is the master in, slave out (SPIMISO) pin. P0.4 is the master out, slave in (SPIMOSI) pin. To configure P0.2 to P0.5 for SPI mode, see the GeneralPurpose I/O section. The master serial clock (SPICLK) synchronizes the data being transmitted and received through the MOSI SPICLK period. Therefore, a byte is transmitted/received after eight SPICLK periods. The SPICLK pin is configured as an output in master mode and as an input in slave mode. In master mode, polarity and phase of the clock are controlled by the SPICON register, and the bit rate is defined in the SPIDIV register as follows: f SERIAL CLOCK = A CONFIGURING EXTERNAL PINS FOR SPI FUNCTIONALITY 6B SPIMOSI (MASTER OUT, SLAVE IN) PIN A In SPI master mode, SPICS is an active low output signal. It asserts itself automatically at the beginning of a transfer and deasserts itself upon completion. A 67B E A E E The SPIMISO pin is configured as an input line in master mode and an output line in slave mode. The SPIMISO line on the master (data in) should be connected to the SPIMISO line in the slave device (data out). The data is transferred as byte wide (8-bit) serial data, MSB first. A f UCLK 2 × (1 + SPIDIV ) The maximum speed of the SPI clock is independent on the clock divider bits. In slave mode, the SPICON register must be configured with the phase and polarity of the expected input clock. The slave accepts data from an external master up to 10 Mb. In both master and slave modes, data is transmitted on one edge of the SPICLK signal and sampled on the other. Therefore, it is important that the polarity and phase are configured the same for the master and slave devices. Rev. A | Page 69 of 96 ADuC7122 Data Sheet SPI Status Register SPI REGISTERS 13B 71B The following MMR registers control the SPI interface: SPISTA, SPIRX, SPITX, SPIDIV, and SPICON. Name: SPISTA Address: 0xFFFF0A00 Default Value: 0x0000 Access: Read only Function: This 16-bit MMR contains the status of the SPI interface in both master and slave modes. Table 111. SPISTA MMR Bit Designations Bit 15:12 11 Name 10:8 SPIRXFSTA[2:0] 7 SPIFOF 6 SPIRXIRQ 5 SPITXIRQ 4 SPITXUF 3:1 SPITXFSTA[2:0] 0 SPIISTA SPIREX Description Reserved bits. SPI Rx FIFO excess bytes present. This bit is set when there are more bytes in the Rx FIFO than indicated in the SPIMDE bits in SPICON. This bit is cleared when the number of bytes in the FIFO is equal to or less than the number in SPIRXMDE. SPI Rx FIFO status bits. 000 = Rx FIFO is empty. 001 = 1 valid byte in the FIFO. 010 = 2 valid bytes in the FIFO. 011 = 3 valid bytes in the FIFO. 100 = 4 valid bytes in the FIFO. SPI Rx FIFO overflow status bit. Set when the Rx FIFO was already full when new data was loaded to the FIFO. This bit generates an interrupt except when SPIRFLH is set in SPICON. Cleared when the SPISTA register is read. SPI Rx IRQ status bit. Set when a receive interrupt occurs. This bit is set when SPITMDE in SPICON is cleared and the required number of bytes have been received. Cleared when the SPISTA register is read. SPI Tx IRQ status bit. Set when a transmit interrupt occurs. This bit is set when SPITMDE in SPICON is set and the required number of bytes have been transmitted. Cleared when the SPISTA register is read. SPI Tx FIFO underflow. This bit is set when a transmit is initiated without any valid data in the Tx FIFO. This bit generates an interrupt except when SPITFLH is set in SPICON. Cleared when the SPISTA register is read. SPI Tx FIFO status bits. 000 = Tx FIFO is empty. 001 = 1 valid byte in the FIFO. 010 = 2 valid bytes in the FIFO. 011 = 3 valid bytes in the FIFO. 100 = 4 valid bytes in the FIFO. Clear this bit to enable 7-bit address mode. SPI interrupt status bit. Set to 1 when an SPI-based interrupt occurs. Cleared after reading SPISTA. Rev. A | Page 70 of 96 Data Sheet ADuC7122 SPIRX Register SPIDIV Register 134B 136B Name: SPIRX Name: SPIDIV Address: 0xFFFF0A04 Address: 0xFFFF0A0C Default Value: 0x00 Default Value: 0x1B Access: Read Access: Read/write Function: This 8-bit MMR is the SPI receive register. Function: This 8-bit MMR is the SPI baud rate selection register. SPITX Register 135B SPI Control Register Name: SPITX Address: 0xFFFF0A08 Default Value: 0x00 Access: Write Function: This 8-bit MMR is the SPI transmit register. 137B Name: SPICON Address: 0xFFFF0A10 Default Value: 0x0000 Access: Read/write Function: This 16-bit MMR configures the SPI peripheral in both master and slave modes. Table 112. SPICON MMR Bit Designations Bit 15:14 Name SPIMDE 13 SPITFLH 12 SPIRFLH 11 SPICONT Description SPI IRQ mode bits. These bits configure when the Tx/Rx interrupts occur in a transfer. 00 = Tx interrupt occurs when one byte has been transferred. Rx interrupt occurs when one or more bytes have been received by the FIFO. 01 = Tx interrupt occurs when two bytes have been transferred. Rx interrupt occurs when two or more bytes have been received by the FIFO. 10 = Tx interrupt occurs when three bytes have been transferred. Rx interrupt occurs when three or more bytes have been received by the FIFO. 11 = Tx interrupt occurs when four bytes have been transferred. Rx interrupt occurs when the Rx FIFO is full, or four bytes present. SPI Tx FIFO flush enable bit. Set this bit to flush the Tx FIFO. This bit does not clear itself and should be toggled if a single flush is required. If this bit is left high, then either the last transmitted value or 0x00 is transmitted depending on the SPIZEN bit. When the flush enable bit is set, the FIFO is cleared within a single microprocessor cycle. Any writes to the Tx FIFO are ignored while this bit is set. Clear this bit to disable Tx FIFO flushing. SPI Rx FIFO flush enable bit. Set this bit to flush the Rx FIFO. This bit does not clear itself and should be toggled if a single flush is required. When the flush enable bit is set, the FIFO is cleared within a single microprocessor cycle. If this bit is set, all incoming data is ignored and no interrupts are generated. If set and SPITMDE = 0, a read of the Rx FIFO initiates a transfer. Clear this bit to disable Rx FIFO flushing. Continuous transfer enable. Set by the user to enable continuous transfer. In master mode, the transfer continues until no valid data is available in the Tx register. SPICS is asserted and remains asserted for the duration of each 8-bit serial transfer until Tx is empty. E A 10 SPILP 9 SPIOEN A Cleared by the user to disable continuous transfer. Each transfer consists of a single 8-bit serial transfer. If valid data exists in the SPITX register, then a new transfer is initiated after a stall period of one serial clock cycle. Loop back enable bit. Set by the user to connect MISO to MOSI and test software. Cleared by the user to place in normal mode. Slave MISO output enable bit. Set this bit for SPIMISO to operate as normal. Clear this bit to disable the output driver on the SPIMISO pin. The SPIMISO pin is open-drain when this bit is clear. Rev. A | Page 71 of 96 ADuC7122 Bit 8 Name SPIROW 7 SPIZEN 6 SPITMDE 5 SPILF 4 SPIWOM 3 SPICPO 2 SPICPH 1 SPIMEN 0 SPIEN Data Sheet Description SPIRX overflow overwrite enable. Set by the user, the valid data in the Rx register is overwritten by the new serial byte received. Cleared by the user, the new serial byte received is discarded. SPI transmit zeros when the Tx FIFO is empty. Set this bit to transmit 0x00 when there is no valid data in the Tx FIFO. Clear this bit to transmit the last transmitted value when there is no valid data in the Tx FIFO. SPI transfer and interrupt mode. Set by the user to initiate transfer with a write to the SPITX register. Interrupt only occurs when Tx is empty. Cleared by the user to initiate transfer with a read of the SPIRX register. Interrupt only occurs when Rx is full. LSB first transfer enable bit. Set by the user, the LSB is transmitted first Cleared by the user, the MSB is transmitted first. SPI wired or mode enable bit Set to 1 to enable open-drain data output enable. External pull-ups required on data out pins. Cleared for normal output levels. Serial clock polarity mode bit. Set by the user, the serial clock idles high. Cleared by the user, the serial clock idles low. Serial clock phase mode bit. Set by the user, the serial clock pulses at the beginning of each serial bit transfer. Cleared by the user, the serial clock pulses at the end of each serial bit transfer. Master mode enable bit. Set by the user to enable master mode. Cleared by the user to enable slave mode. SPI enable bit. Set by the user to enable the SPI. Cleared by the user to disable the SPI. Rev. A | Page 72 of 96 Data Sheet ADuC7122 PROGRAMMABLE LOGIC ARRAY (PLA) The ADuC7122 integrates a fully programmable logic array (PLA) that consists of two, independent but interconnected PLA blocks. Each block consists of eight PLA elements, giving each part a total of 16 PLA elements. Each PLA element contains a two-input look-up table that can be configured to generate any logic output function based on two inputs and a flip-flop. This is represented in Figure 35. 0 2 4 A LOOKUP TABLE 3 B 08755-036 1 Figure 35. PLA Element In total, 32 GPIO pins are available on each ADuC7122 for the PLA. These include 16 input pins and 16 output pins that need to be configured in the GPxCON register as PLA pins before using the PLA. Note that the comparator output is also included as one of the 16 input pins. The PLA is configured via a set of user MMRs. The output(s) of the PLA can be routed to the internal interrupt system, to the CONVST signal of the ADC, to an MMR, or to any of the 16 PLA output pins. E A A PLA MMRs Interface The PLA peripheral interface consists of the 21 MMRs described in Table 114 to Table 128. Table 114. PLAELMx Registers Name PLAELM0 PLAELM1 PLAELM2 PLAELM3 PLAELM4 PLAELM5 PLAELM6 PLAELM7 PLAELM8 PLAELM9 PLAELM10 PLAELM11 PLAELM12 PLAELM13 PLAELM14 PLAELM15 Output of Element 15 (Block 1) can be fed back to Input 0 of Mux 0 of Element 0 (Block 0) Output of Element 7 (Block 0) can be fed back to the Input 0 of Mux 0 of Element 8 (Block 1) Table 113. Element Input/Output PLA Block 0 Element Input 0 P2.7 1 P2.2 2 P0.6 3 P0.7 4 P0.1 5 P0.0 6 P1.1 7 P1.0 Output P3.0 P3.1 P3.2 P3.3 P1.7 P1.6 P2.5 P2.4 PLA Block 1 Element Input 8 P1.4 9 P1.5 10 P0.5 11 P0.4 12 P2.1 13 P2.0 14 P2.3 15 P2.6 Default Value 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W PLAELMx are Element 0 to Element 15 control registers. They configure the input and output mux of each element, select the function in the look-up table, and bypass/use the flip-flop. See Table 115 and Table 118. The two blocks can be interconnected as follows: Address 0xFFFF0B00 0xFFFF0B04 0xFFFF0B08 0xFFFF0B0C 0xFFFF0B10 0xFFFF0B14 0xFFFF0B18 0xFFFF0B1C 0xFFFF0B20 0xFFFF0B24 0xFFFF0B28 0xFFFF0B2C 0xFFFF0B30 0xFFFF0B34 0xFFFF0B38 0xFFFF0B3C Output P3.4 P3.5 P3.6 P3.7 P0.3 P0.2 P1.3 P1.2 Rev. A | Page 73 of 96 ADuC7122 Data Sheet Table 115. PLAELMx MMR Bit Descriptions Bit 31:11 10:9 8:7 6 Value 1 0 5 1 0 4:1 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 Description Reserved. Mux 0 control (see Table 118). Mux 1 control (see Table 118). Mux 2 control. Set by user to select the output of Mux 0. Cleared by user to select the bit value from the PLADIN register. Mux 3 control. Set by user to select the input pin of the particular element. Cleared by user to select the output of Mux 1. Look-up table control. 0. NOR. B AND NOT A. NOT A. A AND NOT B. NOT B. EXOR. NAND. AND. EXNOR. B. NOT A OR B. A. A OR NOT B. OR. 1. Mux 4 control. Set by user to bypass the flipflop. Cleared by user to select the flip-flop (cleared by default). Table 116. PLACLK Register Name PLACLK Address 0xFFFF0B40 Default Value 0x00 PLACLK is the clock selection for the flip-flops of Block 0 and Block 1. Note that the maximum frequency when using the GPIO pins as the clock input for the PLA blocks is 41.78 MHz. Table 117. PLACLK MMR Bit Descriptions Bit 7 6:4 Value 000 001 010 011 100 101 Other 3 2:0 000 001 010 011 100 101 Other Description Reserved. Block 1 clock source selection. GPIO clock on P0.5. GPIO clock on P0.0. GPIO clock on P0.7. HCLK. External crystal (OCLK) (32.768 kHz). Timer1 overflow. Reserved. Reserved. Block 0 clock source selection. GPIO clock on P0.5. GPIO clock on P0.0. GPIO clock on P0.7. HCLK. External crystal (OCLK) (32.768 kHz). Timer1 overflow. Reserved. Table 118. Feedback Configuration Bit 10:9 8:7 Value 00 01 10 11 00 01 10 11 PLAELM0 Element 15 Element 2 Element 4 Element 6 Element 1 Element 3 Element 5 Element 7 Access R/W PLAELM1 to PLAELM7 Element 0 Element 2 Element 4 Element 6 Element 1 Element 3 Element 5 Element 7 Rev. A | Page 74 of 96 PLAELM8 Element 7 Element 10 Element 12 Element 14 Element 9 Element 11 Element 13 Element 15 PLAELM9 to PLAELM15 Element 8 Element 10 Element 12 Element 14 Element 9 Element 11 Element 13 Element 15 Data Sheet ADuC7122 Table 119. PLAIRQ Register Name PLAIRQ Address 0xFFFF0B44 Table 123. PLADIN Register Default Value 0x00000000 Access R/W PLAIRQ enables IRQ0 and/or IRQ1 and selects the source of the IRQ. Value 1 0 11:8 0000 0001 1111 7:5 4 3:0 0000 0001 1111 Description Reserved. PLA IRQ1 enable bit. Set by the user to enable the IRQ1 output from PLA. Cleared by the user to disable IRQ1 output from PLA. PLA IRQ1 source. PLA Element 0. PLA Element 1. PLA Element 15. Reserved. PLA IRQ0 enable bit. Set by the user to enable IRQ0 output from PLA. Cleared by the user to disable IRQ0 output from PLA. PLA IRQ0 source. PLA Element 0. PLA Element 1. PLA Element 15. Bit 31:16 15:0 Address 0xFFFF0B48 Default Value 0x00000000 Name PLADOUT 1 0 3:0 0000 0001 1111 Description Reserved. Input bit to Element 15 to Element 0. Address 0xFFFF0B50 Default Value 0x00000000 Access R PLADOUT is a data output MMR for PLA. This register is always updated. Table 126. PLADOUT MMR Bit Descriptions Bit 31:16 15:0 Description Reserved. Output bit from Element 15 to Element 0. Table 127. PLACLK Register Name PLACLK Address 0xFFFF0B40 Default Value 0x00 Access W PLACLK is a PLA lock option. Bit 0 is written only once. When set, it does not allow modification of any of the PLA MMRs, except PLADIN. A PLA tool is provided in the development system to easily configure the PLA. Access R/W Table 122. PLAADC MMR Bit Descriptions Value Access R/W Table 125. PLADOUT Register PLAADC is the PLA source for the ADC start conversion signal. Bit 31:5 4 Default Value 0x00000000 PLADIN is a data input MMR for PLA. Table 121. PLAADC Register Name PLAADC Address 0xFFFF0B4C Table 124. PLADIN MMR Bit Descriptions Table 120. PLAIRQ MMR Bit Descriptions Bit 15:13 12 Name PLADIN Description Reserved. ADC start conversion enable bit. Set by the user to enable ADC start conversion from PLA. Cleared by the user to disable ADC start conversion from PLA. ADC start conversion source. PLA Element 0. PLA Element 1. PLA Element 15. Rev. A | Page 75 of 96 ADuC7122 Data Sheet INTERRUPT SYSTEM 17B There are 27 interrupt sources on the ADuC7122 that are controlled by the interrupt controller. All interrupts are generated from the on-chip peripherals, except for the software interrupt (SWI), which is programmable by the user. The ARM7TDMI CPU core only recognizes interrupts as one of two types: a normal interrupt request (IRQ) and a fast interrupt request (FIQ). All the interrupts can be masked separately. The ADuC7122 contains a vectored interrupt controller (VIC) that supports nested interrupts up to eight levels. The VIC also allows the programmer to assign priority levels to all interrupt sources. Interrupt nesting needs to be enabled by setting the ENIRQN bit in the IRQCONN register. A number of extra MMRs are used when the full vectored interrupt controller is enabled. The control and configuration of the interrupt system is managed through a number of interrupt-related registers. The bits in each IRQ and FIQ register represent the same interrupt source, as described in Table 128. IRQSTA/FIQSTA should be saved immediately upon entering the interrupt service routine (ISR) to ensure that all valid interrupt sources are serviced. Table 128. IRQ/FIQ1 MMRs Bit Designations Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 1 Description All interrupts OR’ed (FIQ only) Software interrupt Timer0 Timer1 Timer2 or wake-up timer Timer3 or watchdog timer Timer4 Reserved PSM Undefined Flash Control 0 Flash Control 1 ADC UART SPI I2C0 master IRQ I2C0 slave IRQ I2C1 master IRQ I2C1 slave IRQ XIRQ0 (GPIO IRQ0 ) XIRQ1 (GPIO IRQ1) XIRQ2 (GPIO IRQ2 ) XIRQ3 (GPIO IRQ3) PWM XIRQ4 (GPIO IRQ4 ) XIRQ5 (GPIO IRQ5) PLA IRQ0 PLA IRQ1 Comments This bit is set if any FIQ is active User programmable interrupt source General-Purpose Timer0 General-Purpose Timer1 General-Purpose Timer2 or wake-up timer General-Purpose Timer3 or watchdog timer General-Purpose Timer4 Reserved Power supply monitor This bit is not used Flash controller for Block 0 interrupt Flash controller for Block 1 interrupt ADC interrupt source bit UART interrupt source bit SPI interrupt source bit I2C master interrupt source bit I2C slave interrupt source bit I2C master interrupt source bit I2C slave interrupt source bit External Interrupt 0 External Interrupt 1 External Interrupt 2 External Interrupt 3 PWM trip interrupt source bit External Interrupt 4 External Interrupt 5 PLA Block 0 IRQ bit PLA Block 1 IRQ bit Applies to IRQEN, FIQEN, IRQCLR, FIQCLR, IRQSTA, and FIQSTA registers. Rev. A | Page 76 of 96 Data Sheet ADuC7122 IRQSTA IRQ 142B 72B IRQSTA is a read-only register that provides the current enabled IRQ source status (effectively a logic AND of the IRQSIG and IRQEN bits). When set to 1, that source generates an active IRQ request to the ARM7TDMI core. There is no priority encoder or interrupt vector generation. This function is implemented in software in a common interrupt handler routine. The IRQ is the exception signal to enter the IRQ mode of the processor. It services general-purpose interrupt handling of internal and external events. All 32 bits are logically OR’ed to create a single IRQ signal to the ARM7TDMI core. The four 32-bit registers dedicated to IRQ are IRQSIG, IRQEN, IRQCLR, and IRQSTA. IRQSTA Register IRQSIG 18B 139B Name: IRQSTA Address: 0xFFFF0000 Default Value: 0x00000000 Access: Read only IRQSIG reflects the status of the different IRQ sources. If a peripheral generates an IRQ signal, the corresponding bit in the IRQSIG is set; otherwise, it is cleared. The IRQSIG bits clear when the interrupt in the particular peripheral is cleared. All IRQ sources can be masked in the IRQEN MMR. IRQSIG is read only. IRQSIG Register FAST INTERRUPT REQUEST (FIQ) 178B Name: IRQSIG Address: 0xFFFF0004 Default Value: 0x00000000 Access: Read only 73B The fast interrupt request (FIQ) is the exception signal to enter the FIQ mode of the processor. It is provided to service data transfer or communication channel tasks with low latency. The FIQ interface is identical to the IRQ interface and provides the second level interrupt (highest priority). Four 32-bit registers are dedicated to FIQ: FIQSIG, FIQEN, FIQCLR, and FIQSTA. IRQEN Bit 31 to Bit 1 of FIQSTA are logically OR’ed to create the FIQ signal to the core and to Bit 0 of both the FIQ and IRQ registers (FIQ source). 140B IRQEN provides the value of the current enable mask. When a bit is set to 1, the corresponding source request is enabled to create an IRQ exception. When a bit is set to 0, the corresponding source request is disabled or masked, which does not create an IRQ exception. The IRQEN register cannot be used to disable an interrupt. The logic for FIQEN and FIQCLR does not allow an interrupt source to be enabled in both IRQ and FIQ masks. A bit set to 1 in FIQEN clears, as a side effect, the same bit in IRQEN. Likewise, a bit set to 1 in IRQEN clears, as a side effect, the same bit in FIQEN. An interrupt source can be disabled in both IRQEN and FIQEN masks. IRQEN Register 179B Name: IRQEN Address: 0xFFFF0008 Default Value: 0x00000000 Access: Read/write FIQSIG 143B FIQSIG reflects the status of the different FIQ sources. If a peripheral generates an FIQ signal, the corresponding bit in the FIQSIG is set; otherwise, it is cleared. The FIQSIG bits are cleared when the interrupt in the particular peripheral is cleared. All FIQ sources can be masked in the FIQEN MMR. FIQSIG is read only. IRQCLR 14B IRQCLR is a write-only register that allows the IRQEN register to clear to mask an interrupt source. Each bit that is set to 1 clears the corresponding bit in the IRQEN register without affecting the remaining bits. The pair of registers, IRQEN and IRQCLR, allows independent manipulation of the enable mask without requiring an atomic read-modify-write. IRQCLR Register 180B Name: IRQCLR Address: 0xFFFF000C Default Value: 0x00000000 Access: Write only FIQSIG Register 182B Name: FIQSIG Address: 0xFFFF0104 Default Value: 0x00000000 Access: Read only Rev. A | Page 77 of 96 ADuC7122 Data Sheet FIQEN FIQEN provides the value of the current enable mask. When a bit is set to 1, the corresponding source request is enabled to create an FIQ exception. When a bit is set to 0, the corresponding source request is disabled or masked, which does not create an FIQ exception. The FIQEN register cannot be used to disable an interrupt. The 32-bit register dedicated to software interrupt is SWICFG, described in Table 129. This MMR allows the control of a programmed source interrupt. Table 129. SWICFG MMR Bit Designations Bit 31 to 3 2 FIQEN Register 183B Name: FIQEN Address: 0xFFFF0108 Default Value: 0x00000000 Access: Read/write 1 0 Description Reserved. Programmed Interrupt FIQ. Setting/clearing this bit corresponds to setting/clearing Bit 1 of FIQSTA and FIQSIG. Programmed Interrupt IRQ. Setting/clearing this bit corresponds to setting/clearing Bit 1 of IRQSTA and IRQSIG. Reserved. Any interrupt signal must be active for at least the minimum interrupt latency time to be detected by the interrupt controller and by the user in the IRQSTA/FIQSTA register. FIQCLR FIQCLR is a write-only register that allows the FIQEN register to clear to mask an interrupt source. Each bit that is set to 1 clears the corresponding bit in the FIQEN register without affecting the remaining bits. The pair of registers, FIQEN and FIQCLR, allows independent manipulation of the enable mask without requiring an atomic read-modify-write. PROGRAMMABLE PRIORITY PER INTERRUPT (IRQP0/IRQP1/IRQP2) IRQ_SOURCE FIQ_SOURCE INTERNAL ARBITER LOGIC POINTER TO FUNCTION (IRQVEC) FIQCLR Register 184B FIQCLR Address: 0xFFFF010C Default Value: 0x00000000 Access: Write only INTERRUPT VECTOR BIT 31 TO BIT 22 TO BIT 7 (IRQBASE) BIT 23 UNUSED BIT 6 TO BIT 1 TO BIT 2 BIT 0 HIGHEST LSB PRIORITY ACTIVE IRQ 08755-037 Name: Figure 36. Interrupt Structure FIQSTA Vectored Interrupt Controller (VIC) FIQSTA is a read-only register that provides the current enabled FIQ source status (effectively a logic AND of the FIQSIG and FIQEN bits). When set to 1, that source generates an active FIQ request to the ARM7TDMI core. There is no priority encoder or interrupt vector generation. This function is implemented in software in a common interrupt handler routine. FIQSTA Register The ADuC7122 incorporates an enhanced interrupt control system or vectored interrupt controller. The vectored interrupt controller for IRQ interrupt sources is enabled by setting Bit 0 of the IRQCONN register. Similarly, Bit 1 of IRQCONN enables the vectored interrupt controller for the FIQ interrupt sources. The vectored interrupt controller provides the following enhancements to the standard IRQ/FIQ interrupts: Name: FIQSTA Address: 0xFFFF0100 Default Value: 0x00000000 Access: Read only 185B Programmed Interrupts Because the programmed interrupts are not maskable, they are controlled by another register (SWICFG) that writes into both IRQSTA and IRQSIG registers and/or the FIQSTA and FIQSIG registers at the same time. Rev. A | Page 78 of 96 Vectored interrupts—allow a user to define separate interrupt service routine addresses for every interrupt source. This is achieved by using the IRQBASE and IRQVEC registers. IRQ/FIQ interrupts—can be nested up to eight levels depending on the priority settings. An FIQ still has a higher priority than an IRQ. Therefore, if the VIC is enabled for both the FIQ and IRQ and prioritization is maximized, then it is possible to have 16 separate interrupt levels. Programmable interrupt priorities—using the IRQP0 to IRQP2 registers, an interrupt source can be assigned an interrupt priority level value between 1 and 8. Data Sheet ADuC7122 VIC MMRs IRQBASE Register Priority Registers IRQP0 Register 149B 15B 186B 187B The vector base register, IRQBASE, is used to point to the start address of memory used to store 32 pointer addresses. These pointer addresses are the addresses of the individual interrupt service routines. Name: IRQBASE Address: 0xFFFF0014 Default Value: 0x00000000 Access: Read and write Name: IRQP0 Address: 0xFFFF0020 Default Value: 0x00000000 Access: Read and write Table 132. IRQP0 MMR Bit Designations Bit 31:27 26:24 Name Reserved T4PI 23 22:20 Reserved T3PI 19 18:16 Reserved T2PI The IRQ interrupt vector register, IRQVEC points to a memory address containing a pointer to the interrupt service routine of the currently active IRQ. This register should only be read when an IRQ occurs and IRQ interrupt nesting has been enabled by setting Bit 0 of the IRQCONN register. 15 14:12 Reserved T1PI 11 10:8 Reserved T0PI Name: IRQVEC Address: 0xFFFF001C 7 6:4 Reserved SWINTP Default Value: 0x00000000 3:0 Reserved Access: Read only Table 130. IRQBASE MMR Bit Designations Bit 31:16 15:0 Type Read only R/W Initial Value Reserved 0 Description Always read as 0 Vector base address IRQVEC Register 150B Description Reserved bit. A priority level of 0 to 7 can be set for Timer4. Reserved bit. A priority level of 0 to 7 can be set for Timer3. Reserved bit. A priority level of 0 to 7 can be set for Timer2. Reserved bit. A priority level of 0 to 7 can be set for Timer1. Reserved bit. A priority level of 0 to 7 can be set for Timer0. Reserved bit. A priority level of 0 to 7 can be set for the software interrupt source. Interrupt 0 cannot be prioritized. IRQP1 Register 18B Table 131. IRQVEC MMR Bit Designations Bit 31:23 22:7 6:2 Type Read only R/W Read only Initial Value 0 0 0 1:0 Reserved 0 Description Always read as 0. IRQBASE register value. Highest priority IRQ source. This is a value between 0 to 27 representing the possible interrupt sources. For example, if the highest currently active IRQ is Timer1, then these bits are 00011. Reserved bits. Name: IRQP1 Address: 0xFFFF0024 Default Value: 0x00000000 Access: Read and write Rev. A | Page 79 of 96 ADuC7122 Data Sheet IRQP3 Register Table 133. IRQP1 MMR Bit Designations Bit 31 30:28 Name Reserved I2C0MPI 27 26:24 Reserved SPIPI 23 22:20 Reserved UARTPI 19 18:16 Reserved ADCPI 15 14:12 Reserved Flash1PI 11 10:8 Reserved Flash0PI 7:3 2:0 Reserved PSMPI 190B Description Reserved bit. A priority level of 0 to 7 can be set for the I2C0 master. Reserved bit. A priority level of 0 to 7 can be set for the SPI. Reserved bit. A priority level of 0 to 7 can be set for the UART. Reserved bit. A priority level of 0 to 7 can be set for the ADC interrupt source. Reserved bit. A priority level of 0 to 7 can be set for the Flash Block 1 controller interrupt source. Reserved bit. A priority level of 0 to 7 can be set for the Flash Block 0 controller interrupt source. Reserved bits. A priority level of 0 to 7 can be set for the Power supply monitor interrupt source. IRQP2 Register Name: IRQP3 Address: 0xFFFF002C Default Value: 0x00000000 Access: Read and write Table 135. IRQP3 MMR Bit Designations Bit 31:15 14:12 11 10:8 7 6:4 3 2:0 Name Reserved PLA1PI Reserved PLA0PI Reserved IRQ5PI Reserved IRQ4PI Description Reserved bit. A priority level of 0 to 7 can be set for PLA0. Reserved bit. A priority level of 0 to 7 can be set for PLA0. Reserved bit. A priority level of 0 to 7 can be set for IRQ5. Reserved bit. A priority level of 0 to 7 can be set for IRQ4. IRQCONN Register 152B The IRQCONN register is the IRQ and FIQ control register. It contains two active bits. The first enables nesting and prioritization of IRQ interrupts and the other enables nesting and prioritization of FIQ interrupts. Name: IRQP2 Address: 0xFFFF0028 If these bits are cleared, then FIQs and IRQs can still be used, but it is not possible to nest IRQs or FIQs. Neither is it possible to set an interrupt source priority level. In this default state, an FIQ does have a higher priority than an IRQ. Default Value: 0x00000000 Name: IRQCONN Access: Read and write Address: 0xFFFF0030 Table 134. IRQP2 MMR Bit Designations Default Value: 0x00000000 Bit 31 30:28 27 26:24 23 22:20 19 18:16 15 14:12 11 10:8 Name Reserved PWMPI Reserved IRQ3PI Reserved IRQ2PI Reserved IRQ1PI Reserved IRQ0PI Reserved I2C1SPI Access: Read and write 7 6:4 Reserved I2C1MPI 3 2:0 Reserved I2C0SPI 189B Description Reserved bit. A priority level of 0 to 7 can be set for PWM. Reserved bit. A priority level of 0 to 7 can be set for IRQ3. Reserved bit. A priority level of 0 to 7 can be set for IRQ2. Reserved bit. A priority level of 0 to 7 can be set for IRQ1. Reserved bit. A priority level of 0 to 7 can be set for IRQ0. Reserved bit. A priority level of 0 to 7 can be set for I2C1 slave. Reserved bit. A priority level of 0 to 7 can be set for I2C1 master. Reserved bit. A priority level of 0 to 7 can be set for I2C0 slave. Table 136. IRQCONN MMR Bit Designations Bit 31:2 Name Reserved 1 ENFIQN 0 ENIRQN Rev. A | Page 80 of 96 Description These bits are reserved and should not be written to. Setting this bit to 1 enables nesting of FIQ interrupts. Clearing this bit means no nesting or prioritization of FIQs is allowed. Setting this bit to 1 enables nesting of IRQ interrupts. Clearing this bit means no nesting or prioritization of IRQs is allowed. Data Sheet ADuC7122 IRQSTAN Register FIQSTAN Register 153B 15B If IRQCONN[0] is asserted and IRQVEC is read, then one of these bits is asserted. The bit that asserts depends on the priority of the IRQ. For example, if the IRQ is of Priority 0 then Bit 0 asserts; if it is Priority 1, then Bit 1 asserts. When a bit is set in this register, all interrupts of that priority and lower are blocked. If IRQCONN[1] is asserted and FIQVEC is read then one of these bits assert. The bit that asserts depends on the priority of the FIQ. For example, if the FIQ is of Priority 0, then Bit 0 asserts; if it is Priority 1, then Bit 1 asserts. To clear a bit in this register, all bits of a higher priority must be cleared first. It is only possible to clear one bit at a time. For example, if this register is set to 0x09, then writing 0xFF changes the register to 0x08, and writing 0xFF a second time changes the register to 0x00. When a bit is set in this register, all interrupts of that priority and lower are blocked. Name: IRQSTAN To clear a bit in this register, all bits of a higher priority must be cleared first. It is only possible to clear one bit as a time. For example, if this register is set to 0x09, then writing 0xFF changes the register to 0x08 and writing 0xFF a second time changes the register to 0x00. Address: 0xFFFF003C Name: FIQSTAN Default Value: 0x00000000 Address: 0xFFFF013C Access: Read and write Default Value: 0x00000000 Access: Read and write Table 137. IRQSTAN MMR Bit Designations Bit 31:8 Name Reserved 7:0 Description These bits are reserved and should not be written to. Setting this bit to 1 enables nesting of FIQ interrupts. Clearing this bit means no nesting or prioritization of FIQs is allowed. Table 139. FIQSTAN MMR Bit Designations Bit 31:8 Name Reserved 7:0 FIQVEC Register 154B The FIQ interrupt vector register, FIQVEC points to a memory address containing a pointer to the interrupt service routine of the currently active FIQ. This register should only be read when an FIQ occurs and FIQ interrupt nesting has been enabled by setting Bit 1 of the IRQCONN register. Name: FIQVEC Address: 0xFFFF011C Default Value: 0x00000000 Access: Read only Description These bits are reserved and should not be written to. Setting this bit to 1 enables nesting of FIQ interrupts. Clearing this bit means no nesting or prioritization of FIQs is allowed. External Interrupts (IRQ0 to IRQ5) 156B The ADuC7122 provides up to six external interrupt sources. These external interrupts can be individually configured as level or rising/falling edge triggered. To enable the external interrupt source, the appropriate bit must first be set in the FIQEN or IRQEN register. To select the required edge or level to trigger on, the IRQCONE register must be appropriately configured. To properly clear an edge based external IRQ interrupt, set the appropriate bit in the IRQCLRE register. IRQCONE Register 19B Table 138. FIQVEC MMR Bit Designations Bit 31:23 22:7 6:2 Type Read only R/W 1:0 Reserved Initial Value 0 0 0 0 Description Always read as 0. IRQBASE register value. Highest priority FIQ source. This is a value between 0 to 27, which represents the possible interrupt sources. For example, if the highest currently active FIQ is Timer1, then these bits are 00011. Reserved bits. Name: IRQCONE Address: 0xFFFF0034 Default Value: 0x00000000 Access: Read and write Rev. A | Page 81 of 96 ADuC7122 Data Sheet Table 140. IRQCONE MMR Bit Designations Bit 31:12 11:10 9:8 7:6 5:4 3:2 1:0 Value 11 10 01 00 11 10 01 00 11 10 01 00 11 10 01 00 11 10 01 00 11 10 01 00 Name Reserved IRQ5SRC[1:0] IRQ4SRC[1:0] IRQ3SRC[1:0] IRQ2SRC[1:0] IRQ1SRC[1:0] IRQ0SRC[1:0] Description These bits are reserved and should not be written to. External IRQ5 triggers on falling edge. External IRQ5 triggers on rising edge. External IRQ5 triggers on low level. External IRQ5 triggers on high level. External IRQ4 triggers on falling edge. External IRQ4 triggers on rising edge. External IRQ4 triggers on low level. External IRQ4 triggers on high level. External IRQ3 triggers on falling edge. External IRQ3 triggers on rising edge. External IRQ3 triggers on low level. External IRQ3 triggers on high level. External IRQ2 triggers on falling edge. External IRQ2 triggers on rising edge. External IRQ2 triggers on low level. External IRQ2 triggers on high level. External IRQ1 triggers on falling edge. External IRQ1 triggers on rising edge. External IRQ1 triggers on low level. External IRQ1 triggers on high level. External IRQ0 triggers on falling edge. External IRQ0 triggers on rising edge. External IRQ0 triggers on low level. External IRQ0 triggers on high level. Rev. A | Page 82 of 96 Data Sheet ADuC7122 In normal mode, an IRQ is generated each time the value of the counter reaches zero if counting down, or full scale if counting up. An IRQ can be cleared by writing any value to the clear register of the particular timer (TxCLRI). IRQCLRE Register 192B Name: IRQCLRE Address: 0xFFFF0038 Default Value: 0x00000000 Access: Write only The event selection feature allows flexible interrupt generation based on Timer0 and Timer1. T0CON and T1CON can be used to configure the interrupt sources, as shown in Table 142. When either Timer0 or Timer1 expires, an interrupt occurs based on the event selection in T0CON and T1CON MMRs. Table 141. IRQCLRE MMR Bit Designations Bit 31:26 Name Reserved 25 IRQ5CLRI 24 IRQ4CLRI 23 Reserved 22 IRQ3CLRI 21 IRQ2CLRI 20 IRQ1CLRI 19 IRQ0CLRI 18:0 Reserved Description These bits are reserved and should not be written to. A 1 must be written to this bit in the IRQ5 interrupt service routine to clear an edge. A 1 must be written to this bit in the IRQ4 interrupt service routine to clear an edge. This bit is reserved and should not be written to. A 1 must be written to this bit in the IRQ3 interrupt service routine to clear an edge triggered IRQ3 interrupt. A 1 must be written to this bit in the IRQ2 interrupt service routine to clear an edge triggered IRQ2 interrupt. A 1 must be written to this bit in the IRQ1 interrupt service routine to clear an edge triggered IRQ1 interrupt. A 1 must be written to this bit in the IRQO interrupt service routine to clear an edge triggered IRQ0 interrupt. These bits are reserved and should not be written to. Table 142. Event Selection Numbers Event Selection (TxCON[16:12]) 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 Interrupt Number 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Name Timer0 Timer1 Wake-up timer (Timer2) Watchdog timer (Timer3) Timer4 Reserved Power supply monitor Undefined Flash Block 0 Flash Block 1 ADC UART SPI I2C0 master I2C0 slave I2C1 master I2C1 slave External IRQ0 HOUR:MINUTE:SECOND:1/128 FORMAT TIMERS 75B 74B The ADuC7122 has five general-purpose timers/counters. • • • • • Timer0 Timer1 Timer2 or wake-up timer Timer3 or watchdog timer Timer4 The five timers in their normal mode of operation can be either free-running or periodic. In free-running mode, the counter decrements/increments from the maximum/minimum value until zero scale/full scale and starts again at the maximum/minimum value. In periodic mode, the counter decrements/increments from the value in the load register (TxLD MMR) until zero scale/full scale and starts again at the value stored in the load register. The value of a counter can be read at any time by accessing its value register (TxVAL). Timers are started by writing in the control register of the corresponding timer (TxCON). To use the timer in hour:minute:second:hundredths format, select the 32,768 kHz clock and prescaler of 256. The hundredths field does not represent milliseconds but 1/128 of a second (256/32,768). The bits representing the hour, minute, and second are not consecutive in the register. This arrangement applies to TxLD and TxVAL when using the hour:minute:second: hundredths format as set in TxCON[5:4]. See Table 143 for additional details. Table 143. Hour:Minnute:Second:Hundredths Format Bit 31:24 23:22 21:16 15:14 13.8 7 6:0 Rev. A | Page 83 of 96 Value 0 to 23 or 0 to 255 0 0 to 59 0 0 to 59 0 0 to 127 Description Hours Reserved Minutes Reserved Seconds Reserved 1/128 second ADuC7122 Data Sheet TIMER0—LIFETIME TIMER Table 147. Timer0 Control Register Timer0 is a general-purpose 48-bit count up or a 16-bit count up/down timer with a programmable prescaler. Timer0 is clocked from the core clock, with a prescaler of 1, 16, 256, or 32,768. This gives a minimum resolution of 22 ns when the core is operating at 41.78 MHz and with a prescaler of 1. Timer0 can also be clocked from the undivided core clock, internal 32 kHz oscillator, or external 32 kHz crystal. Name T0CON 76B In 48-bit mode, Timer0 counts up from zero. The current counter value can be read from T0VAL0 and T0VAL1. In 16-bit mode, Timer0 can count up or count down. A 16-bit value can be written to T0LD that is loaded into the counter. The current counter value can be read from T0VAL0. Timer0 has a capture register (T0CAP) that can be triggered by a selected IRQ’s source initial assertion. When triggered, the current timer value is copied to T0CAP, and the timer keeps running. This feature can be used to determine the assertion of an event with more accuracy than by servicing an interrupt alone. Timer0 reloads the value from T0LD either when TIMER0 overflows or immediately when T0CLRI is written. The Timer0 interface consists of six MMRs, shown in Table 144. Address 0xFFFF030C T0CAP T0VAL0/T0VAL1 T0CLRI T0CON Description 16-bit register that holds the 16-bit value loaded into the counter. Available only in 16-bit mode. 16-bit register that holds the 16-bit value captured by an enabled IRQ event. Available only in 16-bit mode. TOVAL0 is a 16-bit register that holds the 16 least significant bits (LSBs). T0VAL1 is a 32-bit register that holds the 32 most significant bits (MSBs). 8-bit register. Writing any value to this register clears the interrupt. Available only in 16-bit mode. Configuration MMR. Table 148. T0CON MMR Bit Designations Bit 31:18 17 Value 16:12 11 10:9 00 01 10 11 8 7 6 5 4 0 1 3:0 0000 0100 1000 1111 Table 145. Timer0 Value Register Name T0VAL0 T0VAL1 Address 0xFFFF0304 0xFFFF0308 Default Value 0x00, 0x00 Access R R T0VAL0 and T0VAL1 are 16-bit and 32-bit registers that hold the 16 least significant bits and 32 most significant bits, respectively. T0VAL0 and T0VAL1 are read-only. In 16-bit mode, 16-bit T0VAL0 is used. In 48-bit mode, both 16-bit T0VAL0 and 32-bit T0VAL1 are used. Address 0xFFFF0314 Default Value 0x00 Description Reserved. Event select bit. Set by the user to enable time capture of an event. Cleared by the user to disable time capture of an event. Event select (ES) range, 0 to 17. The events are as described in the Timers section. Reserved. Clock select. Internal 32 kHz oscillator. UCLK. External 32 kHz crystal. HCLK. Count up. Available only in 16-bit mode. Set by the user for Timer0 to count up. Cleared by the user for Timer0 to count down (default). Timer0 enable bit. Set by the user to enable Timer0. Cleared by the user to disable Timer0 (default). Timer0 mode. Set by the user to operate in periodic mode. Cleared by the user to operate in free-running mode (default). Reserved. Timer0 mode of operation. 16-bit operation (default). 48-bit operation. Prescaler. Source clock/1 (default). Source clock/16. Source clock/256. Source clock/32,768. Table 149. Timer0 Load Registers Name T0LD Address 0xFFFF0300 Default Value 0x00 Access R/W T0LD is a 16-bit register that holds the 16-bit value that is loaded into the counter; it is available only in 16-bit mode. Table 150. Timer0 Clear Register Table 146. Timer0 Capture Register Name T0CAP Access R/W The 17-bit MMR configures the mode of operation of Timer0. Table 144. Timer0 Interface MMRs Name T0LD Default Value 0x00 Access R This is a 16-bit register that holds the 16-bit value captured by an enabled IRQ event; it is only available in 16-bit mode. Name T0CLRI Address 0xFFFF0310 Default Value 0x00 Access W This 8-bit, write-only MMR is written (with any value) by user code to refresh (reload) Timer0. Rev. A | Page 84 of 96 Data Sheet ADuC7122 TIMER1—GENERAL-PURPOSE TIMER 7B Timer1 is a 32-bit general-purpose timer, count down or count up, with a programmable prescaler. The prescaler source can be from the 32 kHz internal oscillator, the 32 kHz external crystal, the core clock, or from the undivided PLL clock output. This source can be scaled by a factor of 1, 16, 256, or 32,768. This gives a minimum resolution of 42 ns when operating at CD = 0, the core is operating at 41.78 MHz, and with a prescaler of 1. The counter can be formatted as a standard 32-bit value or as hours:minutes:seconds:hundredths. Timer1 has a capture register (T1CAP) that can be triggered by a selected IRQ’s source initial assertion. When triggered, the current timer value is copied to T1CAP, and the timer keeps running. This feature can be used to determine the assertion of an event with increased accuracy. The Timer1 interface consists of five MMRs, as shown in Table 151. T1VAL T1CAP T1CLRI T1CON Description 32-bit register. Holds 32-bit unsigned integers. This register is read only. 32-bit register. Holds 32-bit unsigned integers. 32-bit register. Holds 32-bit unsigned integers. This register is read only. 8-bit register. Writing any value to this register clears the Timer1 interrupt. Configuration MMR. Note that if the part is in a low power mode, and Timer1 is clocked from the GPIO or low power oscillator source, then Timer1 continues to operate. Table 152. Timer1 Load Registers Name Address Default Value Access T1LD 0xFFFF0320 0x00000 R/W T1LD is a 32-bit register that holds the 32-bit value that is loaded into the counter. Table 153. Timer1 Clear Register Name T1CLRI Address 0xFFFF032C Default Value 0x00 Access W This 8-bit, write-only MMR is written (with any value) by user code to refresh (reload) Timer1. Table 154. Timer1 Value Register Name T1VAL Address 0xFFFF0324 Default Value 0x0000 Access R T1VAL is a 32-bit register that holds the current value of Timer1. Table 151. Timer1 Interface Registers Register T1LD Timer1 reloads the value from T1LD either when Timer1 overflows or immediately when T1ICLR is written. Table 155. Timer1 Capture Register Name T1CAP Address 0xFFFF0330 Default Value 0x00 Access R This is a 32-bit register that holds the 32-bit value captured by an enabled IRQ event. Table 156. Timer1 Control Register. Name T1CON Address 0xFFFF0328 Default Value 0x0000 Access R/W This 32-bit MMR configures the mode of operation of Timer1. Rev. A | Page 85 of 96 ADuC7122 Data Sheet Table 157. T1CON MMR Bit Designations Bit 31:24 23 22:20 19 18 17 Value 1 0 16:12 11:9 000 001 010 011 8 1 0 7 1 0 6 1 0 5:4 00 01 10 11 3:0 0000 0100 1000 1111 Description 8-bit postscaler. Enable write to postscaler. Reserved. Postscaler compare flag. T1 interrupt generation selection flag. Event select bit. Set by the user to enable time capture of an event. Cleared by the user to disable time capture of an event. Event select range, 0 to 17. The events are as described in the Timers section. Clock select. Internal 32 kHz oscillator (default). Core clock. UCLK. P0.6. Count up. Set by the user for Timer1 to count up. Cleared by the user for Timer1 to count down (default). Timer1 enable bit. Set by the user to enable Timer1. Cleared by the user to disable Timer1 (default). Timer1 mode. Set by the user to operate in periodic mode. Cleared by the user to operate in free-running mode (default). Format. Binary (default). Reserved. Hr:min:sec:hundredths: 23 hours to 0 hours. Hr:min:sec:hundredths: 255 hours to 0 hours. Prescaler. Source clock/1 (default). Source clock/16. Source clock/256. Source clock/32,768. Rev. A | Page 86 of 96 Data Sheet ADuC7122 TIMER2—WAKE-UP TIMER Table 159. Timer2 Load Registers Timer2 is a 32-bit wake-up timer, count down or count up, with a programmable prescaler. The prescaler is clocked directly from 1 of 4 clock sources, including the core clock (default selection), the internal 32.768 kHz oscillator, the external 32.768 kHz watch crystal, or the PLL undivided clock. The selected clock source can be scaled by a factor of 1, 16, 256, or 32,768. The wake-up timer continues to run when the core clock is disabled. This gives a minimum resolution of 22 ns when the core is operating at 41.78 MHz and with a prescaler of 1. Capture of the current timer value is enabled if the Timer2 interrupt is enabled via IRQEN[4] (see Table 128). Name T2LD 78B Table 160. Timer2 Clear Register Name T2CLRI Address 0xFFFF034C Default Value 0x00 Access W This 8-bit write-only MMR is written (with any value) by user code to refresh (reload) Timer2. Address 0xFFFF0344 Default Value 0x0000 Access R T2VAL is a 32-bit register that holds the current value of Timer2. The Timer2 interface consists of four MMRs, shown in Table 158. Table 162. Timer2 Control Register Name T2CON Table 158. Timer2 Interface Registers T2CON Access R/W T2LD is a 32-bit register, which holds the 32-bit value that is loaded into the counter. Name T2VAL Timer2 reloads the value from T2LD either when Timer2 overflows or immediately when T2ICLR is written. T2CLRI Default Value 0x00000 Table 161. Timer2 Value Register The counter can be formatted as plain 32-bit value or as hours:minutes:seconds:hundredths. Register T2LD T2VAL Address 0xFFFF0340 Description 32-bit register. Holds 32-bit unsigned integers. 32-bit register. Holds 32-bit unsigned integers. This register is read only. 8-bit register. Writing any value to this register clears the Timer2 interrupt. Configuration MMR. Address 0xFFFF0348 Default Value 0x0000 Access R/W This 32-bit MMR configures the mode of operation for Timer2. Rev. A | Page 87 of 96 ADuC7122 Data Sheet Table 163. T2CON MMR Bit Designations Bit 31:11 10:9 Value 00 01 10 11 8 1 0 7 1 0 6 1 0 5:4 00 01 10 11 3:0 0000 0100 1000 1111 Description Reserved. Clock source select. Internal 32.768 kHz oscillator (default). Core clock. External 32.768 kHz watch crystal. UCLK. Count up. Set by the user for Timer2 to count up. Cleared by the user for Timer2 to count down (default). Timer2 enable bit. Set by the user to enable Timer2. Cleared by the user to disable Timer2 (default). Timer2 mode. Set by the user to operate in periodic mode. Cleared by the user to operate in free-running mode (default). Format. Binary (default). Reserved. Hr:min:sec:hundredths. 23 hours to 0 hours. Hr:min:sec:hundredths. 255 hours to 0 hours. Prescaler. Source clock/1 (default). Source clock/16. Source clock/256 (this setting should be used in conjunction with Timer2 Format 10 and Format 11). Source clock/32,768. Rev. A | Page 88 of 96 Data Sheet ADuC7122 Timer3 is automatically halted during JTAG debug access and only recommences counting after JTAG has relinquished control of the ARM7 core. By default, Timer3 continues to count during power-down. This can be disabled by setting Bit 0 in T3CON. It is recommended that the default value is used, that is, the watchdog timer continues to count during power-down. TIMER3—WATCHDOG TIMER 79B 16-BIT LOAD 16-BIT UP/DOWN COUNTER WATCHDOG RESET TIMER3 IRQ TIMER3 VALUE Timer3 Interface 08755-038 PRESCALER 1, 16, OR 256 LOW POWER 32.768kHz 159B Timer3 interface consists of four MMRS as shown in the table below. Figure 37. Timer3 Block Diagram Timer3 has two modes of operation: normal mode and watchdog mode. The watchdog timer is used to recover from an illegal software state. Once enabled, it requires periodic servicing to prevent it from forcing a reset of the processor. Timer3 reloads the value from T3LD either when Timer3 overflows or immediately when T3ICLR is written. Table 164. Timer3 Interface Registers Register T3CON T3LD T3VAL Normal Mode 157B T3ICLR Description The configuration MMR. 6-bit registers (Bit 0 to Bit15); holds 16-bit unsigned integers. 6-bit registers (Bit 0 to Bit 15); holds 16-bit unsigned integers. This register is read only. 8-bit register. Writing any value to this register clears the Timer3 interrupt in normal mode or resets a new timeout period in watchdog mode. The Timer3 in normal mode is identical to Timer0 in 16-bit mode of operation, except for the clock source. The clock source is the 32.768 kHz oscillator and can be scaled by a factor of 1, 16, or 256. Timer3 also features a capture facility that allows capture of the current timer value if the Timer2 interrupt is enabled via IRQEN[5]. Table 165. Timer3 Load Register Watchdog Mode This 16-bit MMR holds the Timer3 reload value. Watchdog mode is entered by setting T3CON[5]. Timer3 decrements from the timeout value present in the T3LD register until 0. The maximum timeout is 512 seconds, using the maximum prescalar/256 and full scale in T3LD. Table 166. Timer3 Value Register 158B User software should only configure a minimum timeout period of 30 milliseconds. This is to avoid any conflict with Flash/EE memory page erase cycles, requiring 20 ms to complete a single page erase cycle and kernel execution. Name T3LD Name T3VAL Address 0xFFFF0360 Address 0xFFFF0364 Default Value 0x03D7 Default Value 0x03D7 Access R/W Access R This 16-bit, read-only MMR holds the currentTimer3 count value. Table 167. Timer3 Clear Register Name T3CLRI If T3VAL reaches 0, a reset or an interrupt occurs, depending on T3CON[1]. To avoid a reset or an interrupt event, any value must be written to T3ICLR before T3VAL reaches zero. This reloads the counter with T3LD and begins a new timeout period. Once watchdog mode is entered, T3LD and T3CON are write protected. These two registers cannot be modified until a power-on reset event resets the watchdog timer. After any other reset event, the watchdog timer continues to count. The watchdog timer should be configured in the initial lines of user code to avoid an infinite loop of watchdog resets. Address 0xFFFF036C Default Value 0x00 Access W This 8-bit, write-only MMR is written (with any value) by user code to refresh (reload), Timer3 in watchdog mode to prevent a watchdog timer reset event. Table 168. Timer3 Control Register Name T3CON Address 0xFFFF0368 Default Value 0x0000 Access R/W once only The 16-bit MMR configures the mode of operation of Timer3 as is described in detail in Table 169. Rev. A | Page 89 of 96 ADuC7122 Data Sheet Table 169. T3CON MMR Bit Designations Bit 16:9 8 Value 1 0 7 1 0 6 1 0 5 1 0 4 1 0 3:2 00 01 10 11 1 1 0 0 1 0 Description These bits are reserved and should be written as 0s by user code. Count up/down enable. Set by user code to configure Timer3 to count up. Cleared by user code to configure Timer3 to count down. Timer3 enable. Set by user code to enable Timer3. Cleared by user code to disable Timer3. Timer3 operating mode. Set by user code to configure Timer3 to operate in periodic mode. Cleared by user to configure Timer3 to operate in free-running mode. Watchdog timer mode enable. Set by user code to enable watchdog mode. Cleared by user code to disable watchdog mode. Secure clear bit. Set by the user to use the secure clear option. Cleared by the user to disable the secure clear option by default. Timer3 clock (32.768 kHz) prescaler. Source clock/1 (default). Reserved. Reserved. Reserved. Watchdog timer IRQ enable. Set by the user code to produce an IRQ instead of a reset when the watchdog reaches 0. Cleared by the user code to disable the IRQ option. PD_OFF. Set by user code to stop Timer3 when the peripherals are powered down via Bits[6:4] in the POWCON MMR. Cleared by user code to enable Timer3 when the peripherals are powered down via Bits[6:4] in the POWCON MMR. Rev. A | Page 90 of 96 Data Sheet ADuC7122 Secure Clear Bit (Watchdog Mode Only) The Timer4 interface consists of five MMRS. The secure clear bit(T3CPM[4]) is provided for a higher level of protection. When set, a specific sequential value must be written to T3CLRI to avoid a watchdog reset. The value is a sequence generated by the 8-bit linear feedback shift register (LFSR) polynomial = X8 + X6 + X5 + X + 1 (see Figure 38). • T4LD, T4VAL, and T4CAP are 32-bit registers and hold 32-bit unsigned integers. T4VAL and T4CAP are read only. • T4ICLR is an 8-bit register. Writing any value to this register clears the Timer1 interrupt. • T4CON is the configuration MMR. 160B The initial value or seed is written to T3ICLR before entering watchdog mode. After entering watchdog mode, a write to T3CLRI must match this expected value. If it matches, the LFSR is advanced to the next state when the counter reload happens. If it fails to match the expected state, a reset is immediately generated, even if the count has not yet expired. Note that if the part is in a low power mode, and Timer4 is clocked from the GPIO or oscillator source, then Timer4 continues to operate. Timer4 reloads the value from T4LD either when Timer 4 overflows or immediately when T4CLRI is written. The value 0x00 should not be used as an initial seed due to the properties of the polynomial. The value 0x00 is always guaranteed to force an immediate reset. The value of the LFSR cannot be read; it must be tracked/generated in software. Table 170. Timer4 Load Registers Name T4LD 2. 3. 4. 5. Enter initial seed, 0xAA, in T3CLRI before starting Timer3 in watchdog mode. Enter 0xAA in T3CLRI; Timer3 is reloaded. Enter 0x37 in T3CLRI; Timer3 is reloaded. Enter 0x6E in T3CLRI; Timer3 is reloaded. Enter 0x66. 0xDC was expected; the watchdog resets the chip. Name T4CLRI Name T4VAL Q D 5 Default Value 0x0000 Name T4CAP Address 0xFFFF0390 Default Value 0x00 Access R Access R This is a 32-bit register that holds the 32-bit value captured by an enabled IRQ event. Table 174. Timer4 Control Register Name T4CON Address 0xFFFF0388 Default Value 0x0000 Access R/W This 32-bit MMR configures the mode of operation of Timer4. Q D 4 Q D 3 Q D 2 Q D 1 Q D 0 08755-039 D Address 0xFFFF0384 Table 173. Timer4 Capture Register Timer4 has a capture register (T4CAP) that can be triggered by a selected IRQ’s source initial assertion. When triggered, the current timer value is copied to T4CAP, and the timer keeps running. This feature can be used to determine the assertion of an event with increased accuracy. 6 Access W T4VAL is a 32-bit register that holds the current value of Timer4. The counter can be formatted as a standard 32-bit value or as hours:minutes:seconds:hundredths. Q Default Value 0x00 Table 172. Timer4Value Register Timer4 is a 32-bit general-purpose timer, count down or count up, with a programmable prescalar. The prescalar source can be the 32 kHz oscillator, the core clock, or the PLL undivided output. This source can be scaled by a factor of 1, 16, 256, or 32,768. This gives a minimum resolution of 42 ns when operating at CD = 0, the core is operating at 41.78 MHz, and with a prescalar of 1 (ignoring external GPIO). D Address 0xFFFF038C This 8-bit, write only MMR is written (with any value) by user code to refresh (reload) Timer4. TIMER4—GENERAL-PURPOSE TIMER 7 Access R/W Table 171. Timer4 Clear Register 80B Q Default Value 0x00000 T4LD is a 32-bit register, which holds the 32-bit value that is loaded into the counter. Example of a sequence: 1. Address 0xFFFF0380 CLOCK Figure 38. 8-Bit LFSR Rev. A | Page 91 of 96 ADuC7122 Data Sheet Table 175. T4CON MMR Bit Designations Bit 31:18 17 Value 1 0 16:12 11:9 000 001 010 011 8 1 0 7 1 0 6 1 0 5:4 00 01 10 11 3:0 0000 0100 1000 1111 Description Reserved. Set by user to 0. Event select bit. Set by the user to enable time capture of an event. Cleared by the user to disable time capture of an event. Event select range, 0 to 31. The events are as described in the Timers section. Clock select. 32.768 kHz oscillator. Core clock. UCLK. UCLK. Count up. Set by the user for Timer4 to count up. Cleared by the user for Timer4 to count down (default). Timer4 enable bit. Set by the user to enable Timer4. Cleared by the user to disable Timer4 (default). Timer4 mode. Set by the user to operate in periodic mode. Cleared by the user to operate in free-running mode (default). Format. Binary (default). Reserved. Hr:min:sec:hundredths: 23 hours to 0 hours. Hr:min:sec:hundredths: 255 hours to 0 hours. Prescaler. Source clock/1 (default). Source clock/16. Source clock/256. Source clock/32,768. Rev. A | Page 92 of 96 Data Sheet ADuC7122 HARDWARE DESIGN CONSIDERATIONS 18B POWER SUPPLIES 81B The ADuC7122 operational power supply voltage range is 3.0 V to 3.6 V. Separate analog and digital power supply pins (AVDD and IOVDD, respectively) allow AVDD to be kept relatively free of noisy digital signals often present on the system IOVDD line. In this mode, the part can also operate with split supplies, that is, using different voltage levels for each supply. For example, the system can be designed to operate with an IOVDD voltage level of 3.3 V while the AVDD level can be at 3 V, or vice versa. A typical split supply configuration is shown in Figure 39. ANALOG SUPPLY DIGITAL SUPPLY 10µF + – Notice that in both Figure 39 and Figure 40, a large value (10 µF) reservoir capacitor sits on IOVDD, and a separate 10 µF capacitor sits on AVDD. In addition, local small-value (0.1 µF) capacitors are located at each AVDD and IOVDD pin of the chip. As per standard design practice, be sure to include all of these capacitors and ensure the smaller capacitors are close to each AVDD pin with trace lengths as short as possible. Connect the ground terminal of each of these capacitors directly to the underlying ground plane. Finally, note that the analog and digital ground pins on the ADuC7122 must be referenced to the same system ground reference point at all times. IOVDD Supply Sensitivity ADuC7122 10µF + – The IOVDD supply is sensitive to high frequency noise because it is the supply source for the internal oscillator and PLL circuits. When the internal PLL loses lock, the clock source is removed by a gating circuit from the CPU, and the ARM7TDMI core stops executing code until the PLL regains lock. This feature ensures that no flash interface timings or ARM7TDMI timings are violated. AVDD IOVDD IOVDD 0.1µF AVDD 0.1µF 0.1µF AVDD 0.1µF AGND Typically, frequency noise greater than 50 kHz and 50 mV p-p on top of the supply causes the core to stop working. IOGND AGND IOGND AGND If decoupling values recommended in the Power Supplies section do not sufficiently dampen all noise sources below 50 mV on IOVDD, a filter such as the one shown in Figure 41 is recommended. AGND AGND 08755-040 AGND 1µH Figure 39. External Dual Supply Connections DIGITAL SUPPLY 10µF + – ANALOG SUPPLY BEAD ADuC7122 IOVDD 10µF 0.1µF AVDD 0.1µF 0.1µF AVDD 0.1µF AGND IOGND AGND IOGND AGND AGND 08755-041 AGND AGND 10µF ADuC7122 IOVDD IOVDD 0.1µF 0.1µF IOGND IOGND Figure 41. Recommended IOVDD Supply Filter AVDD IOVDD DIGITAL + SUPPLY – Figure 40. External Single Supply Connections Rev. A | Page 93 of 96 08755-042 As an alternative to providing two separate power supplies, the user can reduce noise on AVDD by placing a small series resistor and/or ferrite bead between AVDD and IOVDD, and then decouple AVDD separately to ground. An example of this configuration is shown in Figure 40. With this configuration, other analog circuitry (such as op amps, voltage reference, and others) can be powered from the AVDD supply line as well. ADuC7122 Data Sheet Linear Voltage Regulator Each ADuC7122 requires a single 3.3 V supply, but the core logic requires a 2.6 V supply. An on-chip linear regulator generates the 2.6 V from IOVDD for the core logic. The LVDD pins are the 2.6 V supply for the core logic. An external compensation capacitor of 0.47 µF must be connected between each LVDD and DGND (as close as possible to these pins) to act as a tank of charge as shown in Figure 42. An internal LDO provides a stable 2.5 V supply. The REG_PWR pin is the 2.5 V supply output. An external compensation capacitor of 0.47 µF must be connected between REG_PWR and DGND (as close as possible to these pins) to act as a tank of charge as shown in Figure 42. a. b. PLACE ANALOG COMPONENTS HERE PLACE DIGITAL COMPONENTS HERE AGND DGND PLACE ANALOG COMPONENTS HERE PLACE DIGITAL COMPONENTS HERE AGND DGND PLACE ANALOG COMPONENTS HERE PLACE DIGITAL COMPONENTS HERE ADuC7122 LVDD 0.47µF DGND c. LVDD DGND DGND 0.47µF Figure 43. System Grounding Schemes 08755-043 REG_PWR 08755-044 0.47µF Figure 42. Voltage Regulator Connections The LVDD pins should not be used for any other chip. It is also recommended to use excellent power supply decoupling on IOVDD to help improve line regulation performance of the on-chip voltage regulator. GROUNDING AND BOARD LAYOUT RECOMMENDATIONS As with all high resolution data converters, special attention must be paid to grounding and PC board layout of ADuC7122based designs to achieve optimum performance from the ADCs and DAC. Although the part has separate has separate pins for analog and digital ground (AGND and IOGND), the user must not tie these to two separate ground planes unless the two ground planes are connected very close to the part. This is illustrated in the simplified example shown in Figure 43a. In systems where digital and analog ground planes are connected together somewhere else (at the system’s power supply, for example), the planes can not be reconnected near the part, because a ground loop would result. In these cases, tie all the AGND and IOGND pins of the ADuC7122 to the analog ground plane, as illustrated in Figure 43b. In systems with only one ground plane, ensure that the digital and analog components are physically separated onto separate halves of the board so that digital return currents do not flow near analog circuitry and vice versa. The ADuC7122 can then be placed between the digital and analog sections, as illustrated in Figure 43c. In all of these scenarios, and in more complicated real-life applications, pay particular attention to the flow of current from the supplies and back to ground. Make sure the return paths for all currents are as close as possible to the paths the currents took to reach their destinations. For example, do not power components on the analog side, as seen in Figure 43b, with IOVDD because that would force return currents from IOVDD to flow through AGND. Also, avoid digital currents flowing under analog circuitry, which could occur if a noisy digital chip is placed on the left half of the board shown in Figure 43c. If possible, avoid large discontinuities in the ground plane(s) (such as those formed by a long trace on the same layer), because they force return signals to travel a longer path. In addition, make all connections to the ground plane directly, with little or no trace separating the pin from its via to ground. When connecting fast logic signals (rise/fall time < 5 ns) to any of the ADuC7122 digital inputs, add a series resistor to each relevant line to keep rise and fall times longer than 5 ns at the input pins of the part. A value of 100 Ω or 200 Ω is usually sufficient enough to prevent high speed signals from coupling capacitively into the part and affecting the accuracy of ADC conversions. Rev. A | Page 94 of 96 Data Sheet ADuC7122 The clock source for the ADuC7122 can be generated by the internal PLL or by an external clock input. To use the internal PLL, connect a 32.768 kHz parallel resonant crystal between XTALI and XTALO, and connect a capacitor from each pin to ground as shown Figure 44. This crystal allows the PLL to lock correctly to give a frequency of 41.78 MHz. If no external crystal is present, the internal oscillator is used to give a frequency of 41.78 MHz ±3% typically. To use an external source clock input instead of the PLL (see Figure 45), Bit 1 and Bit 0 of PLLCON must be modified.The external clock uses P1.4 and XCLK. ADuC7122 XTALO XTALI EXTERNAL CLOCK SOURCE 12pF XTALO 08755-045 32.768kHz TO INTERNAL PLL TO FREQUENCY DIVIDER Figure 45. Connecting an External Clock Source ADuC7122 XTALI 12pF XCLK 08755-046 CLOCK OSCILLATOR Using an external clock source, the ADuC7122 specified operational clock speed range is 50 kHz to 41.78 MHz ±1% to ensure correct operation of the analog peripherals and Flash/EE. Figure 44. External Parallel Resonant Crystal Connections Rev. A | Page 95 of 96 ADuC7122 Data Sheet OUTLINE DIMENSIONS A1 BALL CORNER 7.10 7.00 SQ 6.90 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M BALL A1 PAD CORNER 5.50 BSC SQ 0.50 BSC BOTTOM VIEW TOP VIEW DETAIL A *1.40 MAX *1.11 MAX DETAIL A 0.15 MIN COPLANARITY 0.08 SEATING PLANE *COMPLIANT WITH JEDEC STANDARDS MO-195-BD WITH EXCEPTION TO PACKAGE HEIGHT AND THICKNESS. 090408-A 0.35 0.30 0.25 BALL DIAMETER Figure 46. 108-Ball Chip Scale Package Ball Grid Array [CSP_BGA] (BC-108-4) Dimensions shown in millimeters ORDERING GUIDE Model1 ADuC7122BBCZ ADuC7122BBCZ-RL EVAL-ADUC7122QSPZ 1 Temperature Range −10°C to +95°C −10°C to +95°C Package Description 108-Ball Chip Scale Package Ball Grid Array [CSP_BGA] 108-Ball Chip Scale Package Ball Grid Array [CSP_BGA], 13” Tape and Reel ADuC7122 Quickstart Plus Development System Z = RoHS Compliant Part. I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2010–2014 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08755-0-11/14(A) Rev. A | Page 96 of 96 Package Option BC-108-4 BC-108-4