Elpida EDS1232CATA 128m bits sdram Datasheet

DATA SHEET
128M bits SDRAM
EDS1232CATA (4M words × 32 bits)
Description
Pin Configurations
/xxx indicate active low signal.
86-pin Plastic TSOP(II)
EO
The EDS1232CA is a 128M bits SDRAM organized as
1,048,576 words × 32 bits × 4 banks. All inputs and
outputs are synchronized with the positive edge of the
clock.
It is packaged in 86-pin plastic TSOP (II).
Features
•
•
•
•
•
L
2.5V power supply
Clock frequency: 100MHz (max.)
Single pulsed /RAS
×32 organization
4 banks can operate simultaneously and
independently
• Burst read/write operation and burst read/single write
operation capability
• Programmable burst length (BL): 1, 2, 4, 8 and full
page
• 2 variations of burst sequence
⎯ Sequential (BL = 1, 2, 4, 8, full page)
⎯ Interleave (BL = 1, 2, 4, 8)
• Programmable /CAS latency (CL): 2, 3
• Byte control by DQM
• Refresh cycles: 4096 refresh cycles/64ms
• 2 variations of refresh
⎯ Auto refresh
⎯ Self refresh
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
od
Pr
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
VDD
DQM0
/WE
/CAS
/RAS
/CS
A11
BA0
BA1
A10(AP)
A0
A1
A2
DQM2
VDD
NC
DQ16
VSSQ
DQ17
DQ18
VDDQ
DQ19
DQ20
VSSQ
DQ21
DQ22
VDDQ
DQ23
VDD
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
VSS
DQM1
NC
NC
CLK
CKE
A9
A8
A7
A6
A5
A4
A3
DQM3
VSS
NC
DQ31
VDDQ
DQ30
DQ29
VSSQ
DQ28
DQ27
VDDQ
DQ26
DQ25
VSSQ
DQ24
VSS
(Top view)
Address inputs
Bank select
DQ0 to DQ31 Data input/output
Chip select
/CS
Row address strobe
/RAS
/CAS
Column address strobe
/WE
Write enable
A0 to A11,
BA0, BA1
DQM0 to DQM3 DQ mask enable
CKE
CLK
VDD
VSS
Supply voltage
Ground
Supply voltage for DQ
t
uc
VDDQ
VSSQ
Clock enable
Clock input
NC
Document No. E0388E11 (Ver. 1.1)
Date Published May 2003 (K) Japan
URL: http://www.elpida.com
Ground for DQ
No connection
This product became EOL in March, 2007.
©Elpida Memory, Inc. 2003
EDS1232CATA
Ordering Information
Part number
Supply
voltage
Organization
(words × bits) Internal Banks
Clock frequency
MHz (max.)
/CAS latency
Package
EDS1232CATA-1A
2.5V
4M × 32
100
2, 3
86-pin plastic
4
EDS1232CATA-1AL
TSOP (II)
Part Number
E D S 12 32 C A TA - 1A L
EO
Elpida Memory
Type
D: Monolithic Device
Spec. Detail
Blank: Normal
L: Low Power
Product Code
S: SDRAM
Density / Bank
12: 128M / 4-bank
Speed
1A: 100MHz/CL2,3
Bit Organization
32: x32
L
Voltage, Interface
C: 2.5V, LVTTL
Die Rev.
Package
TA: TSOP (II)
t
uc
od
Pr
Data Sheet E0388E11 (Ver. 1.1)
2
EDS1232CATA
CONTENTS
Description .................................................................................................................................................... 1
Features ........................................................................................................................................................ 1
Pin Configurations......................................................................................................................................... 1
Ordering Information ..................................................................................................................................... 2
Part Number.................................................................................................................................................. 2
Electrical Specifications ................................................................................................................................ 4
Block Diagram............................................................................................................................................... 9
Pin Function ................................................................................................................................................ 10
Command Operation................................................................................................................................... 11
EO
Truth Table.................................................................................................................................................. 15
Simplified State Diagram ............................................................................................................................ 21
Programming Mode Registers .................................................................................................................... 22
Mode Register............................................................................................................................................. 23
Power-up sequence .................................................................................................................................... 26
Operation of the SDRAM ............................................................................................................................ 27
Timing Waveforms ...................................................................................................................................... 43
Package Drawing........................................................................................................................................ 50
L
Recommended Soldering Conditions ......................................................................................................... 51
t
uc
od
Pr
Data Sheet E0388E11 (Ver. 1.1)
3
EDS1232CATA
Electrical Specifications
• All voltages are referenced to VSS (GND).
• After power up, execute power up sequence and initialization sequence before proper device operation is achieved
(refer to the Power up sequence).
Absolute Maximum Ratings
Symbol
Rating
Unit
Voltage on any pin relative to VSS
VT
–0.5 to +3.6
V
Supply voltage relative to VSS
VDD, VDDQ
–0.5 to +3.6
V
Short circuit output current
IOS
50
mA
Power dissipation
PD
1.0
W
Operating ambient temperature
TA
0 to +70
°C
Storage temperature
Tstg
–55 to +125
°C
EO
Parameter
Note
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended DC Operating Conditions (TA = 0 to +70°C)
Supply voltage
Symbol
min.
typ.
max.
Unit
VDD, VDDQ
2.3
2.5
2.7
V
VSS
0
0
0
L
Parameter
Notes
V
Input high voltage
VIH
1.7
⎯
VDD + 0.3*
V
Input low voltage
VIL
–0.3
⎯
0.7
V
1
t
uc
od
Pr
Notes: 1. VIH (max.) = VDDQ + 1.5V (pulse width ≤ 5ns).
2. VIL (min.) = –1.5V (pulse width ≤ 5ns).
Data Sheet E0388E11 (Ver. 1.1)
4
EDS1232CATA
DC Characteristics 1 (TA = 0 to +70°C, VDD, VDDQ = 2.5V±0.2V, VSS, VSSQ = 0V)
Parameter
/CAS latency
Symbol
Operating current
(CL = 2)
max.
Unit
IDD1
100
mA
(CL = 3)
IDD1
100
mA
Standby current in power down
IDD2P
1
mA
Standby current in power down
(input signal stable)
IDD2PS
1
mA
Standby current in non power
down
EO
Standby current in non power
down
(input signal stable)
Active standby current in power
down
Active standby current in power
down (input signal stable)
Active standby current in non
power down
Grade
Test condition
Burst length = 1
tRC ≥ tRC (min.)
IO = 0mA
One bank active
1
CKE ≤ VIL (max.) tCK = 15ns
CKE ≤ VIL (max.) tCK = ∞
IDD2N
20
mA
CKE ≥ VIH (min.) tCK = 15ns
CS ≥ VIH (min.)
Input signals are changed one
time during 30ns
IDD2NS
8
mA
CKE ≥ VIH (min.) tCK = ∞
IDD3P
5
mA
CKE ≤ VIL (max.) tCK = 15ns
IDD3PS
4
mA
CKE ≤ VIL (max.), tCK = ∞
25
mA
CKE ≥ VIH (min.), tCK = 15 ns,
/CS ≥ VIH (min.),
Input signals are changed one
time during 30ns.
IDD3N
Notes
L
IDD3NS
15
mA
CKE ≥ VIH (min.), tCK = ∞,
Burst operating current
IDD4
130
mA
tCK ≥ tCK (min.),
IO = 0mA, All banks active
2
Refresh current
IDD5
200
mA
tRC ≥ tRC (min.)
3
2.0
mA
VIH ≥ VDD − 0.2V,
VIL ≤ GND + 0.2V
0.6
mA
Pr
Active standby current in non
power down
(input signal stable)
Self refresh current
IDD6
Self refresh current
(L-version)
IDD6
-xxL
od
Notes: 1. IDD1 depends on output loading and cycle rates. Specified values are obtained with the output open. In
addition to this, IDD1 is measured condition that addresses are changed only one time during tCK (min.).
2. IDD4 depends on output loading and cycle rates. Specified values are obtained with the output open.
In addition to this, IDD4 is measured condition that addresses are changed only one time during tCK
(min.).
3. IDD5 is measured on condition that addresses are changed only one time during tCK (min.).
DC Characteristics 2 (TA = 0 to +70°C, VDD, VDDQ = 2.5V±0.2V, VSS, VSSQ = 0V)
Symbol
min.
max.
Unit
Test condition
Input leakage current
ILI
–1.0
1.0
µA
0 = VIN = VDDQ, VDDQ = VDD,
All other pins not under test = 0V
Output leakage current
Output high voltage
ILO
–1.5
1.5
µA
0 = VIN = VDDQ DOUT is disabled
VOH
2.0
—
V
IOH = –1mA
Output low voltage
VOL
—
0.4
V
IOL = 1mA
Data Sheet E0388E11 (Ver. 1.1)
5
Notes
t
uc
Parameter
EDS1232CATA
Pin Capacitance (TA = 25°C, f = 1MHz)
Parameter
Symbol Pins
min.
Typ
max.
Unit
Input capacitance
CI1
Address
2.5
—
4.0
pF
CI2
CLK, CKE, /CS, /RAS,
2.5
/CAS, /WE, DQM
—
4.0
pF
CI/O
DQ
—
6.5
pF
Data input/output
capacitance
4.0
Notes
AC Characteristics (TA = 0 to +70°C, VDD, VDDQ = 2.5V±0.2V, VSS, VSSQ = 0V)
-1A
Parameter
min.
max.
Unit
System clock cycle time
(CL = 2)
tCK
10
—
ns
(CL = 3)
tCK
10
—
ns
CLK high pulse width
tCH
3
—
ns
CLK low pulse width
tCL
3
—
ns
Access time from CLK
tAC
—
6
ns
Data-out hold time
tOH
2
—
ns
CLK to Data-out low impedance
tLZ
0
—
ns
CLK to Data-out high impedance
tHZ
2
6
ns
Input setup time
tSI
2
—
ns
tHI
1
—
ns
CKE setup time (Power down exit)
tCKSP
2
—
ns
ACT to REF/ACT command period
(operation)
tRC
70
⎯
ns
tRC
70
⎯
ns
tRAS
50
120000
ns
Active command to column command (same bank) tRCD
20
⎯
ns
Input hold time
L
EO
Symbol
Pr
(refresh)
Active to Precharge command period
20
⎯
ns
tDPL
20
⎯
ns
Last data into active latency
tDAL
Active (a) to Active (b) command period
tRRD
Mode register set cycle time
tRSC
Transition time (rise and fall)
tT
Refresh period
(4096 refresh cycles)
tREF
od
tRP
Write recovery or data-in to precharge lead time
Precharge to active command period
2CLK + 20ns
Notes
—
20
—
ns
2
⎯
CLK
0.5
30
ns
—
64
ms
t
uc
Data Sheet E0388E11 (Ver. 1.1)
6
EDS1232CATA
Test Conditions
• AC high level input voltage / low level input voltage: 2.1V / 0.3V
• Input timing measurement reference level: 1.2V
• Transition time (Input rise and fall time): 1ns
• Output timing measurement reference level: 1.2V
• Termination voltage (Vtt): 1.2V
tCK
tCH
CLK
tCL
2.1V
1.2V
0.3V
EO
tSETUP tHOLD
Input
2.1V
1.2V
0.3V
tAC
tOH
Output
L
Vtt
Z = 50 Ω
50 Ω
Output
Pr
30pF
Input Waveforms and Output Load
t
uc
od
Data Sheet E0388E11 (Ver. 1.1)
7
EDS1232CATA
Relationship Between Frequency and Minimum Latency
Parameter
-1A
Frequency (MHz)
100
77
Symbol
10
13
Unit
Notes
lRCD
2
2
tCK
1
lRC
7
6
tCK
1
lRAS
5
4
tCK
1
lRP
2
2
tCK
1
lDPL
2
2
tCK
1
lRRD
2
2
tCK
1
Self refresh exit time
lSREX
1
1
tCK
2
Last data in to active command
(Auto precharge, same bank)
lDAL
4
4
tCK
= [lDPL + lRP]
Self refresh exit to command input
lSEC
7
6
tCK
= [lRC]
3
Precharge command to high impedance
(CL = 2)
lHZP
2
2
tCK
(CL = 3)
lHZP
3
3
tCK
lAPR
1
1
tCK
lEP
–1
–1
tCK
lEP
–2
–2
Column command to column command
lCCD
1
1
tCK
Write command to data in latency
lWCD
0
0
tCK
lDID
0
0
tCK
lDOD
2
2
tCK
1
tCK
tCK (ns)
L
EO
Active command to column command
(same bank)
Active command to active command
(same bank)
Active command to precharge command
(same bank)
Precharge command to active command
(same bank)
Write recovery or data-in to precharge
command (same bank)
Active command to active command
(different bank)
Last data out to active command
(Auto precharge, same bank)
Last data out to precharge
(early precharge)
(CL = 2)
DQM to data in
DQM to data out
CKE to CLK disable
tCK
2
2
tCK
0
tCK
1
tCK
lCLE
1
Register set to active command
lMRD
/CS to command disable
lCDD
0
Power down exit to command input
lPEC
1
od
Pr
(CL = 3)
Notes: 1. lRCD to lRRD are recommended value.
2. Be valid [DESL] or [NOP] at next command of self refresh exit.
3. Except [DESL] and [NOP]
t
uc
Data Sheet E0388E11 (Ver. 1.1)
8
EDS1232CATA
Block Diagram
CLK
CKE
Clock
Generator
Bank 3
Bank 2
Bank 1
Mode
Register
Data Control Circuit
Input & Output
Buffer
/WE
DQM
Column Decoder &
Latch Circuit
Column
Address
Buffer
&
Burst
Counter
Latch Circuit
/CAS
Bank 0
Sense Amplifier
Control Logic
/RAS
Command Decoder
EO
/CS
Row
Address
Buffer
&
Refresh
Counter
Row Decoder
Address
DQ
L
t
uc
od
Pr
Data Sheet E0388E11 (Ver. 1.1)
9
EDS1232CATA
Pin Function
CLK (input pin)
CLK is the master clock input. Other inputs signals are referenced to the CLK rising edge.
CKE (input pins)
CKE determine validity of the next CLK (clock). If CKE is high, the next CLK rising edge is valid; otherwise it is
invalid. If the CLK rising edge is invalid, the internal clock is not issued and the Synchronous DRAM suspends
operation.
When the Synchronous DRAM is not in burst mode and CKE is negated, the device enters power down mode.
During power down mode, CKE must remain low.
EO
/CS (input pins)
/CS low starts the command input cycle. When /CS is high, commands are ignored but operations continue.
/RAS, /CAS, and /WE (input pins)
/RAS, /CAS and /WE have the same symbols on conventional DRAM but different functions. For details, refer to the
command table.
L
A0 to A11 (input pins)
Row Address is determined by A0 to A11 at the CLK (clock) rising edge in the active command cycle.
Column Address is determined by A0 to 7 at the CLK rising edge in the read or write command cycle.
A10 defines the precharge mode. When A10 is high in the precharge command cycle, all banks are precharged;
when A10 is low, only the bank selected by BA0 and BA1 is precharged.
When A10 is high in read or write command cycle, the precharge starts automatically after the burst access.
[Bank Select Signal Table]
Pr
BA0 and BA1 (input pin)
BA0 and BA1 are bank select signal. (See Bank Select Signal Table)
BA0
Bank 0
Bank 1
Bank 2
Remark: H: VIH. L: VIL.
L
L
H
L
L
H
H
od
Bank 3
BA1
H
DQ0 to DQ31 (input/output pins)
DQ pins have the same function as I/O pins on a conventional DRAM.
t
uc
DQM (input pins)
DQM controls I/O buffers. DQM0 controls DQ0 to 7, DQM1 controls DQ8 to DQ15, DQM2 controls DQ16 to DQ23,
DQM3 controls DQ24 to DQ31. In read mode, DQM controls the output buffers like a conventional /OE pin. DQM
high and DQM low turn the output buffers off and on, respectively. The DQM latency for the read is two clocks. In
write mode, DQM controls the word mask. Input data is written to the memory cell if DQM is low but not if DQM is
high. The DQM latency for the write is zero.
VDD, VSS, VDDQ, VSSQ (Power supply)
VDD and VSS are power supply pins for internal circuits. VDDQ and VSSQ are power supply pins for the output
buffers.
Data Sheet E0388E11 (Ver. 1.1)
10
EDS1232CATA
Command Operation
Mode register set command (/CS, /RAS, /CAS, /WE)
The Synchronous DRAM has a mode register that defines how the device operates. In this command, A0 through
A11 are the data input pins. After power on, the mode register set command must be executed to initialize the
device. The mode register can be set only when all banks are in idle state. During 2CLK (tRSC) following this
command, the Synchronous DRAM cannot accept any other commands.
CLK
CKE
H
/CS
/RAS
/CAS
EO
/WE
BA0, BA1
(Bank select)
A10
Add
Mode Register Set Command
L
Activate command (/CS, /RAS = Low, /CAS, /WE = High)
The Synchronous DRAM has four banks, each with 4,096 rows. This command activates the bank selected by BA0
and BA1 and a row address selected by A0 through A11. This command corresponds to a conventional DRAM's
/RAS falling.
CLK
CKE
H
/CS
Pr
/RAS
/CAS
/WE
BA0, BA1
(Bank select)
A10
Row
od
Add
Row
Row Address Strobe and Bank Activate Command
t
uc
Data Sheet E0388E11 (Ver. 1.1)
11
EDS1232CATA
Precharge command (/CS, /RAS, /WE = Low, /CAS = High)
This command begins precharge operation of the bank selected by BA0 and BA1. When A10 is High, all banks are
precharged, regardless of BA0 and BA1. When A10 is Low, only the bank selected by BA0 and BA1 is precharged.
After this command, the Synchronous DRAM can’t accept the activate command to the precharging bank during tRP
(precharge to activate command period). This command corresponds to a conventional DRAM’s /RAS rising.
CLK
CKE
H
/CS
/RAS
/CAS
/WE
EO
BA0, BA1
(Bank select)
A10
(Precharge select)
Add
Precharge Command
Write command (/CS, /CAS, /WE = Low, /RAS = High)
If the mode register is in the burst write mode, this command sets the burst start address given by the column
address to begin the burst write operation. The first write data in burst mode can input with this command with
subsequent data on following clocks.
L
CLK
CKE
H
/CS
/RAS
Pr
/CAS
/WE
BA0, BA1
(Bank select)
A10
Add
Col.
t
uc
od
Column Address and Write Command
Data Sheet E0388E11 (Ver. 1.1)
12
EDS1232CATA
Read command (/CS, /CAS = Low, /RAS, /WE = High)
Read data is available after /CAS latency requirements have been met. This command sets the burst start address
given by the column address.
CLK
CKE
H
/CS
/RAS
/CAS
/WE
BA0, BA1
(Bank select)
EO
A10
Add
Col.
Column Address and and Read Command
CBR (auto) refresh command (/CS, /RAS, /CAS = Low, /WE, CKE = High)
This command is a request to begin the CBR (auto) refresh operation. The refresh address is generated internally.
Before executing CBR (auto) refresh, all banks must be precharged. After this cycle, all banks will be in the idle
(precharged) state and ready for a row activate command. During tRC period (from refresh command to refresh or
activate command), the Synchronous DRAM cannot accept any other command
L
CLK
CKE
H
/CS
/RAS
/CAS
Pr
/WE
BA0, BA1
(Bank select)
A10
Add
CBR (auto) Refresh Command
t
uc
od
Data Sheet E0388E11 (Ver. 1.1)
13
EDS1232CATA
Self refresh entry command (/CS, /RAS, /CAS, CKE = Low, /WE = High)
After the command execution, self refresh operation continues while CKE remains low. When CKE goes high, the
Synchronous DRAM exits the self refresh mode. During self refresh mode, refresh interval and refresh operation are
performed internally, so there is no need for external control. Before executing self refresh, all banks must be
precharged.
CLK
CKE
/CS
/RAS
/CAS
/WE
EO
BA0, BA1
(Bank select)
A10
Add
Self Refresh Entry Command
Burst stop command (/CS = /WE = Low, /RAS, /CAS = High)
This command can stop the current burst operation.
CLK
L
CKE
H
/CS
/RAS
/CAS
Pr
/WE
BA0, BA1
(Bank select)
A10
Add
Burst Stop Command in Full Page Mode
od
No operation (/CS = Low, /RAS, /CAS, /WE = High)
This command is not an execution command. No operations begin or terminate by this command.
CLK
CKE
H
/CS
/RAS
/WE
BA0, BA1
(Bank select)
A10
Add
No Operation
Data Sheet E0388E11 (Ver. 1.1)
14
t
uc
/CAS
EDS1232CATA
Truth Table
Command Truth Table
CKE
BA0,
A9 - A0,
Symbol
n–1
n
/CS
/RAS
/CAS
/WE
BA1
A10
A11
Device deselect
DESL
H
×
H
×
×
×
×
×
×
No operation
NOP
H
×
L
H
H
H
×
×
×
Burst stop
BST
H
×
L
H
H
L
×
×
×
Read
READ
H
×
L
H
L
H
V
L
V
Read with auto precharge
READA
H
×
L
H
L
H
V
H
V
Write
WRIT
H
×
L
H
L
L
V
L
V
Write with auto precharge
WRITA
H
×
L
H
L
L
V
H
V
EO
Function
Bank activate
ACT
H
×
L
L
H
H
V
V
V
Precharge select bank
PRE
H
×
L
L
H
L
V
L
×
Precharge all banks
PALL
H
×
L
L
H
L
×
H
×
Mode register set
MRS
H
×
L
L
L
L
L
L
V
Remark: H: VIH. L: VIL. ×: VIH or VIL, V = Valid data
DQM Truth Table
L
Function
CKE
DQM
0
1
2
3
n–1
n
Data write / output enable
ENB
H
×
L
L
L
L
Data mask / output disable
MASK
H
×
H
H
H
H
DQ0 to DQ7 write enable/output enable
ENB0
H
×
L
×
×
×
DQ8 to DQ15 write enable/output enable
ENB1
H
×
×
L
×
×
DQ16 to DQ23 write enable/output enable
ENB2
H
×
×
×
L
×
DQ24 to DQ31 write enable/output enable
ENB3
H
×
×
×
×
L
DQ0 to DQ7 write inhibit/output disable
MASK0
H
×
H
×
×
×
DQ8 to DQ15 write inhibit/output disable
MASK 1
H
×
×
H
×
×
DQ16 to DQ23 write inhibit/output disable
MASK 2
H
×
×
×
H
×
DQ24 to DQ31 write inhibit/output disable
MASK 3
H
×
×
×
×
H
Remark: H: VIH. L: VIL. ×: VIH or VIL
t
uc
od
Pr
Symbol
Data Sheet E0388E11 (Ver. 1.1)
15
EDS1232CATA
CKE Truth Table
CKE
Current state
Function
n–1
n
/CS
/RAS
/CAS
/WE
Address
Activating
Clock suspend mode entry
Symbol
H
L
×
×
×
×
×
Any
Clock suspend mode
L
L
×
×
×
×
×
Clock suspend
Clock suspend mode exit
L
H
×
×
×
×
×
Idle
CBR (auto) refresh command
REF
H
H
L
L
L
H
×
Idle
Self refresh entry
SELF
Self refresh
Self refresh exit
Idle
Power down entry
EO
Power down
Power down exit
H
L
L
L
L
H
×
L
H
L
H
H
H
×
L
H
H
×
×
×
×
H
L
L
H
H
H
×
H
L
H
×
×
×
×
L
H
H
×
×
×
×
L
H
L
H
H
H
×
Remark: H: VIH. L: VIL. ×: VIH or VIL
L
t
uc
od
Pr
Data Sheet E0388E11 (Ver. 1.1)
16
EDS1232CATA
1
Function Truth Table*
Current state
/CS
Idle
Command
Operation
Notes
H
×
×
×
×
L
H
H
×
×
DESL
Nop or power down
2
NOP or BST
Nop or power down
2
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL
3
L
H
L
L
BA, CA, A10
WRIT/ WRITA
ILLEGAL
3
L
L
H
H
L
L
H
L
BA, RA
ACT
Row activating
BA, A10
PRE/PALL
Nop
L
L
L
H
×
REF/SELF
CBR (auto) refresh or self refresh
L
L
L
L
OPCODE
MRS
Mode register accessing
H
×
L
H
×
×
×
DESL
Nop
H
×
×
NOP or BST
Nop
L
H
L
H
BA, CA, A10
READ/READA
Begin read: Determine AP
5
L
H
L
L
BA, CA, A10
WRIT/ WRITA
Begin write: Determine AP
5
L
L
H
H
BA, RA
ACT
ILLEGAL
3
L
L
H
L
BA, A10
PRE/PALL
Precharge
6
L
L
L
H
×
REF/SELF
ILLEGAL
L
L
L
L
OPCODE
MRS
ILLEGAL
Read
H
×
×
×
×
DESL
Continue burst to end → Row active
L
H
H
H
×
NOP
Continue burst to end → Row active
L
H
H
L
×
BST
Burst stop → Row active
L
H
L
H
BA, CA, A10
READ/READA
Terminate burst, new read: Determine AP
L
H
L
L
L
H
L
L
H
L
L
L
L
L
×
×
L
H
L
7
L
BA, CA, A10
WRIT/WRITA
Terminate burst, begin write: Determine AP 7, 8
BA, RA
ACT
ILLEGAL
L
BA, A10
PRE/PALL
Terminate burst, Precharging
H
×
REF/SELF
ILLEGAL
3
L
OPCODE
MRS
ILLEGAL
×
×
DESL
Continue burst to end → Write recovering
H
H
×
H
H
L
×
od
L
H
4
H
Pr
Write
L
EO
Row active
/RAS /CAS /WE Address
H
L
H
BA, CA, A10
H
L
L
BA, CA, A10
L
L
H
H
BA, RA
L
L
H
L
BA, A10
L
L
L
H
×
L
L
L
L
OPCODE
Continue burst to end → Write recovering
BST
Burst stop → Row active
READ/READA
Terminate burst, start read : Determine AP
7, 8
WRIT/WRITA
Terminate burst, new write : Determine AP
7
ACT
ILLEGAL
3
PRE/PALL
Terminate burst, Precharging
9
REF/SELF
ILLEGAL
MRS
ILLEGAL
Data Sheet E0388E11 (Ver. 1.1)
17
t
uc
L
L
NOP
EDS1232CATA
Current state
/CS
/RAS /CAS /WE Address
Command
Operation
Read with auto
H
×
×
×
×
DESL
Continue burst to end → Precharging
precharge
L
H
H
H
×
NOP
Continue burst to end → Precharging
L
H
H
L
×
BST
ILLEGAL
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL
3
L
H
L
L
BA, CA, A10
WRIT/ WRITA
ILLEGAL
3
L
L
H
H
BA, RA
ACT
ILLEGAL
3
3
L
L
H
L
BA, A10
PRE/PALL
ILLEGAL
L
L
L
H
×
REF/SELF
ILLEGAL
L
L
L
L
OPCODE
MRS
ILLEGAL
EO
Write with auto
precharge
H
×
×
×
×
DESL
Continue burst to end → Write
recovering with auto precharge
L
H
H
H
×
NOP
Continue burst to end → Write
recovering with auto precharge
L
H
H
L
×
BST
ILLEGAL
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL
3
L
H
L
L
BA, CA, A10
WRIT/ WRITA
ILLEGAL
3
L
L
H
H
BA, RA
ACT
ILLEGAL
3
3
L
L
H
L
BA, A10
PRE/PALL
ILLEGAL
L
L
L
H
×
REF/SELF
ILLEGAL
L
L
L
L
OPCODE
MRS
ILLEGAL
H
×
×
×
×
DESL
Nop → Enter idle after tRP
L
H
H
H
×
NOP
Nop → Enter idle after tRP
L
H
H
L
×
BST
ILLEGAL
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL
3
L
H
L
L
BA, CA, A10
WRIT/WRITA
ILLEGAL
3
L
L
H
H
BA, RA
ACT
ILLEGAL
3
L
L
H
L
BA, A10
PRE/PALL
Nop → Enter idle after tRP
L
L
L
H
×
L
L
L
L
OPCODE
H
×
×
×
×
L
H
H
H
×
Pr
Row activating
L
od
Precharging
Notes
REF/SELF
ILLEGAL
MRS
ILLEGAL
DESL
Nop → Enter bank active after tRCD
NOP
Nop → Enter bank active after tRCD
BST
ILLEGAL
READ/READA
ILLEGAL
H
H
L
×
H
L
H
BA, CA, A10
L
H
L
L
BA, CA, A10
WRIT/WRITA
ILLEGAL
L
L
H
H
BA, RA
ACT
ILLEGAL
L
L
H
L
BA, A10
PRE/PALL
ILLEGAL
L
L
L
H
×
REF/SELF
ILLEGAL
L
L
L
L
OPCODE
MRS
ILLEGAL
Data Sheet E0388E11 (Ver. 1.1)
18
3
t
uc
L
L
3
3, 10
3
EDS1232CATA
Current state
/CS
/RAS /CAS /WE Address
Command
Operation
Write recovering
H
×
×
×
×
DESL
Nop → Enter row active after tDPL
L
H
H
H
×
NOP
Nop → Enter row active after tDPL
Notes
L
H
H
L
×
BST
Nop → Enter row active after tDPL
L
H
L
H
BA, CA, A10
READ/READA
Start read, Determine AP
L
H
L
L
BA, CA, A10
WRIT/ WRITA
New write, Determine AP
L
L
H
H
BA, RA
ACT
ILLEGAL
3
3
L
L
H
L
BA, A10
PRE/PALL
ILLEGAL
L
L
L
H
×
REF/SELF
ILLEGAL
L
L
L
L
OPCODE
MRS
ILLEGAL
8
H
×
×
×
×
DESL
Nop → Enter precharge after tDPL
with auto
L
H
H
H
×
NOP
Nop → Enter precharge after tDPL
precharge
L
H
H
L
×
BST
Nop → Enter row active after tDPL
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL
L
H
L
L
BA, CA, A10
WRIT/WRITA
ILLEGAL
3, 8
L
L
H
H
BA, RA
ACT
ILLEGAL
3
L
L
H
L
BA, A10
PRE/PALL
ILLEGAL
3
L
L
L
H
×
REF/SELF
ILLEGAL
L
L
L
L
OPCODE
MRS
ILLEGAL
Refresh
L
EO
Write recovering
×
×
×
×
DESL
Nop → Enter idle after tRC
L
H
H
H
×
NOP/BST
Nop → Enter idle after tRC
L
H
H
L
×
READ/READA
ILLEGAL
L
H
L
H
×
ACT/PRE/PALL ILLEGAL
H
L
H
×
×
accessing
L
H
H
L
H
H
L
H
L
L
L
L
L
×
REF/SELF/MRS ILLEGAL
×
×
DESL
Nop → Enter idle after tRSC
H
×
NOP
Nop → Enter idle after tRSC
L
×
BST
ILLEGAL
H
×
READ/READA
ILLEGAL
L
×
od
L
Mode register
Pr
H
ACT/PRE/PLL/
ILLEGAL
REF/SELF/MRS
Remark: H: VIH. L: VIL. ×: VIH or VIL, V = Valid data
BA: Bank Address, CA: Column Address, RA: Row Address
t
uc
Notes: 1. All entries assume that CKE was active (High level) during the preceding clock cycle.
2. If all banks are idle, and CKE is inactive (Low level), the Synchronous DRAM will enter Power down
mode.
3. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA),
depending on the state of that bank.
4. If all banks are idle, and CKE is inactive (Low level), the Synchronous DRAM will enter Self refresh mode.
All input buffers except CKE will be disabled.
5. Illegal if tRCD is not satisfied.
6. Illegal if tRAS is not satisfied.
7. Must satisfy burst interrupt condition.
8. Must satisfy bus contention, bus trun around, and/or write recovery requirements.
9. Must mask preceding data which don’t satisfy tDPL.
10. Illegal if tRRD is not satisfied.
Data Sheet E0388E11 (Ver. 1.1)
19
EDS1232CATA
Command Truth Table for CKE
CKE
Current State
n–1 n
Self refresh
Self refresh recovery
Operation
Notes
H
×
×
×
×
×
×
INVALID, CLK (n – 1) would exit self refresh
H
H
×
×
×
×
Self refresh recovery
L
H
L
H
H
×
×
Self refresh recovery
L
H
L
H
L
×
×
ILLEGAL
L
H
L
L
×
×
×
ILLEGAL
L
L
×
×
×
×
×
Continue self refresh
H
H
H
×
×
×
×
Idle after tRC
H
H
L
H
H
×
×
Idle after tRC
H
H
L
H
L
×
×
ILLEGAL
H
H
L
L
×
×
×
ILLEGAL
H
L
H
×
×
×
×
ILLEGAL
H
L
L
H
H
×
×
ILLEGAL
H
L
L
H
L
×
×
ILLEGAL
×
H
L
L
L
×
×
H
×
×
×
×
×
L
H
H
×
×
×
L
H
L
H
H
H
×
EXIT power down
L
L
×
×
×
×
×
Continue power down mode
L
All banks idle
/RAS /CAS /WE Address
L
EO
Power down
/CS
ILLEGAL
INVALID, CLK (n – 1) would exit power down
×
EXIT power down
H
H
H
×
×
×
Refer to operations in Function Truth Table
H
H
L
H
×
×
Refer to operations in Function Truth Table
H
H
L
Refer to operations in Function Truth Table
H
×
Pr
L
H
H
L
L
L
H
×
H
H
L
L
L
L
OPCODE Refer to operations in Function Truth Table
H
L
H
×
×
×
Begin power down next cycle
H
L
L
H
×
×
Refer to operations in Function Truth Table
H
L
L
L
H
×
Refer to operations in Function Truth Table
L
L
L
L
H
L
L
L
L
L
L
H
×
×
×
×
od
H
H
CBR (auto) Refresh
×
Self refresh
×
Exit power down next cycle
L
L
×
×
×
×
H
×
×
×
×
×
L
×
×
×
×
×
Any state other than
H
H
×
×
×
×
listed above
H
L
×
×
×
×
×
Begin clock suspend next cycle
L
H
×
×
×
×
×
Exit clock suspend next cycle
L
L
×
×
×
×
×
Maintain clock suspend
Row active
1
OPCODE Refer to operations in Function Truth Table
×
Power down
×
Refer to operations in Function Truth Table
×
Clock suspend
1
1
t
uc
Refer to operations in Function Truth Table
2
Remark: H = VIH, L = VIL, × = VIH or VIL
Notes: 1. Self refresh can be entered only from the all banks idle state. Power down can be entered only from all
banks idle or row active state.
2. Must be legal command as defined in Function Truth Table.
Data Sheet E0388E11 (Ver. 1.1)
20
EDS1232CATA
Simplified State Diagram
Self
Refresh
SE
LF
SE
LF
MRS
Mode
Register
Set
exi
t
REF
IDLE
CBR(auto)
Refresh
CK
E
ACT
CKE
ROW
ACTIVE
e
ite
wit
pre h
ch
arg
Wr
Au
CKE
Read
T
ad
WRITE
Write
Precharge
CKE
CKE
READA
CKE
READ
SUSPEND
READA
SUSPEND
od
POWER
ON
PR
E(
Pre
cha
rge
ter
min
atio
n)
CKE
n)
atio
min
ter
rge
cha
Pre
E(
PR
WRITEA
CKE
READ
CKE
CKE
Read
h
wit
ad arge
h
Re
c
pre
to
PRE
W
Re
Au
e
rit
Write
BS
T
to
BS
Active
Power
Down
CKE
Pr
WRITEA
SUSPEND
E
Power
Down
L
EO
WRITE
SUSPEND
CK
Precharge
t
uc
Automatic sequence
Manual input
Data Sheet E0388E11 (Ver. 1.1)
21
EDS1232CATA
Programming Mode Registers
The mode register is programmed by the Mode register set command using address bits A11 through A0, BA0 and
BA1 as data inputs. The registers retain data until it is re-programmed, or the device loses power.
The mode register has three fields;
Options
/CAS latency
Wrap type
Burst length
:
:
:
:
A11 through A7, BA0, BA1
A6 through A4
A3
A2 through A0
Following mode register programming, no command can be issued before at least 2 CLK have elapsed.
EO
/CAS Latency
/CAS latency is the most critical of the parameters being set. It tells the device how many clocks must elapse before
the data will be available. The value is determined by the frequency of the clock and the speed grade of the device.
”Relationship between Frequency and Latency” shows the relationship of /CAS latency to the clock period and the
speed grade of the device.
L
Burst Length
Burst Length is the number of words that will be output or input in a read or write cycle. After a read burst is
completed, the output bus will become High-Z. The burst length is programmable as 1, 2, 4, 8 or full page.
t
uc
od
Pr
Wrap Type (Burst Sequence)
The wrap type specifies the order in which the burst data will be addressed. This order is programmable as either
“Sequential” or “Interleave”. The method chosen will depend on the type of CPU in the system.
Some microprocessor cache systems are optimized for sequential addressing and others for interleaved addressing.
“Burst Length Sequence” shows the addressing sequence for each burst length using them. Both sequences
support bursts of 1, 2, 4 and 8. Additionally, sequence supports the full page length.
Data Sheet E0388E11 (Ver. 1.1)
22
EDS1232CATA
Mode Register
BA0 BA1 A11
0
0
0
BA0 BA1 A11
x
x
x
BA0 BA1 A11
BA0 BA1 A11
x
x
x
BA0 BA1 A11
0
0
A9
A8
A7
0
0
0
1
A10
A9
A8
A7
x
1
0
0
A10
A9
A8
A7
1
0
A6
A5
A4
A3
A2
A1
A0
JEDEC Standard Test Set (refresh counter test)
A6
A5
A4
LTMODE
A6
A5
A3
A2
WT
A4
A3
A1
A0
BL
A2
A1
Burst Read and Single Write
(for Write Through Cache)
A0
Use in future
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
x
x
1
1
V
V
V
V
V
V
V
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0
0
0
0
LTMODE
WT
Vender Specific
V = Valid
x = Don’t care
BL
L
EO
0
A10
Mode Register Set
Burst length
Bits2-0
000
001
010
011
100
101
110
111
Wrap type
0
1
WT = 1
1
2
4
8
R
R
R
R
Sequential
Interleave
Bits6-4
000
001
010
011
100
101
110
111
/CAS latency
R
R
2
3
R
R
R
R
Remark R : Reserved
od
Pr
Latency
mode
WT = 0
1
2
4
8
R
R
R
Full page
Mode Register Set Timing
CLK
CKE
/CS
t
uc
/RAS
/CAS
/WE
A0 - A11,
BA0, BA1
Mode Register Set
Data Sheet E0388E11 (Ver. 1.1)
23
EDS1232CATA
Burst Length and Sequence
[Burst of Two]
Starting address
(column address A0, binary)
Sequential addressing sequence
(decimal)
Interleave addressing sequence
(decimal)
0
0, 1
0, 1
1
1, 0
1, 0
Starting address
(column address A1 to A0, binary)
Sequential addressing sequence
(decimal)
Interleave addressing sequence
(decimal)
00
0, 1, 2, 3
0, 1, 2, 3
01
1, 2, 3, 0
1, 0, 3, 2
10
2, 3, 0, 1
2, 3, 0, 1
11
3, 0, 1, 2
3, 2, 1, 0
Sequential addressing sequence
(decimal)
Interleave addressing sequence
(decimal)
[Burst of Four]
EO
[Burst of Eight]
Starting address
(column address A2 to A0, binary)
001
010
011
L
000
100
110
111
0, 1, 2, 3, 4, 5, 6, 7
1, 2, 3, 4, 5, 6, 7, 0
1, 0, 3, 2, 5, 4, 7, 6
2, 3, 4, 5, 6, 7, 0, 1
2, 3, 0, 1, 6, 7, 4, 5
3, 4, 5, 6, 7, 0, 1, 2
3, 2, 1, 0, 7, 6, 5, 4
4, 5, 6, 7, 0, 1, 2, 3
4, 5, 6, 7, 0, 1, 2, 3
Pr
101
0, 1, 2, 3, 4, 5, 6, 7
5, 6, 7, 0, 1, 2, 3, 4
5, 4, 7, 6, 1, 0, 3, 2
6, 7, 0, 1, 2, 3, 4, 5
6, 7, 4, 5, 2, 3, 0, 1
7, 0, 1, 2, 3, 4, 5, 6
7, 6, 5, 4, 3, 2, 1, 0
Full page burst is an extension of the above tables of sequential addressing, with the length being 256.
t
uc
od
Data Sheet E0388E11 (Ver. 1.1)
24
EDS1232CATA
Address Bits of Bank-Select and Precharge
Row
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
BA1 BA0
(Activate command)
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
EO
(/CAS strobes)
A1
A2
A3
Result
Select Bank 0
“Activate” command
Select Bank 1
“Activate” command
0
0
0
1
1
0
Select Bank 2
“Activate” command
1
1
Select Bank 3
“Activate” command
A10
0
0
0
0
1
BA1
0
0
1
1
x
BA0
0
1
0
1
x
Result
Precharge Bank 0
Precharge Bank 1
Precharge Bank 2
Precharge Bank 3
Precharge All Banks
x : Don’t care
0
A4
A5
A6
L
A0
BA0
BA1 BA0
(Precharge command)
Col.
BA1
A7
A8
A9
A10
x
BA1 BA0
1
BA1
disables Auto-Precharge
(End of Burst)
enables Auto-Precharge
(End of Burst)
BA0
Result
0
0
0
1
1
0
enables Read/Write
commands for Bank 2
1
1
enables Read/Write
commands for Bank 3
t
uc
od
Pr
enables Read/Write
commands for Bank 0
enables Read/Write
commands for Bank 1
Data Sheet E0388E11 (Ver. 1.1)
25
EDS1232CATA
Power-up sequence
Power-up sequence
The SDRAM should be goes on the following sequence with power up.
The CLK, CKE, /CS, DQM and DQ pins keep low till power stabilizes.
The CLK pin is stabilized within 100 µs after power stabilizes before the following initialization sequence.
The CKE and DQM is driven to high between power stabilizes and the initialization sequence.
This SDRAM has VDD clamp diodes for CLK, CKE, /CS DQM and DQ pins. If these pins go high before power up,
the large current flows from these pins to VDD through the diodes.
Initialization sequence
EO
When 200 µs or more has past after the above power-up sequence, all banks must be precharged using the
precharge command (PALL). After tRP delay, set 8 or more auto refresh commands (REF). Set the mode register
set command (MRS) to initialize the mode register. We recommend that by keeping DQM and CKE to High, the
output buffer becomes High-Z during Initialization sequence, to avoid DQ bus contention on memory system formed
with a number of device.
100 μs
200 μs
0V
L
VDD, VDDQ
Initialization sequence
Power up sequence
Low
CLK
Low
/CS, DQ
Low
Pr
CKE, DQM
Power stabilize
Power-up sequence and Initialization sequence
t
uc
od
Data Sheet E0388E11 (Ver. 1.1)
26
EDS1232CATA
Operation of the SDRAM
Read/Write Operations
Bank active
Before executing a read or write operation, the corresponding bank and the row address must be activated by the
bank active (ACT) command. An interval of tRCD is required between the bank active command input and the
following read/write command input.
EO
Read operation
A read operation starts when a read command is input. Output buffer becomes Low-Z in the (/CAS Latency - 1)
cycle after read command set. The SDRAM can perform a burst read operation.
The burst length can be set to 1, 2, 4 and 8. The start address for a burst read is specified by the column address
and the bank select address at the read command set cycle. In a read operation, data output starts after the number
of clocks specified by the /CAS Latency. The /CAS Latency can be set to 2 or 3.
When the burst length is 1, 2, 4 and 8 the DOUT buffer automatically becomes High-Z at the next clock after the
successive burst-length data has been output.
The /CAS latency and burst length must be specified at the mode register.
CLK
Command
DQ
READ
ACT
L
Address
tRCD
Row
Column
out 0
CL = 2
CL = 3
out 1
out 2
out 3
out 0
out 1
out 2
out 3
Pr
CL = /CAS latency
Burst Length = 4
/CAS Latency
CLK
tRCD
ACT
READ
Address
Row
Column
BL = 1
out 0
out 0 out 1
DQ
BL = 2
od
Command
out 0 out 1 out 2 out 3
BL = 4
out 3 out 4 out 5 out 6 out 7
t
uc
out 0 out 1 out 2
BL = 8
BL : Burst Length
/CAS Latency = 2
Burst Length
Data Sheet E0388E11 (Ver. 1.1)
27
EDS1232CATA
Write operation
Burst write or single write mode is selected by the OPCODE of the mode register.
1. Burst write: A burst write operation is enabled by setting OPCODE (A9, A8) to (0, 0). A burst write starts in the
same clock as a write command set. (The latency of data input is 0 clock.) The burst length can be set to 1, 2, 4
and 8, like burst read operations. The write start address is specified by the column address and the bank select
address at the write command set cycle.
CLK
tRCD
Command
ACT
WRIT
Address
Row
Column
in 0
EO
BL = 1
DQ
in 0
in 1
in 0
in 1
in 2
in 3
in 0
in 1
in 2
in 3
BL = 2
BL = 4
in 4
in 5
in 6
in 7
BL = 8
CL = 2, 3
Burst write
L
2. Single write: A single write operation is enabled by setting OPCODE (A9, A8) to (1, 0). In a single write
operation, data is only written to the column address and the bank select address specified by the write
command set cycle without regard to the burst length setting. (The latency of data input is 0 clock).
CLK
Command
DQ
WRIT
Pr
Address
ACT
tRCD
Row
Column
in 0
Single write
t
uc
od
Data Sheet E0388E11 (Ver. 1.1)
28
EDS1232CATA
Auto Precharge
Read with auto-precharge
In this operation, since precharge is automatically performed after completing a read operation, a precharge
command need not be executed after each read operation. The command executed for the same bank after the
execution of this command must be the bank active (ACT) command. In addition, an interval defined by lAPR is
required before execution of the next command.
[Clock cycle time]
/CAS latency
Precharge start cycle
3
2 cycle before the final data is output
2
1 cycle before the final data is output
EO
CLK
CL=2 Command
ACT
READA
ACT
lRAS
DQ
CL=3 Command
out0
out1
out2
out3
lAPR
ACT
READA
ACT
lRAS
DQ
out0
out1
L
Note: Internal auto-precharge starts at the timing indicated by " ".
And an interval of tRAS (lRAS) is required between previous active (ACT) command and internal precharge "
out2
out3
lAPR
".
Burst Read (BL = 4)
CLK
ACT
WRITA
od
Command
Pr
Write with auto-precharge
In this operation, since precharge is automatically performed after completing a burst write or single write operation,
a precharge command need not be executed after each write operation. The command executed for the same bank
after the execution of this command must be the bank active (ACT) command. In addition, an interval of lDAL is
required between the final valid data input and input of next command.
ACT
lRAS
DQ
in0
in1
in2
in3
lDAL
Burst Write (BL = 4)
Data Sheet E0388E11 (Ver. 1.1)
29
t
uc
Note: Internal auto-precharge starts at the timing indicated by " ".
and an interval of tRAS (lRAS) is required between previous active (ACT) command
and internal precharge " ".
EDS1232CATA
CLK
Command
ACT
ACT
WRITA
lRAS
DQ
in
lDAL
EO
Note: Internal auto-precharge starts at the timing indicated by " ".
and an interval of tRAS (lRAS) is required between previous active (ACT) command
and internal precharge " ".
Single Write
L
t
uc
od
Pr
Data Sheet E0388E11 (Ver. 1.1)
30
EDS1232CATA
Burst Stop Command
During a read cycle, when the burst stop command is issued, the burst read data are terminated and the data bus
goes to High-Z after the /CAS latency from the burst stop command.
CLK
READ
Command
BST
DQ
(CL = 2)
out
DQ
(CL = 3)
out
out
out
out
High-Z
out
High-Z
EO
Burst Stop at Read
During a write cycle, when the burst stop command is issued, the burst write data are terminated and data bus goes
to High-Z at the same clock with the burst stop command.
CLK
Command
BST
High-Z
in
L
DQ
WRITE
in
in
in
Burst Stop at Write
t
uc
od
Pr
Data Sheet E0388E11 (Ver. 1.1)
31
EDS1232CATA
Command Intervals
Read command to Read command interval
1. Same bank, same ROW address: When another read command is executed at the same ROW address of the
same bank as the preceding read command execution, the second read can be performed after an interval of no
less than 1 clock. Even when the first command is a burst read that is not yet finished, the data read by the
second command will be valid.
CLK
Command
ACT
Address
Row
READ
READ
Column A Column B
BS
EO
DQ
Bank0
Active
out A0 out B0 out B1 out B2 out B3
CL = 3
BL = 4
Bank 0
Column =A Column =B Column =A Column =B
Dout
Read
Read
Dout
READ to READ Command Interval (same ROW address in same bank)
L
2. Same bank, different ROW address: When the ROW address changes on same bank, consecutive read
commands cannot be executed; it is necessary to separate the two read commands with a precharge command
and a bank active command.
3. Different bank: When the bank changes, the second read can be performed after an interval of no less than 1
clock, provided that the other bank is in the bank active state. Even when the first command is a burst read that
is not yet finished, the data read by the second command will be valid.
CLK
Command
ACT
READ READ
Row 0
Row 1
Column A Column B
BS
DQ
Pr
Address
ACT
out A0 out B0 out B1 out B2 out B3
Bank0
Active
Bank3 Bank0 Bank3
Active Read Read
CL = 3
BL = 4
Bank0 Bank3
Dout
Dout
READ to READ Command Interval (different bank)
t
uc
od
Data Sheet E0388E11 (Ver. 1.1)
32
EDS1232CATA
Write command to Write command interval
1. Same bank, same ROW address: When another write command is executed at the same ROW address of the
same bank as the preceding write command, the second write can be performed after an interval of no less than
1 clock. In the case of burst writes, the second write command has priority.
CLK
Command
ACT
Address
Row
WRIT
WRIT
Column A Column B
BS
DQ
in A0
EO
Bank0
Active
in B0
in B1
in B2
in B3
Burst Write Mode
BL = 4
Bank 0
Column =A Column =B
Write
Write
WRITE to WRITE Command Interval (same ROW address in same bank)
L
2. Same bank, different ROW address: When the ROW address changes, consecutive write commands cannot be
executed; it is necessary to separate the two write commands with a precharge command and a bank active
command.
3. Different bank: When the bank changes, the second write can be performed after an interval of no less than 1
clock, provided that the other bank is in the bank active state. In the case of burst write, the second write
command has priority.
CLK
Command
Row 0
BS
DQ
ACT
WRIT
Row 1
Column A Column B
in A0
Bank0
Active
WRIT
Pr
Address
ACT
in B0
in B1
in B2
in B3
Burst Write Mode
BL = 4
Bank3 Bank0 Bank3
Active Write Write
od
WRITE to WRITE Command Interval (different bank)
t
uc
Data Sheet E0388E11 (Ver. 1.1)
33
EDS1232CATA
Read command to Write command interval
1. Same bank, same ROW address: When the write command is executed at the same ROW address of the same
bank as the preceding read command, the write command can be performed after an interval of no less than 1
clock. However, DQM must be set High so that the output buffer becomes High-Z before data input.
CLK
Command
READ WRIT
CL=2
DQM
CL=3
in B0
DQ (input)
in B1
in B2
in B3
EO
BL = 4
Burst write
High-Z
DQ (output)
READ to WRITE Command Interval (1)
CLK
Command
READ
WRIT
L
DQM
CL=2
2 clock
out
out
out
in
in
in
in
out
out
in
in
in
in
DQ
CL=3
Pr
READ to WRITE Command Interval (2)
t
uc
od
2. Same bank, different ROW address: When the ROW address changes, consecutive write commands cannot be
executed; it is necessary to separate the two commands with a precharge command and a bank active
command.
3. Different bank: When the bank changes, the write command can be performed after an interval of no less than 1
cycle, provided that the other bank is in the bank active state. However, DQM must be set High so that the
output buffer becomes High-Z before data input.
Data Sheet E0388E11 (Ver. 1.1)
34
EDS1232CATA
Write command to Read command interval:
1. Same bank, same ROW address: When the read command is executed at the same ROW address of the same
bank as the preceding write command, the read command can be performed after an interval of no less than 1
clock. However, in the case of a burst write, data will continue to be written until one clock before the read
command is executed.
CLK
Command
WRIT
READ
DQM
DQ (input)
in A0
EO
DQ (output)
out B0
Column = A
Write
Column = B
Read
out B1
out B2
out B3
Burst Write Mode
CL = 2
BL = 4
Bank 0
/CAS Latency
Column = B
Dout
WRITE to READ Command Interval (1)
CLK
DQM
DQ (input)
L
Command
in A0
READ
in A1
out B0
Pr
DQ (output)
WRIT
Column = A
Write
out B1
out B2
/CAS Latency
Column = B
Read
Column = B
Dout
out B3
Burst Write Mode
CL = 2
BL = 4
Bank 0
WRITE to READ Command Interval (2)
t
uc
od
2. Same bank, different ROW address: When the ROW address changes, consecutive read commands cannot be
executed; it is necessary to separate the two commands with a precharge command and a bank active
command.
3. Different bank: When the bank changes, the read command can be performed after an interval of no less than 1
clock, provided that the other bank is in the bank active state. However, in the case of a burst write, data will
continue to be written until one clock before the read command is executed (as in the case of the same bank and
the same address).
Data Sheet E0388E11 (Ver. 1.1)
35
EDS1232CATA
Read with auto precharge to Read command interval
1. Different bank: When some banks are in the active state, the second read command (another bank) is executed.
Even when the first read with auto-precharge is a burst read that is not yet finished, the data read by the second
command is valid. The internal auto-precharge of one bank starts at the next clock of the second command.
CLK
Command
READA
READ
BS
DQ
out A0
bank0
Read A
out A1
out B0
out B1
bank3
Read
EO
Note: Internal auto-precharge starts at the timing indicated by "
CL= 3
BL = 4
".
Read with Auto Precharge to Read Command Interval (Different bank)
2. Same bank: The consecutive read command (the same bank) is illegal.
Write with auto precharge to Write command interval
1. Different bank: When some banks are in the active state, the second write command (another bank) is executed.
In the case of burst writes, the second write command has priority. The internal auto-precharge of one bank
starts 2 clocks later from the second command.
L
CLK
Command
WRITA
WRIT
BS
DQ
in A0
in A1
in B0
in B1
in B2
Pr
bank0
Write A
in B3
bank3
Write
Note: Internal auto-precharge starts at the timing indicated by "
BL= 4
".
Write with Auto Precharge to Write Command Interval (Different bank)
2. Same bank: The consecutive write command (the same bank) is illegal.
t
uc
od
Data Sheet E0388E11 (Ver. 1.1)
36
EDS1232CATA
Read with auto precharge to Write command interval
1. Different bank: When some banks are in the active state, the second write command (another bank) is executed.
However, DQM must be set High so that the output buffer becomes High-Z before data input. The internal autoprecharge of one bank starts at the next clock of the second command.
CLK
Command
READA
WRIT
BS
CL = 2
DQM
CL = 3
DQ (input)
EO
in B0
DQ (output)
in B1
in B2
in B3
High-Z
bank0
ReadA
BL = 4
bank3
Write
Note: Internal auto-precharge starts at the timing indicated by "
".
Read with Auto Precharge to Write Command Interval (Different bank)
L
2. Same bank: The consecutive write command from read with auto precharge (the same bank) is illegal. It is
necessary to separate the two commands with a bank active command.
Write with auto precharge to Read command interval
1. Different bank: When some banks are in the active state, the second read command (another bank) is executed.
However, in case of a burst write, data will continue to be written until one clock before the read command is
executed. The internal auto-precharge of one bank starts at 2 clocks later from the second command.
Pr
CLK
Command
WRITA
BS
DQ (input)
in A0
DQ (output)
od
DQM
READ
out B0
bank0
WriteA
bank3
Read
out B1
out B2
out B3
".
t
uc
Note: Internal auto-precharge starts at the timing indicated by "
CL = 3
BL = 4
Write with Auto Precharge to Read Command Interval (Different bank)
2. Same bank: The consecutive read command from write with auto precharge (the same bank) is illegal. It is
necessary to separate the two commands with a bank active command.
Data Sheet E0388E11 (Ver. 1.1)
37
EDS1232CATA
Read command to Precharge command interval (same bank)
When the precharge command is executed for the same bank as the read command that preceded it, the minimum
interval between the two commands is one clock. However, since the output buffer then becomes High-Z after the
clocks defined by lHZP, there is a case of interruption to burst read data output will be interrupted, if the precharge
command is input during burst read. To read all data by burst read, the clocks defined by lEP must be assured as
an interval from the final data output to precharge command execution.
CLK
PRE/PALL
READ
Command
DQ
out A0
out A1
EO
CL=2
out A2
out A3
lEP = -1 cycle
READ to PRECHARGE Command Interval (same bank): To output all data (CL = 2, BL = 4)
CLK
Command
PRE/PALL
READ
DQ
out A0
out A1
L
CL=3
out A2
out A3
lEP = -2 cycle
READ to PRECHARGE Command Interval (same bank): To output all data (CL = 3, BL = 4)
CLK
READ
Pr
Command
PRE/PALL
High-Z
DQ
out A0
lHZP = 2
CLK
Command
READ
PRE/PALL
od
READ to PRECHARGE Command Interval (same bank): To stop output data (CL = 2, BL = 1, 2, 4, 8)
High-Z
DQ
out A0
t
uc
lHZP =3
READ to PRECHARGE Command Interval (same bank): To stop output data (CL = 3, BL = 1, 2, 4, 8)
Data Sheet E0388E11 (Ver. 1.1)
38
EDS1232CATA
Write command to Precharge command interval (same bank)
When the precharge command is executed for the same bank as the write command that preceded it, the minimum
interval between the two commands is 1 clock. However, if the burst write operation is unfinished, the input data
must be masked by means of DQM for assurance of the clock defined by tDPL.
CLK
WRIT
Command
PRE/PALL
DQM
DQ
EO
tDPL
CLK
Command
PRE/PALL
WRIT
DQM
DQ
in A0
in A1
L
tDPL
WRITE to PRECHARGE Command Interval (same bank) (BL = 4 (To stop write operation))
CLK
Pr
Command
WRIT
DQM
in A0
DQ
in A1
in A2
PRE/PALL
in A3
od
tDPL
WRITE to PRECHARGE Command Interval (same bank) (BL = 4 (To write all data))
t
uc
Data Sheet E0388E11 (Ver. 1.1)
39
EDS1232CATA
Bank active command interval
1. Same bank: The interval between the two bank active commands must be no less than tRC.
2. In the case of different bank active commands: The interval between the two bank active commands must be no
less than tRRD.
CLK
Command
ACT
ACT
Address
ROW
ROW
BS
EO
tRC
Bank 0
Active
Bank 0
Active
Bank Active to Bank Active for Same Bank
CLK
ACT
Command
ACT
L
Address
ROW:0
ROW:1
BS
tRRD
Bank 3
Active
Pr
Bank 0
Active
Bank Active to Bank Active for Different Bank
Mode register set to Bank active command interval
The interval between setting the mode register and executing a bank active command must be no less than lMRD.
Command
Address
MRS
OPCODE
od
CLK
ACT
BS & ROW
lMRD
Bank
Active
t
uc
Mode
Register Set
Mode register set to Bank active command interval
Data Sheet E0388E11 (Ver. 1.1)
40
EDS1232CATA
DQM Control
The DQM mask the DQ data. The UDQM and LDQM mask the upper and lower bytes of the DQ data, respectively.
The timing of UDQM/LDQM is different during reading and writing.
Reading
When data is read, the output buffer can be controlled by DQM. By setting DQM to Low, the output buffer becomes
Low-Z, enabling data output. By setting DQM to High, the output buffer becomes High-Z, and the corresponding
data is not output. However, internal reading operations continue. The latency of DQM during reading is 2 clocks.
Writing
Input data can be masked by DQM. By setting DQM to Low, data can be written. In addition, when DQM is set to
High, the corresponding data is not written, and the previous data is held. The latency of DQM during writing is 0
clock.
EO
CLK
DQM
High-Z
DQ
out 0
out 1
out 3
lDOD = 2 Latency
L
Reading
CLK
DQ
Pr
DQM
in 0
in 3
in 1
od
lDID = 0 Latency
Writing
t
uc
Data Sheet E0388E11 (Ver. 1.1)
41
EDS1232CATA
Refresh
Auto-refresh
All the banks must be precharged before executing an auto-refresh command. Since the auto-refresh command
updates the internal counter every time it is executed and determines the banks and the ROW addresses to be
refreshed, external address specification is not required. The refresh cycles are required to refresh all the ROW
addresses within tREF (max.). The output buffer becomes High-Z after auto-refresh start. In addition, since a
precharge has been completed by an internal operation after the auto-refresh, an additional precharge operation by
the precharge command is not required.
EO
Self-refresh
After executing a self-refresh command, the self-refresh operation continues while CKE is held Low. During selfrefresh operation, all ROW addresses are refreshed by the internal refresh timer. A self-refresh is terminated by a
self-refresh exit command. Before and after self-refresh mode, execute auto-refresh to all refresh addresses in or
within tREF (max.) period on the condition 1 and 2 below.
1. Enter self-refresh mode within time as below* after either burst refresh or distributed refresh at equal interval to
all refresh addresses are completed.
2. Start burst refresh or distributed refresh at equal interval to all refresh addresses within time as below*after
exiting from self-refresh mode.
Note: tREF (max.) / refresh cycles.
Others
L
Power-down mode
The SDRAM enters power-down mode when CKE goes Low in the IDLE state. In power down mode, power
consumption is suppressed by deactivating the input initial circuit. Power down mode continues while CKE is held
Low. In addition, by setting CKE to High, the SDRAM exits from the power down mode, and command input is
enabled from the next clock. In this mode, internal refresh is not performed.
t
uc
od
Pr
Clock suspend mode
By driving CKE to Low during a bank active or read/write operation, the SDRAM enters clock suspend mode. During
clock suspend mode, external input signals are ignored and the internal state is maintained. When CKE is driven
High, the SDRAM terminates clock suspend mode, and command input is enabled from the next clock. For details,
refer to the "CKE Truth Table".
Data Sheet E0388E11 (Ver. 1.1)
42
EDS1232CATA
Timing Waveforms
Read Cycle
tCK
tCH t CL
CLK
t RC
VIH
CKE
t RP
tRAS
tRCD
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
/CS
tSI tHI
tSI tHI
/RAS
EO
tSI tHI
tSI tHI
/CAS
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
/WE
tSI tHI
BS
tSI tHI
tSI tHI
A10
Address
tSI tHI
tSI tHI
L
tSI tHI
tSI
DQM
Pr
DQ (input)
tHI
tAC
DQ (output)
tAC
tAC
tHZ
t AC
tOH
tOH
Bank 0
Active
Bank 0
Read
tLZ
tOH
tOH
Bank 0
Precharge
/CAS latency = 2
Burst length = 4
Bank 0 access
= VIH or VIL
t
uc
od
Data Sheet E0388E11 (Ver. 1.1)
43
EDS1232CATA
Write Cycle
tCK
tCH tCL
CLK
tRC
VIH
CKE
tRP
tRAS
tRCD
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
/CS
tSI tHI
tSI tHI
/RAS
tSI tHI
tSI tHI
EO
/CAS
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
/WE
tSI tHI
tSI tHI
BS
tSI tHI
tSI tHI
A10
tSI tHI
tSI tHI
tSI tHI
Address
L
tSI
DQM
tSI
DQ (input)
tHI
t HI
tSI
tHI tSI
tHI
tSI
tHI
tDPL
Pr
DQ (output)
Bank 0
Write
Bank 0
Active
Mode Register Set Cycle
1
2
3
4
5
CKE
VIL
/CS
/RAS
/CAS
/WE
6
7
8
9
10
11
code
valid
DQM
DQ (output)
b
High-Z
DQ (input)
lMRD
lRP
Precharge
If needed
Mode
register
Set
Bank 3
Active
lRCD
Output mask
Bank 3
Read
Data Sheet E0388E11 (Ver. 1.1)
44
13
14
15
16
17
18
19
C: b’
C: b
R: b
12
t
uc
BS
Address
CL = 2
BL = 4
Bank 0 access
= VIH or VIL
od
0
CLK
Bank 0
Precharge
b+3
b’
b’+1
b’+2
b’+3
lRCD = 3
/CAS latency = 3
Burst length = 4
= VIH or VIL
EDS1232CATA
Read Cycle/Write Cycle
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
CLK
CKE
VIH
Read cycle
/RAS-/CAS delay = 3
/CAS latency = 3
Burst length = 4
= VIH or VIL
/CS
/RAS
/CAS
/WE
BS
Address
R:a
C:a
R:b
C:b
C:b'
C:b"
DQM
DQ (output)
DQ (input)
a
b
b+1 b+2 b+3 b'
b'+1 b"
b"+1 b"+2 b"+3
High-Z
Bank 0
Active
EO
CKE
a+1 a+2 a+3
Bank 0
Read
Bank 3
Active
Bank 3 Bank 0
Read
Precharge
Bank 3
Read
Bank 3
Read
Bank 3
Precharge
VIH
Write cycle
/RAS-/CAS delay = 3
/CAS latency = 3
Burst length = 4
= VIH or VIL
/CS
/RAS
/CAS
/WE
BS
Address
R:a
C:a
R:b
C:b
C:b'
C:b"
DQM
High-Z
DQ (output)
DQ (input)
a
a+1 a+2 a+3
L
Bank 0
Active
Bank 0
Write
Bank 3
Active
b
Bank 3
Write
b+1 b+2 b+3 b'
Bank 0
Precharge
Bank 3
Write
b'+1 b"
Bank 3
Write
b"+1 b"+2 b"+3
Bank 3
Precharge
t
uc
od
Pr
Data Sheet E0388E11 (Ver. 1.1)
45
EDS1232CATA
Read/Single Write Cycle
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
CLK
CKE
VIH
/CS
/RAS
/CAS
/WE
BS
R:a
Address
C:a
R:b
C:a' C:a
DQM
a
DQ (input)
EO
DQ (output)
Bank 0
Active
CKE
a
Bank 0
Read
Bank 3
Active
C:a
R:b
a+1 a+2 a+3
a
a+1 a+2 a+3
Bank 0 Bank 0
Write
Read
Bank 0
Precharge
Bank 3
Precharge
VIH
/CS
/RAS
/CAS
/WE
BS
Address
R:a
L
C:a
C:b C:c
a
b
DQM
DQ (input)
DQ (output)
Bank 0
Active
Bank 0
Read
a
a+1
c
a+3
Bank 0
Write
Bank 3
Active
Bank 0 Bank 0
Write
Write
Bank 0
Precharge
t
uc
od
Pr
Read/Single write
/RAS-/CAS delay = 3
/CAS latency = 3
Burst length = 4
= VIH or VIL
Data Sheet E0388E11 (Ver. 1.1)
46
EDS1232CATA
Read/Burst Write Cycle
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
CLK
CKE
/CS
/RAS
/CAS
/WE
BS
R:a
Address
C:a
R:b
C:a'
DQM
a
DQ (input)
EO
DQ (output)
a
Bank 0
Active
CKE
Bank 0
Read
a+1 a+2 a+3
a+1 a+2 a+3
Clock
suspend
Bank 3
Active
Bank 0
Precharge
Bank 0
Write
Bank 3
Precharge
VIH
/CS
/RAS
/CAS
/WE
BS
DQM
DQ (input)
DQ (output)
L
Address
R:a
C:a
Bank 0
Active
Bank 0
Read
1
2
a
a
Bank 0
Write
3
4
5
6
7
VIH
/CS
/RAS
/CAS
/WE
8
9
10
11
12
Read/Burst write
/RAS-/CAS delay = 3
/CAS latency = 3
Burst length = 4
= VIH or VIL
13
14
15
R:a
A10=1
DQM
DQ (input)
t RP
t RC
Auto Refresh
16
t RC
Auto Refresh
Data Sheet E0388E11 (Ver. 1.1)
47
17
18
19
20
C:a
a
High-Z
DQ (output)
Precharge
If needed
Bank 0
Precharge
t
uc
BS
Address
a+1 a+2 a+3
a+3
Bank 3
Active
CLK
CKE
a+1
od
0
C:a
Pr
Auto Refresh Cycle
R:b
Active
Bank 0
Read
Bank 0
a+1
Refresh cycle and
Read cycle
/RAS-/CAS delay = 2
/CAS latency = 2
Burst length = 4
= VIH or VIL
EDS1232CATA
Self Refresh Cycle
CLK
lSREX
CKE Low
CKE
/CS
/RAS
/CAS
/WE
BS
Address
A10=1
EO
DQM
DQ (input)
High-Z
DQ (output)
t RP
Precharge command
If needed
t RC
t RC
Self refresh entry
command
Next
clock
enable
Self refresh exit
ignore command
or No operation
Auto
Next
clock refresh
enable
Self refresh entry
command
Self refresh cycle
/RAS-/CAS delay = 3
CL = 3
BL = 4
= VIH or VIL
Clock Suspend Mode
L
tSI
0
CLK
CKE
1
2
3
4
5
tSI
tHI
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Read cycle
/RAS-/CAS delay = 2
/CAS latency = 2
Burst length = 4
= VIH or VIL
/CS
Pr
/RAS
/CAS
/WE
BS
Address
R:a
C:a
DQM
DQ (output)
R:b
a
C:b
a+1 a+2
a+3
b
b+1 b+2 b+3
High-Z
DQ (input)
Active clock Bank0
suspend end Read
Bank3
Active
/CS
/RAS
/CAS
/WE
BS
C:a R:b
R:a
od
Bank0 Active clock
Active suspend start
CKE
Address
20
Read suspend
start
Read suspend
end
Bank3
Read
Bank0
Precharge
Bank0
Active
Active clock
suspend start
a+1 a+2
Active clock Bank0 Bank3
supend end Write Active
Write suspend
start
a+3 b
Write suspend
end
Data Sheet E0388E11 (Ver. 1.1)
48
t
uc
High-Z
DQ (output)
a
Write cycle
/RAS-/CAS delay = 2
/CAS latency = 2
Burst length = 4
= VIH or VIL
C:b
DQM
DQ (input)
Earliest Bank3
Precharge
b+1 b+2 b+3
Bank3 Bank0
Write Precharge
Earliest Bank3
Precharge
EDS1232CATA
Power Down Mode
CLK
CKE Low
CKE
/CS
/RAS
/CAS
/WE
BS
EO
Address
R: a
A10=1
DQM
DQ (input)
High-Z
DQ (output)
tRP
Precharge command
If needed
Power down cycle
Power down entry
Power down
/RAS-/CAS delay = 3
mode exit
Active Bank 0 /CAS latency = 3
Burst length = 4
= VIH or VIL
L
Initialization Sequence
0
CLK
CKE
1
2
3
4
5
6
7
8
9
10
48
49
50
51
52
53
54
55
VIH
/CS
Pr
/RAS
/CAS
/WE
valid
Address
DQM
VIH
code
Valid
od
High-Z
DQ
t RC
tRP
All banks
Precharge
Auto Refresh
tRC
Auto Refresh
lMRD
Mode register
Set
Bank active
If needed
t
uc
Data Sheet E0388E11 (Ver. 1.1)
49
EDS1232CATA
Package Drawing
86-pin Plastic TSOP (II)
Unit: mm
22.22 ± 0.10
*1
A
EO
PIN#1 ID
1
0.15 to 0.30
43
0.50
11.76 ± 0.20
44
10.16
86
B
0.10 M S A B
0.80
Nom
0.10 +0.08
−0.05
0.09 to 0.20
0.10 S
1.2 max.
S
0.25
0 to 8°
L
1.0 ± 0.05
0.81 max.
0.60 ± 0.15
Pr
Note: 1. This dimension does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or
gate burrs shall not exceed 0.20mm per side.
ECA-TS2-0030-01
t
uc
od
Data Sheet E0388E11 (Ver. 1.1)
50
EDS1232CATA
Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the EDS1232CA.
Type of Surface Mount Device
EDS1232CATA: 86-pin Plastic TSOP (II)
L
EO
t
uc
od
Pr
Data Sheet E0388E11 (Ver. 1.1)
51
EDS1232CATA
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR MOS DEVICES
Exposing the MOS devices to a strong electric field can cause destruction of the gate
oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop
generation of static electricity as much as possible, and quickly dissipate it, when once
it has occurred. Environmental control must be adequate. When it is dry, humidifier
should be used. It is recommended to avoid using insulators that easily build static
electricity. MOS devices must be stored and transported in an anti-static container,
static shielding bag or conductive material. All test and measurement tools including
work bench and floor should be grounded. The operator should be grounded using
wrist strap. MOS devices must not be touched with bare hands. Similar precautions
need to be taken for PW boards with semiconductor MOS devices on it.
EO
2
HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES
No connection for CMOS devices input pins can be a cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input level may be
generated due to noise, etc., hence causing malfunction. CMOS devices behave
differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected
to VDD or GND with a resistor, if it is considered to have a possibility of being an output
pin. The unused pins must be handled in accordance with the related specifications.
L
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Pr
Power-on does not necessarily define initial status of MOS devices. Production process
of MOS does not define the initial operation status of the device. Immediately after the
power source is turned ON, the MOS devices with reset function have not yet been
initialized. Hence, power-on does not guarantee output pin levels, I/O settings or
contents of registers. MOS devices are not initialized until the reset signal is received.
Reset operation must be executed immediately after power-on for MOS devices having
reset function.
CME0107
t
uc
od
Data Sheet E0388E11 (Ver. 1.1)
52
EDS1232CATA
The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.
No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of Elpida Memory, Inc.
Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights
(including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or
third parties by or arising from the use of the products or information listed in this document. No license,
express, implied or otherwise, is granted under any patents, copyrights or other intellectual property
rights of Elpida Memory, Inc. or others.
Descriptions of circuits, software and other related information in this document are provided for
illustrative purposes in semiconductor product operation and application examples. The incorporation of
these circuits, software and information in the design of the customer's equipment shall be done under
the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses
incurred by customers or third parties arising from the use of these circuits, software and information.
EO
[Product applications]
Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability.
However, users are instructed to contact Elpida Memory's sales office before using the product in
aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment,
medical equipment for life support, or other such application in which especially high quality and
reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury.
L
[Product usage]
Design your application so that the product is used within the ranges and conditions guaranteed by
Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation
characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no
responsibility for failure or damage when the product is used beyond the guaranteed ranges and
conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure
rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so
that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other
consequential damage due to the operation of the Elpida Memory, Inc. product.
[Usage environment]
This product is not designed to be resistant to electromagnetic waves or radiation. This product must be
used in a non-condensing environment.
M01E0107
t
uc
od
Pr
If you export the products or technology described in this document that are controlled by the Foreign
Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance
with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by
U.S. export control regulations, or another country's export control laws or regulations, you must follow
the necessary procedures in accordance with such laws or regulations.
If these products/technology are sold, leased, or transferred to a third party, or a third party is granted
license to use these products, that third party must be made aware that they are responsible for
compliance with the relevant laws and regulations.
Data Sheet E0388E11 (Ver. 1.1)
53