TI1 DS90UR124Q Mhz dc-balanced 24-bit fpd-link ii serializer and deserializer chipset Datasheet

DS90UR124Q, DS90UR241Q
www.ti.com
SNLS231N – SEPTEMBER 2006 – REVISED MARCH 2013
DS90UR124Q DS90UR241Q 5-43 MHz DC-Balanced 24-Bit FPD-Link II Serializer and
Deserializer Chipset
Check for Samples: DS90UR124Q, DS90UR241Q
FEATURES
APPLICATIONS
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Supports Displays with 18-bit Color Depth
5MHz to 43MHz Pixel Clock
Automotive Grade Product AEC-Q100 Grade 2
Qualified
24:1 Interface Compression
Embedded Clock with DC Balancing Supports
AC-coupled Data Transmission
Capable to Drive up to 10 Meters Shielded
Twisted-pair Cable
No Reference Clock Required (Deserializer)
Meets ISO 10605 ESD - Greater than 8 kV HBM
ESD Structure
Hot Plug Support
EMI Reduction - Serializer Accepts Spread
Spectrum Input; Data randomization and
shuffling on serial link; Deserializer provides
Adjustable PTO (progressive turn-on) LVCMOS
outputs
@Speed BIST (built-in self test) to validate
LVDS transmission path
Individual power-down controls for both
Transmitter and Receiver
Power supply range 3.3V ± 10%
48-pin TQFP package for Transmitter and 64pin TQFP package for Receiver
Temperature range -40°C to +105°C
Backward Compatible Mode with
DS90C241/DS90C124
Automotive Central Information Display
Automotive Instrument Cluster Display
Automotive Heads-Up Display
Remote Camera-based Driver Assistance
Systems
DESCRIPTION
The DS90UR241/124 Chipset translates a 24-bit
parallel bus into a fully transparent data/control FPDLink II LVDS serial stream with embedded clock
information. This chipset is ideally suited for driving
graphical data to displays requiring 18-bit color depth
- RGB666 + HS, VS, DE + 3 additional general
purpose data channels. This single serial stream
simplifies transferring a 24-bit bus over PCB traces
and cable by eliminating the skew problems between
parallel data and clock paths. It saves system cost by
narrowing data paths that in turn reduce PCB layers,
cable width, and connector size and pins.
The DS90UR241/124 incorporates FPD-Link II LVDS
signaling on the high-speed I/O. FPD-Link II LVDS
provides a low power and low noise environment for
reliably transferring data over a serial transmission
path. By optimizing the Serializer output edge rate for
the operating frequency range EMI is further reduced.
In addition, the device features pre-emphasis to boost
signals over longer distances using lossy cables.
Internal DC balanced encoding/decoding is used to
support AC-Coupled interconnects. Using TI’s
proprietary random lock, the Serializer’s parallel data
are randomized to the Deserializer without the need
of REFCLK.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2013, Texas Instruments Incorporated
DS90UR124Q, DS90UR241Q
SNLS231N – SEPTEMBER 2006 – REVISED MARCH 2013
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Applications Diagram
Display
Host
(Infotainment, Instrument Cluster, CID)
(Graphics/Video Processor, ECU)
DE
Video
Source
DE
FPD-Link II
RGB Data
DS90UR241
Serializer
Clock
RGB Data
LCD
DS90UR124
Deserializer
1 Pair
Clock
(LVDS)
HSYNC
HSYNC
VSYNC
VSYNC
(LVCMOS)
(LVCMOS)
Block Diagram
TCLK
TPWDNB
PLL
Output Latch
DC Balance Decoder
RT = 100:
Timing
and
Control
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RIN-
RAOFF
RRFB
RPWDNB
BISTEN
BISTM
SLEW
PTOSEL
PLL
SERIALIZER ± DS90UR241
2
DOUT-
RIN+
RT = 100:
DOUT+
Serial to Parallel
REN
Parallel to Serial
TRFB
DC Balance Encoder
24
DIN
Input Latch
VODSEL
PRE
DEN
RAOFF
Timing
and
Control
Clock
Recovery
24
ROUT
LOCK
RCLK
PASS
DESERIALIZER ± DS90UR124
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SNLS231N – SEPTEMBER 2006 – REVISED MARCH 2013
Absolute Maximum Ratings (1) (2)
−0.3V to +4V
Supply Voltage (VDD)
LVCMOS Input Voltage
−0.3V to (VDD +0.3V)
LVCMOS Output Voltage
−0.3V to (VDD +0.3V)
LVDS Receiver Input Voltage
−0.3V to +3.9V
LVDS Driver Output Voltage
−0.3V to +3.9V
LVDS Output Short Circuit Duration
10 ms
Junction Temperature
+150°C
Storage Temperature
−65°C to +150°C
Lead Temperature (Soldering, 4 seconds)
Maximum Package
Power Dissipation
Capacity
+260°C
45.8 (4L); 75.4 (2L)°C/W (3)
DS90UR241 − 48L
TQFP
θJA
θJC
21.0°C/W
DS90UR124 − 64L
TQFP
θJA
42.8 (4L); 67.2 (2L)°C/W (3)
θJC
14.6°C/W
Package De-rating:
1/θJA °C/W above
+25°C
≥±8 kV
ESD Rating (HBM)
ESD Rating (ISO10605)
(1)
(2)
(3)
Contact Discharge (DOUT+, DOUT−)
±10 kV
Air Discharge (DOUT+, DOUT−)
±30 kV
Contact Discharge (RIN+, RIN−)
±10 kV
Air Discharge (RIN+, RIN−)
±30 kV
RD = 2 kΩ, CS = 330
pF
“Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
4L = 4 layer PCB per JEDEC specification, 2L = 2 layer PCB per JEDEC specification.
Recommended Operating Conditions
Min
Nom
Max
Units
Supply Voltage (VDD)
3.0
3.3
3.6
V
Operating Free Air Temperature (TA)
−40
+25
+105
°C
43
MHz
±100
mVP-P
Clock Rate
5
Supply Noise
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ELECTRICAL CHARACTERISTICS (1) (2) (3)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Pin/Freq.
Min
Typ
Max
Unit
2.0
VDD
V
GND
0.8
V
-0.8
-1.5
V
LVCMOS DC SPECIFICATIONS
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
VCL
Input Clamp Voltage
IIN
Input Current
Tx: DIN[0:23], TCLK,
TPWDNB, DEN, TRFB,
RAOFF, VODSEL, RES0.
Rx: RPWDNB, RRFB, REN,
PTOSEL, BISTEN, BISTM,
SLEW, RES0.
ICL = −18 mA
VIN = 0V or 3.6V
Tx: DIN[0:23], TCLK,
TPWDNB, DEN, TRFB,
RAOFF, RES0.
Rx: RRFB, REN, PTOSEL,
BISTEN, BISTM, SLEW,
RES0.
−10
±2
+10
µA
Rx: RPWDNB
−20
±5
+20
µA
Rx: ROUT[0:23], RCLK,
LOCK, PASS.
2.3
3.0
VDD
V
VOH
High Level Output
Voltage
IOH = −2 mA, SLEW = L
IOH = −4 mA, SLEW = H
VOL
Low Level Output
Voltage
IOL = +2 mA, SLEW = L
IOL = +4 mA, SLEW = H
GND
0.33
0.5
V
IOS
Output Short Circuit
Current
VOUT = 0V
−40
−70
−110
mA
IOZ
TRI-STATE Output
Current
RPWDNB, REN = 0V,
VOUT = 0V or VDD
Rx: ROUT[0:23], RCLK,
LOCK, PASS.
−30
±0.4
+30
µA
VCM = +1.8V
Rx: RIN+, RIN−
+50
mV
LVDS DC SPECIFICATIONS
VTH
Differential Threshold
High Voltage
VTL
Differential Threshold
Low Voltage
IIN
Input Current
VOD
ΔVOD
VOS
ΔVOS
IOS
IOZ
(1)
(2)
(3)
4
−50
mV
VIN = +2.4V, VDD = 3.6V
±100
±250
µA
VIN = 0V, VDD = 3.6V
±100
±250
µA
380
500
630
500
900
1100
1
50
mV
1.25
1.50
V
3
50
mV
Output Differential
RL = 100Ω, w/o preVoltage (DOUT+)–(DOUT−) emphasis Figure 10
VODSEL = L
Tx: DOUT+, DOUT−
Output Differential
Voltage Unbalance
RL = 100Ω,
w/o pre-emphasis
VODSEL = L
Offset Voltage
RL = 100Ω,
w/o pre-emphasis
VODSEL = L
Offset Voltage
Unbalance
RL = 100Ω,
w/o pre-emphasis
VODSEL = L
Output Short Circuit
Current
DOUT = 0V, DIN = H,
TPWDNB = 2.4V
VODSEL = L
−2.0
−5.0
−8.0
VODSEL = H
−4.5
−7.9
−14.0
TRI-STATE Output
Current
TPWDNB = 0V,
DOUT = 0V OR VDD
−15
±1
+15
µA
TPWDNB = 2.4V, DEN = 0V
DOUT = 0V OR VDD
−15
±1
+15
µA
TPWDNB = 2.4V, DEN = 2.4V,
DOUT = 0V OR VDD
NO LOCK (NO TCLK)
−15
±1
+15
µA
VODSEL = H
VODSEL = H
1.00
VODSEL = H
VODSEL = H
mV
mA
The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not guaranteed.
Typical values represent most likely parametric norms at VDD = 3.3V, Ta = +25 degC, and at the Recommended Operation Conditions at
the time of product characterization and are not guaranteed.
Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD, ΔVOD, VTH and VTL which are differential voltages.
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SNLS231N – SEPTEMBER 2006 – REVISED MARCH 2013
ELECTRICAL CHARACTERISTICS(1)(2)(3) (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Pin/Freq.
Min
Typ
Max
Unit
60
85
mA
65
90
mA
66
90
mA
45
µA
SER/DES SUPPLY CURRENT (DVDD*, PVDD* AND AVDD* PINS) *DIGITAL, PLL, AND ANALOG VDDS
IDDT
Serializer
Total Supply Current
(includes load current)
RL = 100Ω, PRE = OFF,
RAOFF = H, VODSEL = L
f = 43 MHz,
CHECKER BOARD Pattern
Figure 1 (4)
RL = 100Ω, PRE = 12 kΩ,
RAOFF = H, VODSEL = L
RL = 100Ω, PRE = OFF,
RAOFF = H, VODSEL = H
IDDTZ
IDDR
IDDRZ
(4)
f = 43 MHz,
RANDOM pattern
Serializer
Supply Current Powerdown
TPWDNB = 0V
(All other LVCMOS Inputs = 0V)
Deserializer
Total Supply Current
(includes load current)
CL = 4 pF,
SLEW = H
f = 43 MHz,
CHECKER BOARD
Pattern LVCMOS Output
Figure 2 (4)
85
105
mA
CL = 4 pF,
SLEW = H
f = 43 MHz,
RANDOM pattern
LVCMOS Output
80
100
mA
50
µA
Deserializer
Supply Current Powerdown
RPWDNB = 0V
(All other LVCMOS Inputs = 0V,
RIN+/RIN-= 0V)
Figure 1, Figure 2, Figure 8, Figure 12 and Figure 14 show a falling edge data strobe (TCLK IN/RCLK OUT).
Serializer Input Timing Requirements for TCLK
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Figure 5 (1)
Min
Typ
Max
Units
23.25
T
200
ns
0.3T
0.5T
0.7T
ns
0.3T
0.5T
0.7T
ns
tTCP
Transmit Clock Period
tTCIH
Transmit Clock High Time
tTCIL
Transmit Clock Low Time
tCLKT
TCLK Input Transition Time
Figure 4 (2)
tJIT
TCLK Input Jitter
f = 43MHz (3)
±100
ps
f = 33MHz
±130
ps
(1)
(2)
(3)
2.5
ns
Figure 5, Figure 15 and Figure 16 show a rising edge data strobe (TCLK IN/RCLK OUT).
Specification is guaranteed by characterization and is not tested in production.
tJIT (@BER of 10e-9) specifies the allowable jitter on TCLK. tJIT not included in TxOUT_E_O parameter.
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Serializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
tLLHT
LVDS Low-to-High Transition Time
tLHLT
LVDS High-to-Low Transition Time
tDIS
DIN (0:23) Setup to TCLK
tDIH
DIN (0:23) Hold from TCLK
tHZD
DOUT ± HIGH to TRI-STATE Delay
tLZD
DOUT ± LOW to TRI-STATE Delay
tZHD
DOUT ± TRI-STATE to HIGH Delay
tZLD
DOUT ± TRI-STATE to LOW Delay
tPLD
Serializer PLL Lock Time
RL = 100Ω
tSD
Serializer Delay
RL = 100Ω, PRE = OFF,
RAOFF = L, TRFB = H,
Figure 8 (4)
RL = 100Ω, PRE = OFF,
RAOFF = L, TRFB = L,
Figure 8 (4)
TxOUT_E_O
(1)
(2)
(3)
(4)
(5)
(6)
(7)
6
Min
RL = 100Ω, VODSEL = L,
CL = 10 pF to GND, Figure 3
RL = 100Ω, CL = 10 pF to GND (1)
Figure 5 (2)
TxOUT_Eye_Opening.
TxOUT_E_O centered on (tBIT/)2
Max
Units
245
550
ps
264
550
ps
4
ns
4
ns
RL = 100Ω,
CL = 10 pF to GND (3)
Figure 6
5 MHz–43 MHz,
RL = 100Ω, CL = 10 pF to GND,
RANDOM pattern (5) (6) (7)
Figure 9
Typ
10
15
ns
10
15
ns
75
150
ns
75
150
ns
10
ms
3.5T+2
3.5T+10
ns
3.5T+2
3.5T+10
ns
0.76
0.84
UI
Specification is guaranteed by characterization and is not tested in production.
Figure 5, Figure 15 and Figure 16 show a rising edge data strobe (TCLK IN/RCLK OUT).
When the Serializer output is at TRI-STATE the Deserializer will lose PLL lock. Resynchronization MUST occur before data transfer.
Figure 1, Figure 2, Figure 8, Figure 12 and Figure 14 show a falling edge data strobe (TCLK IN/RCLK OUT).
tJIT (@BER of 10e-9) specifies the allowable jitter on TCLK. tJIT not included in TxOUT_E_O parameter.
UI – Unit Interval, equivalent to one ideal serialized data bit width. The UI scales with frequency.
TxOUT_E_O is affected by pre-emphasis value.
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SNLS231N – SEPTEMBER 2006 – REVISED MARCH 2013
Deserializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Pin/Freq.
tRCP
Receiver out Clock Period
tRCP = tTCP,
PTOSEL = H
tRDC
RCLK Duty Cycle
PTOSEL = H,
SLEW = L
tCLH
LVCMOS Low-to-High
Transition Time
tCHL
LVCMOS High-to-Low
Transition Time
CL = 4 pF
(lumped load),
SLEW = H (2) (1)
tCLH
LVCMOS Low-to-High
Transition Time
tCHL
LVCMOS High-to-Low
Transition Time
tROS
ROUT (0:7) Setup Data to
RCLK (Group 1)
tROH
ROUT (0:7) Hold Data to RCLK
(Group 1)
tROS
ROUT (8:15) Setup Data to
RCLK (Group 2)
tROH
ROUT (8:15) Hold Data to
RCLK (Group 2)
tROS
ROUT (16:23) Setup Data to
RCLK (Group 3)
tROH
ROUT (16:23) Setup Data to
RCLK (Group 3)
tROS
ROUT (0:7) Setup Data to
RCLK (Group 1)
tROH
ROUT (0:7) Hold Data to RCLK
(Group 1)
tROS
ROUT (8:15) Setup Data to
RCLK (Group 2)
tROH
ROUT (8:15) Hold Data to
RCLK (Group 2)
tROS
ROUT (16:23) Setup Data to
RCLK (Group 3)
tROH
ROUT (16:23) Setup Data to
RCLK (Group 3)
tHZR
HIGH to TRI-STATE Delay
tLZR
LOW to TRI-STATE Delay
tZHR
TRI-STATE to HIGH Delay
tZLR
TRI-STATE to LOW Delay
tDD
Deserializer Delay
PTOSEL = H,
Figure 12 (3)
RCLK
tDSR
Deserializer PLL Lock Time
from Powerdown
See (2) (4)
CL = 4 pF
(lumped load),
SLEW = L (2) (1)
PTOSEL = L,
SLEW = H,
Figure 16 (1)
PTOSEL = L,
SLEW = H,
Figure 16 (1)
RCLK
Figure 15 (1)
ROUT[0:7]
ROUT [8:15],
LOCK
ROUT[0:7]
ROUT [16:23]
(2) (5) (6)
23.25
T
200
ns
45
50
55
%
1.5
2.5
ns
1.5
2.5
ns
2.0
3.5
ns
2.0
3.5
ns
(0.35)*
tRCP
(0.5*tRCP)–3 UI
ns
(0.35)*
tRCP
(0.5*tRCP)–3 UI
ns
(0.35)*
tRCP
(0.5*tRCP)–3 UI
ns
(0.35)*
tRCP
(0.5*tRCP)–3 UI
ns
(0.35)*
tRCP
(0.5*tRCP)–3 UI
ns
(0.35)*
tRCP
(0.5*tRCP)–3 UI
ns
(0.35)*
tRCP
(0.5*tRCP)–2 UI
ns
(0.35)*
tRCP
(0.5*tRCP)+2 UI
ns
(0.35)*
tRCP
(0.5*tRCP)−1 UI
ns
(0.35)*
tRCP
(0.5*tRCP)+1 UI
ns
(0.35)*
tRCP
(0.5*tRCP)+1 UI
ns
(0.35)*
tRCP
(0.5*tRCP)–1 UI
ns
3
10
ns
3
10
ns
3
10
ns
3
10
ns
[5+(5/56)]T+3.7
[5+(5/56)]T
+8
ns
5 MHz
128k*T
ms
43 MHz
128k*T
ms
0.25
UI
0.25
UI
Receiver INput TOLerance
Left
See
Figure 17
5 MHz–43 MHz
RxIN_TOL-R
Receiver INput TOLerance
Right
See (2) (5) (6)
Figure 17
5 MHz–43 MHz
(6)
Units
ROUT [0:23],
RCLK, LOCK
RxIN_TOL-L
(1)
(2)
(3)
(4)
(5)
Max
ROUT [0:23],
RCLK, LOCK
ROUT [8:15],
LOCK
PTOSEL = H,
Figure 14 (3)
Typ
ROUT [0:23],
RCLK, LOCK
ROUT [16:23]
PTOSEL = H,
SLEW = H,
Figure 15 (1)
Min
Figure 5, Figure 15 and Figure 16 show a rising edge data strobe (TCLK IN/RCLK OUT).
Specification is guaranteed by characterization and is not tested in production.
Figure 1, Figure 2, Figure 8, Figure 12 and Figure 14 show a falling edge data strobe (TCLK IN/RCLK OUT).
tDSR is the time required by the Deserializer to obtain lock when exiting powerdown mode.
RxIN_TOL is a measure of how much phase noise (jitter) the Deserializer can tolerate in the incoming data stream before bit errors
occur. It is a measurement in reference with the ideal bit position, please see AN-1217 (SNLA053) for detail.
UI – Unit Interval, equivalent to one ideal serialized data bit width. The UI scales with frequency.
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AC Timing Diagrams and Test Circuits
Device Pin Name
Signal Pattern
TCLK
ODD DIN
EVEN DIN
Figure 1. Serializer Input Checkerboard Pattern
Device Pin Name
Signal Pattern
RCLK
ODD ROUT
EVEN ROUT
Figure 2. Deserializer Output Checkerboard Pattern
DOUT+
10 pF
Vdiff
100:
80%
80%
20%
DOUT-
10 pF
Vdiff = 0V
20%
tLLHT
tLHLT
Vdiff = (DOUT+) - (DOUT-)
Figure 3. Serializer LVDS Output Load and Transition Times
80%
VDD
80%
TCLK
20%
20%
0V
tCLKT
tCLKT
Figure 4. Serializer Input Clock Transition Times
8
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tTCP
TCLK
VDD/2
tDIS
VDD/2
VDD/2
tDIH
VDD
DIN [0:23]
Setup
VDD/2
Hold
VDD/2
0V
Figure 5. Serializer Setup/Hold Times
Parasitic package and
Trace capacitance
DOUT+
5 pF
100:
DOUTDEN
tLZD
DEN
VCC/2
(single-ended)
0V
VCC/2
0V
CLK1
CLK1
tTCP
tTCP
DOUT±
(differential)
200 mV
DCA
tZLD
200 mV
DCA
DCA
DCA
$OO GDWD ³0´V
DCA
DCA
DCA
DCA
tHZD
DEN
VCC/2
(single-ended)
0V
VCC/2
0V
$OO GDWD ³1´V
tZHD
200 mV
DCA
DCA
DCA
DCA
DCA
DCA
DCA
DCA
200 mV
DOUT±
(differential)
tTCP
CLK0
tTCP
CLK0
Figure 6. Serializer TRI-STATE Test Circuit and Delay
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2.0V
PWDWN
0.8V
tHZD or
tLZD
TCLK
tZHD or
tZLD
tPLD
Output
Active
TRI-STATE
DOUT±
TRI-STATE
DIN
SYMBOL N
SYMBOL N+1
SYMBOL N+2
| |
Figure 7. Serializer PLL Lock Time, and TPWDNB TRI-STATE Delays
SYMBOL N+3
|
tSD
TCLK
2
23
0
1
2
23
0
1
2
23
0
1
2
STOP START
BIT BIT
23
0
STOP
BIT
SYMBOL N
1
2
| |
1
STOP START
BIT BIT
SYMBOL N-1
| |
0
| |
DCA, DCB
| |
DOUT0-23
STOP START
BIT BIT
SYMBOL N-2
| |
STOP START
BIT BIT
SYMBOL N-3
SYMBOL N-4
23
Figure 8. Serializer Delay
Ideal Data Bit
End
Ideal Data Bit
Beginning
TxOUT_E_O
tBIT(1/2 UI)
tBIT(1/2 UI)
Ideal Center Position (tBIT/2)
tBIT (1 UI)
Figure 9. Transmitter Output Eye Opening (TxOUT_E_O)
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PARALLEL-TO-SERIAL
www.ti.com
24
DIN
DOUT+
RL
20194528
DOUT-
TCLK
VOD = (DOUT+) – (DOUT−)
Differential output signal is shown as (DOUT+) – (DOUT−), device in Data Transfer mode.
Figure 10. Serializer VOD Diagram
80%
80%
Deserializer
20%
4 pF
lumped
20%
tCLH
tCHL
Figure 11. Deserializer LVCMOS Output Load and Transition Times
2
23
0
1
2
23
0
1
2
23
0
1
2
STOP
BIT
| |
1
STOP START
BIT BIT
SYMBOL N+3
| |
0
STOP START
BIT BIT
SYMBOL N+2
| |
RIN0-23
DCA, DCB
STOP START
BIT BIT
SYMBOL N+1
SYMBOL N
| |
START
BIT
23
tDD
RCLK
ROUT0-23
SYMBOL N-3
SYMBOL N-2
SYMBOL N-1
SYMBOL N
Figure 12. Deserializer Delay
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500:
VREF
CL = 8 pF
VREF = VDD/2 for tZLR or tLZR,
+
-
VREF = 0V for tZHR or tHZR
REN
NOTE:
CL includes instrumentation and fixture capacitance within 6 cm of ROUT [23:0].
VOH
VDD/2
REN
VDD/2
VOL
tLZR
tZLR
VOL + 0.5V
VOL + 0.5V
VOL
ROUT [23:0]
tHZR
tZHR
VOH
VOH - 0.5V
VOH + 0.5V
Figure 13. Deserializer TRI-STATE Test Circuit and Timing
2.0V
PWDN
0.8V
| |
tDSR
RIN±
LOCK
}v[š
TRI-STATE
Œ
TRI-STATE
tHZR or tLZR
ROUT [0:23]
TRI-STATE
TRI-STATE
RCLK
TRI-STATE
TRI-STATE
REN
Figure 14. Deserializer PLL Lock Times and RPWDNB TRI-STATE Delay
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tRCP
tRDC
RCLK
tRDC
VDD/2
VDD/2
tROS
ROUT [7:0]
VDD/2
(group 1)
Data Valid
Before RCLK
tROH
Data Valid
After RCLK
VDD/2
| -2 UI
| +2 UI
tROS
ROUT [15:8]
VDD/2
(group 2)
Data Valid
Before RCLK
| -1 UI
ROUT [23:16]
VDD/2
(group 3)
tROS
Data Valid
Before RCLK
tROH
Data Valid
After RCLK
VDD/2
| +1 UI
tROH
Data Valid
After RCLK
VDD/2
| +1 UI
| -1 UI
Figure 15. Deserializer Setup and Hold Times and PTO, PTOSEL = H
ROUT
(Ideal)
½ Symbol
½ Symbol
RCLK
ROUT
GRP1
2 UI EARLY
1 + 3/28 Symbol
1 - 2/28 Symbol
1 UI LATE
1 + 3/28 Symbol
1 UI EARLY
1 - 4/28 Symbol
2 UI LATE
2 UI EARLY
Group 1 will be latched internally by sequence of (early 2UI, late 1UI, early 1UI, late 2UI)
Group 2 will be latched internally by sequence of (late 1UI, early 1UI, late 2UI, early 2UI)
Group 3 will be latched internally by sequence of (early 1UI, late 2UI, early 2UI, late 1UI)
Figure 16. Deserializer Setup and Hold Times and PTO Spread, PTOSEL = L
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Sampling
Window
Ideal Data Bit
Beginning
Ideal Data Bit
End
RxIN_TOL -L
RxIN_TOL -R
Ideal Center Position (tBIT/2)
tBIT (1 UI)
RxIN_TOL_L is the ideal noise margin on the left of the figure, with respect to ideal.
RxIN_TOL_R is the ideal noise margin on the right of the figure, with respect to ideal.
Figure 17. Receiver Input Tolerance (RxIN_TOL) and Sampling Window
DIN[9]
DIN[8]
DIN[7]
DIN[6]
DIN[5]
VSS
VDD
DIN[4]
DIN[3]
DIN[2]
DIN[1]
DIN[0]
36
35
34
33
32
31
30
29
28
27
26
25
DS90UR241 Pin Diagram
DIN[10]
37
24
VODSEL
DIN[11]
38
23
PRE
DIN[12]
39
22
VDD
DIN[13]
40
21
VSS
DIN[14]
41
20
DOUT+
VDD
42
19
DOUT-
VSS
43
18
DEN
DIN[15]
44
17
VSS
DIN[16]
45
16
VDD
DIN[17]
46
15
VSS
DIN[18]
47
14
VDD
DIN[19]
48
13
RES0
7
8
9
VDD
RES0
TPWDNB
12
6
VSS
RAOFF
5
RES0
11
4
DIN[23]
TRFB
3
DIN[22]
10
2
DIN[21]
TCLK
1
DIN[20]
DS90UR241
Figure 18. Serializer - DS90UR241
TOP VIEW
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SNLS231N – SEPTEMBER 2006 – REVISED MARCH 2013
DS90UR241 Serializer Pin Descriptions
Pin #
Pin Name
I/O/PWR
Description
LVCMOS PARALLEL INTERFACE PINS
4-1,
DIN[23:0]
48-44,
41-32,
29-25
LVCMOS_I
Transmitter Parallel Interface Data Input Pins. Tie LOW if unused, do not float.
10
LVCMOS_I
Transmitter Parallel Interface Clock Input Pin. Strobe edge set by TRFB configuration pin.
TCLK
CONTROL AND CONFIGURATION PINS
9
TPWDNB
LVCMOS_I
Transmitter Power Down Bar
TPWDNB = H; Transmitter is Enabled and ON
TPWDNB = L; Transmitter is in power down mode (Sleep), LVDS Driver DOUT (+/-) Outputs are in
TRI-STATE stand-by mode, PLL is shutdown to minimize power consumption.
24
VODSEL
LVCMOS_I
VOD Level Select
VODSEL = L; LVDS Driver Output is ±500 mV (RL = 100Ω)
VODSEL = H; LVDS Driver Output is ±900 mV (RL = 100Ω)
For normal applications, set this pin LOW. For long cable applications where a larger VOD is
required, set this pin HIGH.
18
DEN
LVCMOS_I
Transmitter Data Enable
DEN = H; LVDS Driver Outputs are Enabled (ON).
DEN = L; LVDS Driver Outputs are Disabled (OFF), Transmitter LVDS Driver DOUT (+/-) Outputs
are in TRI-STATE, PLL still operational and locked to TCLK.
23
PRE
LVCMOS_I
Pre-emphasis Level Select
PRE = NC (No Connect); Pre-emphasis is Disabled (OFF).
Pre-emphasis is active when input is tied to VSS through external resistor RPRE. Resistor value
determines pre-emphasis level. Recommended value RPRE ≥ 6 kΩ; Imax = [48 / RPRE], RPREmin =
6 kΩ
11
TRFB
LVCMOS_I
Transmitter Clock Edge Select Pin
TRFB = H; Parallel Interface Data is strobed on the Rising Clock Edge.
TRFB = L; Parallel Interface Data is strobed on the Falling Clock Edge
12
RAOFF
LVCMOS_I
Randomizer Control Input Pin
RAOFF = H, Backwards compatible mode for use with DS90C124 Deserializer.
RAOFF = L; Additional randomization ON (Default), Selects 2E7 LSFR setting.
See Table 1 for more details.
5, 8,
13
RES0
LVCMOS_I
Reserved. This pin MUST be tied LOW.
LVDS SERIAL INTERFACE PINS
20
DOUT+
LVDS_O
Transmitter LVDS True (+) Output.
This output is intended to be loaded with a 100Ω load to the DOUT+ pin. The interconnect should
be AC Coupled to this pin with a 100 nF capacitor.
19
DOUT−
LVDS_O
Transmitter LVDS Inverted (-) Output
This output is intended to be loaded with a 100Ω load to the DOUT-pin. The interconnect should be
AC Coupled to this pin with a 100 nF capacitor.
POWER / GROUND PINS
22
VDD
VDD
Analog Voltage Supply, LVDS Output POWER
21
VSS
GND
Analog Ground, LVDS Output GROUND
16
VDD
VDD
Analog Voltage Supply, VCO POWER
17
VSS
GND
Analog Ground, VCO GROUND
14
VDD
VDD
Analog Voltage Supply, PLL POWER
15
VSS
GND
Analog Ground, PLL GROUND
30
VDD
VDD
Digital Voltage Supply, Serializer POWER
31
VSS
GND
Digital Ground, Serializer GROUND
7
VDD
VDD
Digital Voltage Supply, Serializer Logic POWER
6
VSS
GND
Digital Ground, Serializer Logic GROUND
42
VDD
VDD
Digital Voltage Supply, Serializer INPUT POWER
43
VSS
GND
Digital Ground, Serializer Input GROUND
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PTOSEL
49
RES0
50
VDD
ROUT[3]
VDD
VSS
ROUT[4]
ROUT[5]
ROUT[6]
ROUT[7]
RES0
RES0
39
38
37
36
35
34
33
ROUT[2]
42
40
ROUT[1]
43
41
PASS
ROUT[0]
46
44
VDD
47
45
RPWDNB
VSS
48
DS90UR124 Pin Diagram
32
PTO GROUP 1
VDD
31
VSS
51
30
ROUT[8]
52
29
ROUT[9]
53
28
ROUT[10]
RIN-
54
27
ROUT[11]
RRFB
55
26
VDD
VSS
56
25
VSS
VDD
57
24
RCLK
VSS
58
23
LOCK
VDD
59
22
ROUT[12]
REN
60
21
ROUT[13]
BISTEN
61
20
ROUT[14]
BISTM
62
19
ROUT[15]
RAOFF
63
18
RES0
SLEW
64
17
RES0
PTO GROUP 2
VSS
RIN+
DS90UR124
8
9
10
11
12
13
14
15
16
ROUT[22]
ROUT[21]
ROUT[20]
VDD
VSS
ROUT[19]
ROUT[18]
ROUT[17]
ROUT[16]
5
RES0
7
4
RES0
6
3
RES0
RES0
2
RES0
ROUT[23]
1
RES0
PTO GROUP 3
Figure 19. Deserializer - DS90UR124
TOP VIEW
DS90UR124 Deserializer Pin Descriptions
Pin #
Pin Name
I/O/PWR
Description
LVCMOS PARALLEL INTERFACE PINS
35-38, ROUT[7:0]
41-44
LVCMOS_O
Receiver Parallel Interface Data Outputs – Group 1
19-22, ROUT[15:8]
27-30
LVCMOS_O
Receiver Parallel Interface Data Outputs – Group 2
7-10,
13-16
ROUT[23:16]
LVCMOS_O
Receiver Parallel Interface Data Outputs – Group 3
24
RCLK
LVCMOS_O
Parallel Interface Clock Output Pin. Strobe edge set by RRFB configuration pin.
CONTROL AND CONFIGURATION PINS
55
RRFB
LVCMOS_I
Receiver Clock Edge Select Pin
RRFB = H; ROUT LVCMOS Outputs strobed on the Rising Clock Edge.
RRFB = L; ROUT LVCMOS Outputs strobed on the Falling Clock Edge.
60
REN
LVCMOS_I
Receiver Data Enable
REN = H; ROUT[23-0] and RCLK are Enabled (ON).
REN = L; ROUT[23-0] and RCLK are Disabled (OFF), Receiver ROUT[23-0] and RCLK Outputs are
in TRI-STATE, PLL still operational and locked to TCLK.
48
RPWDNB
LVCMOS_I
Receiver Power Down Bar
RPWDNB = H; Receiver is Enabled and ON
RPWDNB = L; Receiver is in power down mode (Sleep), ROUT[23-0], RCLK, and LOCK are in
TRI-STATE stand-by mode, PLL is shutdown to minimize power consumption.
49
PTOSEL
LVCMOS_I
Progressive Turn On Operation Selection
PTO = H; ROUT[23:0] are grouped into three groups of eight, with each group switching about ±1
UI to ±2 UI apart relative to RCLK. (Figure 15)
PTO = L; PTO Spread Mode, ROUT[23:0] outputs are spread ±1 UI to ±2 UI and RCLK spread ±1
UI. (Figure 16) See Applications Informations section for more details.
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SNLS231N – SEPTEMBER 2006 – REVISED MARCH 2013
DS90UR124 Deserializer Pin Descriptions (continued)
Pin #
Pin Name
I/O/PWR
Description
63
RAOFF
LVCMOS_I
Randomizer Control Input Pin (See Table 2 for more details.)
RAOFF = H, Backwards compatible mode for use with DS90C241 Serializer.
RAOFF = L; Additional randomization ON (Default), Selects 2E7 LSFR setting.
64
SLEW
LVCMOS_I
LVCMOS Output Slew Rate Control
SLEW = L; Low drive output at 2 mA (default)
SLEW = H; High drive output at 4 mA
23
LOCK
LVCMOS_O
LOCK indicates the status of the receiver PLL
LOCK = H; receiver PLL is locked
LOCK = L; receiver PLL is unlocked, ROUT[23-0] and RCLK are at TRI-STATE.
50
RES0
LVCMOS_I
Reserved. This pin MUST be tied LOW.
NC
No Connection. Pins are not physically connected to the die. Recommendation is to leave pin
open or tie it to LOW.
1-6,
RES0
17,
18,
33, 34
BIST MODE PINS(See Applications Informations section for more details.)
61
BISTEN
LVCMOS_I
Control Pin for BIST Mode Enable
BISTEN = L; Default at Low, Normal Mode.
BISTEN = H; BIST mode active. When BISTEN = H and DS90UR241 DIN[23:0] = Low or
Floating; device will go to BIST mode accordingly. Check PASS output pin for test status.
62
BISTM
LVCMOS_I
BIST Mode selection. Control pin for which Deserializer is set for BIST reporting mode.
BISTM = L; Default at Low, Status of all ROUT with respective bit error on cycle-by-cycle basis
BISTM = H; Total accumulated bit error count provided on ROUT[7:0] (binary counter up to 255)
45
PASS
LVCMOS_O
Pass flag output for @Speed BIST Test operation.
PASS = L; BIST failure
PASS = H; LOCK = H before BIST can be enabled, then 1x10-9 error rate achieved across link.
LVDS SERIAL INTERFACE PINS
53
RIN+
LVDS_I
Receiver LVDS True (+) Input — This input is intended to be terminated with a 100Ω load to the
RIN+ pin. The interconnect should be AC Coupled to this pin with a 100 nF capacitor.
54
RIN−
LVDS_I
Receiver LVDS Inverted (−) Input — This input is intended to be terminated with a 100Ω load to
the RIN-pin. The interconnect should be AC Coupled to this pin with a 100 nF capacitor.
POWER / GROUND PINS
51
VDD
VDD
Analog LVDS Voltage Supply, POWER
52
VSS
GND
Analog LVDS GROUND
59
VDD
VDD
Analog Voltage Supply, PLL POWER
58
VSS
GND
Analog Ground, PLL GROUND
57
VDD
VDD
Analog Voltage supply, PLL VCO POWER
56
VSS
GND
Analog Ground, PLL VCO GROUND
32
VDD
VDD
Digital Voltage Supply, LOGIC POWER
31
VSS
GND
Digital Ground, Logic GROUND
46
VDD
VDD
Digital Voltage Supply, LOGIC POWER
47
VSS
GND
Digital Ground, LOGIC GROUND
40
VDD
VDD
Digital Voltage Supply, LVCMOS Output POWER
39
VSS
GND
Digital Ground, LVCMOS Output GROUND
26
VDD
VDD
Digital Voltage Supply, LVCMOS Output POWER
25
VSS
GND
Digital Ground, LVCMOS Output GROUND
11
VDD
VDD
Digital Voltage Supply, LVCMOS Output POWER
12
VSS
GND
Digital Ground, LVCMOS Output GROUND
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Functional Description
The DS90UR241 Serializer and DS90UR124 Deserializer chipset is an easy-to-use transmitter and receiver pair
that sends 24-bits of parallel LVCMOS data over a single serial LVDS link from 120 Mbps to 1.03 Gbps
throughput. The DS90UR241 transforms a 24-bit wide parallel LVCMOS data into a single high speed LVDS
serial data stream with embedded clock and scrambles / DC Balances the data to enhance signal quality to
support AC coupling. The DS90UR124 receives the LVDS serial data stream and converts it back into a 24-bit
wide parallel data and recovered clock. The 24-bit Serializer/Deserializer chipset is designed to transmit data up
to 10 meters over shielded twisted pair (STP) at clock speeds from 5 MHz to 43MHz.
The Deserializer can attain lock to a data stream without the use of a separate reference clock source; greatly
simplifying system complexity and overall cost. The Deserializer synchronizes to the Serializer regardless of data
pattern, delivering true automatic “plug and lock” performance. It will lock to the incoming serial stream without
the need of special training patterns or sync characters. The Deserializer recovers the clock and data by
extracting the embedded clock information and validating data integrity from the incoming data stream and then
deserializes the data. The Deserializer monitors the incoming clock information, determines lock status, and
asserts the LOCK output high when lock occurs.
In addition the Deserializer also supports an optional @SPEED BIST (Built In Self Test) mode, BIST error flag,
and LOCK status reporting pin. Signal quality on the wide parallel output is controlled by the SLEW control and
bank slew (PTOSEL) inputs to help reduce noise and system EMI. Each device has a power down control to
enable efficient operation in various applications.
INITIALIZATION AND LOCKING MECHANISM
Initialization of the DS90UR241 and DS90UR124 must be established before each device sends or receives
data. Initialization refers to synchronizing the Serializer’s and Deserializer’s PLL’s together. After the Serializers
locks to the input clock source, the Deserializer synchronizes to the Serializers as the second and final
initialization step.
Step 1: When VDD is applied to both Serializer and/or Deserializer, the respective outputs are held in TRI-STATE
and internal circuitry is disabled by on-chip power-on circuitry. When VDD reaches VDD OK (~2.2V) the PLL in
Serializer begins locking to a clock input. For the Serializer, the local clock is the transmit clock, TCLK. The
Serializer outputs are held in TRI-STATE while the PLL locks to the TCLK. After locking to TCLK, the Serializer
block is now ready to send data patterns. The Deserializer output will remain in TRI-STATE while its PLL locks to
the embedded clock information in serial data stream. Also, the Deserializer LOCK output will remain low until its
PLL locks to incoming data and sync-pattern on the RIN± pins.
Step 2: The Deserializer PLL acquires lock to a data stream without requiring the Serializer to send special
patterns. The Serializer that is generating the stream to the Deserializer will automatically send random (nonrepetitive) data patterns during this step of the Initialization State. The Deserializer will lock onto embedded clock
within the specified amount of time. An embedded clock and data recovery (CDR) circuit locks to the incoming bit
stream to recover the high-speed receive bit clock and re-time incoming data. The CDR circuit expects a coded
input bit stream. In order for the Deserializer to lock to a random data stream from the Serializer, it performs a
series of operations to identify the rising clock edge and validates data integrity, then locks to it. Because this
locking procedure is independent on the data pattern, total random locking duration may vary. At the point when
the Deserializer’s CDR locks to the embedded clock, the LOCK pin goes high and valid RCLK/data appears on
the outputs. Note that the LOCK signal is synchronous to valid data appearing on the outputs. The Deserializer’s
LOCK pin is a convenient way to ensure data integrity is achieved on receiver side.
DATA TRANSFER
After Serializer lock is established, the inputs DIN0–DIN23 are used to input data to the Serializer. Data is
clocked into the Serializer by the TCLK input. The edge of TCLK used to strobe the data is selectable via the
TRFB pin. TRFB high selects the rising edge for clocking data and low selects the falling edge. The Serializer
outputs (DOUT±) are intended to drive point-to-point connections.
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CLK1, CLK0, DCA, DCB are four overhead bits transmitted along the single LVDS serial data stream (Figure 24).
The CLK1 bit is always high and the CLK0 bit is always low. The CLK1 and CLK0 bits function as the embedded
clock bits in the serial stream. DCB functions as the DC Balance control bit. It does not require any pre-coding of
data on transmit side. The DC Balance bit is used to minimize the short and long-term DC bias on the signal
lines. This bit operates by selectively sending the data either unmodified or inverted. The DCA bit is used to
validate data integrity in the embedded data stream. Both DCA and DCB coding schemes are integrated and
automatically performed within Serializer and Deserializer.
The chipset supports clock frequency ranges of 5 MHz to 43 MHz. Every clock cycle, 24 databits are sent along
with 4 additional overhead control bits. Thus the line rate is 1.20 Gbps maximum (140Mbps minimum). The link is
extremely efficient at 86% (24/28). Twenty five (24 data + 1 clock) plus associated ground signals are reduced to
only 1 single LVDS pair providing a compression ratio of better then 25 to 1.
In the serialized data stream, data/embedded clock & control bits (24+4 bits) are transmitted from the Serializer
data output (DOUT±) at 28 times the TCLK frequency. For example, if TCLK is 43 MHz, the serial rate is 43 x 28
= 1.20 Giga bits per second. Since only 24 bits are from input data, the serial “payload” rate is 24 times the
TCLK frequency. For instance, if TCLK = 43 MHz, the payload data rate is 43 x 24 = 1.03 Gbps. TCLK is
provided by the data source and must be in the range of 5 MHz to 43 MHz nominal. The Serializer outputs
(DOUT±) can drive a point-to-point connection as shown in Figure 23. The outputs transmit data when the enable
pin (DEN) is high and TPWDNB is high. The DEN pin may be used to TRI-STATE the outputs when driven low.
When the Deserializer channel attains lock to the input from a Serializer, it drives its LOCK pin high and
synchronously delivers valid data and recovered clock on the output. The Deserializer locks onto the embedded
clock, uses it to generate multiple internal data strobes, and then drives the recovered clock to the RCLK pin.
The recovered clock (RCLK output pin) is synchronous to the data on the ROUT[23:0] pins. While LOCK is high,
data on ROUT[23:0] is valid. Otherwise, ROUT[23:0] is invalid. The polarity of the RCLK edge is controlled by the
RRFB input. ROUT[23:0], LOCK and RCLK outputs will each drive a maximum of 4 pF load with a 43 MHz clock.
REN controls TRI-STATE for ROUTn and the RCLK pin on the Deserializer.
RESYNCHRONIZATION
If the Deserializer loses lock, it will automatically try to re-establish lock. For example, if the embedded clock
edge is not detected one time in succession, the PLL loses lock and the LOCK pin is driven low. The Deserializer
then enters the operating mode where it tries to lock to a random data stream. It looks for the embedded clock
edge, identifies it and then proceeds through the locking process.
The logic state of the LOCK signal indicates whether the data on ROUT is valid; when it is high, the data is valid.
The system may monitor the LOCK pin to determine whether data on the ROUT is valid.
POWERDOWN
The Powerdown state is a low power sleep mode that the Serializer and Deserializer may use to reduce power
when no data is being transferred. The TPWDNB and RPWDNB are used to set each device into power down
mode, which reduces supply current to the µA range. The Serializer enters powerdown when the TPWDNB pin is
driven low. In powerdown, the PLL stops and the outputs go into TRI-STATE, disabling load current and reducing
current supply. To exit Powerdown, TPWDNB must be driven high. When the Serializer exits Powerdown, its PLL
must lock to TCLK before it is ready for the Initialization state. The system must then allow time for Initialization
before data transfer can begin. The Deserializer enters powerdown mode when RPWDNB is driven low. In
powerdown mode, the PLL stops and the outputs enter TRI-STATE. To bring the Deserializer block out of the
powerdown state, the system drives RPWDNB high.
Both the Serializer and Deserializer must reinitialize and relock before data can be transferred. The Deserializer
will initialize and assert LOCK high when it is locked to the embedded clock.
TRI-STATE
For the Serializer, TRI-STATE is entered when the DEN or TPWDNB pin is driven low. This will TRI-STATE both
driver output pins (DOUT+ and DOUT−). When DEN is driven high, the serializer will return to the previous state
as long as all other control pins remain static (TPWDNB, TRFB).
When you drive the REN or RPWDNB pin low, the Deserializer enters TRI-STATE. Consequently, the receiver
output pins (ROUT0–ROUT23) and RCLK will enter TRI-STATE. The LOCK output remains active, reflecting the
state of the PLL. The Deserializer input pins are high impedance during receiver powerdown (RPWDNB low) and
power-off (VDD = 0V).
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PRE-EMPHASIS
The DS90UR241 features a Pre-Emphasis function used to compensate for long or lossy transmission media.
Cable drive is enhanced with a user selectable Pre-Emphasis feature that provides additional output current
during transitions to counteract cable loading effects. The transmission distance will be limited by the loss
characteristics and quality of the media. Pre-Emphasis adds extra current during LVDS logic transition to reduce
the cable loading effects and increase driving distance. In addition, Pre-Emphasis helps provide faster
transitions, increased eye openings, and improved signal integrity. The ability of the DS90UR241 to use the PreEmphasis feature will extend the transmission distance up to 10 meters in most cases.
To enable the Pre-Emphasis function, the “PRE” pin requires one external resistor (Rpre) to Vss in order to set
the additional current level. Values of Rpre should be between 6kΩ and 100MΩ. Values less than 6kΩ should not
be used. A lower input resistor value on the ”PRE” pin increases the magnitude of dynamic current during data
transition. The additional source current is based on the following formula: PRE = (RPRE ≥ 6kΩ); IMAX = [48 /
RPRE]. For example if Rpre = 15kΩ , then the Pre-Emphasis current is increase by an additional 3.2 mA.
The amount of Pre-Emphasis for a given media will depend on the transmission distance of the application. In
general, too much Pre-Emphasis can cause over or undershoot at the receiver input pins. This can result in
excessive noise, crosstalk and increased power dissipation. For short cables or distances, Pre-Emphasis may
not be required. Signal quality measurements are recommended to determine the proper amount of PreEmphasis for each application.
AC-COUPLING AND TERMINATION
The DS90UR241 and DS90UR124 supports AC-coupled interconnects through integrated DC balanced
encoding/decoding scheme. To use the Serializer and Deserializer in an AC coupled application, insert external
AC coupling capacitors in series in the LVDS signal path as illustrated in Figure 23. The Deserializer input stage
is designed for AC-coupling by providing a built-in AC bias network which sets the internal VCM to +1.8V. With AC
signal coupling, capacitors provide the ac-coupling path to the signal input.
For the high-speed LVDS transmissions, the smallest available package should be used for the AC coupling
capacitor. This will help minimize degradation of signal quality due to package parasitics. The most common
used capacitor value for the interface is 100 nF (0.1 uF) capacitor. NPO class 1 or X7R class 2 type capacitors
are recommended. 50 WVDC should be the minimum used for the best system-level ESD performance.
A termination resistor across DOUT± and RIN± is also required for proper operation to be obtained. The
termination resistor should be equal to the differential impedance of the media being driven. This should be in the
range of 90 to 132 Ohms. 100 Ohms is a typical value common used with standard 100 Ohm transmission
media. This resistor is required for control of reflections and also completes the current loop. It should be placed
as close to the Serializer DOUT± outputs and Deserializer RIN± inputs to minimize the stub length from the pins.
To match with the deferential impedance on the transmission line, the LVDS I/O are terminated with 100 Ohm
resistors on Serializer DOUT± outputs pins and Deserializer RIN± input pins.
Receiver Termination Option 1
A single 100 Ohm termination resistor is placed across the RIN± pins (see Figure 23). This provides the signal
termination at the Receiver inputs. Other options may be used to increase noise tolerance.
Receiver Termination Option 2
For additional EMI tolerance, two 50 Ohm resistors may be used in place of the single 100 Ohm resistor. A small
capacitor is tied from the center point of the 50 Ohm resistors to ground (see Figure 25). This provides a highfrequency low impedance path for noise suppression. Value is not critical, 4.7nF maybe used with general
applications.
Receiver Termination Option 3
For high noise environments an additional voltage divider network may be connected to the center point. This
has the advantage of a providing a DC low-impedance path for noise suppression. Use resistor values in the
range of 100Ω-2KΩ for the pullup and pulldown. Ratio the resistor values to bias the center point at 1.8V. For
example (see Figure 26): VDD=3.3V, Rpullup=1KΩ, Rpulldown=1.2KΩ; or Rpullup=100Ω, Rpulldown=120Ω
(strongest). The smaller values will consume more bias current, but will provide enhanced noise suppression.
20
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SNLS231N – SEPTEMBER 2006 – REVISED MARCH 2013
SIGNAL QUALITY ENHANCERS
The DS90UR124 Deserializer supports two signal quality enhancers. The SLEW pin is used to increase the drive
strength of the LVCMOS outputs when driving heavy loads. SLEW allows output drive strength for high or low
current drive. Default setting is LOW for low drive at 2 mA and HIGH for high drive at 4 mA.
There are two types of Progressive Turn-On modes (Fixed and PTO Frequency Spread) to help reduce EMI,
simultaneous switching noise, and system ground bounce. The PTOSEL pin introduces bank skew in the
data/clock outputs to limit the number of outputs switching simultaneously. For Fixed-PTO mode, the Deserializer
ROUT[23:0] outputs are grouped into three groups of eight, with each group switching about 2 or 1 UI apart in
phase from RCLK for Group 1 and Groups 2, 3 respectively (see Figure 15). In the PTO Frequency Spread
mode, ROUT[23:0] are also grouped into three groups of eight, with each group is separated out of phase with
the adjacent groups (see Figure 16) per every 4 cycles. Note that in the PTO Frequency Spread operating mode
RCLK is also spreading and separated by 1 UI.
@SPEED-BIST TEST FEATURE
To assist vendors with test verification, the DS90UR241/DS90UR124 is equipped with built-in self-test (BIST)
capability to support both system manufacturing and field diagnostics. BIST mode is intended to check the entire
high-speed serial link at full link-speed, without the use of specialized and expensive test equipment. This feature
provides a simple method for a system host to perform diagnostic testing of both Serializer and Deserializer. The
BIST function is easily configured through the 2 control pins on the DS90UR124. When the BIST mode is
activated, the Serializer has the ability to transfer an internally generated PRBS data pattern. This pattern
traverses across interconnecting links to the Deserializer. The DS90UR124 includes an on-chip PRBS pattern
verification circuit that checks the data pattern for bit errors and reports any errors on the data output pins on the
Deserializer.
The @SPEED-BIST feature uses 2 signal pins (BISTEN and BISTM) on the DS90UR124 Deserializer. The
BISTEN and BISTM pins together determine the functions of the BIST mode. The BISTEN signal (HIGH)
activates the test feature on the Deserializer. After the BIST mode is enabled, all the data input channels
DIN[23:0] on the DS90UR241 Serializer must be set logic LOW or floating in order for Deserializer to start
accepting data. An input clock signal (TCLK) for the Serializer must also be applied during the entire BIST
operation. The BISTM pin selects error reporting status mode of the BIST function. When BIST is configured in
the error status mode (BISTM = LOW), each of the ROUT[23:0] outputs will correspond to bit errors on a cycleby-cycle basis. The result of bit mismatches are indicated on the respective parallel inputs on the ROUT[23:0]
data output pins. In the BIST error-count accumulator mode (BISTM = HIGH), an 8-bit counter on ROUT[7:0] is
used to represent the number of errors detected (0 to 255 max). The successful completion of the BIST test is
reported on the PASS pin on the Deserializer. The Deserializer's PLL must first be locked to ensure the PASS
status is valid. The PASS status pin will stay LOW and then transition to HIGH once a BER of 1x10-9 is achieved
across the transmission link.
BACKWARDS COMPATIBLE MODE WITH DS90C241 AND DS90C124
The RAOFF pin allows a backward compatible mode with DS90C241/DS90C124 devices. To interface with either
DS90C241 Serializer or DS90C124 Deserializer, the RAOFF pin on DS90UR241 or DS90UR124 must be tied
HIGH to disable the additional LSFR coding. For normal operation directly with DS90UR241 to DS90UR124,
RAOFF pins are set LOW. See Table 1 and Table 2 for more details.
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APPLICATION INFORMATION
USING THE DS90UR241 AND DS90UR124
The DS90UR241/DS90UR124 Serializer/Deserializer (SERDES) pair sends 24 bits of parallel LVCMOS data
over a serial LVDS link up to 1.03 Gbps. Serialization of the input data is accomplished using an on-board PLL at
the Serializer which embeds clock with the data. The Deserializer extracts the clock/control information from the
incoming data stream and deserializes the data. The Deserializer monitors the incoming clock information to
determine lock status and will indicate lock by asserting the LOCK output high.
DISPLAY APPLICATION
The DS90UR241/124 chipset is intended for interface between a host (graphics processor) and a Display. It
supports an 18-bit color depth (RGB666) and up to 1280 X 480 display formats. In a RGB666 configuration 18
color bits (R[5:0], G[5:0], B[5:0]), Pixel Clock (PCLK) and three control bits (VS, HS and DE) along with three
spare bits are supported across the serial link with PCLK rates from 5 to 43 MHz.
TYPICAL APPLICATION CONNECTION
Figure 20 shows a typical application of the DS90UR241 Serializer (SER). The LVDS outputs utilize a 100 ohm
termination and 100nF coupling capacitors to the line. Bypass capacitors are placed near the power supply pins.
At a minimum, three 0.1uF capacitors should be used for local bypassing. A system GPO (General Purpose
Output) controls the TPWDNB pin. In this application the TRFB pin is tied High to latch data on the rising edge of
the TCLK. The DEN signal is not used and is tied High also. The application is to the companion Deserializer
(DS90UR124) so the RAOFF pin is tied low to scramble the data and improve link signal quality. In this
application the link is typical, therefore the VODSEL pin is tied Low for the standard LVDS swing. The preemphasis input utilizes a resistor to ground to set the amount of pre-emphasis desired by the application.
Figure 22 shows a typical application of the DS90UR124 Deserializer (DES). The LVDS inputs utilize a 100 ohm
termination and 100nF coupling capacitors to the line. Bypass capacitors are placed near the power supply pins.
At a minimum, four 0.1uF capacitors should be used for local bypassing. A system GPO (General Purpose
Output) controls the RPWDNB pin. In this application the RRFB pin is tied High to strobe the data on the rising
edge of the RCLK. The REN signal is not used and is tied High also. The application is to the companion
Serializer (DS90UR241) so the RAOFF pin is tied low to descramble the data. Output (LVCMOS) signal quality is
set by the SLEW pin, and the PTOSEL pin can be used to reduce simultaneous output switching by introducing a
small amount of delay between output banks.
22
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SNLS231N – SEPTEMBER 2006 – REVISED MARCH 2013
DS90UR241 (SER)
DIN0
DIN1
DIN2
DIN3
DIN4
DIN5
DIN6
DIN7
DIN8
DIN9
DIN10
DIN11
DIN12
DIN13
DIN14
DIN15
LVCMOS
Parallel
Interface
DIN16
DIN17
DIN18
DIN19
DIN20
DIN21
DIN22
DIN23
Notes:
TPWDNB = System GPO
DEN = High (ON)
TRFB = High (Rising edge)
RAOFF = Low (Default)
VODSEL = Low (500 mV)
PRE = Rpre
RES0 = Low
R2
VODSEL
RAOFF
RES0(3)
C5
C2
C6
C3
DOUT+
C7
Serial
LVDS
Interface
R1
DOUT-
DEN
TRFB
PRE
C1
VDD
VDD
TPWDNB
3.3V
C4
VDD
VDD
TCLK
GPOs if used, or tie High (ON)
3.3V
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
C8
C1 to C3 = 0.1 PF
C4 to C6 = 0.01 PF (optional)
C7 to C8 = 100 nF 50WVDC, NPO or X7R
R1 = 100 :
R2 = Open (OFF)
or Rpre 8 6 k: (ON) (cable specific)
Figure 20. DS90UR241 Typical Application Connection
POWER CONSIDERATIONS
An all LVCMOS design of the Serializer and Deserializer makes them inherently low power devices. Additionally,
the constant current source nature of the LVDS outputs minimize the slope of the speed vs. IDD curve of
LVCMOS designs.
NOISE MARGIN
The Deserializer noise margin is the amount of input jitter (phase noise) that the Deserializer can tolerate and still
reliably recover data. Various environmental and systematic factors include:
• Serializer: VDD noise, TCLK jitter (noise bandwidth and out-of-band noise)
• Media: ISI, VCM noise
• Deserializer: VDD noise
For a graphical representation of noise margin, please see Figure 17.
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TRANSMISSION MEDIA
The Serializer and Deserializer are to be used in point-to-point configuration, through a PCB trace, or through
twisted pair cable. In a point-to-point configuration, the transmission media needs be terminated at both ends of
the transmitter and receiver pair. Interconnect for LVDS typically has a differential impedance of 100 Ohms. Use
cables and connectors that have matched differential impedance to minimize impedance discontinuities. In most
applications that involve cables, the transmission distance will be determined on data rates involved, acceptable
bit error rate and transmission medium.
The resulting signal quality at the receiving end of the transmission media may be assessed by monitoring the
differential eye opening of the serial data stream. The Receiver Input Tolerance and Differential Threshold
Voltage specifications define the acceptable data eye opening. A differential probe should be used to measure
across the termination resistor at the DS90UR124 inputs. Figure 21 illustrates the eye opening and relationship
to the Receiver Input Tolerance and Differential Threshold Voltage specifications
Ideal Data Bit
Beginning
RxIN_TOL -L
Minimum Eye
Width
• VTH - VTL
Ideal Data Bit
End
RxIN_TOL -R
tBIT
(1UI)
Figure 21. Receiver Input Eye Opening
LIVE LINK INSERTION
The Serializer and Deserializer devices support live pluggable applications. The automatic receiver lock to
random data “plug & go” hot insertion capability allows the DS90UR124 to attain lock to the active data stream
during a live insertion event.
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SNLS231N – SEPTEMBER 2006 – REVISED MARCH 2013
DS90UR124 (DES)
3.3V
3.3V
VDD
VDD
C1
VDD
VDD
C5
C6
RIN+
RINC10
RPWDNB
BISTM
3.3V
REN
RRFB
RAOFF
PTOSEL
SLEW
RES0(11)
RCLK
LOCK
PASS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Notes:
RPWDNB = System GPO
REN = High (ON)
RRFB = High (Rising edge)
RAOFF = Low (Default)
PTOSEL = Low (Defaut)
SLEW = Low (Default)
RES0 = Low
BISTEN = GPO or Low
BISTM = GPO or Low
LVCMOS
Parallel
Interface
ROUT16
ROUT17
ROUT18
ROUT19
ROUT20
ROUT21
ROUT22
ROUT23
BISTEN
GPOs if used,
or tie Low (OFF)
C4
ROUT8
ROUT9
ROUT10
ROUT11
ROUT12
ROUT13
ROUT14
ROUT15
R1
GPO if used, or tie High (ON)
C8
ROUT0
ROUT1
ROUT2
ROUT3
ROUT4
ROUT5
ROUT6
ROUT7
C9
Serial
LVDS
Interface
C3
VDD
VDD
VDD
VDD
C2
C7
C1 to C4 = 0.1 PF
C5 to C8 = 0.01 PF (optional)
C9 to C10 = 100 nF;
50WVDC, NPO or X7R
R1 = 100:
Figure 22. DS90UR124 Typical Application Connection
PCB LAYOUT AND POWER SYSTEM CONSIDERATIONS
Circuit board layout and stack-up for the LVDS SERDES devices should be designed to provide low-noise power
feed to the device. Good layout practice will also separate high frequency or high-level inputs and outputs to
minimize unwanted stray noise pickup, feedback and interference. Power system performance may be greatly
improved by using thin dielectrics (2 to 4 mils) for power / ground sandwiches. This arrangement provides plane
capacitance for the PCB power system with low-inductance parasitics, which has proven especially effective at
high frequencies, and makes the value and placement of external bypass capacitors less critical. External bypass
capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the
range of 0.01 uF to 0.1 uF. Tantalum capacitors may be in the 2.2 uF to 10 uF range. Voltage rating of the
tantalum capacitors should be at least 5X the power supply voltage being used.
Surface mount capacitors are recommended due to their smaller parasitics. When using multiple capacitors per
supply pin, locate the smaller value closer to the pin. A large bulk capacitor is recommend at the point of power
entry. This is typically in the 50uF to 100uF range and will smooth low frequency switching noise. It is
recommended to connect power and ground pins directly to the power and ground planes with bypass capacitors
connected to the plane with via on both ends of the capacitor. Connecting power or ground pins to an external
bypass capacitor will increase the inductance of the path.
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A small body size X7R chip capacitor, such as 0603, is recommended for external bypass. Its small body size
reduces the parasitic inductance of the capacitor. The user must pay attention to the resonance frequency of
these external bypass capacitors, usually in the range of 20-30 MHz range. To provide effective bypassing,
multiple capacitors are often used to achieve low impedance between the supply rails over the frequency of
interest. At high frequency, it is also a common practice to use two vias from power and ground pins to the
planes, reducing the impedance at high frequency.
Some devices provide separate power and ground pins for different portions of the circuit. This is done to isolate
switching noise effects between different sections of the circuit. Separate planes on the PCB are typically not
required. Pin Description tables typically provide guidance on which circuit blocks are connected to which power
pin pairs. In some cases, an external filter many be used to provide clean power to sensitive circuits such as
PLLs.
Use at least a four layer board with a power and ground plane. Locate LVCMOS signals away from the LVDS
lines to prevent coupling from the LVCMOS lines to the LVDS lines. Closely-coupled differential lines of 100
Ohms are typically recommended for LVDS interconnect. The closely coupled lines help to ensure that coupled
noise will appear as common-mode and thus is rejected by the receivers. The tightly coupled lines will also
radiate less.
Termination of the LVDS interconnect is required. For point-to-point applications, termination should be located at
both ends of the devices. Nominal value is 100 Ohms to match the line’s differential impedance. Place the
resistor as close to the transmitter DOUT± outputs and receiver RIN± inputs as possible to minimize the resulting
stub between the termination resistor and device.
LVDS INTERCONNECT GUIDELINES
See AN-1108 (SNLA008) and AN-905 (SNLA035) for full details.
• Use 100Ω coupled differential pairs
• Use the S/2S/3S rule in spacings
– S = space between the pair
– 2S = space between pairs
– 3S = space to LVCMOS signal
• Minimize the number of Vias
• Use differential connectors when operating above 500Mbps line speed
• Maintain balance of the traces
• Minimize skew within the pair
• Terminate as close to the TX outputs and RX inputs as possible
Additional general guidance can be found in the LVDS Owner’s Manual - available in PDF format from the TI
web site at: www.ti.com/lvds
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SNLS231N – SEPTEMBER 2006 – REVISED MARCH 2013
100 nF
DOUT+
100 nF RIN+
100:
DOUT-
100:
100 nF
RIN-
100 nF
bit23
CLK0
bit21
bit22
bit20
bit19
bit17
bit18
bit16
bit15
bit14
bit12
bit13
DCB
bit11
DCA
bit9
bit10
bit8
bit7
bit6
bit4
bit5
bit3
bit1
bit2
bit0
CLK1
Figure 23. AC Coupled Application
1 CLK cycle
*Note: bits [0-23] are not physically located in positions shown above since bits [0-23] are scrambled and DC
Balanced
Figure 24. Single Serialized LVDS Bitstream*
0.1 PF
0.1 PF
RIN+
50:
DS90UR241
DS90UR124
100:
4.7 nF
50:
RIN0.1 PF
0.1 PF
Figure 25. Receiver Termination Option 2
VDD
0.1 PF
0.1 PF
RIN+
50:
RPU
DS90UR241
DS90UR124
100:
RPD
4.7 nF
50:
RIN0.1 PF
0.1 PF
Figure 26. Receiver Termination Option 3
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Truth Tables
Table 1. DS90UR241 Serializer Truth Table
TPWDNB
(Pin 9)
DEN
(Pin 18)
RAOFF
(Pin 12)
Tx PLL Status
(Internal)
LVDS Outputs
(Pins 19 and 20)
L
X
X
X
Hi Z
H
L
X
X
Hi Z
H
H
X
Not Locked
Hi Z
H
H
L
Locked
Serialized Data with Embedded Clock
(DS90UR124 compatible)
H
H
H
Locked
Serialized Data with Embedded Clock
(DS90C124 compatible)
Table 2. DS90UR124 Deserializer Truth Table
RPWDNB
(Pin 48)
REN
(Pin 60)
RAOFF
(Pin 63)
Rx PLL Status
(Internal)
ROUTn and RCLK
(See Pin Diagram)
LOCK
(Pin 23)
L
X
X
X
Hi Z
Hi Z
H
L
X
X
Hi Z
L = PLL Unocked;
H = PLL Locked
H
H
X
Not Locked
Hi Z
L
H
H
L
Locked
Data and RCLK Active
(DS90UR241 compatible)
H
H
H
H
Locked
Data and RCLK Active
(DS90C241 compatible)
H
Revision History
•
Revision M, October 4, 2011
Updated Applications Information for Transmission Media. Added figure describing Receiver Input Eye
Opening
Changes from Revision M (March 2013) to Revision N
•
28
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 28
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PACKAGE OPTION ADDENDUM
www.ti.com
24-Nov-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
DS90UR124IVS/NOPB
ACTIVE
TQFP
PAG
64
160
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 105
DS90UR124
IVS
DS90UR124IVSX/NOPB
ACTIVE
TQFP
PAG
64
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 105
DS90UR124
IVS
DS90UR124QVS/NOPB
ACTIVE
TQFP
PAG
64
160
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 105
DS90UR124
QVS
DS90UR124QVSX/NOPB
ACTIVE
TQFP
PAG
64
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 105
DS90UR124
QVS
DS90UR241IVS/NOPB
ACTIVE
TQFP
PFB
48
250
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 105
DS90UR24
1IVS
DS90UR241IVSX/NOPB
ACTIVE
TQFP
PFB
48
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 105
DS90UR24
1IVS
DS90UR241QVS/NOPB
ACTIVE
TQFP
PFB
48
250
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 105
DS90UR24
1QVS
DS90UR241QVSX/NOPB
ACTIVE
TQFP
PFB
48
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 105
DS90UR24
1QVS
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
(4)
24-Nov-2013
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF DS90UR124, DS90UR124-Q1, DS90UR241, DS90UR241-Q1 :
• Catalog: DS90UR124, DS90UR241
• Automotive: DS90UR124-Q1, DS90UR241-Q1
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Mar-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
DS90UR124IVSX/NOPB
TQFP
PAG
64
1000
330.0
24.4
13.0
13.0
1.45
16.0
24.0
Q2
DS90UR124QVSX/NOPB
TQFP
PAG
64
1000
330.0
24.4
13.0
13.0
1.45
16.0
24.0
Q2
DS90UR241IVSX/NOPB
TQFP
PFB
48
1000
330.0
16.4
9.3
9.3
2.2
12.0
16.0
Q2
DS90UR241QVSX/NOPB
TQFP
PFB
48
1000
330.0
16.4
9.3
9.3
2.2
12.0
16.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Mar-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DS90UR124IVSX/NOPB
TQFP
PAG
64
1000
367.0
367.0
45.0
DS90UR124QVSX/NOPB
TQFP
PAG
64
1000
367.0
367.0
45.0
DS90UR241IVSX/NOPB
TQFP
PFB
48
1000
367.0
367.0
38.0
DS90UR241QVSX/NOPB
TQFP
PFB
48
1000
367.0
367.0
38.0
Pack Materials-Page 2
MECHANICAL DATA
MTQF006A – JANUARY 1995 – REVISED DECEMBER 1996
PAG (S-PQFP-G64)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
48
0,08 M
33
49
32
64
17
0,13 NOM
1
16
7,50 TYP
Gage Plane
10,20
SQ
9,80
12,20
SQ
11,80
0,25
0,05 MIN
1,05
0,95
0°– 7°
0,75
0,45
Seating Plane
0,08
1,20 MAX
4040282 / C 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MTQF019A – JANUARY 1995 – REVISED JANUARY 1998
PFB (S-PQFP-G48)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
36
0,08 M
25
37
24
48
13
0,13 NOM
1
12
5,50 TYP
7,20
SQ
6,80
9,20
SQ
8,80
Gage Plane
0,25
0,05 MIN
0°– 7°
1,05
0,95
Seating Plane
0,75
0,45
0,08
1,20 MAX
4073176 / B 10/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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