ON AMIS30622C6227G I2c micro-stepping motor driver Datasheet

AMIS-30622
I2C Micro-Stepping Motor
Driver
INTRODUCTION
The AMIS−30622 is a single−chip micro−stepping motor driver
with a position controller and control/diagnostic interface. It is ready
to build intelligent peripheral systems where up to 32 drivers can be
connected to one I2C master. This significantly reduces system
complexity.
The chip receives positioning instructions through the bus and
subsequently drives the stator coils so the two−phase stepper motor
moves to the desired position. The on−chip position controller is
configurable (OTP or RAM) for different motor types, positioning
ranges and parameters for speed, acceleration and deceleration.
Micro−stepping allows silent motor operation and increased
positioning resolution. The advanced motion qualification mode
enables verification of the complete mechanical system in function of
the selected motion parameters. The AMIS−30622 can easily be
connected to an I2C bus where the I2C master can fetch specific status
information like actual position, error flags, etc. from each individual
slave node.
The chip is implemented in I2T100 technology, enabling both high
voltage analog circuitry and digital functionality on the same chip.
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SOIC−20
3 or 7 SUFFIX
CASE 751AQ
NQFP−32
8 SUFFIX
CASE 560AA
PRODUCT FEATURES
Motor Driver
•
•
•
•
•
•
Micro−Stepping Technology
Peak Current Up to 800 mA
Fixed Frequency PWM Current−Control
Automatic Selection of Fast and Slow Decay Mode
No external Fly−back Diodes Required
14 V/24 V Compliant
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
Controller with RAM and OTP Memory
• Position Controller
• Configurable Speeds and Acceleration
• Input to Connect Optional Motion Switch
I2C Interface
• Bi−Directional 2−Wire Bus for Inter IC Control
• Field Programmable Node Addresses
• Full Diagnostics and Status Information
Protection
•
•
•
•
•
Overcurrent Protection
Undervoltage Management
Open−circuit Detection
High Temperature Warning and Management
Low Temperature Flag
© Semiconductor Components Industries, LLC, 2013
July, 2013 − Rev. 5
EMI Compatibility
• High Voltage Outputs with Slope Control
• This is a Pb−Free Device
1
Publication Order Number:
AMIS−30622/D
AMIS−30622
APPLICATIONS
The AMIS−30622 is ideally suited for small positioning
applications. Target markets include: automotive (headlamp
alignment, HVAC, idle control, cruise control), industrial
equipment (lighting, fluid control, labeling, process control,
XYZ tables, robots) and building automation (HVAC,
surveillance, satellite dish, renewable energy systems).
Suitable applications typically have multiple axes or require
mechatronic solutions with the driver chip mounted directly
on the motor.
Table 1. ORDERING INFORMATION
Part No.
Peak Current
AMIS30622C6223G
800 mA
AMIS30622C6223RG
800 mA
AMIS30622C6227G
800 mA
AMIS30622C6227RG
800 mA
AMIS30622C6228G
800 mA
AMIS30622C6228RG
800 mA
Package*
Shipping†
SOIC−20
(Pb−Free)
38 Rail
SOIC−20
(Pb−Free)
1500 Tape & Reel
SOIC−20
(Pb−Free)
38 Rail
SOIC−20
(Pb−Free)
1500 Tape & Reel
NQFP−32 (7 x 7 mm)
(Pb−Free)
40 Rail
NQFP−32 (7 x 7 mm)
(Pb−Free)
2500 Tape & Reel
End Market/Version
Automotive
High Voltage Version
Industrial
High Voltage Version
*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specification Brochure, BRD8011/D.
QUICK REFERENCE DATA
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameter
Min
Max
Unit
VBB, VHW, VSWI
Supply voltage, hardwired address and SWI pins
−0.3
+40 (Note 1)
V
TJ
Junction temperature range (Note 2)
−50
+175
°C
Tst
Storage temperature
−55
+160
°C
Vesd (Note 3)
Human Body Model (HBM) Electrostatic discharge voltage on pins
−2
+2
kV
−200
+200
V
Machine Model (MM) Electrostatic discharge voltage on pins
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. For limited time: VBB < 0.5 s, SWI and HW pins <1.0 s.
2. The circuit functionality is not guaranteed.
3. HBM according to AEC−Q100: EIA−JESD22−A114−B (100 pF via 1.5 kW) and MM according to AEC−Q100: EIA−JESD22−A115−A.
Table 3. OPERATING RANGES
Parameter
Min
Max
Unit
VBB
Supply voltage
+6.5
+29
V
TJ
Operating temperature range
−40
+165
°C
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2
AMIS−30622
Table of Contents
Positioning Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Structural Description . . . . . . . . . . . . . . . . . . . . . . . . . 14
Functions Description . . . . . . . . . . . . . . . . . . . . . . . . . 15
Position Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Main Control and Register . . . . . . . . . . . . . . . . . . . . . . 22
OTP Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Priority Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Motordriver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
I2C Bus Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
I2C Application Commands . . . . . . . . . . . . . . . . . . . . . 40
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Product Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Quick Reference Data . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Package Thermal Resistance . . . . . . . . . . . . . . . . . . . . . 5
DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Typical Application . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
SDA
SCK
SWI
AMIS−30622
I2C−bus
Interface
Position
Controller
HW
PWM
regulator
X
Controller
TST1
TST2
MOTXP
MOTXN
I−sense
Decoder
Main Control
Registers
OTP − ROM
Sinewave
Table
Stall detection
DAC’s
4MHz
Temp
sense
Vref
Voltage
Regulator
VBB
VDD
Oscillator
PWM
regulator
Y
Charge Pump
CPN
CPP
I−sense
VCP
GND
Figure 1. Block Diagram
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MOTYP
MOTYN
AMIS−30622
GND
GND
YP
YP
XN
XN
GND
GND
32
25
1
20
SWI
SCK
2
19
VBB
XP
1
31 30 29 28 27 26 24
YN
VDD
3
18
MOTXP
XP
2
23
YN
GND
4
17
GND
VBB
3
22
VBB
MOTXN
VBB
4
21
VBB
VBB
5
20
VBB
SWI
6
19
VCP
NC
7
18
CPP
SDA
8
10 11 12 13 14 15 17
CPN
TST1
TST2
AMIS−30622
SDA
5
6
GND
7
HW
16
MOTYP
15
14
GND
8
13
MOTYN
CPN
9
12
VBB
CPP
10
11
VCP
AMIS−30622
(Top View)
9
16
NC
HW
GND
TST2
TST1
GND
VDD
SCK
SOIC−20
Figure 2. SOIC−20 and NQFP−32 Pin−out
Table 4. PIN DESCRIPTION
Pin Name
Pin Description
SOIC−20
NQFP−32
SDA
I2C
1
8
SCK
I2C serial clock line
2
9
VDD
Internal supply (needs external decoupling capacitor)
3
10
GND
Ground, heat sink
4, 7, 14, 17
11, 14, 25, 26, 31, 32
TST1
Test pin (to be tied to ground in normal operation)
5
12
TST2
Test pin (to be left open in normal operation: internally pulled up)
6
13
serial data line
HW
Hard wired address bit
8
15
CPN
Negative connection of pump−capacitor (charge pump)
9
17
CPP
Positive connection of pump−capacitor (charge pump)
10
18
VCP
Charge−pump filter−capacitor
11
19
VBB
Battery voltage supply
12, 19
3, 4, 5, 20, 21, 22
MOTYN
Negative end of phase Y coil
13
23, 24
MOTYP
Positive end of phase Y coil
15
27, 28
MOTXN
Negative end of phase X coil
16
29, 30
MOTXP
Positive end of phase X coil
18
1, 2
SWI
Switch input
20
6
NC
Not connected (to be tied to ground)
7, 16
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AMIS−30622
PACKAGE THERMAL RESISTANCE
The AMIS−30622 is available in SOIC−20 or optimized
NQFP−32 packages. For cooling optimizations, the NQFP
has an exposed thermal pad which has to be soldered to the
PCB ground plane. The ground plane needs thermal vias to
conduct the head to the bottom layer. Figures 3 and 4 give
examples for good power distribution solutions.
For precise thermal cooling calculations the major
thermal resistances of the devices are given. The thermal
media to which the power of the devices has to be given are:
• Static environmental air (via the case)
• PCB board copper area (via the device pins and
exposed pad)
The thermal resistances are presented in Table 5: DC
Parameters.
Package
Rth
Junction−to−Leads and
Exposed Pad − Rthjp
SOIC−20
NQFP−32
The major thermal resistances of the device are the Rth
from the junction to the ambient (Rthja) and the overall Rth
from the junction to the leads (Rthjp).
The NQFP device is designed to provide superior thermal
performance. Using an exposed die pad on the bottom
surface of the package is mainly contributing to this
performance. In order to take full advantage of the exposed
pad, it is most important that the PCB has features to conduct
heat away from the package. A thermal grounded pad with
thermal vias can achieve this.
In the table below, one can find the values for the Rthja and
Rthjp, simulated according to the JESD−51 norm:
Rth
Junction−to−Leads
Rthjp
Rth
Junction−to−Ambient
Rthja (1S0P)
Rth
Junction−to−Ambient
Rthja (2S2P)
19
62
39
60
30
0,95
The Rthja for 2S2P is simulated conform to JESD−51 as
follows:
• A 4−layer printed circuit board with inner power planes
and outer (top and bottom) signal layers is used
• Board thickness is 1.46 mm (FR4 PCB material)
• The 2 signal layers: 70 mm thick copper with an area of
5500 mm2 copper and 20% conductivity
• The 2 power internal planes: 36 mm thick copper with
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÏÏ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÏÏ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÏÏ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
an area of 5500 mm2 copper and 90% conductivity
The Rthja for 1S0P is simulated conform to JESD−51 as
follows:
• A 1−layer printed circuit board with only 1 layer
• Board thickness is 1.46 mm (FR4 PCB material)
• The layer has a thickness of 70 mm copper with an area
of 5500 mm2 copper and 20% conductivity
SOIC−20
NQFP−32
Figure 3. Example of SOIC−20 PCB Ground Plane
Layout (preferred layout at top and bottom)
Figure 4. Example of NQFP−32 PCB Ground Plane
Layout (preferred layout at top and bottom)
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AMIS−30622
DC PARAMETERS
The DC parameters are guaranteed overtemperature and VBB in the operating range, unless otherwise specified. Convention:
currents flowing into the circuit are defined as positive.
Table 5. DC PARAMETERS
Symbol
Pin(s)
Parameter
Test Conditions
Min
Typ
Max
Unit
IMSmax,Peak
Max current through motor coil
in normal operation
VBB = 14 V
800
mA
IMSmax,RMS
Max rms current through coil in
normal operation
VBB = 14 V
570
mA
Absolute error on coil
current (Note 4)
VBB = 14 V
−10
VBB = 14 V
−7
MOTORDRIVER
IMSabs
IMSrel
RDS(on)
MOTXP
MOTXN Matching of X & Y
MOTYP coil currents
MOTYN
On resistance for each
motor pin at IMSmax
(Note 5)
IMSL
I2C
Pulldown current
10
%
0
7
%
VBB = 12 V, Tj = 50°C
0.50
1
W
VBB = 8 V, Tj = 50°C
0.55
1
W
VBB = 12 V, Tj = 150°C
0.70
1
W
VBB = 8 V, Tj = 150°C
0.85
1
W
HiZ mode, VBB = 7.8 V
2
mA
SERIAL INTERFACE
VIL
Input level low (Note 10)
−0.5
0.3 * VDD
V
VIH
Input level high (Note 11)
0.7 * VDD
VDD + 0.5
V
Noise margin at the LOW level
for each connected device
(including hysteresis)
0.1 * VDD
Noise margin at the HIGH level
for each connected device
(including hysteresis)
0.2 * VDD
VnL
SDA
SCK
VnH
V
THERMAL WARNING & SHUTDOWN
Ttw
Thermal warning
(Notes 6 and 7)
138
145
152
Ttsd
Thermal shutdown (Note 8)
Ttw + 10
°C
Tlow
Low temperature warning (Note
8)
Ttw − 155
°C
°C
SUPPLY AND VOLTAGE REGULATOR
VbbOTP
UV1
UV2
Ibat
VBB
Supply voltage for OTP
zapping (Note 9)
9.0
Stop voltage high threshold
7.7
Stop voltage low threshold
7.0
Total current consumption
Unloaded outputs
VBB = 29 V
10.0
V
8.3
8.9
V
7.5
8.0
V
3.50
10.0
mA
4. Tested in production for 800 mA, 400 mA, 200 mA and 100 mA current settings for both X and Y coil.
5. Not measured in production. Guaranteed by design.
6. Parameter guaranteed by trimming relevant OTP’s in production test at 143°C (±5°C) and VBB = 14 V.
7. No more than 100 cumulated hours in life time above Tw.
8. Thermal shutdown and low temperature warning are derived from thermal warning. Guaranteed by design.
9. A buffer capacitor of minimum 100 mF is needed between VBB and GND. Short connections to the power supply are recommended.
10. If input voltages < − 0.3 V, than a resistor between 22 W to 100 W needs to be put in series.
11. If the I2C−bus is operated in Fast Mode VIHmin = 0.7 * VDD.
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AMIS−30622
Table 5. DC PARAMETERS
Symbol
Pin(s)
Parameter
Test Conditions
Min
Typ
Max
Unit
8 V < VBB < 29 V
4.75
5
5.50
V
4.5
V
45
mA
SUPPLY AND VOLTAGE REGULATOR
Regulated internal supply
(Note 12)
VDD
VddReset
VDD
IddLim
Digital supply reset level @
power down (Note 13)
Current limitation
Pin shorted to ground
VBB = 14 V
SWITCH INPUT AND HARDWIRE ADDRESS INPUT
Switch OPEN resistance
(Note 14)
Rt_OFF
Rt_ON
Switch ON resistance
SWI HW (Note 14)
Vbb_sw
VBB range for guaranteed
operation of SWI and HW
Ilim_sw
Current limitation
10
kW
Switch to GND or VBB
6
Short to GND or Vbat
VBB = 29 V
20
Input level high
VBB = 14 V
0.7 * Vdd
Input level low
VBB = 14 V
Hysteresis
VBB = 14 V
30
2
kW
29
V
45
mA
TEST PINS
Vihigh
Vilow
TSTx
Vihyst
V
0.3 * Vdd
0.075 * Vdd
V
V
CHARGE PUMP
Vcp
Output voltage
Cpump
CPP
CPN
2 * VBB − 2.5
V
VBB + 10
VBB + 15
V
External buffer capacitor
220
470
nF
External pump capacitor
220
470
nF
VCP
Cbuffer
7 V ≤ VBB ≤ 14 V
14 V ≤ VBB ≤ 30 V
PACKAGE THERMAL RESISTANCE VALUES
Rthja
SO
Thermal resistance junction
to ambient (2S2P)
39
K/W
Rthjp
SO
Thermal resistance junction
to leads
19
K/W
Rthja
NQ
Thermal resistance junction
to ambient (2S2P)
30
K/W
Rthjp
NQ
Thermal resistance junction
to leads and exposed pad
0.95
K/W
Simulated conform
JEDEC JESD51
12. Pin VDD must not be used for any external supply
13. The RAM content will not be altered above this voltage.
14. External resistance value seen from pin SWI or HW, including 1 kW series resistor. For the switch OPEN, the maximum allowed leakage
current is represented by a minimum resistance seen from the pin.
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AMIS−30622
AC PARAMETERS
The AC parameters are guaranteed for temperature and VBB in the operating range unless otherwise specified.
Table 6. AC PARAMETERS
Symbol
Pin(s)
Parameter
Test Conditions
Min
Typ
Max
Unit
10
ms
4.4
MHz
100
kHz
POWERUP
Power−up time
Tpu
Guaranteed by design
INTERNAL OSCILLATOR
Frequency of internal oscillator
fosc
VBB = 14 V
3.6
4.0
I2C TRANSCEIVER (STANDARD MODE)
fSCL
SCL clock frequency
tHD,START
Hold time (repeated) START condition. After
this period the first clock pulse is generated.
4.0
ms
tLOW
LOW period of the SCK clock
4.7
ms
tHIGH
HIGH period of the SCK clock
4.0
ms
Set−up time for a repeated START condition
4.7
tSU,START
tHD,DATA
SDA
SCK
tSU,DATA
Data hold time for I2C bus devices
0
(Note 16)
Data set−up time
ms
3.45
(Note 17)
250
ms
ns
tR
Rise time of SDA and SCK signals
1.0
ms
tF
Fall time of SDA and SCK signals
0.3
ms
tSU,STOP
tBUF
Set−up time for STOP condition
4.0
ms
Bus free time between STOP and START
condition
4.7
ms
I2C TRANSCEIVER (FAST MODE)
fSCL
SCL clock frequency
tHD,START
360
kHz
Hold time (repeated) START condition. After
this period the first clock pulse is generated.
0.6
ms
tLOW
LOW period of the SCK clock
1.3
ms
tHIGH
HIGH period of the SCK clock
0.6
ms
Set−up time for a repeated START condition
0.6
ms
tSU,START
tHD,DATA
tSU,DATA
Data hold time for
SDA
SCK
I2C
bus devices
0
(Note 16)
Data set−up time
0.9
(Note 17)
100
(Note 18)
ms
ns
tR
Rise time of SDA and SCK signals
20 +
0.1 CB
300
ns
tF
Fall time of SDA and SCK signals
20 +
0.1 CB
300
ns
tSU,STOP
tBUF
Set−up time for STOP condition
0.6
ms
Bus free time between STOP and START
condition
1.3
ms
15. The maximum number of connected I2C devices is dependent on the number of available addresses and the maximum bus capacitance
to still guarantee the rise and fall times of the bus signals.
16. An I2C device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge
the undefined region of the falling edge of SCL.
17. The maximum tHD,DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCL signal.
18. A Fast−mode I2C−bus device can be used in a standard−mode I2C bus system, but the requirement tSU,DATA w 250 ns must than be met.
This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW
period of the SCL signal, it must output the next data bit to the SDA line trmax + tSU,DATA = 1000 + 250 = 1250 ns (according to the
standard−mode I2C−bus specification) before the SCL line is released.
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AMIS−30622
Table 6. AC PARAMETERS
Symbol
Pin(s)
Parameter
Test Conditions
Min
Typ
Max
Unit
SWITCH INPUT AND HARDWIRE ADDRESS INPUT
Tsw
SWI
HW
Tsw_on
Scan pulse period (Note 19)
VBB = 14 V
1024
ms
Scan pulse duration
(Note 19)
VBB = 14 V
64
ms
MOTORDRIVER
Fpwm
PWM frequency (Note 19)
Tbrise
Turn−on transient time
MOTxx
Tbfall
18
Between 10% and 90%
Turn−off transient time
Tstab
Run current stabilization time (Note 19)
20
22
kHz
140
ns
130
ns
1/Vmin
ms
250
kHz
CHARGE PUMP
fCP
CPN
CPP
Charge pump frequency
(Note 19)
VBB = 14 V
19. Derived from the internal oscillator
20. See SetMotorParam
START
SDA
REPEATED START
STOP
START
VIHmin
VILmax
tF
SCK
tSU,DATA
tR
tHD,START
tHD,DATA
tLOW
tBUF
tSU,START
tSP
tHIGH
Figure 5. I2C Timing Diagrams
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tSU,STOP
AMIS−30622
Typical Application
VBAT
C8
100 nF
C7
100 mF
C5
CPN
VDD
SDA
I2C
Bus
Connect
to VBAT
or GND
SCK
1k
C1
HW
C6
220 nF
CPP VCP
10
9
3
C4
C3
220 nF
100 nF
VBB
VBB
11
19
20
12
1
18
AMIS−30622
2
8
15
13
6
5
4
7
1k
SWI
C2
2,7 nF
MOTXP
14
MOTYP
MOTYN
17
TST1
GND
Figure 6. Typical Application Diagram for SO Device
NOTES: All resistors are ± 5%, 1/4 W
C1, C2 minimum value is 2.7 nF, maximum value is 10 nF
Depending on the application, the ESR value and working voltage of C7 must be carefully chosen
C3 and C4 must be close to pins VBB and GND
C5 and C6 must be as close as possible to pins CPN, CPP, VCP, and VBB to reduce EMC radiation
C9 must be a ceramic capacitor to assure low ESR
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10
Connect
to VBAT
or GND
16 MOTXN
2,7 nF
TST2
100 nF
M
AMIS−30622
POSITIONING PARAMETERS
Stepping Modes
Maximum Velocity
One of four possible stepping modes can be programmed:
• Half−stepping
• 1/4 micro−stepping
• 1/8 micro−stepping
• 1/16 micro−stepping
For each stepping mode, the maximum velocity Vmax can
be programmed to 16 possible values given in the table below.
The accuracy of Vmax is derived from the internal
oscillator. Under special circumstances it is possible to
change the Vmax parameter while a motion is ongoing. All
16 entries for the Vmax parameter are divided into four
groups. When changing Vmax during a motion the
application must take care that the new Vmax parameter
stays within the same group.
Table 7. MAXIMUM VELOCITY SELECTION TABLE
Vmax Index
Stepping Mode
Half−stepping
1/4th
Micro−stepping
1/8th
Micro−stepping
1/16th
Micro−stepping
Hex
Dec
Vmax
(full step/s)
Group
(half−step/s)
(micro−step/s)
(micro−step/s)
(micro−step/s)
0
0
99
A
197
395
790
1579
1
1
136
273
546
1091
2182
2
2
167
334
668
1335
2670
3
3
197
395
790
1579
3159
4
4
213
425
851
1701
3403
5
5
228
456
912
1823
3647
6
6
243
486
973
1945
3891
7
7
273
546
1091
2182
4364
8
8
303
607
1213
2426
4852
9
9
334
668
1335
2670
5341
A
10
364
729
1457
2914
5829
B
11
395
790
1579
3159
6317
C
12
456
912
1823
3647
7294
D
13
546
1091
2182
4364
8728
E
14
729
1457
2914
5829
11658
F
15
973
1945
3891
7782
15564
B
C
D
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AMIS−30622
Minimum Velocity
Once the maximum velocity is chosen, 16 possible values can be programmed for the minimum velocity Vmin. The table
below provides the obtainable values in full−step/s. The accuracy of Vmin is derived from the internal oscillator.
Table 8. OBTAINABLE VALUES IN FULL−STEP/s FOR THE MINIMUM VELOCITY
Vmax (Full−step/s)
Vmin Index
A
Hex
99
136
167
197
213
228
243
273
303
334
364
395
456
546
729
973
Vmax
Dec Factor
B
C
D
0
0
1
99
136
167
197
213
228
243
273
303
334
364
395
456
546
729
973
1
1
1/32
3
4
5
6
6
7
7
8
8
10
10
11
13
15
19
27
2
2
2/32
6
8
10
11
12
13
14
15
17
19
21
23
27
31
42
57
3
3
3/32
9
12
15
18
19
21
22
25
27
31
32
36
42
50
65
88
4
4
4/32
12
16
20
24
26
28
30
32
36
40
44
48
55
65
88
118
5
5
5/32
15
21
26
31
32
35
37
42
46
51
55
61
71
84
111
149
6
6
6/32
18
25
31
36
39
42
45
50
55
61
67
72
84
99
134
179
7
7
7/32
21
30
36
43
46
50
52
59
65
72
78
86
99
118
156
210
8
8
8/32
24
33
41
49
52
56
60
67
74
82
90
97
113
134
179
240
9
9
9/32
28
38
47
55
59
64
68
76
84
93
101
111
128
153
202
271
A
10
10/32
31
42
51
61
66
71
75
84
93
103
113
122
141
168
225
301
B
11
11/32
34
47
57
68
72
78
83
93
103
114
124
135
156
187
248
332
C
12
12/32
37
51
62
73
79
85
91
101
113
124
135
147
170
202
271
362
D
13
13/32
40
55
68
80
86
93
98
111
122
135
147
160
185
221
294
393
E
14
14/32
43
59
72
86
93
99
106
118
132
145
158
172
198
237
317
423
F
15
15/32
46
64
78
93
99
107
113
128
141
156
170
185
214
256
340
454
NOTES: The Vmax factor is an approximation.
In case of motion without acceleration (AccShape = 1) the length of the steps = 1/Vmin. In case of accelerated motion
(AccShape = 0) the length of the first step is shorter than 1/Vmin depending of Vmin, Vmax and Acc.
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AMIS−30622
Acceleration and Deceleration
combinations of acceleration index and maximum speed
(gray cells).
The accuracy of Acc is derived from the internal
oscillator.
Sixteen possible values can be programmed for Acc
(acceleration and deceleration between Vmin and Vmax).
The table below provides the obtainable values in
full−step/s2. One observes restrictions for some
Table 9. ACCELERATION AND DECELERATION SELECTION TABLE
Vmax (FS/s) "
99
136
167
197
213
228
243
273
303
334
364
395
456
546
729
973
O Acc Index
Acceleration (Full−step/s2)
Hex
Dec
0
0
1
1
218
2
2
1004
3
3
3609
4
4
6228
5
5
8848
6
6
11409
7
7
13970
8
8
16531
9
9
19092
A
10
21886
B
11
24447
C
12
D
13
E
14
F
15
49
106
14785
473
735
27008
29570
34925
29570
40047
Positioning
The formula to compute the number of equivalent
full−steps during acceleration phase is:
Nstep +
Vmax 2
2
The position programmed in command SetPosition
is given as a number of (micro−)steps. According to the
chosen stepping mode, the position words must be aligned
as described in the table below. When using command
GotoSecurePosition, data is automatically aligned.
Vmin 2
*
Acc
Table 10. POSITION WORD ALIGNMENT
Stepping Mode
Position Word: Pos[15:0]
Shift
1/16th
S
B14 B13 B12 B11 B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
LSB
No shift
1/8th
S
B13 B12 B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
LSB
0
1−bit left ⇔ ×2
1/4th
S
B12 B11 B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
LSB
0
0
2−bit left ⇔ ×4
Half−stepping
S
B11 B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
LSB
0
0
0
3−bit left ⇔ ×8
SecurePosition
S
B9
B7
B6
B5
B4
B3
B2
B1
LSB
0
0
0
0
0
No shift
B8
NOTES: LSB: Least Significant Bit
S: Sign bit
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AMIS−30622
Position Ranges
A position is coded by using the binary two’s complement format. According to the positioning commands used and to the
chosen stepping mode, the position range will be as shown in the following table.
Table 11. POSITION RANGE
Command
SetPosition
Stepping Mode
Position Range
Full Range Excursion
Number of Bits
Half−stepping
−4096 to +4095
8192 half−steps
13
1/4th
micro−stepping
−8192 to +8191
16384 micro−steps
14
1/8th
micro−stepping
−16384 to +16383
32768 micro−steps
15
−32768 to +32767
65536 micro−steps
16
1/16th
micro−stepping
Secure Position
When using the command SetPosition, although
coded on 16 bits, the position word will have to be shifted to
the left by a certain number of bits, according to the stepping
mode.
A secure position can be programmed. It is coded in
11−bits, thus having a lower resolution than normal
positions, as shown in the following table. See also
command GotoSecurePosition.
Table 12. SECURE POSITION
Stepping Mode
Secure Position Resolution
Half−stepping
4 half−steps
1/4th
micro−stepping
8 micro−steps (1/4th)
1/8th micro−stepping
16 micro−steps (1/8th)
1/16th micro−stepping
32 micro−steps (1/16th)
Important
NOTES: The secure position is disabled in case the programmed value is the reserved code “10000000000” (0x400 or most negative
position).
The resolution of the secure position is limited to 9 bit at start−up. The OTP register is copied in RAM as illustrated below. The
RAM bits SecPos1 and SecPos0 are set to 0.
SecPos10
SecPos9
SecPos8
SecPos2
SecPos10
SecPos9
SecPos8
SecPos2
SecPos1
SecPos0
RAM
OTP
• Shaft = 0 ⇒ MOTXP is used as positive pin of the X
Shaft
A shaft bit, which can be programmed in OTP or with
command SetMotorParam, defines whether a positive
motion is a clockwise (CW) or counter−clockwise rotation
(CCW) (an outer or an inner motion for linear actuators):
•
coil, while MOTXN is the negative one.
Shaft = 1 ⇒ opposite situation
STRUCTURAL DESCRIPTION
• The control block for the H−bridges, including the
See also the Block Diagram in Figure 1.
PWM control, the synchronous rectification and the
internal current sensing circuitry.
• The charge pump to allow driving of the H−bridges’
high side transistors.
• Two pre−scale 4−bit DAC’s to set the maximum
magnitude of the current through X and Y.
• Two DAC’s to set the correct current ratio through X
and Y.
Battery voltage monitoring is also performed by this
block, which provides the required information to the
control logic part. The same applies for detection and
Stepper Motordriver
The Motordriver receives the control signals from the
control logic. The main features are:
• Two H−bridges, designed to drive a stepper motor with
two separated coils. Each coil (X and Y) is driven by
one H−bridge, and the driver controls the currents
flowing through the coils. The rotational position of the
rotor, in unloaded condition, is defined by the ratio of
current flowing in X and Y. The torque of the stepper
motor when unloaded is controlled by the magnitude of
the currents in X and Y.
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AMIS−30622
Miscellaneous
reporting of an electrical problem that could occur on the
coils or the charge pump.
The AMIS−30622 also contains the following:
• An internal oscillator, needed for the control logic
Control Logic (Position Controller and Main Control)
The control logic block stores the information provided by
the I2C interface (in a RAM or an OTP memory) and
digitally controls the positioning of the stepper motor in
terms of speed and acceleration, by feeding the right signals
to the motordriver state machine.
It will take into account the successive positioning
commands to properly initiate or stop the stepper motor in
order to reach the set point in a minimum time.
It also receives feedback from the motordriver part in
order to manage possible problems and decide on internal
actions and reporting to the I2C interface.
•
•
•
handler as well as the control logic and the PWM
control of the motordriver.
An internal trimmed voltage source for precise
referencing.
A protection block featuring a thermal shutdown and a
power−on−reset circuit.
A 5 V regulator (from the battery supply) to supply the
internal logic circuitry.
FUNCTIONS DESCRIPTION
Position Controller
This chapter describes the following functional blocks in
more detail:
• Position controller
• Main control and register, OTP memory + ROM
• Motordriver
Ì
Ì
Ì
Ì
Ì
Ì
ÌÌ
Ì
Ì
Positioning and Motion Control
A positioning command will produce a motion as
illustrated in Figure 7. A motion starts with an acceleration
phase from minimum velocity (Vmin) to maximum velocity
(Vmax) and ends with a symmetrical deceleration. This is
defined by the control logic according to the position
required by the application and the parameters programmed
by the application during the configuration phase. The
current in the coils is also programmable.
Velocity
Acceleration
range
Deceleration
range
Vmax
Zero Speed
Hold Current
Zero Speed
Hold Current
Vmin
Pstart
P=0
Pmin
ÌÌ
ÌÌ
ÌÌ
ÌÌ
ÌÌ
ÌÌ
ÌÌ
ÌÌ
ÌÌ
ÌÌ
Pstop
Pmax
Figure 7. Positioning and Motion Control
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Position
AMIS−30622
Table 13. POSITION RELATED PARAMETERS
Parameter
Reference
Pmax – Pmin
See Positioning
Zero Speed Hold Current
See Ihold
Maximum Current
See Irun
Acceleration and Deceleration
See Acceleration and Deceleration
Vmin
See Minimum Velocity
Vmax
See Maximum Velocity
Different positioning examples are shown in the table below.
Table 14. POSITIONING EXAMPLES
Short motion.
Velocity
time
New positioning command in same direction, shorter or longer, while a motion
is running at maximum velocity.
Velocity
time
New positioning command in same direction while in deceleration phase
(Note 21)
Note: there is no wait time between the
deceleration phase and the new acceleration phase.
Velocity
New positioning command in reverse
direction while motion is running at maximum velocity.
Velocity
time
time
New positioning command in reverse
direction while in deceleration phase.
Velocity
time
New velocity programming while motion
is running.
Velocity
time
21. Reaching the end position is always guaranteed, however velocity rounding errors might occur after consecutive accelerations during a
deceleration phase. The velocity rounding error will be removed at Vmin (e.g. at end of acceleration or when AccShape=1).
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AMIS−30622
Dual Positioning
A SetDualPosition command allows the user to
perform a positioning using two different velocities. The first
motion is done with the specified Vmin and Vmax velocities
in the SetDualPosition command, with the acceleration
(deceleration) parameter already in RAM, to a position
Pos1[15:0] also specified in SetDualPosition.
Then a second motion to a physical position
Pos2[15:0] is done at the specified Vmin velocity in the
SetDualPosition command (no acceleration). Once
the second motion is achieved, the ActPos register is reset
to zero, whereas TagPos register is not changed.
When the Secure position is enabled, after the dual
positioning, the secure positioning is executed. The figure
below gives a detailed overview of the dual positioning
function. After the dual positioning is executed an internal
flag is set to indicate the AMIS−30622 is referenced.
A new motion will
start here
Depends on
AccShape
Vmax
Profile:
Vmin
first movement
27 ms
00
0
Motion status:
0
0
00
00
100 101
xx
Pos: xx
27 ms
Secure
positioning
(if enabled)
0
5 steps
During one Vmin time the
ActPos is 100
Position:
second
movement
ActPos: 100 ActPos: 100
104 105
105 0
ActPos:0
60
ActPos: 60
Assume:
First Position = 100
Second Position = 105
Secure Position = 60
ResetPos
Figure 8. Dual Positioning
Remark: This operation cannot be interrupted or influenced by any further command unless the occurrence of the conditions
driving to a motor shutdown or by a HardStop command. Sending a SetDualPosition command while a motion is
already ongoing is not recommended.
22. The priority encoder is describing the management of states and commands.
23. A DualPosition sequence starts by setting TagPos buffer register to SecPos value, provided secure position is enabled otherwise TagPos
is reset to zero. If a SetPosition(Short) command is issued during a DualPosition sequence, it will be kept in the position buffer memory and
executed afterwards. This applies also for the command GotoSecurePosition.
24. Commands such as GetFullStatus1 or GetFullStatus2 will be executed while a Dual Positioning is running.
25. The Pos1, Pos2, Vmax and Vmin values programmed in a SetDualPosition command apply only for this sequence. All other motion
parameters are used from the RAM registers (programmed for instance by a former SetMotorParam command). After the DualPosition
motion is completed, the former Vmin and Vmax become active again.
26. Commands ResetPosition, SetDualPosition, and SoftStop will be ignored while a DualPosition sequence is ongoing, and will not be executed
afterwards.
27. Recommendation: a SetMotorParam command should not be sent during a SetDualPosition sequence: all the motion parameters
defined in the command, except Vmin and Vmax, become active immediately.
Position Periodicity
The figure below illustrates that the moving direction
going from ActPos = +30000 to TagPos = –30000 is
clockwise.
If a counter clockwise motion is required in this example,
several consecutive SetPosition commands can be
used.
Depending on the stepping mode the position can range
from −4096 to +4095 in half−step to −32768 to +32767 in
1/16th micro−stepping mode. One can project all these
positions lying on a circle. When executing the command
SetPosition, the position controller will set the
movement direction in such a way that the traveled distance
is minimal.
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AMIS−30622
+10000
+20000
Hardwired Address HW
In the drawing below, a simplified schematic diagram is
shown of the HW comparator circuit.
The HW pin is sensed via 2 switches. The DriveHS and
DriveLS control lines are alternatively closing the top and
bottom switch connecting HW pin with a current to resistor
converter. Closing STOP (DriveHS = 1) will sense a current
to GND. In that case the top I³ R converter output is low,
via the closed passing switch SPASS_T this signal is fed to the
“R” comparator which output HW_Cmp is high. Closing
bottom switch SBOT (DriveLS = 1) will sense a current to
VBAT. The corresponding I ³ R converter output is low and
via SPASS_B fed to the comparator. The output HW_Cmp
will be high.
ActPos = +30000
0
Motion direction
TagPos = −30000
−10000
−20000
Figure 9. Motion Direction is Function of
Difference between ActPos and TagPos
SPASS_T
I/R
State
1k
STOP
HW
SBOT
1
2
1 = R2GND
2 = R2VBAT
3 = OPEN
High
DriveHS
Low
LOGIC
DriveLS
3
‘‘R”−Comp
I/R
SPASS_B
Debouncer
COMP
Rth
32 ms
HW_Cmp
Figure 10. Simplified Schematic Diagram of the HW Comparator
3 cases can be distinguished (see also Figure 10 above):
• HW is connected to ground: R2GND or drawing 1
• HW is connected to VBAT: R2VBAT or drawing 2
• HW is floating: OPEN or drawing 3
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Float
AMIS−30622
Table 15. STATE DIAGRAM OF THE HW COMPARATOR
Previous State
DriveLS
DriveHS
HW_Cmp
New State
Condition
Drawing
Float
1
0
0
Float
R2GND or OPEN
1 or 3
Float
1
0
1
High
R2VBAT
2
Float
0
1
0
Float
R2VBAT or OPEN
2 or 3
Float
0
1
1
Low
R2GND
1
Low
1
0
0
Low
R2GND or OPEN
1 or 3
Low
1
0
1
High
R2VBAT
2
Low
0
1
0
Float
R2VBAT or OPEN
2 or 3
Low
0
1
1
Low
R2GND
1
High
1
0
0
Float
R2GND or OPEN
1 or 3
High
1
0
1
High
R2VBAT
2
High
0
1
0
High
R2VBAT or OPEN
2 or 3
High
0
1
1
Low
R2GND
1
As illustrated in the table above (Table 15), the state is
depending on the previous state, the condition of the 2
switch controls (DriveLS and DriveHS) and the output of
HW_Cmp. Figure 11 shows an example of a practical case
where a connection to VBAT is interrupted.
The logic is controlling the correct sequence in closing the
switches and in interpreting the 32 ms debounced HW_Cmp
output accordingly. The output of this small state−machine
is corresponding to:
• High or address = 1
• Low or address = 0
• Floating
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AMIS−30622
Condition
R2 VBAT
OPEN
R2 VBAT
R2 GND
t
Tsw = 1024 ms
DriveLS
t
Tsw_on = 64 ms
DriveHS
t
“R”−Comp
Rth
t
HW_Cmp
t
Low
High
Float
High
Float
State
t
Figure 11. Timing Diagram Showing the Change in States for HW Comparator
R2VBAT
a motion to secure position after a debounce time of 64 ms,
which prevents false triggering in case of micro−
interruptions of the power supply.
A resistor is connected between VBAT and HW. Every
1024 ms SBOT is closed and a current is sensed. The output
of the I ⇒ R converter is low and the HW_Cmp output is
high. Assuming the previous state was floating, the internal
logic will interpret this as a change of state and the new state
will be high (see also Table 15). The next time SBOT is closed
the same conditions are observed. The previous state was
high so based on Table 15 the new state remains unchanged.
This high state will be interpreted as HW address = 1.
R2GND
If a resistor is connected between HW and the GND, a
current is sensed every 1024 ms when STOP is closed. The
output of the top I ⇒ R converter is low and as a result the
HW_Cmp output switches to high. Again based on the stated
diagram in Table 15 one can see that the state will change to
Low. This low state will be interpreted as HW address = 0.
OPEN
External Switch SWI
In case the HW connection is lost (broken wire, bad
contact in connector) the next time SBOT is closed, this will
be sensed. There will be no current, the output of the
corresponding I ⇒ R converter is high and the HW_Cmp
will be low. The previous state was high. Based in Table 15
one can see that the state changes to float. This will trigger
As illustrated in Figure 12 the SWI comparator is almost
identical to HW. The major difference is in the limited
number of states. Only open or closed is recognized leading
to respectively ESW = 0 and ESW = 1.
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AMIS−30622
SPASS_T
I/R
State
DriveHS
STOP
Closed
1k
LOGIC
SWI
DriveLS
Open
SBOT
1
2
3
‘‘R”−Comp
1 = R2GND
2 = R2VBAT
3 = OPEN
I/R
SPASS_B
COMP
32 ms Debouncer
SWI_Cmp
Rth
Figure 12. Simplified Schematic Diagram of the SWI Comparator
As illustrated in the drawing above, a change in state is
always synchronized with DriveHS or DriveLS. The same
synchronization is valid for updating the internal position
register. This means that after every current pulse (or closing
of STOP or SBOT) the state of the position switch together
with the corresponding position is memorized.
The FullStatus1 command reads back the
<ActPos> register and the status of ESW. In this way the
master node may get synchronous information about the
state of the switch together with the position of the motor.
See Table 16 below.
Table 16. GetFullStatus1 I2C COMMAND
GetFullStatus1 Response Frame
Structure
Byte
Content
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
Address
1
1
OTP3
OTP2
OTP1
OTP0
HW
1
1
Address
1
1
1
OTP3
OTP2
OTP1
OTP0
HW
2
Data 1
Irun[3:0]
Ihold[3:0]
3
Data 2
Vmax[3:0]
Vmin[3:0]
4
Data 3
AccShape
5
Data 4
VddReset
6
Data 5
7
Data 6
1
1
8
Data 7
1
1
StepMode[1:0]
StepLoss
Shaft
ElDef
Acc[3:0]
UV2
TSD
TW
ESW
OVC1
OVC2
1
CPFail
1
1
1
1
1
1
1
1
1
1
1
1
Motion[2:0]
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Tinfo[1:0]
AMIS−30622
DriveHS
512 ms
Tsw = 1024 ms
t
Tsw_on = 64 ms
DriveLS
t
“R”−Comp
Rth
t
SWI_Cmp
60 ms
t
ESW
0
1
1
1
ActPos + 3
ActPos + 2
ActPos
ActPos
ActPos + 1
t
t
Figure 13. Simplified Timing Diagram Showing the Change in States for SWI Comparator
Main Control and Register, OTP memory + ROM
level), the H−bridges will be in high−impedance mode, and
the registers and flags will be in a predetermined position.
This is documented in Table 19: RAM Registers and
Table 20: Flags Table.
Power−up Phase
Power−up phase of the AMIS−30622 will not exceed
10 ms. After this phase, the AMIS−30622 is in standby
mode, ready to receive I2C messages and execute the
associated commands. After power−up, the registers and
flags are in the reset state, while some of them are being
loaded with the OTP memory content (see Table 19: RAM
Registers).
Soft−stop
A soft−stop is an immediate interruption of a motion, but
with a deceleration phase. At the end of this action, the
register <TagPos> is loaded with the value contained in
register <ActPos>, see Table 19: Ram Registers). The
circuit is then ready to execute a new positioning command,
provided thermal and electrical conditions allow for it.
Reset
After power−up, or after a reset occurrence (e.g. a
micro−cut on pin VBB has made VDD to go below VddReset
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AMIS−30622
Thermal Shutdown Mode
diagram and illustration of Figure 14: State Diagram
Temperature Management below. The only condition to
reset flags <TW> and <TSD> (respectively thermal warning
and thermal shutdown) is to be at a temperature lower than
Ttw and to get the occurrence of a GetFullStatus1 I2C
frame.
When thermal shutdown occurs, the circuit performs a
<SoftStop> command and goes to motor shutdown
mode (see Figure 14: State Diagram Temperature
Management).
Temperature Management
The AMIS−30622 monitors temperature by means of two
thresholds and one shutdown level, as illustrated in the state
Normal Temp.
− <Tinfo> = “00”
− <TW> = ‘0’
− <TSD> = ‘0’
Thermal warning
T° > Ttw
T° > Ttsd
−<Tinfo> = “10”
−<TW> = ‘1’
−<TSD> = ‘0’
T° < Ttw &
T° > Ttw
I2C Frame:
GetFullStatus1
T° < Ttw
Post thermal
warning
Thermal shutdown
− <Tinfo> = “11”
− <TW> = ‘1’
− <TSD> = ‘1’
−SoftStop if
motion ongoing
− Motor shutdown
(motion disabled)
T° > Ttsd
−<Tinfo> = “00”
−<TW> = ‘1’
−<TSD> = ‘0’
T° < Tlow
Post thermal
shutdown 1
T° < Ttw
T° > Tlow
Low Temp.
− <Tinfo> = “01”
− <TW> = ‘0’
− <TSD> = ‘0’
Post thermal
shutdown 2
− <Tinfo> = “00”
− <TW> = ‘1’
− <TSD> = ‘1’
− Motor shutdown
(motion disabled)
− <Tinfo> = “10”
− <TW> = ‘1’
− <TSD> = ‘1’
− Motor shutdown
(motion disabled)
T° > Ttw
Figure 14. State Diagram Temperature Management
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T° < Ttsd
AMIS−30622
T shutdown level
T
T warning level
t
T <tw> bit
T < Ttw and
getfullstatus1
T <tsd> bit
T > Ttsd, motor
stops and
shutdown
T < Ttw and
getfullstatus1
Figure 15. Illustration of Thermal Management Situation
Battery Voltage Management
to reset flags <UV2> and <StepLoss> is to recover by a
battery voltage higher than UV1 and to receive a
GetFullStatus1 command.
The AMIS−30622 monitors the battery voltage by means
of one threshold and one shutdown level. The only condition
− <UV2> = ‘0’
− <Steploss> = ‘0’
NORMAL
VOLTAGE
VBB > UV1
VBB > UV1
& LIN Frame
& LIN Frame
<GetFullStatus> or
<GetFullStatus> or
<GetStatus
<GetStatus>
VBB < UV2
VBB < UV2
No Motion & Motion Ongoing
− <UV2> = ‘1’
− <Steploss> = ‘0’
− Motor Shutdown
STOP
MODE
1
− <UV2> = ‘1’
− <Steploss> = ‘1’
− HardStop
− Motor Shutdown
STOP
MODE
2
Figure 16. State Diagram Battery Voltage Management
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AMIS−30622
In Stop mode 1 the motor is put in shutdown state. The
<UV2> flag is set. In case VBB > UV1, AMIS−30622 accepts
updates of the target position by means of the reception of
SetPosition or GotoSecurePosition commands,
only AFTER the <UV2> flag is cleared by receiving a
GetFullStatus1 or GetFullStatus2 command.
In Stop mode 2 the motor is stopped immediately and put
in shutdown state. The <UV2> and <Steploss> flags are
set. In case VBB > UV1, AMIS−30622 accepts updates of the
target position by means of the reception of SetPosition
or GotoSecurePosition commands, only AFTER the
<UV2> and <Steploss> flags are cleared by receiving a
GetFullStatus1 or GetFullStatus2 command.
Important Notes:
• In the case of Stop mode 2, care needs to be taken
•
•
because the accumulated steploss can cause a
significant deviation between physical and stored actual
position.
The SetDualPosition command will only be
executed after clearing the <UV2> and <Steploss>
flags.
RAM reset occurs when VDD < VDDReset (digital POR
level).
OTP Register
OTP Memory Structure
The table below shows how the parameters to be stored in the OTP memory are located.
Table 17. OTP MEMORY STRUCTURE
Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x00
OSC3
OSC2
OSC1
OSC0
IREF3
IREF2
IREF1
IREF0
0x01
0
TSD2
TSD1
TSD0
BG3
BG2
BG1
BG0
PA3
PA2
PA1
PA0
0x02
0x03
Irun3
Irun2
Irun1
Irun0
Ihold3
Ihold2
Ihold1
Ihold0
0x04
Vmax3
Vmax2
Vmax1
Vmax0
Vmin3
Vmin2
Vmin1
Vmin0
0x05
SecPos10
SecPos9
SecPos8
Shaft
Acc3
Acc2
Acc1
Acc0
0x06
SecPos7
SecPos6
SecPos5
SecPos4
SecPos3
SecPos2
SecPos1
SecPos0
StepMode1
StepMode0
LOCKBT
LOCKBG
0x07
Parameters stored at address 0x00 and 0x01 and bit
<LOCKBT> are already programmed in the OTP memory at
circuit delivery. They correspond to the calibration of the
circuit and are just documented here as an indication.
Each OTP bit is at ‘0’ when not zapped. Zapping a bit will
set it to ‘1’. Thus only bits having to be at ‘1’ must be zapped.
Zapping of a bit already at ‘1’ is disabled. Each OTP byte
will be programmed separately (see command
SetOTPparam). Once OTP programming is completed, bit
<LOCKBG> can be zapped to disable future zapping,
otherwise any OTP bit at ‘0’ could still be zapped by using
a SetOTPparam command.
programming is SetMotorParam. This allows for a
functional verification before using a SetOTPparam
command to program and zap separately one OTP memory
byte. A GetOTPparam command issued after each
SetOTPparam command allows verifying the correct byte
zapping.
Note: Zapped bits will become active only after a power
cycle. After programming the I2C bits the power cycle has
to be performed first to guarantee further communication
with the device.
Application Parameters Stored in OTP Memory
Except for the physical address <PA[3:0]> these
parameters, although programmed in a non−volatile
memory can still be overridden in RAM by a I2C writing
operation.
PA[3:0] In combination with hired wired (HW)
address, it forms the physical address AD[6:0]
of the stepper−motor. Up to 32 stepper motors
can theoretically be connected to the same I2C
bus.
Table 18. OTP OVERWRITE PROTECTION
Lock Bit
Protected Bytes
LOCKBT (factory zapped
before delivery)
0x00 to 0x01
LOCKBG
0x00 to 0x07
The command used to load the application parameters via
the I2C bus in the RAM prior to an OTP Memory
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AMIS−30622
Irun[3:0] Current amplitude value to be fed to
each coil of the stepper−motor. The table below
provides the 16 possible values for <IRUN>.
Ihold[3:0] Hold current for each coil of the
stepper−motor. The table below provides the 16
possible values for <IHOLD>.
Index
Run Current (mA)
Index
Irun
Ihold
Hold Current (mA)
0
0
0
0
0
59
0
0
0
0
0
59
1
0
0
0
1
71
1
0
0
0
1
71
2
0
0
1
0
84
2
0
0
1
0
84
3
0
0
1
1
100
3
0
0
1
1
100
4
0
1
0
0
119
4
0
1
0
0
119
5
0
1
0
1
141
5
0
1
0
1
141
6
0
1
1
0
168
6
0
1
1
0
168
7
0
1
1
1
200
7
0
1
1
1
200
8
1
0
0
0
238
8
1
0
0
0
238
9
1
0
0
1
283
9
1
0
0
1
283
A
1
0
1
0
336
A
1
0
1
0
336
B
1
0
1
1
400
B
1
0
1
1
400
C
1
1
0
0
476
C
1
1
0
0
476
D
1
1
0
1
566
D
1
1
0
1
566
E
1
1
1
0
673
E
1
1
1
0
673
F
1
1
1
1
800
F
1
1
1
1
800
Note: When the motor is stopped, the current is reduced
from <IRUN> to <IHOLD>.
StepMode Setting of step modes.
StepMode
Step Mode
0
0
1/2 stepping
0
1
1/4 stepping
1
0
1/8 stepping
1
1
1/16 stepping
Shaft This bit distinguishes between a clock−wise
or counter−clock−wise rotation. The shaft bit is
not working in RunVelocity mode.
SecPos[10:0] Secure Position of the
stepper−motor. This is the position to which the
motor is driven in case of a HW pin connection
is lost. If <SecPos[10:0]> = “100 000000
00”, secure positioning is disabled; the
stepper−motor will be kept in the position
occupied at the moment these events occur.
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AMIS−30622
Note: The Secure Position is coded on 11 bits only,
providing actually the most significant bits of the position, the
non coded least significant bits being set to ‘0’.
Vmax[3:0] Maximum velocity
Index
Vmax
Acc[3:0] Acceleration and deceleration between
Vmax and Vmin.
Index
Acceleration (Full−step/s2)
Acc
0
0
0
0
0
Vmax(full step/s)
Group
49
(*)
1
0
0
0
A
2
0
0
1
1
218
(*)
0
1004
.
0
0
0
0
0
99
1
0
0
0
1
136
3
0
0
1
1
3609
.
2
0
0
1
0
167
4
0
1
0
0
6228
.
3
0
0
1
1
197
5
0
1
0
1
8848
.
4
0
1
0
0
213
6
0
1
1
0
11409
.
5
0
1
0
1
228
7
0
1
1
1
13970
.
6
0
1
1
0
243
8
1
0
0
0
16531
.
7
0
1
1
1
273
9
1
0
0
1
19092
(*)
8
1
0
0
0
303
A
1
0
1
0
21886
(*)
9
1
0
0
1
334
B
1
0
1
1
24447
(*)
A
1
0
1
0
364
C
1
1
0
0
27008
(*)
B
1
0
1
1
395
D
1
1
0
1
29570
(*)
C
1
1
0
0
456
E
1
1
1
0
34925
(*)
D
1
1
0
1
546
F
1
1
1
1
40047
(*)
E
1
1
1
0
729
F
1
1
1
1
973
B
C
D
(*) restriction on speed
Vmin[3:0] Minimum velocity.
Index
Vmin
Vmax Factor
0
0
0
0
0
1
1
0
0
0
1
1/32
2
0
0
1
0
2/32
3
0
0
1
1
3/32
4
0
1
0
0
4/32
5
0
1
0
1
5/32
6
0
1
1
0
6/32
7
0
1
1
1
7/32
8
1
0
0
0
8/32
9
1
0
0
1
9/32
A
1
0
1
0
10/32
B
1
0
1
1
11/32
C
1
1
0
0
12/32
D
1
1
0
1
13/32
E
1
1
1
0
14/32
F
1
1
1
1
15/32
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AMIS−30622
Table 19. RAM REGISTERS
Mnemonic
Length
(bit)
ActPos
16
GetFullStatus2
GotoSecurePos
ResetPosition
16−bit signed
Pos/TagPos
16/11
GetFullStatus2
GotoSecurePos
ResetPosition
SetPosition
16−bit signed or
11−bit signed for half stepping
(see Positioning)
AccShape
1
GetFullStatus1
SetMotorParam
ResetToDefault
‘0’ ⇒ normal acceleration from Vmin to Vmax
‘1’ ⇒ motion at Vmin without acceleration
Coil peak current
Irun
4
GetFullStatus1
SetMotorParam
ResetToDefault
Operating current
See look−up table Irun
Coil hold current
Ihold
4
GetFullStatus1
SetMotorParam
ResetToDefault
Standstill current
See look−up table Ihold
Minimum Velocity
Vmin
4
GetFullStatus1
SetMotorParam
ResetToDefault
See Section Minimum Velocity
See look−up table Vmin
Maximum Velocity
Vmax
4
GetFullStatus1
SetMotorParam
ResetToDefault
See Section Maximum Velocity
See look−up table Vmax
Register
Actual position
Last programmed
Position
Acceleration shape
Shaft
Related Commands
Comment
Shaft
1
GetFullStatus1
SetMotorParam
ResetToDefault
Direction of movement
Acc
4
GetFullStatus1
SetMotorParam
ResetToDefault
See Section Acceleration
See look−up table Acc
Secure Position
SecPos
11
GetFullStatus2
SetMotorParam
ResetToDefault
Target position when HW connection fails; 11
MSB’s of 16−bit position (LSB’s fixed to ‘0’)
Stepping mode
StepMode
2
GetFullStatus1
SetStallParam
ResetToDefault
See Section Stepping Modes
See look−up table StepMode
Acceleration/
deceleration
Reset
State
‘0’
From
OTP
memory
28. A ResetToDefault command will act as a reset of the RAM content, except for ActPos and TagPos, which are registers that are not
modified. Therefore, the application should not send a ResetToDefault during a motion, to avoid any unwanted change of parameter.
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AMIS−30622
Table 20. FLAGS TABLE
Flag
Mnemonic
Length
(bit)
Related Commands
Charge pump failure
CPFail
1
GetFullStatus1
‘0’ = charge pump OK
‘1’ = charge pump failure
Resets only after GetFullStatus1
‘0’
Electrical defect
ElDef
1
GetFullStatus1
<OVC1> or <OVC2> or
‘open−load on coil X’ or ‘open−load on
coil XY or <CPFail>
Resets only after GetFullStatus1
‘0’
External switch status
ESW
1
GetFullStatus1
‘0’ = open
‘1’ = close
‘0’
Electrical flag
HS
1
Internal use
<CPFail> or <UV2> or <ElDef> or <VDDreset>
‘0’
Motion status
Motion
3
GetFullStatus1
“x00” = Stop
“001” = inner (CCW) motion acceleration
“010” = inner (CCW) motion deceleration
“011” = inner (CCW) motion max. speed
“101” = outer (CW) motion acceleration
“110” = outer (CW) motion deceleration
“111” = outer (CW) motion max. speed
Comment
Reset
State
“000”
Over current in coil X
OVC1
1
GetFullStatus1
‘1’ = over current; reset only after GetFullStatus1
‘0’
Over current in coil Y
OVC2
1
GetFullStatus1
‘1’ = over current; reset only after GetFullStatus1
‘0’
Secure position
enabled
SecEn
1
Internal use
‘0’ if <SecPos> = “100 0000 0000”
‘1’ otherwise
StepLoss
1
GetFullStatus1
‘1’ = step loss due to under voltage, over current,
open circuit or stall; Resets only after GetFullStatus1
Motor stop
Stop
1
Internal use
Temperature info
Tinfo
2
GetFullStatus1
Step loss
n.a.
‘1’
‘0’
“00” = normal temperature range
“01” = low temperature warning
“10” = high temperature warning
“11” = motor shutdown
“00”
Thermal shutdown
TSD
1
GetFullStatus1
‘1’ = shutdown (Tj > Ttsd)
Resets only after GetFullStatus1
and if <Tinfo> = “00”
‘0’
Thermal warning
TW
1
GetFullStatus1
‘1’ = over temperature (Tj > Ttw)
Resets only after GetFullStatus1
and if <Tinfo> = “00”
‘0’
Battery stop voltage
UV2
1
GetFullStatus1
‘0’ = VBB > UV2
‘1’ = VBB ≤ UV2
Resets only after GetFullStatus1
‘0’
Digital supply reset
VddReset
1
GetActualPos
GetStatus
GetFullStatus1
Set at ‘1’ after power−up of the circuit. If this was due to
a supply micro−cut, it warns that the RAM contents
may have been lost; can be reset to ‘0’ with a
Get(Full)Status1 command
‘1’
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AMIS−30622
Priority Encoder
The table below describes the simplified state management performed by the main control block.
Table 21. PRIORITY ENCODER
State "
Standby
GotoPos
DualPosition
Motor
Stopped,
Ihold in Coils
Motor Motion
Ongoing
No Influence on
RAM and TagPos
GetOTPparam
OTP refresh;
I2C slave
response
OTP refresh;
I2C slave
response
GetFullStatus1
[attempt to clear
all flags]
(Note 29)
I2C slave
response
GetFullStatus2
ResetToDefault
[ ActPos and
TagPos are not
altered ]
Command
O
SetMotorParam
[Master takes
care about
proper update]
RAM update
Stopped
HardStop
ShutDown
Motor
Decelerating
Motor Forced to
Stop
Motor Stopped,
H−bridges in
Hi−Z
OTP refresh;
I2C slave
response
OTP refresh;
I2C slave
response
OTP refresh;
I2C slave
response
OTP refresh;
I2C slave
response
I2C slave
response
I2C slave
response
I2C slave
response
I2C slave
response
I2C slave
response;
if (<TSD> or
<ElFlag> = ‘0’
then → Stopped
I2C slave
response
I2C slave
response
I2C slave
response
I2C slave
response
I2C slave
response
I2C slave
response
OTP refresh;
OTP to RAM;
AccShape
reset
OTP refresh;
OTP to RAM;
AccShape reset
OTP refresh;
OTP to RAM;
AccShape reset
(Note 31)
OTP refresh;
OTP to RAM;
AccShape reset
OTP refresh;
OTP to RAM;
AccShape reset
OTP refresh;
OTP to RAM;
AccShape reset
RAM update
RAM update
RAM update
RAM update
RAM update
RAM update
ResetPosition
<TagPos> and
<ActPos> reset
SetPosition
<TagPos>
updated;
→ GotoPos
GotoSecPosition
If <SecEn> =
‘1’ then
<TagPos> =
<SecPos>;
→ GotoPos
DualPosition
→ DualPosition
SoftStop
<TagPos> and
<ActPos>
reset
<TagPos>
updated
HardUnder
ShutUnder
RAM update
RAM update
<TagPos> and
<ActPos>
reset
<TagPos>
updated
If <SecEn> = ‘1’ If <SecEn> = ‘1’
then <TagPos> = then <TagPos> =
<SecPos>
<SecPos>
SoftStop
→ SoftStop
HardStop
→ HardStop
→ HardStop
→ HardStop
VBB < UV2
→ HardUnder
→ HardUnder
→ HardStop
→ HardUnder
<ElDef> = ‘1’ ⇒
<HS> = ‘1’
→ Shutdown
→ HardStop;
<StepLoss> = ‘1’
→ HardStop;
<StepLoss> = ‘1’
→ HardStop;
<StepLoss> = ‘1’
Thermal
shutdown
[<TSD> = ‘1’]
→ Shutdown
→ SoftStop
→ SoftStop
Motion finished
n.a.
→ Stopped
→ Stopped
→ Shutdown
→ Shutdown
→ Stopped;
<TagPos> =
<ActPos>
→ Stopped;
<TagPos> =
<ActPos>
n.a.
With the Following Color Code:
Command Ignored
NOTE:
Transition to Another State
Master is responsible for proper update (see Note 34)
See table notes on the following page.
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AMIS−30622
29. <ElFlag> = <CPFail> or <UV2> or <ElDef> or <VDDreset>
30. After power−on−reset, the <Standby> state is entered.
31. A DualPosition sequence runs with a separate set of RAM registers. The parameters that are not specified in a DualPosition command are
loaded with the values stored in RAM at the moment the DualPosition sequence starts. <AccShape> is forced to ‘1’ during second motion.
<AccShape> at ‘0’ will be taken into account after the DualPosition sequence. A GetFullStatus1 command will return the default
parameters for <Vmax> and <Vmin> stored in RAM.
32. Shutdown state can be left only when <TSD> and <HS> flags are reset.
33. Flags can be reset only after the master could read them via a GetFullStatus1 command, and provided the physical conditions allow
for it (normal temperature, correct battery voltage and no electrical or charge pump defect).
34. A SetMotorParam command sent while a motion is ongoing (state <GotoPos>) should not attempt to modify <Acc> and <Vmin> values.
This can be done during a DualPosition sequence since this motion uses its own parameters, the new parameters will be taken into account
at the next SetPosition command.
35. <SecEn> = ‘1’ when register <SecPos> is loaded with a value different from the most negative value (i.e. different from 0x400 = “100 0000
0000”).
36. <Stop> flag allows distinguishing whether state <Stopped> was entered after HardStop/SoftStop or not. <Stop> is set to ‘1’ when leaving
state <HardStop> or <SoftStop> and is reset during first clock edge occurring in state <Stopped>.
37. While in state <Stopped>, if <ActPos> → <TagPos> there is a transition to state <GotoPos>. This transition has the lowest priority,
meaning that <Stop>, <TSD>, etceteras are first evaluated for possible transitions.
38. If <StepLoss> is active, then SetPosition and GotoSecurePosition commands are not ignored. <StepLoss> can only be cleared
by a GetFullStatus1 command.
POR
Thermal Shutdown
Referencing
HardStop
Shutdown
HardStop
Thermal
ShutDown
SoftStop
HardStop
Dual Positioning Motion finished
Motion Finished
GotoSecPos
HardStop
Thermal Shutdown
Soft−stop
HardStop
SetPosition
Stopped
Motion Finished
GotoPos
GetFullStatus1
Motion Finished
Priorities
1
2
3
Vbb < UV2 or CPFAIL
4
Vbb < UV2 or CPFAIL
HardStop
Figure 17. Simplified State Diagram
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AMIS−30622
Motordriver
Current Waveforms in the Coils
Figure 18 below illustrates the current fed to the motor coils by the motordriver in half−step mode.
Ix
Coil X
Iy
t
Coil Y
Figure 18. Current Waveforms in Motor Coils X and Y in Halfstep Mode
Whereas Figure 19 below shows the current fed to the coils in 1/16th micro stepping (1 electrical period).
Coil X
Iy
Ix
t
Coil Y
Figure 19. Current Waveforms in Motor Coils X and Y in 1/16th Micro−Step Mode
PWM Regulation
regulation loop performs a comparison of the sensed output
current to an internal reference, and features a digital
regulation generating the PWM signal that drives the output
switches. The zoom over one micro−step in the Figure 19
above shows how the PWM circuit performs this regulation.
In order to force a given current (determined by <Irun>
or <Ihold> and the current position of the rotor) through
the motor coil while ensuring high energy transfer
efficiency, a regulation based on PWM principle is used. The
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AMIS−30622
Motor Starting Phase
Motor Stopping Phase
At motion start, the currents in the coils are directly
switched from <Ihold> to <Irun> with a new
sine/cosine ratio corresponding to the first half (or micro−)
step of the motion.
At the end of the deceleration phase, the currents are
maintained in the coils at their actual DC level (hence
keeping the sine/cosine ratio between coils) during the
stabilization time tstab (see AC Table). The currents are then
set to the hold values, respectively Ihold x sin(TagPos)
and Ihold x cos(TagPos), as illustrated below. A new
positioning order can then be executed.
Iy
Ix
t
Figure 20. Motor Stopping Phase
t stab
Charge Pump Monitoring
Motor Shutdown Mode
If the charge pump voltage is not sufficient for driving the
high side transistors (due to failure), an internal HardStop
command is issued. This is acknowledged to the master by
raising flag <CPFail> (available with command
GetFullStatus1).
In case this failure occurs while a motion is ongoing, the
flag <StepLoss> is also raised.
A motor shutdown occurs when:
• The chip temperature rises above the thermal shutdown
threshold Ttsd (see Thermal Shutdown Mode).
• The battery voltage goes below UV2 for longer than 15
seconds (see Battery Voltage Management).
• The charge pump voltage goes below the charge pump
comparator level for more than 15 seconds.
• Flag <ElDef> = ‘1’, meaning an electrical problem is
detected on one or both coils, e.g. a short circuit.
Electrical Defect on Coils, Detection and Confirmation
The principle relies on the detection of a voltage drop on
at least one transistor of the H−bridge. Then the decision is
taken to open the transistors of the defective bridge.
This allows the detection the following short circuits:
• External coil short circuit
• Short between one terminal of the coil and Vbat or GND
A motor shutdown leads to the following:
• H−bridges in high impedance mode.
• The <TagPos> register is loaded with the <ActPos>,
except in autarkic states.
The conditions to get out of a motor shutdown mode are:
• Reception of a GetFullStatus1 command AND
• The four above causes are no longer detected
One cannot detect an internal short in the motor.
Open circuits are detected by 100% PWM duty cycle
value during one electrical period with duration, determined
by Vmin.
This leads to H−bridges going in Ihold mode. Hence, the
circuit is ready to execute any positioning command.
Table 22. ELECTRICAL DEFECT DETECTION
Pins
Fault Mode
Yi or Xi
Short−circuit to GND
Yi or Xi
Short−circuit to Vbat
Yi or Xi
Open
Y1 and Y2
Short circuited
X1 and X2
Short circuited
Xi and Yi
Short circuited
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AMIS−30622
This can be illustrated in the following sequence given as an application example. The master can check whether there is
a problem or not and decide which application strategy to adopt.
Table 23. Example of Possible Sequence used to Detect and Determine Cause of Motor Shutdown
Tj ≥ Tsd or
VBB ≤ UV2 or
<ElDef> = ‘1’ or
<CPFail> = ‘1’
↓
− The circuit is driven in motor shutdown
mode
− The application is not aware of this
SetPosition
frame
↓
− The position set−point is
updated by the I2C Master
− Motor shutdown mode
⇒ no motion
− The application is still
unaware
GetFullStatus1 frame
↓
GetFullStatus1 frame
↓...
− The application is aware
of a problem
− Possible confirmation of
the problem
− Reset <TW> or <TSD> or <UV2> or <StepLoss> or
<ElDef> or <CPFail> by the application
− Possible new detection of over temperature or low
voltage or electrical problem ⇒ Circuit sets <TW> or
<TSD> or <UV2> or <StepLoss> or <ElDef> or
<CPFail> again at ‘1’
Warning: The application should limit the number of
consecutive GetFullStatus1 commands to try to get the
AMIS−30622 out of shutdown mode when this proves to be
unsuccessful, e.g. there is a permanent defect. The reliability
of the circuit could be altered since GetFullStatus1 attempts
to disable the protection of the H−bridges.
Important: While in shutdown mode, since there is no hold
current in the coils, the mechanical load can cause a step loss,
which indeed cannot be flagged by the AMIS−30622.
Note: The Priority Encoder is describing the management of
states and commands.
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AMIS−30622
I2C BUS DESCRIPTION
• No need to design bus interfaces because I2C−bus
General Description
AMIS−30622 uses a simple bi−directional 2−wire bus for
efficient inter−ic control. This bus is called the Inter IC or
I2C−bus.
Features include:
• Only two bus lines are required; a serial data line
(SDA) and a serial clock line (SCK).
• Each device connected to the bus is software
addressable by a unique address and simple
master/slave relationships exists at all times; master can
operate as master−transmitter or as master receiver.
• Serial, 8−bit oriented, bi−directional data transfers can
be made up to 400 kb/s.
• On−chip filtering rejects spikes on the bus data line to
preserve data integrity.
interface is already integrated on−chip.
• IC’s can be added to or removed from a system without
affecting any other circuits on the bus.
Concept
The I2C−bus consists of two wires, serial data (SDA) and
serial clock (SCK), carrying information between the
devices connected on the bus. Each device connected to the
bus is recognized by a unique address and operates as either
a transmitter or receiver, depending on the function of the
device. AMIS−30622 can both receive and transmit data. In
addition to transmitters and receivers, devices can also be
considered as masters or slaves when performing data
transfers. AMIS−30622 is a slave device. See Table 25.
Table 24. DEFINITION OF I2C–BUS TERMINOLOGY
Term
Description
Transmitter
The device which sends data on the bus
Receiver
The device which receives data from the bus
Master
The device which initiates a transfer, generates clock signals and terminates a transfer
Slave
The devices addressed by a master
Synchronization
Procedure to synchronizer the clock signals of two or more devices
Micro−
controller
Motordriver_2
Motordriver_4
AMIS−30622
AMIS−30622
SDA
SCL
Motordriver_1
Motordriver_3
AMIS−30622
AMIS−30622
Figure 21. Example of an I2C−bus Configuration Using One Microcontroller and Four Slaves
2. If the microcontroller wants to receive information
from motordriver_2:
♦ Microcontroller (master) addresses
motordriver_2 (slave)
♦ Microcontroller (master−receiver) receives data
from motordriver_2 (slave−transmitter)
♦ Microcontroller terminates the transfer
Even in this case the master generates the timing and
terminates the transfer.
Generation of the signals on the I2C−bus is always the
responsibility of the master device. It generates its own
clock signal when transferring data on the bus. Bus clock
signals from a master can only be altered when they are
stretched by a slow slave device holding−down the clock
line.
Figure 21
highlights
the
master−slave
and
receiver−transmitter relationships to be found on the
I2C−bus. It should be noted that these relationships are not
permanent but only depend on the direction of data transfer
at that time. The transfer of data would proceed as follows:
1. Suppose the microcontroller wants to send
information to motordriver_1:
♦ Microcontroller (master) addresses
motordriver_1 (slave)
♦ Microcontroller (master−transmitter) sends data
to motordriver_1 (slave−receiver)
♦ Microcontroller terminates the transfer
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AMIS−30622
General Characteristics
+5 V
Rp
Rp
Serial Data Line
Serial Clock Line
SCK
SDA
2
Clock IN
SCL
1
Data IN
Clock OUT
SDA
Clock IN
Data OUT
Data IN
Clock OUT
AMIS−30624,
NCV70624
Data OUT
MASTER
Figure 22. Connection of a Device to the I2C−bus
START and STOP Conditions
Both SDA and SCK are bi−directional lines connected to
a positive supply voltage via a pull−up resistor (see
Figure 22). When the bus is free both lines are HIGH. The
output stages of the devices connected to the bus must have
an open drain to perform the wired−AND function. Data on
the I2C−bus can be transferred up to 400 kb/s in fast mode.
The number of interfaces connected to the bus is dependent
on the maximum bus capacitance limit (See CB in Table 6)
and the available number of addresses.
Within the procedure of the I2C−bus, unique situations
arise, which are defined as START (S) and STOP (P)
conditions (See Figure 24).
A HIGH to LOW transition on the SDA line while SCK
is HIGH is one such unique case. This situation indicates a
START condition. LOW to HIGH transition on the SDA line
while SCK is HIGH defines a STOP condition.
START and STOP conditions are always generated by the
master. The bus is considered to be busy after the START
condition. The bus is considered to be free again a certain
time after the STOP condition. The bus free situation is
specified as tBUF in Table 6.
The bus stays busy if a repeated START (Sr) is generated
instead of a STOP condition. In this respect, the START (S)
and repeated START (Sr) conditions are functionally
identical (See Figure 25). The symbol S will be used to
represent START and repeated START, unless otherwise
noted.
Bit Transfer
The levels for logic ‘0’ (LOW) and ‘1’ (HIGH) are not
fixed in the I2C standard but dependent on the used VDD
level. Using AMIS−30622, the levels are specified in
Table 5. One clock pulse is generated for each data bit
transferred.
Data Validity
The data on the SDA line must be stable during the HIGH
period of the clock. The HIGH or LOW state of the data line
can only change when the clock signal on the SCL line is
LOW (See Figure 23).
START
STOP
SDA
SDA
SCK
SCK
Data line stable
−> Data valid
Change of
data allowed
START
condition
Figure 23. Bit Transfer on the I2C−bus
STOP
condition
Figure 24. START and STOP Conditions
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AMIS−30622
Transferring Data
most significant bit (MSB) first (See Figure 25). If a slave
can’t receive or transmit another complete byte of data, it can
hold the clock line SCK LOW to force the master into a wait
state. Data transfer then continues when the slave is ready for
another byte of data and releases clock line SCK.
Byte Format
Every byte put on the SDA line must be 8−bits long. The
number of bytes that can be transmitted per transfer to
AMIS−30622 is restricted to eight. Each byte has to be
followed by an acknowledge bit. Data is transferred with the
START
STOP
SDA
MSB
Acknowledgement
signal from slave
SCK
1
7
2
8
Clock line held
low by slave
9
1
2
3−8
9
ACK
START
condition
STOP
condition
Aknowledge related
clock puse from master
Figure 25. Data Transfer on the I2C−bus
Acknowledge
If AMIS−30622 as slave−receiver does acknowledge the
slave address but later in the transfer cannot receive any
more data bytes, this is indicated by generating a
not−acknowledge on the first byte to follow. The master
generates than a STOP or a repeated START condition.
If a master−receiver is involved in the transfer, it must
signal the end of data to the slave−transmitter by not
generating an acknowledge on the last byte that was clocked
out of the slave. AMIS−30622 as slave−transmitter shall
release the data line to allow the master to generate STOP or
repeated START condition.
Data transfer with acknowledge is obligatory. The
acknowledge−related clock pulse is generated by the master.
The transmitter releases the SDA line (HIGH) during the
acknowledge clock pulse. The receiver must pull down the
SDA line during the acknowledge clock pulse so that it
remains stable LOW during the HIGH period of this clock
pulse (see Figure 26). Of course, set−up and hold times must
also taken into account (see Table 6). When AMIS−30622
doesn’t acknowledge the slave address, the data line will be
left HIGH. The master can than generate either a STOP
condition to abort the transfer, or a repeated START
condition to start a new transfer.
START
Master releases the Data line
SDA by master
transmitter
MSB
Not acknowledged
SDA by slave
receiver
Acknowledged
SCK from
master
1
START
condition
8
2
Slave pulls data line
low if Acknowledged
9
Aknowledge related
clock puse from master
Figure 26. Acknowledge on the I2C−bus
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AMIS−30622
Clock Generation
address is 7−bit long followed by an eighth bit which is a data
direction bit (R/W) − a ‘zero’ indicates a transmission
(WRITE), a ‘one’ indicates a request for data (READ). A
data transfer is always terminated by a STOP condition (P)
generated by the master.
The master generates the clock on the SCK line to transfer
messages on the I2C−bus. Data is only valid during the
HIGH period of the clock.
Data Formats with 7−bit Addresses
Data transfers follow the format shown in Figure 27. After
the START condition (S), a slave address is sent. This
START
STOP
SDA
SCK
1−7
START
condition
ADDRESS
8
9
R/W
ACK
8
1−7
9
DATA
1−7
ACK
9
8
DATA
ACK
STOP
condition
Figure 27. A Complete Data Transfer
However, if a master still wishes to communicate on the
bus, it can generate a repeated START (Sr) and address
another slave without first generating a STOP condition.
Various combinations of read/write formats are then
possible within such a transfer.
♦
♦
♦
Data Transfer Formats
Writing Data to AMIS−30622
When writing to AMIS−30622, the master−transmitter
transmits to slave−receiver and the transfer direction is not
changed. A complete transmission consists of:
♦ Start condition
♦ The slave address (7−bit)
S
Slave Address
R/W
A
♦
Data
AMIS−30624 to Master
A
Data
A
P
N bytes + Acknowledge
”0” = WRITE
Master to AMIS−30624
Read/Write bit (‘0’ = write)
Acknowledge bit
Any further data bytes are followed by an
acknowledge bit. The acknowledge bit is used to
signal a correct reception of the data to the
transmitter. In this case the AMIS−30622 pulls the
SDA line to ‘0’. The AMIS−30622 reads the
incoming data at SDA on every rising edge of the
SCK signal
Stop condition to finish the transmission
S = Start condition
P = Stop condition
A = Acknowledge (SDA = LOW)
A = No Acknowledge (SDA = HIGH)
Figure 28. Master Writing Data to AMIS−30622
Some commands for the AMIS−30622 are supporting
eight bytes of data, other commands are transmitting two
bytes of data. See Table 25.
1. The first transmission consists of two bytes of
data:
♦ The first byte contains the slave address and the
write bit.
♦ The second byte contains the address of an
internal register in the
AMIS−30622. This internal
register address is stored in the circuit RAM.
Reading Data to AMIS−30622
When reading data from AMIS−30622 two transmissions
are needed:
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AMIS−30622
S
Slave Address
R/W
A
Internal Address
A
P
”0” = WRITE
Figure 29. Master Reading Data from AMIS−30622: First Transmission is Addressing
2. The second transmission consists of the slave
address and the read bit. Then the master can read
the data bits on the SDA line on every rising edge
of signal SCK. After each byte of data the master
has to acknowledge correct data reception by
S
Slave Address
R/W
A
pulling SDA LOW. The last byte is not
acknowledged by the master and therefore the
slave knows the end of transmission.
Data
Data
A
P
N bytes + Acknowledge
”0” = WRITE
Master to AMIS−30624
A
S = Start condition
P = Stop condition
A = Acknowledge (SDA = LOW)
A = No Acknowledge (SDA = HIGH)
AMIS−30624 to Master
Figure 30. Master Reading Data from AMIS−30622: Second Transmission is Reading Data
Notes:
1. Each byte is followed by an acknowledgment bit as indicated by the A or A in the sequence.
2. I2C−bus compatible devices must reset their bus logic on receipt of a START condition such that they all anticipate the sending of a
slave address, even if these START conditions are not positioned according to the proper format.
3. A START condition immediately followed by a STOP condition (void message) is an illegal format.
7−bit Addressing
The addressing procedure for the I2C−bus is such that the
first byte after the START condition usually determines
which slave will be selected by the master. The exception is
the general call address which can call all devices. When this
address is used all devices should respond with an
acknowledge. The second byte of the general call address
then defines the action to be taken.
AMIS−30622 is provided with a physical address in order
to discriminate this circuit from other circuits on the I2C bus.
This address is coded on seven bits (two bits being internally
hardwired to ‘1’), yielding the theoretical possibility of 32
different circuits on the same bus. It is a combination of four
OTP memory bits (OTP Memory Structure OPEN) and of
the externally hardwired address bits (pin HW). HW must
either be connected to ground or to Vbat. When HW is not
connected and is left floating, correct functionality of the
positioner is not guaranteed. The motor will be driven to the
programmed secure position (See Hardwired Address –
OPEN).
Definition of Bits in the First Byte
The first seven bits of the first byte make up the slave
address. The eighth bit is the least significant bit (LSB). It
determines the direction of the message. If the LSB is a
“zero” it means that the master will write information to a
selected slave. A “one” in this position means that the master
will read information from the slave. When an address is
sent, each device in a system compares the first seven bits
after the START condition with its address. If they match,
the device considers itself addressed by the master as a
slave−receiver or slave−transmitter, depending on the R/W
bit.
MSB
LSB
MSB
1
1
PA3 PA2 PA1 PA0 HW R/W
OTP memory
Hardwired Address Bit
Figure 32. First Byte after START Procedure
LSB
General Call Address
R/W
The AMIS−30622 supports also a “general call” address
“000 0000”, which can address all devices. When this
address is used all devices should respond with an
acknowledge. The second byte of the general call address
then defines the action to be taken.
SLAVE ADDRESS
Figure 31. First Byte after START Procedure
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AMIS−30622
I2C APPLICATION COMMANDS
Introduction
Communications between the AMIS−30622 and a 2−wire
serial bus interface master takes place via a large set of
commands.
Reading commands are used to:
♦ Get actual status information, e.g. error flags
♦ Get actual position of the stepper motor
♦ Verify the right programming and configuration of
the AMIS−30622.
Writing commands are used to:
♦ Program the OTP memory
♦ Configure the positioner with motion parameters
(max/min speed, acceleration, stepping mode, etc.)
♦ Provide target positions to the Stepper motor
The I2C−bus master will have to use commands to manage
the different application tasks the AMIS−30622 can feature.
The commands summary is given in Table 25.
Commands Table
Table 25. I2C COMMANDS WITH CORRESPONDING ROM POINTER
Command Byte
Command Mnemonic
Function
Binary
Hexadecimal
GetFullStatus1
Returns complete status of the chip
“1000 0001”
0x81
GetFullStatus2
Returns actual, target and secure position
“1111 1100”
0xFC
GetOTPParam
Returns OTP parameter
“1000 0010”
0x82
GotoSecurePosition
Drives motor to secure position
“1000 0100”
0x84
HardStop
Immediate full stop
“1000 0101”
0x85
ResetPosition
Sets actual position to zero
“1000 0110”
0x86
ResetToDefault
Overwrites the chip RAM with OTP contents
“1000 0111”
0x87
SetDualPosition
Drives the motor to two different positions with
different speed
“1000 1000”
0x88
SetMotorParam
Sets motor parameter
“1000 1001”
0x89
SetOTP
Zaps the OTP memory
“1001 0000”
0x90
SetPosition
Programs a target and secure position
“1000 1011”
0x8B
SoftStop
Motor stopping with deceleration phase
“1000 1111”
0x8F
These commands are described hereafter, with their
corresponding I2C frames. Refer to Data Transfer Formats
for more details. A color coding is used to distinguish
between master and slave parts within the frames. An
example is shown below.
Light Gray: Master Data
White: Slave Response
Figure 33. Color Code Used in the Definition of I2C Frames
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AMIS−30622
Application Commands
Note: A GetFullStatus1 command will attempt to
reset flags <TW>, <TSD>, <UV2>, <ElDef>,
<StepLoss>, <CPFail>, <OVC1>, <OVC2>, and
<VddReset>.
GetFullStatus1
This command is provided to the circuit by the master to
get a complete status of the circuit and of the stepper motor.
Refer to Tables 19 and 20 to see the meaning of the
parameters sent back to the I2C master.
GetFullStatus1 corresponds to the following I2C command frame:
Table 26. GetFullStatus1 COMMAND FRAME
Structure
Content
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
Address
1
1
OTP3
OTP2
OTP1
OTP0
HW
0
1
Command
1
0
0
0
0
0
0
1
Byte
Table 27. GetFullStatus1 RESPONSE FRAME
Structure
Byte
Content
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
Address
1
1
OTP3
OTP2
OTP1
OTP0
HW
1
1
Address
1
1
1
OTP3
OTP2
OTP1
OTP0
HW
2
Data 1
Irun[3:0]
Ihold[3:0]
3
Data 2
Vmax[3:0]
Vmin[3:0]
4
Data 3
AccShape
5
Data 4
VddReset
6
Data 5
7
Data 6
1
1
8
Data 7
1
1
Where:
OTP(n)
HW
Irun[3:0]
Ihold[3:0]
Vmax[3:0]
Vmin[3:0]
AccShape
StepMode[1:0]
Shaft
Acc[3:0]
VddReset
StepMode[1:0]
StepLoss
ElDef
Shaft
UV2
TSD
TW
ESW
OVC1
OVC2
1
CPFail
1
1
1
1
1
1
1
1
1
1
1
1
Motion[2:0]
StepLoss
ElDef
UV2
TSD
TW
Tinfo[1:0]
Motion[2:0]
ESW
OVC1
OVC2
CPFail
OTP address bits PA[3:0]
Hardwired address bit
Operating current in the motor coil
Standstill current in the motor coil
Maximum velocity
Minimum velocity
Enables motion without acceleration
Step mode definition
Direction of movement
Acceleration form minimum to
maximum velocity
Reset of digital supply
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Acc[3:0]
Tinfo[1:0]
Step loss occurred
Electrical defect
Battery under voltage detected
Thermal shutdown
Thermal warning
Temperature Info
Motion status
External switch status
Over current in X−coil detected
Over current in Y−coil detected
Charge pump failure
AMIS−30622
GetFullStatus2
stepping mode the LSBs of ActPos[15:0] and
TagPos[15:0] may have no meaning and should be
assumed to be ‘0’. This command also gives additional
information concerning stall detection. Refer to Tables 19
and 20 to see the meaning of the parameters sent back to the
I2C master.
This command is provided to the circuit by the master to
get the actual, target and secure position of the stepper
motor. Both the actual and target position are returned in
signed two’s complement 16−bit format. Secure position is
coded in 10−bit format. According to the programmed
GetFullStatus2 corresponds to the following I2C command frame:
Table 28. GetFullStatus2 COMMAND FRAME
Structure
Content
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
Address
1
1
OTP3
OTP2
OTP1
OTP0
HW
0
1
Command
1
1
1
1
1
1
0
0
Byte
Table 29. GetFullStatus2 RESPONSE FRAME
Structure
Byte
Content
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
Address
1
1
OTP3
OTP2
OTP1
OTP0
HW
1
1
Address
1
1
1
OTP3
OTP2
OTP1
OTP0
HW
2
Data 1
ActPos[15:8]
3
Data 2
ActPos[7:0]
4
Data 3
TagPos[15:8]
5
Data 4
TagPos[7:0]
6
Data 5
SecPos[7:0]
7
Data 6
1
1
1
1
1
8
Data 7
1
1
1
1
1
Where:
OTP(n)
HW
ActPos[15:0]
OTP address bits PA[3:0]
Hardwired address bit
Actual position
TagPos[15:0]
SecPos[10:0]
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SecPos[10:8]
1
Target position
Secure position
1
1
AMIS−30622
GetOTPParam
This command is provided to the circuit by the I2C master
to read the content of the OTP memory. More information
can be found in OTP Memory Structure corresponds to the
following I2C command frame:.
GetOTPParam
Table 30. GetOTPParam COMMAND FRAME
Structure
Byte
Content
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
Address
1
1
OTP3
OTP2
OTP1
OTP0
HW
0
1
Command
1
0
0
0
0
0
1
0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
OTP2
OTP1
OTP0
HW
1
Table 31. GetOTPParam RESPONSE FRAME
Structure
Content
Bit 7
Bit 6
Bit 5
0
Address
1
1
OTP3
1
OTP byte 0
OTP byte @0x00
2
OTP byte 1
OTP byte @0x01
3
OTP byte 2
OTP byte @0x02
4
OTP byte 3
OTP byte @0x03
5
OTP byte 4
OTP byte @0x04
6
OTP byte 5
OTP byte @0x05
7
OTP byte 6
OTP byte @0x06
8
OTP byte 7
OTP byte @0x07
Byte
the following I2C command frame: description for more
details. The priority encoder table also acknowledges the
cases where a GotoSecurePosition command will be
ignored.
GotoSecurePosition
This command is provided by the I2C master to one or all
the stepper motors to move to the secure position
SecPos[10:0]. See the priority encoder corresponds to
GotoSecurePosition
Table 32. GotoSecurePosition COMMAND FRAME
Structure
Byte
Content
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
Address
1
1
OTP3
OTP2
OTP1
OTP0
HW
0
1
Command
1
0
0
0
0
1
0
0
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AMIS−30622
HardStop
master at the next GetStatus1 command that steps may
have been lost. Once the motor is stopped, ActPos register
is copied into TagPos register to ensure keeping the stop
position. The I2C master for some safety reasons can also
issue a HardStop command.
This command will be internally triggered when an
electrical problem is detected in one or both coils, leading to
shutdown mode. If this occurs while the motor is moving,
the <StepLoss> flag is raised to allow warning of the I2C
HardStop corresponds to the following I2C command frame:
Table 33. HardStop COMMAND FRAME
Structure
Content
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
Address
1
1
OTP3
OTP2
OTP1
OTP0
HW
0
1
Command
1
0
0
0
0
1
0
1
Byte
ResetPosition
This command is provided to the circuit by the I2C master
to reset ActPos and TagPos registers to zero. This can be
helpful to prepare for instance a relative positioning.
ResetPosition corresponds to the following I2C command frame:
Table 34. ResetPosition COMMAND FRAME
Structure
Byte
Content
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
Address
1
1
OTP3
OTP2
OTP1
OTP0
HW
0
1
Command
1
0
0
0
0
1
1
0
Note: ActPos and TagPos are not modified by a
ResetToDefault command.
Important: Care should be taken not to send a
ResetToDefault command while a motion is ongoing,
since this could modify the motion parameters in a way
forbidden by the position controller.
ResetToDefault
This command is provided to the circuit by the I2C master
in order to reset the whole slave node into the initial state.
ResetToDefault will, for instance, overwrite the RAM
with the reset state of the registers parameters (see Table 19).
This is another way for the I2C master to initialize a slave
node in case of emergency, or simply to refresh the RAM
content.
ResetToDefault corresponds to the following I2C command frame:
Table 35. ResetToDefault COMMAND FRAME
Structure
Byte
Content
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
Address
1
1
OTP3
OTP2
OTP1
OTP0
HW
0
1
Command
1
0
0
0
0
1
1
1
RunVelocity
This command is provided to the circuit by the I2C master
in order to put the motor in continuous motion state.
RunVelocity corresponds to the following I2C command frame:
Table 36. RunVelocity COMMAND FRAME
Structure
Byte
Content
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
Address
1
1
OTP3
OTP2
OTP1
OTP0
HW
0
1
Command
1
0
0
1
0
1
1
1
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AMIS−30622
SetDualPosition
command is issued, the circuit will enter in deadlock state.
Therefore, the application should check the actual position
by a GetFullStatus2 corresponds to the following I2C
command frame command prior to starting a dual
positioning. Another solution may consist of programming
a value out of the stepper motor range for Pos1[15:0].
For the same reason Pos2[15:0] should not be equal to
Pos1[15:0].
This command is provided to the circuit by the I2C master
in order to perform a positioning of the motor using two
different velocities. See Section Dual Positioning.
Note: This sequence cannot be interrupted by another
positioning command.
Important: If for some reason ActPos equals
Pos1[15:0] at the moment the SetDualPosition
SetDualPosition
Table 37. SetDualPosition COMMAND FRAME
Structure
Content
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
Address
1
1
OTP3
OTP2
OTP1
OTP0
HW
0
1
Command
1
0
0
0
1
0
0
0
2
Data 1
1
1
1
1
1
1
1
1
3
Data 2
1
1
1
1
1
1
1
1
4
Data 3
5
Data 4
6
Data 5
Pos1[7:0]
7
Data 6
Pos2[15:8]
8
Data 7
Pos2[7:0]
Byte
Where:
Vmax[3:0]
Vmin[3:0]
Vmax[3:0]
Vmin[3:0]
Pos1[15:8]
Max. velocity for first motion
Min. velocity for first motion and
velocity for the second motion
Pos1[15:0]
Pos2[15:0]
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45
First position to be reached during the
first motion
Relative position of the second motion
AMIS−30622
SetMotorParam
This command is provided to the circuit by the I2C master
to set the values for the stepper motor parameters (listed
below) in RAM. Refer to Table 19 to see the meaning of the
parameters sent by the I2C master.
Important: If a SetMotorParam occurs while a motion
is ongoing, it will modify at once the motion parameters (see
Position Controller corresponds to the following I2C
command frame:). Therefore the application should not
change parameters other than Vmax while a motion is
running, otherwise correct positioning cannot be
guaranteed.
SetMotorParam
Table 38. SetMotorParam COMMAND FRAME
Structure
Byte
Content
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
Address
1
1
OTP3
OTP2
OTP1
OTP0
HW
0
1
Command
1
0
0
0
1
0
0
1
2
Data 1
1
1
1
1
1
1
1
1
3
Data 2
1
1
1
1
1
1
1
1
4
Data 3
Irun[3:0]
Ihold[3:0]
5
Data 4
Vmax[3:0]
Vmin[3:0]
6
Data 5
7
Data 6
8
Data 7
SecPos[10:8]
Shaft
Acc[3:0]
SecPos[7:0]
1
1
1
AccShape
StepMode[1:0]
1
1
SetOTPParam
This command is provided to the circuit by the I2C master
to program and zap the OTP data D[7:0] in OTP address
OTPA[2:0].
Important: This command must be sent under a specific
VBB voltage value. See parameter VBBOTP in Table 5. This
is a mandatory condition to ensure reliable zapping.
SetOTPParam corresponds to the following I2C command frame:
Table 39. SetOTPParam COMMAND FRAME
Structure
Byte
Content
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
Address
1
1
OTP3
OTP2
OTP1
OTP0
HW
0
1
Command
1
0
0
1
0
0
0
0
2
Data 1
1
1
1
1
1
1
1
1
3
Data 2
1
1
1
1
1
1
1
1
4
Data 3
1
1
1
1
1
5
Data 4
Where:
OTPA[2:0]:
D[7:0]:
D[7:0]
OTP address
Corresponding OTP data
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OTPA[2:0]
AMIS−30622
SetPosition
This command is provided to the circuit by the I2C master
to drive the motor to a given absolute position. See
Positioning (see Priority Encoder) for more details. The
priority encoder table acknowledges the cases where a
SetPosition command will be ignored.
SetPosition corresponds to the following I2C command frame:
Table 40. SetPosition COMMAND FRAME
Structure
Byte
Content
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
Address
1
1
OTP3
OTP2
OTP1
OTP0
HW
0
1
Command
1
0
0
0
1
0
1
1
2
Data 1
1
1
1
1
1
1
1
1
3
Data 2
1
1
1
1
1
1
1
1
4
Data 3
Pos[15:8]
5
Data 4
Pos[7:0]
Where:
Pos [15:0]
Signed 16−bit position set−point for motor.
SoftStop
This command will be internally triggered when the chip
temperature rises above the thermal shutdown threshold (see
Table 5 and the Temperature Management Section). It
provokes an immediate deceleration to Vmin (see
Minimum Velocity corresponds to the following I2C
command frame:) followed by a stop, regardless of the
position reached. Once the motor is stopped, TagPos
register is overwritten with value in ActPos register to
ensure keeping the stop position. The I2C Master for some
safety reasons can also issue a SoftStop command.
SoftStop
Table 41. SoftStop COMMAND FRAME
Structure
Byte
Content
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
Address
1
1
OTP3
OTP2
OTP1
OTP0
HW
0
1
Command
1
0
0
0
1
1
1
1
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AMIS−30622
PACKAGE DIMENSIONS
SOIC 20 W
CASE 751AQ
ISSUE O
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AMIS−30622
PACKAGE DIMENSIONS
NQFP−32, 7x7
CASE 560AA
ISSUE O
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AMIS−30622
NQFP−32, 7x7
CASE 560AA
ISSUE O
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AMIS−30622/D