Catalyst CAT25040S 1k/2k/4k spi serial cmos eeprom Datasheet

H
CAT25010/20/40
EE
GEN FR
ALO
1K/2K/4K SPI Serial CMOS EEPROM
LE
FEATURES
A D F R E ETM
■ 1,000,000 program/erase cycles
■ 10 MHz SPI compatible
■ 100 year data retention
■ 1.8 to 6.0 volt operation
■ Self-timed write cycle
■ Hardware and software protection
■ 8-Pin DIP/SOIC, 8-Pin TSSOP and 8-Pin MSOP
■ Low power CMOS technology
■ 16-byte page write buffer
■ SPI modes (0,0 & 1,1)*
■ Block write protection
■ Commercial, industrial, automotive and extended
– Protect 1/4, 1/2 or all of EEPROM array
temperature ranges
DESCRIPTION
The CAT25010/20/40 is a 1K/2K/4K Bit SPI Serial
CMOS EEPROM internally organized as 128x8/256x8/
512x8 bits. Catalyst’s advanced CMOS Technology
substantially reduces device power requirements. The
CAT25010/20/40 features a 16-byte page write buffer.
The device operates via the SPI bus serial interface and
is enabled though a Chip Select (CS). In addition to the
Chip Select, the clock input (SCK), data in (SI) and data
out (SO) are required to access the device. The HOLD
pin may be used to suspend any serial communication
without resetting the serial sequence. The CAT25010/
20/40 is designed with software and hardware write
protection features including Block Write protection. The
device is available in 8-pin DIP, 8-pin SOIC, 8-pin MSOP
and 8-pin TSSOP packages.
PIN CONFIGURATION
BLOCK DIAGRAM
SOIC Package (S, V)
CS
1
8
SO
2
3
4
7
6
5
WP
VSS
MSOP Package (R, Z)*
SI
8
7
6
5
VCC
SENSE AMPS
SHIFT REGISTERS
HOLD
SCK
SI
VCC
HOLD
SCK
SI
WORD ADDRESS
BUFFERS
TSSOP Package (U, Y)
CS
SO
WP
VSS
1
2
3
8
7
6
4
5
VCC
HOLD
SCK
SI
SO
SI
CS
WP
HOLD
SCK
PIN FUNCTIONS
Pin Name
Function
SO
Serial Data Output
SCK
Serial Clock
WP
Write Protect
VCC
+1.8V to +6.0V Power Supply
VSS
Ground
CS
Chip Select
SI
Serial Data Input
HOLD
Suspends Serial Input
NC
No Connect
© 2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
I/O
CONTROL
SPI
CONTROL
LOGIC
BLOCK
PROTECT
LOGIC
CONTROL LOGIC
1
2
3
4
8
7
6
5
*CAT 25010/20 only
DIP Package (P, L)
CS
SO
WP
VSS
1
2
3
4
CS
SO
WP
VSS
VCC
HOLD
SCK
XDEC
COLUMN
DECODERS
E2PROM
ARRAY
DATA IN
STORAGE
HIGH VOLTAGE/
TIMING CONTROL
STATUS
REGISTER
25C128 F02
* Other SPI modes available on request.
1
Doc. No. 1006, Rev. L
CAT25010/20/40
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature Under Bias ................. –55°C to +125°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum
rating for extended periods may affect device performance and reliability.
Storage Temperature ....................... –65°C to +150°C
Voltage on any Pin with
Respect to VSS(1) .................. –2.0V to +VCC +2.0V
VCC with Respect to VSS ................................ –2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(2) ........................ 100 mA
RELIABILITY CHARACTERISTICS
Symbol
Units
Reference Test Method
1,000,000
Cycles/Byte
MIL-STD-883, Test Method 1033
Data Retention
100
Years
MIL-STD-883, Test Method 1008
VZAP
ESD Susceptibility
2000
Volts
MIL-STD-883, Test Method 3015
ILTH(3)(4)
Latch-Up
100
mA
NEND
(3)
TDR(3)
(3)
Parameter
Endurance
Min.
Max.
JEDEC Standard 17
D.C. OPERATING CHARACTERISTICS
VCC = +1.8V to +6.0V, unless otherwise specified.
Limits
Symbol
Parameter
Min.
Typ.
Max.
Units
Test Conditions
ICC1
Power Supply Current
(Operating Write)
5
mA
VCC = 5V @ 5MHz
SO=open; CS=Vss
ICC2
Power Supply Current
(Operating Read)
3
mA
VCC = 5.5V
FCLK = 5MHz
ISB(6)
Power Supply Current
(Standby)
1
µA
CS = VCC
VIN = VSS or VCC
ILI
Input Leakage Current
2
µA
VIN = VSS or VCC
ILO
Output Leakage Current
3
µA
VOUT = 0V to VCC,
CS = 0V
VIL(5)
Input Low Voltage
-1
VCC x 0.3
V
VIH(5)
Input High Voltage
VCC x 0.7
VCC + 0.5
V
VOL1
Output Low Voltage
0.4
V
VOH1
Output High Voltage
VOL2
Output Low Voltage
VOH2
Output High Voltage
VCC - 0.8
V
0.2
VCC-0.2
2.7V≤VCC<5.5V
IOL = 3.0mA
IOH = -1.6mA
V
1.8V≤VCC<2.7V
V
IOL = 150µA
IOH = -100µA
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.
(5) VIL min and VIH max are reference values only and are not tested.
(6) Maximum standby current (ISB ) = 10µA for the Automotive and Extended Automotive temperature range.
Doc. No. 1006, Rev. L
2
CAT25010/20/40
PIN CAPACITANCE (1)
Applicable over recommended operating range from TA=25˚C, f=1.0 MHz, VCC=+5.0V.
Symbol
Test Conditions
Max.
Units
Conditions
COUT
Output Capacitance (SO)
8
pF
VOUT=0V
CIN
Input Capacitance (CS, SCK, SI, WP, HOLD)
6
pF
VIN=0V
A.C. CHARACTERISTICS
Limits
1.8V-6.0V
SYMBOL PARAMETER
Min.
2.5V-6.0V
Max. Min.
Max.
4.5V-5.5V
Min.
Max.
Test
UNITS Conditions
tSU
Data Setup Time
50
20
20
ns
VIH = 2.4V
tH
Data Hold Time
50
20
20
ns
CL = 100pF
tWH
SCK High Time
250
75
40
ns
VOL = 0.8V
tWL
SCK Low Time
250
75
40
ns
VOH = 2.0v
fSCK
Clock Frequency
DC
tLZ
HOLD to Output Low Z
50
tRI(1)
Input Rise Time
tFI(1)
Input Fall Time
tHD
HOLD Setup Time
100
40
40
ns
tCD
HOLD Hold Time
100
40
40
ns
CC
L L==100pF
50pF
tWC(3)
Write Cycle Time
(note 2)
tV
Output Valid from Clock Low
tHO
Output Hold Time
tDIS
Output Disable Time
250
75
75
ns
tHZ
HOLD to Output High Z
150
50
50
ns
tCS
CS High Time
500
100
100
ns
tCSS
CS Setup Time
500
100
100
ns
tCSH
CS Hold Time
500
100
100
ns
tWPS
WP Setup Time
150
50
50
ns
tWPH
WP Hold Time
150
50
50
ns
1
DC
5
DC
10
MHz
50
50
ns
2
2
2
µs
2
2
2
µs
5
5
5
ms
250
75
40
ns
0
0
0
ns
NOTE:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) AC Test Conditions:
Input Pulse Voltages: 0.3VCC to 0.7VCC
Input rise and fall times: ≤10ns
Input and output reference voltages: 0.5VCC
Output load: current source IOL max/IOH max; CL=50pF
(3) tWC is the time from the rising edge of CS after a valid write sequence to the end of the internal write cycle.
3
Doc. No. 1006, Rev. L
CAT25010/20/40
the operation to be performed.
FUNCTIONAL DESCRIPTION
The CAT25010/20/40 supports the SPI bus data
transmission protocol. The synchronous Serial Peripheral
Interface (SPI) helps the CAT25010/20/40 to interface
directly with many of today’s popular microcontrollers.
The CAT25010/20/40 contains an 8-bit instruction
register. (The instruction set and the operation codes
are detailed in the instruction set table)
PIN DESCRIPTION
SI: Serial Input
SI is the serial data input pin. This pin is used to input all
opcodes, byte addresses, and data to be written to the
CAT25010/20/40. Input data is latched on the rising
edge of the serial clock for SPI modes (0, 0 & 1, 1).
After the device is selected with CS going low, the first
byte will be received. The part is accessed via the SI pin,
with data being clocked in on the rising edge of SCK.
The first byte contains one of the six op-codes that define
SO: Serial Output
SO is the serial data output pin. This pin is used to
transfer data out of the CAT25010/20/40. During a read
cycle, data is shifted out on the falling edge of the serial
Figure 1. Sychronous Data Timing
tCS
VIH
CS
VIL
tCSH
tCSS
VIH
tWL
tWH
SCK
VIL
tH
tSU
VIH
VALID IN
SI
VIL
tRI
tFI
tV
VOH
SO
tHO
tDIS
HI-Z
HI-Z
VOL
Note: Dashed Line= mode (1, 1) – – – – –
INSTRUCTION SET
Instruction
Opcode
Operation
WREN
0000 0110
Enable Write Operations
WRDI
0000 0100
Disable Write Operations
RDSR
0000 0101
Read Status Register
WRSR
0000 0001
Write Status Register
READ
0000 X011(1)
Read Data from Memory
WRITE
0000 X010(1)
Write Data to Memory
Power-Up Timing(2)(3)
Symbol
Parameter
Max.
Units
tPUR
Power-up to Read Operation
1
ms
tPUW
Power-up to Write Operation
1
ms
Note:
(1) X=0 for 25010, 25020. X=A8 for 25040
(2) This parameter is tested initially and after a design or process change that affects the parameter.
(3) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
Doc. No. 1006, Rev. L
4
CAT25010/20/40
SCK: Serial Clock
SCK is the serial clock pin. This pin is used to synchronize
the communication between the microcontroller and the
CAT25010/20/40. Opcodes, byte addresses, or data
present on the SI pin are latched on the rising edge of the
SCK. Data on the SO pin is updated on the falling edge
of the SCK for SPI modes (0,0 & 1,1) .
WP
WP: Write Protect
WP is the Write Protect pin. The Write Protect pin will
allow normal read/write operations when held high.
When WP is tied low all write operations are inhibited.
WP held low while CS is low will interrupt a write to the
CAT25010/20/40. If the internal write cycle has already
been initiated, WP going low will have no effect on any
write operation. Figure 10 illustrates the WP timing
sequence during a write operation.
CS
CS: Chip Select
HOLD
HOLD: Hold
CS is the Chip select pin. CS low enables the CAT25010/
20/40 and CS high disables the CAT25010/20/40. CS
high takes the SO output pin to high impedance and
forces the devices into a Standby Mode (unless an
internal write operation is underway) The CAT25010/
20/40 draws ZERO current in the Standby mode. A high
to low transition on CS is required prior to any sequence
being initiated. A low to high transition on CS after a valid
write sequence is what initiates an internal write cycle.
The HOLD pin is used to pause transmission to the
CAT25010/20/40 while in the middle of a serial sequence
without having to re-transmit entire sequence at a later
time. To pause, HOLD must be brought low while SCK
is low. The SO pin is in a high impedance state during
the time the part is paused, and transitions on the SI pins
will be ignored. To resume communication, HOLD is
brought high, while SCK is low. (HOLD should be held
high any time this function is not being used.) HOLD may
be tied high directly to VCC or tied to VCC through a
resistor. Figure 9 illustrates hold timing sequence.
clock for SPI modes (0,0 & 1,1).
STATUS REGISTER
7
6
5
4
3
2
1
0
1
1
1
1
BP1
BP0
WEL
RDY
BLOCK PROTECTION BITS
Status Register Bits
BP1
BP0
Array Address
Protected
Protection
0
0
None
No Protection
0
1
25010: 60-7F
25020: C0-FF
25040: 180-1FF
Quarter Array Protection
1
0
25010: 40-7F
25020: 80-FF
25040: 100-1FF
Half Array Protection
1
1
25010: 00-7F
25020: 00-FF
25040: 000-1FF
Full Array Protection
5
Doc. No. 1006, Rev. L
CAT25010/20/40
STATUS REGISTER
DEVICE OPERATION
The Status Register indicates the status of the device.
The RDY (Ready) bit indicates whether the CAT25010/
20/40 is busy with a write operation. When set to 1 a
write cycle is in progress and when set to 0 the device
indicates it is ready. This bit is read only. The WEL (Write
Enable) bit indicates the status of the write enable latch.
When set to 1, the device is in a Write Enable state and
when set to 0 the device is in a Write Disable state. The
WEL bit can only be set by the WREN instruction and can
be reset by the WRDI instruction.
Write Enable and Disable
The CAT25010/20/40 contains a write enable latch. This
latch must be set before any write operation. The device
powers up in a write disable state when Vcc is applied.
WREN instruction will enable writes (set the latch) to the
device. If WP pin is held low, the write enable latch is
reset to the write disabe state, regardless of the WREN
Instruction. WRDI instruction will disable writes (reset
the latch) to the device. Disabling writes will protect the
device against inadvertent writes.
The BP0 and BP1 (Block Protect) bits indicate which
blocks are currently protected. These bits are set by the
user issuing the WRSR instruction. The user is allowed
to protect quarter of the memory, half of the memory or
the entire memory by setting these bits. Once protected,
the user may only read from the protected portion of the
array. These bits are non-volatile.
READ Sequence
The part is selected by pulling CS low. The 8-bit read
instruction is transmitted to the CAT25010/20/40, followed
by the 8-bit address for CAT25010/20/40 (for the 25040,
bit 3 of the read data instruction contains address A8).
After the correct read instruction and address are sent,
the data stored in the memory at the selected address is
shifted out on the SO pin. The data stored in the memory
at the next address can be read sequentially by continuing
Figure 2. WREN Instruction Timing
CS
SK
SI
0
0
0
0
1
0
1
0
HIGH IMPEDANCE
SO
Note: Dashed Line= mode (1, 1) – – – – –
Figure 3. WRDI Instruction Timing
CS
SK
SI
SO
0
0
0
0
0
0
HIGH IMPEDANCE
Note: Dashed Line= mode (1, 1) – – – – –
Doc. No. 1006, Rev. L
1
6
0
CAT25010/20/40
to provide clock pulses. The internal address pointer is
automatically incremented to the next higher address
after each byte of data is shifted out. When the highest
address is reached, the address counter rolls over to
0000h allowing the read cycle to be continued indefinitely.
The read operation is terminated by pulling the CS high.
To read the status register, RDSR instruction should be
sent. The contents of the status register are shifted out
on the SO line. The status register may be read at any
time even during a write cycle. Read sequece is
illustrated in Figure 4. Reading status register is illustrated
in Figure 5.
WRITE Sequence
The CAT25010/20/40 powers up in a Write Disable
state. Prior to any write instructions, the WREN instruction
must be sent to CAT25010/20/40. The device goes into
Write enable state by pulling the CS low and then
clocking the WREN instruction into CAT25010/20/40.
The CS must be brought high after the WREN instruction
to enable writes to the device. If the write operation is
initiated immediately after the WREN instruction without
CS being brought high, the data will not be written to the
Figure 4. Read Instruction Timing
CS
0
1
2
3
4
5
6
7
8
9
10
20
21
22
23
24
25
26
27
28
29
30
2
1
SK
OPCODE
SI
0
0
0
0
0
0
1
BYTE ADDRESS*
1
DATA OUT
HIGH IMPEDANCE
SO
7
6
5
4
3
0
MSB
*Please check the instruction set table for address
Figure 5. RDSR Instruction Timing
CS
0
1
2
3
4
5
6
7
1
0
1
8
9
10
11
7
6
5
4
12
13
14
2
1
SCK
OPCODE
SI
0
0
0
0
0
DATA OUT
SO
HIGH IMPEDANCE
3
0
MSB
Note: Dashed Line= mode (1, 1) – – – – –
7
Doc. No. 1006, Rev. L
CAT25010/20/40
device is ready for the next instruction
array because the write enable latch will not have been
properly set. Also, for a successful write operation the
address of the memory location(s) to be programmed
must be outside the protected address field location
selected by the block protection level.
Page Write
The CAT25010/20/40 features page write capability.
After the initial byte, the host may continue to write up to
16 bytes of data to the CAT25010/20/40. After each
byte of data received, lower order address bits are
internally incremented by one; the high order bits of
address will remain constant. The only restriction is that
the X (X=16 for CAT25010/20/40) bytes must reside on
the same page. If the address counter reaches the end
of the page and clock continues, the counter will “roll
over” to the first address of the page and overwrite any
data that may have been written. The CAT25010/20/40
is automatically returned to the write disable state at the
completion of the write cycle. Figure 8 illustrates the
page write sequence.
Byte Write
Once the device is in a Write Enable state, the user may
proceed with a write sequence by setting the CS low,
issuing a write instruction via the SI line, followed by the
8-bit address for 25010/20/40 (for the 25040, bit 3 of the
read data instruction contains address A8). Programming
will start after the CS is brought high. Figure 6 illustrates
byte write sequence.
During an internal write cycle, all commands will be
ignored except the RDSR (Read Status Register)
instruction.
To write to the status register, the WRSR instruction
should be sent. Only Bit 2 and Bit 3 of the status register
can be written using the WRSR instruction. Figure 7
illustrates the sequence of writing to status register.
The Status Register can be read to determine if the write
cycle is still in progress. If Bit 0 of the Status Register is
set at 1, write cycle is in progress. If Bit 0 is set at 0, the
Figure 6. Write Instruction Timing
CS
0
1
2
3
4
5
6
7
8
21
22
23
24
25
26
27
28
29
30
31
SK
OPCODE
0
SI
0
0
0
0
DATA IN
0
1
0
D7 D6 D5 D4 D3 D2 D1 D0
ADDRESS
HIGH IMPEDANCE
SO
Note: Dashed Line= mode (1, 1) – – – – –
*X=0 for 25010, 25020 ; X=A8 for 25040
Figure 7. WRSR Timing
CS
0
1
2
3
4
5
6
7
8
9
10
11
1
7
6
5
4
12
13
14
15
2
1
0
SCK
OPCODE
SI
0
0
0
0
0
DATA IN
0
0
MSB
SO
HIGH IMPEDANCE
Note: Dashed Line= mode (1, 1) – – – – –
Doc. No. 1006, Rev. L
8
3
CAT25010/20/40
DESIGN CONSIDERATIONS
The CAT250140/20/40 powers up in a write disable
state and in a low power standby mode. A WREN
instruction must be issued to perform any writes to the
device after power up. Also,on power up CS should be
brought low to enter a ready state and receive an
instruction. After a successful byte/page write or status
register write, the CAT250140/20/40 goes into a write
disable mode. CS must be set high after the proper
number of clock cycles to start an internal write cycle.
Access to the array during an internal write cycle is
ignored and programming is continued. On power up,
SO is in a high impedance. If an invalid op code is
received, no data will be shifted into the CAT250140/
20/40, and the serial output pin (SO) will remain in a
high impedance state until the falling edge of CS is
detected again.
When powering down, the supply should be taken down
to 0V, so that the CAT250140/20/40 will be reset when
power is ramped back up. If this is not possible, then,
following a brown-out episode, the CAT250140/20/40
can be reset by refreshing the contents of the Status
Register (See Application Note AN10).
Figure 8. Page Write Instruction Timing
CS
0
1
2
3
4
5
6
7
8
13
14
15 16-23
24-31
16+(N-1)x8-1..16+(N-1)x8 16+Nx8-1
SK
SI
0
0
0
0
0
X*
DATA IN
BYTE ADDRESS
OPCODE
0
1
0
A7
A0
Data
Byte 1
Data
Byte 2
Data
Byte 3
Data Byte N
0
7..1
HIGH IMPEDANCE
SO
Note: Dashed Line= mode (1, 1) – – – – –
*X=0 for 25010, 25020 ; X=A8 for 25040
Figure 9. HOLD Timing
CS
tCD
tCD
SCK
tHD
tHD
HOLD
tHZ
HIGH IMPEDANCE
SO
tLZ
Note: Dashed Line= mode (1, 1) – – – – –
9
Doc. No. 1006, Rev. L
CAT25010/20/40
Figure 10. WP Timing
t WPS
t WPH
CS
SCK
WP
WP
Note: Dashed Line= mode (1, 1) – – – – –
ORDERING INFORMATION
Prefix
CAT
Optional
Company ID
Device #
Suffix
25040
Product
Number
25040: 4K
25020: 2K
25010: 1K
-1.8
I
S
Temperature Range
Blank = Commercial (0°C to +70°C)
I = Industrial (-40°C to +85°C)
A = Automotive (-40°C to +105°C)
E = Extended (-40°C to +125°C)
Package
P = 8-pin PDIP
R = 8-pin MSOP2
S = 8-pin SOIC
U = 8-pin TSSOP
L = PDIP (Lead free, Halogen free)
V = SOIC, JEDEC (Lead free, Halogen free)
Y = TSSOP (Lead free, Halogen free)
Z = MSOP2 (Lead free, Halogen free)
TE13
Tape & Reel
TE13: 2000/Reel
Operating Voltage
Blank (Vcc=2.5 to 6.0V)
1.8 (Vcc=1.8 to 6.0V)
Notes:
(1) The device used in the above example is a 25040SI-1.8TE13 (SOIC, Industrial Temperature, 1.8 Volt to 6 Volt Operating Voltage,
Tape & Reel)
(2) CAT25010, CAT25020 only
Doc. No. 1006, Rev. L
10
CAT25010/20/40
REVISION HISTORY
Date
Rev.
Reason
8/3/2004
L
Updated Features
Updated DC Operating Characteristics table & notes
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Publication #:
Revison:
Issue date:
11
1006
L
8/3/04
Doc. No. 1006, Rev. L