18-Bit, 2.5 LSB INL, 800 kSPS SAR ADC AD7674 FEATURES 18-bit resolution with no missing codes No pipeline delay (SAR architecture) Differential input range: ±VREF (VREF up to 5 V) Throughput: 800 kSPS (Warp mode) 666 kSPS (Normal mode) 570 kSPS (Impulse mode) INL: ±2.5 LSB max (±9.5 ppm of full scale) Dynamic range : 103 dB typ (VREF = 5 V) S/(N+D): 100 dB typ @ 2 kHz (VREF = 5 V) Parallel (18-,16-, or 8-bit bus) and serial 5 V/3 V interface SPI®/QSPI™/MICROWIRE™/DSP compatible On-board reference buffer Single 5 V supply operation Power dissipation: 98 mW typ @ 800 kSPS 78 mW typ@ 500 kSPS (Impulse mode) 160 µW @ 1 kSPS (Impulse mode) 48-lead LQFP or 48-lead LFCSP package Pin-to-pin compatible upgrade of AD7676/AD7678/AD7679 APPLICATIONS CT scanners High dynamic data acquisition Geophone and hydrophone sensors Σ-∆ replacement (low power, multichannel) Instrumentation Spectrum analysis Medical instruments GENERAL DESCRIPTION The AD7674 is an 18-bit, 800 kSPS, charge redistribution SAR, fully differential analog-to-digital converter that operates on a single 5 V power supply. The part contains a high speed 18-bit sampling ADC, an internal conversion clock, an internal reference buffer, error correction circuits, and both serial and parallel system interface ports. The part is available in 48-lead LQFP or 48-lead LFCSP packages with operation specified from –40°C to +85°C. FUNCTIONAL BLOCK DIAGRAM PDBUF REF REFGND AGND AVDD IN– OVDD AD7674 OGND SERIAL PORT REFBUFIN IN+ DVDD DGND 18 SWITCHED CAP DAC BUSY PARALLEL INTERFACE CLOCK PD RESET D[17:0] RD CS CONTROL LOGIC AND CALIBRATION CIRCUITRY MODE0 MODE1 WARP IMPULSE CNVST 03083–0–001 Figure 1. Functional Block Diagram Table 1. PulSARTM Selection Type/kSPS PseudoDifferential True Bipolar True Differential 18-Bit Multichannel/ Simultaneous 100–250 AD7651 AD7660/AD7661 AD7663 AD7675 500–570 AD7650/AD7652 AD7664/AD7666 AD7665 AD7676 AD7678 AD7679 AD7654 AD7655 800– 1000 AD7653 AD7667 AD7671 AD7677 AD7674 PRODUCT HIGHLIGHTS 1. High Resolution, Fast Throughput. The AD7674 is an 800 kSPS, charge redistribution, 18-bit SAR ADC (no latency). 2. Excellent Accuracy. The AD7674 has a maximum integral nonlinearity of 2.5 LSB with no missing 18-bit codes. 3. Serial or Parallel Interface. Versatile parallel (18-, 16- or 8-bit bus) or 3-wire serial interface arrangement compatible with both 3 V and 5 V logic. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2003 Analog Devices, Inc. All rights reserved. AD7674 TABLE OF CONTENTS Specifications..................................................................................... 3 Digital Interface .......................................................................... 21 Timing Specifications....................................................................... 5 Parallel Interface......................................................................... 21 Absolute Maximum Ratings............................................................ 7 Serial Interface ............................................................................ 21 Pin Configuration and Function Descriptions............................. 8 Master Serial Interface............................................................... 22 Definitions of Specifications ......................................................... 11 Slave Serial Interface .................................................................. 23 Typical Performance Characteristics ........................................... 12 Microprocessor Interfacing....................................................... 25 Circuit Information ........................................................................ 16 Application Hints ........................................................................... 26 Converter Operation.................................................................. 16 Layout .......................................................................................... 26 Typical Connection Diagram ................................................... 18 Evaluating the AD7674’s Performance .................................... 26 Power Dissipation versus Throughput .................................... 20 Outline Dimensions ....................................................................... 27 Conversion Control.................................................................... 20 Ordering Guide .......................................................................... 27 REVISION HISTORY Revision 0: Initial Version Rev. 0 | Page 2 of 28 AD7674 SPECIFICATIONS Table 2. –40°C to +85°C, VREF = 4.096 V, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted. Parameter RESOLUTION ANALOG INPUT Voltage Range Operating Input Voltage Analog Input CMRR Input Current Input Impedance1 THROUGHPUT SPEED Complete Cycle Throughput Rate Time between Conversions Complete Cycle Throughput Rate Complete Cycle Throughput Rate DC ACCURACY Integral Linearity Error Differential Linearity Error No Missing Codes Transition Noise Zero Error, TMIN to TMAX3 Zero Error Temperature Drift Gain Error, TMIN to TMAX3 Gain Error Temperature Drift Zero Error, TMIN to TMAX3 Gain Error, TMIN to TMAX3 Power Supply Sensitivity AC ACCURACY Signal-to-Noise Dynamic Range Spurious-Free Dynamic Range Total Harmonic Distortion Signal-to-(Noise + Distortion) –3 dB Input Bandwidth SAMPLING DYNAMICS Aperture Delay Aperture Jitter Transient Response Overvoltage Recovery Conditions Min 18 VIN+ – VIN– VIN+, VIN– to AGND fIN = 100 kHz 800 kSPS Throughput –VREF –0.1 In Warp Mode In Warp Mode In Warp Mode In Normal Mode In Normal Mode In Impulse Mode In Impulse Mode Typ fIN = 2 kHz, VREF = 5 V VREF = 4.096 V fIN = 10 kHz, VREF = 4.096 V fIN = 100 kHz, VREF = 4.096 V VIN+ = VIN– = VREF/2 = 2.5 V fIN = 2 kHz fIN = 10 kHz fIN = 100 kHz fIN = 2 kHz fIN = 10 kHz fIN = 100 kHz fIN = 2 kHz, VREF = 4.096 V fIN = 2 kHz, –60 dB Input Full-Scale Step Rev. 0 | Page 3 of 28 Unit Bits +VREF AVDD V V dB µA 1.25 800 1 1.5 666 1.75 570 µs kSPS ms µs kSPS µs kSPS +2.5 +1.75 LSB2 LSB Bits LSB LSB ppm/°C % of FSR ppm/°C LSB % of FSR LSB 65 100 1 0 0 –2.5 –1 18 VREF = 5 V In Warp Mode All Modes In Warp Mode All Modes Normal or Impulse Mode3 Normal or Impulse Mode3 AVDD = 5 V ± 5% Max 0.7 –25 +25 ±0.5 –0.034 –85 –0.048 97.5 +0.034 ±1.6 See Note 3 See Note 3 ±4 +85 +0.048 101 99 98 97 103 120 118 105 –115 –113 –98 98 40 26 dB4 dB dB dB dB dB dB dB dB dB dB dB dB MHz 2 5 ns ps rms ns ns 250 250 AD7674 Parameter REFERENCE External Reference Voltage Range REF Voltage with Reference Buffer Reference Buffer Input Voltage Range REFBUFIN Input Current REF Current Drain DIGITAL INPUTS Logic Levels VIL VIH IIL IIH DIGITAL OUTPUTS Data Format5 Pipeline Delay6 VOL VOH POWER SUPPLIES Specified Performance AVDD DVDD OVDD Operating Current8 AVDD DVDD9 OVDD9 POWER DISSIPATION9 TEMPERATURE RANGE11 Specified Performance Conditions Min Typ Max Unit REF REFBUFIN = 2.5 V REFBUFIN 3 4.05 1.8 –1 4.096 4.096 2.5 AVDD + 0.1 4.15 2.6 +1 V V V µA µA +0.8 DVDD + 0.3 +1 +1 V V µA µA 0.4 V V 5.25 5.25 DVDD + 0.37 V V V 90 126 138 mA mA µA mW µW mW mW +85 °C 800 kSPS Throughput 330 –0.3 +2.0 –1 –1 ISINK = 1.6 mA ISOURCE = –500 µA OVDD – 0.6 4.75 4.75 2.7 5 5 800 kSPS Throughput 16 6.5 50 78 160 114 126 PDBUF High @ 500 kSPS10 PDBUF High @ 1 kSPS10 PDBUF High @ 800 kSPS8 PDBUF Low @ 800 kSPS8 TMIN to TMAX 1 –40 See Analog Inputs section. LSB means Least Significant Bit. With the ±4.096 V input range, 1 LSB is 31.25 µV. 3 See Definitions of Specifications section. These parameters are centered on nominal values, which depend on the mode. In Warp mode, nominal zero error and nominal gain error are centered around 0 LSB. In Normal and Impulse modes, nominal zero error is +375 LSB, and nominal gain error is +0.273% of FSR. These specifications are the deviation from these nominal values. These specifications do not include the error contribution from the external reference but do include the error contribution from the reference buffer, if used. 4 All specifications in dB are referred to a full-scale input, FS. Tested with an input signal at 0.5 dB below full scale unless otherwise specified. 5 Data Format Parallel or Serial 18-Bit. 6 Conversion results are available immediately after completed conversion. 7 The max should be the minimum of 5.25 V and DVDD + 0.3 V. 8 In Warp mode. 9 Tested in Parallel Reading mode. 10 In Impulse mode. 11 Contact factory for extended temperature range. 2 Rev. 0 | Page 4 of 28 AD7674 TIMING SPECIFICATIONS Table 3. –40°C to +85°C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted. Parameter Refer to Figure 34 and Figure 35 Convert Pulsewidth Time between Conversions (Warp Mode/Normal Mode/Impulse Mode)1 CNVST LOW to BUSY HIGH Delay BUSY HIGH All Modes Except Master Serial Read after Convert (Warp Mode/Normal Mode/Impulse Mode) Aperture Delay End of Conversion to BUSY LOW Delay Conversion Time (Warp Mode/Normal Mode/Impulse Mode) Acquisition Time RESET Pulsewidth Refer to Figure 36, Figure 37, and Figure 38 (Parallel Interface Modes) CNVST LOW to Data Valid Delay (Warp Mode/Normal Mode/Impulse Mode) Data Valid to BUSY LOW Delay Bus Access Request to Data Valid Bus Relinquish Time Refer to Figure 40 and Figure 41 (Master Serial Interface Modes) 2 CS LOW to SYNC Valid Delay CS LOW to Internal SCLK Valid Delay CS LOW to SDOUT Delay CNVST LOW to SYNC Delay (Warp Mode/Normal Mode/Impulse Mode) SYNC Asserted to SCLK First Edge Delay3 Internal SCLK Period3 Internal SCLK HIGH3 Internal SCLK LOW3 SDOUT Valid Setup Time3 SDOUT Valid Hold Time3 SCLK Last Edge to SYNC Delay3 CS HIGH to SYNC HI-Z CS HIGH to Internal SCLK HI-Z CS HIGH to SDOUT HI-Z BUSY HIGH in Master Serial Read after Convert3 CNVST LOW to SYNC Asserted Delay (Warp Mode/Normal Mode/Impulse Mode) SYNC Deasserted to BUSY LOW Delay Refer to Figure 42 and Figure 43 (Slave Serial Interface Modes) External SCLK Setup Time External SCLK Active Edge to SDOUT Delay SDIN Setup Time SDIN Hold Time External SCLK Period External SCLK HIGH External SCLK LOW 1 Symbol Min t1 t2 t3 10 1.25/1.5/1.75 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 t26 t27 t28 Max Unit 35 ns µs ns 1/1.25/1.5 2 10 1/1.25/1.5 250 10 1/1.25/1.5 20 45 15 5 10 10 10 25/275/525 3 25 12 7 4 2 3 40 10 10 10 1/1.25/1.5 25 Rev. 0 | Page 5 of 28 µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 5 3 5 5 25 10 10 µs ns 18 In Warp mode only, the maximum time between conversions is 1 ms; otherwise, there is no required maximum time. In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum. 3 In Serial Master Read during Convert mode. See Table 4 for Serial Master Read after Convert mode. 2 µs ns ns µs ns ns Table 4 t29 t30 t31 t32 t33 t34 t35 t36 t37 Typ ns ns ns ns ns ns ns AD7674 Table 4. Serial Clock Timings in Master Read after Convert DIVSCLK[1] DIVSCLK[0] SYNC to SCLK First Edge Delay Minimum Internal SCLK Period Minimum Internal SCLK Period Maximum Internal SCLK HIGH Minimum Internal SCLK LOW Minimum SDOUT Valid Setup Time Minimum SDOUT Valid Hold Time Minimum SCLK Last Edge to SYNC Delay Minimum Busy High Width Maximum (Warp) Busy High Width Maximum (Normal) Busy High Width Maximum (Impulse) Symbol t18 t19 t19 t20 t21 t22 t23 t24 t28 t28 t28 0 0 3 25 40 12 7 4 2 3 1.75 2 2.25 Rev. 0 | Page 6 of 28 0 1 17 60 80 22 21 18 4 60 2.5 2.75 3 1 0 17 120 160 50 49 18 30 140 4 4.25 4.5 1 1 17 240 320 100 99 18 89 300 7 7.25 7.5 Unit ns ns ns ns ns ns ns ns µs µs µs AD7674 ABSOLUTE MAXIMUM RATINGS Table 5. AD7674 Absolute Maximum Ratings1 Parameter Analog Inputs IN+2, IN–2, REF, REFBUFIN, REFGND to AGND Ground Voltage Differences AGND, DGND, OGND Supply Voltages AVDD, DVDD, OVDD AVDD to DVDD, AVDD to OVDD DVDD to OVDD Digital Inputs Internal Power Dissipation3 Internal Power Dissipation4 Junction Temperature Storage Temperature Range Lead Temperature Range (Soldering 10 sec) Rating 1.6mA AGND – 0.3 V to AVDD + 0.3 V IOL TO OUTPUT PIN 1.4V CL 60pF1 ±0.3 V 500µA –0.3 V to +7 V ±7 V –0.3 V to +7 V –0.3 V to DVDD + 0.3 V 700 mW 2.5 W 150°C –65°C to +150°C IOH NOTE 1 IN SERIAL INTERFACE MODES,THE SYNC, SCLK, AND SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD CL OF 10pF; OTHERWISE,THE LOAD IS 60pF MAXIMUM. 03083–0–002 Figure 2. Load Circuit for Digital Interface Timing, SDOUT, SYNC, SCLK Outputs, CL = 10 pF 2V 0.8V tDELAY 300°C tDELAY 2V 0.8V 2V 0.8V 03083–0–003 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 See Analog Input section. 3 Specification is for device in free air: 48-Lead LQFP: θJA = 91°C/W, θJC = 30°C/W. 4 Specification is for device in free air: 48-Lead LFCSP: θJA = 26°C/W. Rev. 0 | Page 7 of 28 Figure 3. Voltage Reference Levels for Timing AD7674 REFGND REF NC NC IN– IN+ NC NC AGND AVDD REFBUFIN PDBUF PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 48 47 46 45 44 43 42 41 40 39 38 37 AGND 1 AVDD 2 36 PIN 1 IDENTIFIER CNVST PD 33 RESET MODE0 3 MODE1 4 D0/OB/2C 5 WARP 6 IMPULSE 7 D1/A0 8 AGND 35 34 32 AD7674 CS 31 RD DGND 29 BUSY 28 D17 TOP VIEW (Not to Scale) 30 D2/A1 9 D3 10 D4/DIVSCLK[0] 11 27 D16 26 D5/DIVSCLK[1] 12 25 D15 D14 D11/SCLK D12/SYNC D13/RDERROR OVDD DVDD DGND D10/SDOUT 13 14 15 16 17 18 19 20 21 22 23 24 D6/EXT/INT D7/INVSYNC D8/INVSCLK D9/RDC/SDIN OGND NC = NO CONNECT 03083–0–004 Figure 4. 48-Lead LQFP and 48-Lead LFCSP (ST-48 and CP-48) Table 6. Pin Function Descriptions Pin No. 1, 44 2, 47 3 4 Mnemonic AGND AVDD MODE0 MODE1 Type1 P P DI DI 5 D0/OB/2C DI/O 6 WARP DI 7 IMPULSE DI 8 D1/A0 DI/O 9 D2/A1 DI/O 10 D3 DO 11, 12 D[4:5]or DIVSCLK[0: 1] DI/O Description Analog Power Ground Pin. Input Analog Power Pins. Nominally 5 V. Data Output Interface Mode Selection. Data Output Interface Mode Selection: Interface MODE # MODE1 MODE0 Description 0 0 0 18-Bit Interface 1 0 1 16-Bit Interface 2 1 0 Byte Interface 3 1 1 Serial Interface When MODE = 0 (18-bit interface mode), this pin is Bit 0 of the parallel port data output bus and the data coding is straight binary. In all other modes, this pin allows choice of straight binary/binary twos complement. When OB/2C is HIGH, the digital output is straight binary; when LOW, the MSB is inverted, resulting in a twos complement output from its internal shift register. Conversion Mode Selection. When this input is HIGH and the IMPULSE pin is LOW, WARP selects the fastest mode, the maximum throughput is achievable, and a minimum conversion rate must be applied in order to guarantee full specified accuracy. When LOW, full accuracy is maintained independent of the minimum conversion rate. Conversion Mode Selection. When this input is HIGH and the WARP pin is LOW, IMPULSE selects a reduced power mode. In this mode, the power dissipation is approximately proportional to the sampling rate. When WARP and IMPULSE pins are LOW, the NORMAL mode is selected. When MODE = 0 (18-bit interface mode), this pin is Bit 1 of the parallel port data output bus. In all other modes, this input pin controls the form in which data is output, as shown in Table 7. When MODE = 0 or 1 (18-bit or 16-bit interface mode), this pin is Bit 2 of the parallel port data output bus. In all other modes, this input pin controls the form in which data is output, as shown in Table 7. In all modes except MODE = 3, this output is used as Bit 3 of the parallel port data output bus. This pin is always an output, regardless of the interface mode. In all modes except MODE = 3, these pins are Bit 4 and Bit 5 of the parallel port data output bus. When MODE = 3 (serial mode), when EXT/INT is LOW and RDC/SDIN is LOW (serial master read after convert), these inputs, part of the serial port, are used to slow down, if desired, the internal serial clock that clocks the data output. In other serial modes, these pins are not used. Rev. 0 | Page 8 of 28 AD7674 Pin No. 13 Mnemonic D6 or EXT/INT Type1 DI/O 14 D7 or INVSYNC DI/O 15 D8 or INVSCLK DI/O 16 D9 or RDC/SDIN DI/O 17 18 OGND OVDD P P 19 20 21 DVDD DGND D10 or SDOUT P P DO 22 D11 or SCLK DI/O 23 D12 or SYNC DO 24 D13 or RDERROR DO 25–28 D[14:17] DO 29 BUSY DO 30 31 32 DGND RD CS P DI DI 33 RESET DI Description In all modes except MODE = 3, this output is used as Bit 6 of the parallel port data output bus. When MODE = 3 (serial mode), this input, part of the serial port, is used as a digital select input for choosing the internal data clock or an external data clock. With EXT/INT tied LOW, the internal clock is selected on the SCLK output. With EXT/INT set to a logic HIGH, output data is synchronized to an external clock signal connected to the SCLK input. In all modes except MODE = 3, this output is used as Bit 7 of the parallel port data output bus. When MODE = 3 (serial mode), this input, part of the serial port, is used to select the active state of the SYNC signal. When LOW, SYNC is active HIGH. When HIGH, SYNC is active LOW. In all modes except MODE = 3, this output is used as Bit 8 of the parallel port data output bus. When MODE = 3 (serial mode), this input, part of the serial port, is used to invert the SCLK signal. It is active in both master and slave mode. In all modes except MODE = 3, this output is used as Bit 9 of the parallel port data output bus. When MODE = 3 (serial mode), this input, part of the serial port, is used as either an external data input or a read mode selection input depending on the state of EXT/INT. When EXT/ INT is HIGH, RDC/SDIN could be used as a data input to daisy-chain the conversion results from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is output on SDOUT with a delay of 18 SCLK periods after the initiation of the read sequence. When EXT/INT is LOW, RDC/SDIN is used to select the read mode. When RDC/SDIN is HIGH, the data is output on SDOUT during conversion. When RDC/SDIN is LOW, the data can be output on SDOUT only when the conversion is complete. Input/Output Interface Digital Power Ground. Output Interface Digital Power. Nominally at the same supply as the host interface (5 V or 3 V). Should not exceed DVDD by more than 0.3 V. Digital Power. Nominally at 5 V. Digital Power Ground. In all modes except MODE = 3, this output is used as Bit 10 of the parallel port data output bus. When MODE = 3 (serial mode), this output, part of the serial port, is used as a serial data output synchronized to SCLK. Conversion results are stored in an on-chip register. The AD7674 provides the conversion result, MSB first, from its internal shift register. The data format is determined by the logic level of OB/2C. In serial mode when EXT/INT is LOW, SDOUT is valid on both edges of SCLK. In serial mode when EXT/INT is HIGH and INVSCLK is LOW, SDOUT is updated on the SCLK rising edge and is valid on the next falling edge; if INVSCLK is HIGH, SDOUT is updated on the SCLK falling edge and is valid on the next rising edge. In all modes except MODE = 3, this output is used as Bit 11 of the parallel port data output bus. When MODE = 3 (serial mode), this pin, part of the serial port, is used as a serial data clock input or output, dependent upon the logic state of the EXT/INT pin. The active edge where the data SDOUT is updated depends upon the logic state of the INVSCLK pin. In all modes except MODE = 3, this output is used as Bit 12 of the parallel port data output bus. When MODE = 3 (serial mode), this output, part of the serial port, is used as a digital output frame synchronization for use with the internal data clock (EXT/INT = Logic LOW). When a read sequence is initiated and INVSYNC is LOW, SYNC is driven HIGH and remains HIGH while the SDOUT output is valid. When a read sequence is initiated and INVSYNC is HIGH, SYNC is driven LOW and remains LOW while SDOUT output is valid. In all modes except MODE = 3, this output is used as Bit 13 of the parallel port data output bus. In MODE = 3 (serial mode) and when EXT/ INT is HIGH, this output, part of the serial port, is used as an incomplete read error flag. In slave mode, when a data read is started and not complete when the following conversion is complete, the current data is lost and RDERROR is pulsed high. Bit 14 to Bit 17 of the Parallel Port Data Output Bus. These pins are always outputs regardless of the interface mode. Busy Output. Transitions HIGH when a conversion is started. Remains HIGH until the conversion is complete and the data is latched into the on-chip shift register. The falling edge of BUSY could be used as a data ready clock signal. Must Be Tied to Digital Ground. Read Data. When CS and RD are both LOW, the interface parallel or serial output bus is enabled. Chip Select. When CS and RD are both LOW, the interface parallel or serial output bus is enabled. CS is also used to gate the external clock. Reset Input. When set to a logic HIGH, reset the AD7674. Current conversion, if any, is aborted. If not used, this pin could be tied to DGND. Rev. 0 | Page 9 of 28 AD7674 Pin No. 34 Mnemonic PD Type1 DI 35 CNVST DI 36 37 AGND REF P AI 38 39 40–42, 45 43 46 REFGND IN– NC AI AI IN+ REFBUFIN AI AI 48 PDBUF DI Description Power-Down Input. When set to a logic HIGH, power consumption is reduced and conversions are inhibited after the current one is completed. Start Conversion. A falling edge on CNVST puts the internal sample/hold into the hold state and initiates a conversion. In Impulse mode (IMPULSE HIGH, WARP LOW), if CNVST is held LOW when the acquisition phase (t8) is complete, the internal sample/hold is put into hold and a conversion is immediately started. Must Be Tied to Analog Ground. Reference Input Voltage and Internal Reference Buffer Output. Apply an external reference on REF if the internal reference buffer is not used. Should be decoupled effectively with or without the internal buffer. Reference Input Analog Ground. Differential Negative Analog Input. No Connect. Differential Positive Analog Input. Reference Buffer Input Voltage. The internal reference buffer has a fixed gain. It outputs 4.096 V typically when 2.5 V is applied on this pin. Allows Choice of Buffering Reference. When LOW, buffer is selected. When HIGH, buffer is switched off. 1 AI = Analog Input; DI = Digital Input; DI/O = Bidirectional Digital; DO = Digital Output; P = Power. Table 7. Data Bus Interface Definitions MODE MODE1 MODE0 D0/OB/2C D1/A0 D2/A1 D[3] D[4:9] D[10:11] D[12:15] D[16:17] Description 0 1 0 0 0 1 R[0] OB/2C R[1] A0:0 R[2] R[2] R[3] R[3] R[4:9] R[4:9] R[10:11] R[10:11] R[12:15] R[12:15] R[16:17] R[16:17] 18-Bit Parallel 16-Bit High Word 1 0 1 OB/2C A0:1 R[0] R[1] 2 1 0 OB/2C A0:0 A1:0 All Hi-Z R[10:11] R[12:15] R[16:17] 8-Bit HIGH Byte 2 1 0 OB/2C A0:0 A1:1 All Hi-Z R[2:3] R[4:7] R[8:9] 8-Bit MID Byte 2 1 0 OB/2C A0:1 A1:0 All Hi-Z R[0:1] 2 1 0 OB/2C A0:1 A1:1 All Hi-Z 3 1 1 OB/2C All Hi-Z All Zeros 16-Bit Low Word All Zeros All Zeros Serial Interface R[0:17] is the 18-bit ADC value stored in its output register. Rev. 0 | Page 10 of 28 R[0:1] 8-Bit LOW Byte 8-Bit LOW Byte Serial Interface AD7674 DEFINITIONS OF SPECIFICATIONS Integral Nonlinearity Error (INL) Total Harmonic Distortion (THD) Linearity error refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line. THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal, and is expressed in decibels. Differential Nonlinearity Error (DNL) In an ideal ADC, code transitions are 1 LSB apart. Differential nonlinearity is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed. Gain Error The first transition (from 000…00 to 000…01) should occur for an analog voltage ½ LSB above the nominal negative full scale (–4.095991 V for the ±4.096 V range). The last transition (from 111…10 to 111…11) should occur for an analog voltage 1½ LSB below the nominal full scale (4.095977 V for the ±4.096 V range). The gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transition from the difference between the ideal levels. Zero Error The zero error is the difference between the ideal midscale input voltage (0 V) from the actual voltage producing the midscale output code. Spurious-Free Dynamic Range (SFDR) Dynamic Range Dynamic range is the ratio of the rms value of the full scale to the rms noise measured with the inputs shorted together. The value for dynamic range is expressed in decibels. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels. Signal-to-(Noise + Distortion) Ratio (S/[N+D]) S/(N+D) is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for S/(N+D) is expressed in decibels. Aperture Delay Aperture delay is a measure of the acquisition performance and is measured from the falling edge of the CNVST input to when the input signal is held for a conversion. Transient Response Transient response is the time required for the AD7674 to achieve its rated accuracy after a full-scale step function is applied to its input. SFDR is the difference, in decibels (dB), between the rms amplitude of the input signal and the peak spurious signal. Effective Number of Bits (ENOB) ENOB is a measurement of the resolution with a sine wave input, and is expressed in bits. It is related to S/(N+D) by the following formula: ENOB = (S/[N+D]dB – 1.76)/6.02 Rev. 0 | Page 11 of 28 AD7674 TYPICAL PERFORMANCE CHARACTERISTICS 2.5 2.0 2.0 1.5 1.0 DNL-LSB (18-Bit) INL-LSB (18-Bit) 1.5 1.0 0.5 0 0.5 0 –0.5 –0.5 –1.0 –1.5 0 65536 131072 CODE 196608 262144 –1.0 0 65536 03083-0-005 Figure 5. Integral Nonlinearity vs. Code 131072 CODE 196608 262144 03083-0-008 Figure 8. Differential Nonlinearity vs. Code 70000 90000 59121 60000 VREF = 5V VREF = 5V 80000 58556 28939 70000 50000 40000 COUNTS COUNTS 60000 30000 50000 40000 26939 30000 25964 20000 20000 10000 0 5073 0 0 7165 87 10000 47 0 0 0 2004C 2004D 2004E 2004F 20050 20051 20052 20053 20054 20055 CODE IN HEX 0 1 793 627 8 0 2004D 2004E 2004F 20050 20051 20052 20053 20054 20055 CODE IN HEX 03083-0-009 03083-0-006 Figure 6. Histogram of 131,072 Conversions of a DC Input at the Code Transition Figure 9. Histogram of 131,072 Conversions of a DC Input at the Code Center 100 120 90 80 NUMBER OF UNITS NUMBER OF UNITS 100 80 60 40 70 60 50 40 30 20 20 10 0 0 0.5 1.0 1.5 POSITIVE INL (LSB) 2.0 0 –2.5 2.5 03083-0-007 –2.0 –1.5 1.0 NEGATIVE INL (LSB) –0.5 0 03083-0-010 Figure 10. Typical Negative INL Distribution (424 Units) Figure 7. Typical Positive INL Distribution (424 Units) Rev. 0 | Page 12 of 28 AD7674 120 250 200 NUMBER OF UNITS 80 60 40 150 100 50 20 0 0 0.5 1.0 1.5 POSITIVE DNL (LSB) 0 –2.0 2.0 03083-0-011 Figure 11. Typical Positive DNL Distribution (424 Units) –1.0 –0.5 NEGATIVE DNL (LSB) 0 03083-0-014 Figure 14. TypicalNegative DNL Distribution (424 Units) 0 16.5 102 fS = 800kSPS fIN = 10kHz VREF = 4.096V SNR = 98.4dB THD = 119.1dB SFDR = 120.4dB SINAD = 98.4dB –40 –60 99 16.0 96 SNR AND S/[N+D] (dB) –20 AMPLITUDE (dB of Full Scale) –1.5 –80 –100 –120 SNR 15.5 93 90 15.0 S/(N+D) 87 ENOB (Bits) NUMBER OF UNITS 100 14.5 84 ENOB –140 81 –160 78 14.0 0 50 100 150 200 250 FREQUENCY (kHz) 300 350 75 400 1 03083-0-012 Figure 12. FFT (10 kHz Tone) 03083-0-015 140 –60 fS = 800kSPS fIN = 100kHz VREF = 4.096V SNR = 98.8dB THD = 104.3dB SFDR = 104.9dB SINAD = 97.8dB –40 –60 –70 THD, HARMONICS (dB) –20 –80 –100 –120 120 SFDR 100 –80 80 –90 THIRD HARMONIC –100 60 THD –110 40 SECOND HARMONIC –140 20 –120 –160 –180 13.5 1000 Figure 15. SNR, S/(N+D), and ENOB vs. Frequency 0 AMPLITUDE (dB of Full Scale) 10 100 FREQUENCY (kHz) 0 50 100 150 200 250 FREQUENCY (kHz) 300 350 –130 400 03083-0-013 Figure 13. FFT (100 kHz Tone) 1 10 100 FREQUENCY (kHz) 0 1000 03083-0-016 Figure 16. THD, SFDR, and Harmonics vs. Frequency Rev. 0 | Page 13 of 28 SFDR (dB) –180 AD7674 100000 AVDD, WARP/NORMAL VREF = 4.096V 104 10000 103 OPERATING CURRENTS (µA) SNR REFERRED TO FULL SCALE (dB) 105 102 101 100 SNR S/(N+D) 99 98 97 DVDD, WARP/NORMAL 1000 100 AVDD, IMPULSE 10 DVDD, IMPULSE 1 PDBUF HIGH 0.1 OVDD, ALL MODES 0.01 96 95 –60 –50 –40 –30 –20 –10 0.001 0 INPUT LEVEL (dB) 1 Figure 17. SNR and S/(N+D) vs. Input Level 16.5 POWER-DOWN OPERATING CURRENTS (nA) SNR 16.0 SNR, S/[N+D] (dB) 99 S/(N+D) ENOB 15.5 98 15.0 97 –15 25 5 45 65 105 85 TEMPERATURE (°C) 100k 1M 03083-0-020 800 VREF = 4.096V –35 100 1k 10k SAMPLING RATE (SPS) Figure 20. Operating Current vs. Sampling Rate 100 96 –55 10 03083-0-017 700 600 DVDD 500 400 AVDD 300 OVDD 100 14.5 125 0 –55 –35 –15 5 03083-0-018 Figure 18. SNR, S/(N+D), and ENOB vs. Temperature 25 45 65 TEMPERATURE (°C) 85 105 125 03083-0-021 Figure 21. Power-Down Operating Currents vs. Temperature –100 25 –110 THD –120 –130 ZERO ERROR,POSITIVE AND NEGATIVE FULL SCALE (LSB) THD, HARMONICS (dB) 20 THIRD HARMONIC SECOND HARMONIC 15 10 NEGATIVE FULL SCALE 5 ZERO ERROR 0 –5 –10 POSITIVE FULL SCALE –15 –20 –140 –55 –35 –15 5 25 45 65 85 105 TEMPERATURE (°C) Figure 19. THD and Harmonics vs. Temperature –25 –55 125 –35 –15 5 25 45 65 TEMPERATURE (°C) 03083-0-019 85 105 125 03083-0-022 Figure 22. Zero Error, Positive and Negative Full Scale vs. Temperature Rev. 0 | Page 14 of 28 AD7674 30 50 OVDD = 2.7V @ 85°C 10 0 40 POSITIVE FULL SCALE t12 DELAY (ns) ZERO ERROR,POSITIVE AND NEGATIVE FULL SCALE (LSB) 20 ZERO ERROR 10 30 20 OVDD = 2.7V @ 25°C OVDD = 5V @ 85°C OVDD = 5V @ 25°C 10 20 NEGATIVE FULL SCALE –30 4.50 4.75 5.00 AVDD (V) 5.25 0 5.50 0 50 100 150 CL (pF) 03083-0-023 Figure 23. Zero Error, Positive and Negative Full Scale vs. Supply Figure 24. Typical Delay vs. Load Capacitance CL Rev. 0 | Page 15 of 28 200 03083-0-024 AD7674 CIRCUIT INFORMATION IN+ MSB 262,144C 131,072C LSB 4C 2C C SW+ SWITCHES CONTROL C BUSY REF COMP CONTROL LOGIC REFGND 4C 262,144C 131,072C 2C C C LSB MSB OUTPUT CODE SW– IN– CNVST 03083–0–025 Figure 25. ADC Simplified Schematic The AD7674 is a very fast, low power, single-supply, precise 18-bit analog-to-digital converter (ADC) using successive approximation architecture. The AD7674’s linearity and dynamic range are similar to or better than many Σ-∆ ADCs. With the advantages of its successive architecture, which ease multiplexing and reduce power with throughput, it can be advantageous in applications that normally use Σ-∆ ADCs. The AD7674 features different modes to optimize performance according to the applications. In Warp mode, the AD7674 is capable of converting 800,000 samples per second (800 kSPS). The AD7674 provides the user with an on-chip track/hold, successive approximation ADC that does not exhibit any pipeline or latency, making it ideal for multiple multiplexed channel applications. acquisition phase is complete and the CNVST input goes low, a conversion phase is initiated. When the conversion phase begins, SW+ and SW– are opened first. The two capacitor arrays are then disconnected from the inputs and connected to the REFGND input. Therefore, the differential voltage between the IN+ and IN– inputs captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced. By switching each element of the capacitor array between REFGND and REF, the comparator input varies by binary weighted voltage steps (VREF/2, VREF/4, ... VREF/262144). The control logic toggles these switches, starting with the MSB first, to bring the comparator back into a balanced condition. After completing this process, the control logic generates the ADC output code and brings the BUSY output low. Modes of Operation The AD7674 features three modes of operation: Warp, Normal, and Impulse. Each mode is more suited for specific applications. The AD7674 can be operated from a single 5 V supply and can be interfaced to either 5 V or 3 V digital logic. It is housed in a 48-lead LQFP, or a tiny 48-lead LFCSP package that offers space savings and allows for flexible configurations as either a serial or parallel interface. The AD7674 is a pin-to-pin compatible upgrade of the AD7676, AD7678, and AD7679. CONVERTER OPERATION Warp mode allows conversion rates up to 800 kSPS. However, in this mode and this mode only, the full specified accuracy is guaranteed only when the time between conversions does not exceed 1 ms. If the time between two consecutive conversions is longer than 1 ms (e.g., after power-up), the first conversion result should be ignored. This mode makes the AD7674 ideal for applications where a fast sample rate is required. The AD7674 is a successive approximation ADC based on a charge redistribution DAC. Figure 25 shows the simplified schematic of the ADC. The capacitive DAC consists of two identical arrays of 18 binary weighted capacitors that are connected to the two comparator inputs. Normal mode is the fastest mode (666 kSPS) without any limitation on the time between conversions. This mode makes the AD7674 ideal for asynchronous applications such as data acquisition systems, where both high accuracy and fast sample rate are required. During the acquisition phase, terminals of the array tied to the comparator’s input are connected to AGND via SW+ and SW–. All independent switches are connected to the analog inputs. Thus, the capacitor arrays are used as sampling capacitors and acquire the analog signal on the IN+ and IN– inputs. When the Impulse mode, the lowest power dissipation mode, allows power saving between conversions. The maximum throughput in this mode is 570 kSPS. When operating at 1 kSPS, for example, it typically consumes only 136 µW. This feature makes the AD7674 ideal for battery-powered applications. Rev. 0 | Page 16 of 28 AD7674 Transfer Functions Table 8. Output Codes and Ideal Input Voltages ADC CODE (Straight Binary) Except in 18-bit interface mode, the AD7674 offers straight binary and twos complement output coding when using OB/2C. See Figure 26 and Table 8 for the ideal transfer characteristic. Description FSR – 1 LSB FSR – 2 LSB Midscale + 1 LSB Midscale Midscale – 1 LSB –FSR + 1 LSB –FSR 111...111 111...110 111...101 000...010 1 000...001 000...000 –FS –FS + 1 LSB 2 +FS – 1 LSB –FS + 0.5 LSB Straight Binary (Hex) 3FFFF1 3FFFE 20001 20000 1FFFF 00001 000002 Analog Input VREF = 4.096 V 4.095962 V 4.095924 V 31.25 µV 0V –31.25 µV –4.095962 V –4.096 V Twos Complement (Hex) 1FFFF1 1FFFE 00001 00000 3FFFF 20001 200002 This is also the code for overrange analog input (VIN+ – VIN– above VREF – VREFGND). This is also the code for underrange analog input (VIN+ – VIN– below –VREF + VREFGND). +FS – 1.5 LSB ANALOG INPUT 03083-0-026 Figure 26. ADC Ideal Transfer Function DVDD ANALOG SUPPLY (5V) 20Ω + NOTE 5 10µF 100nF ADR421 AVDD AGND DIGITAL SUPPLY (3.3V OR 5V) + 10µ F 100nF DGND DVDD REFBUFIN 2.5V REF 1MΩ NOTE 1 50kΩ 100nF REF BUSY REFGND CNVST 50Ω – U1 + AD8021 CC µC/µP/DSP D IN+ AD7674 2.7nF MODE1 MODE0 OB/2C DVDD NOTE 4 PDBUF CLOCK CS – U2 + AD8021 50Ω NOTE 6 15Ω 50Ω ANALOG INPUT– SERIAL PORT SCLK 47µF NOTE 1 NOTE 3 OGND SDOUT CREF ANALOG INPUT+ OVDD 10µ F 100nF NOTE 2 NOTE 3 100nF + RD 15Ω IN– RESET PD CC 2.7nF NOTE 4 NOTES 1. SEE VOLTAGE REFERENCE INPUT SECTION. 2. OPTIONAL CIRCUITRY FOR HARDWARE GAIN CALIBRATION. 3.THE AD8021 IS RECOMMENDED. SEE DRIVER AMPLIFIER CHOICE SECTION. 4. SEE ANALOG INPUTS SECTION. 5. OPTION, SEE POWER SUPPLY SECTION. 6. OPTIONAL LOW JITTER CNVST, SEE CONVERSION CONTROL SECTION. Figure 27. Typical Connection Diagram (Internal Reference Buffer, Serial Interface) Rev. 0 | Page 17 of 28 03083-0-027 AD7674 TYPICAL CONNECTION DIAGRAM Figure 27 shows a typical connection diagram for the AD7674. Different circuitry shown on this diagram is optional and is discussed later in this data sheet. Analog Inputs Figure 28 shows a simplified analog input section of the AD7674. The diodes shown in Figure 28 provide ESD protection for the inputs. Care must be taken to ensure that the analog input signal never exceeds the absolute ratings on these inputs. This will cause these diodes to become forward biased and start conducting current. These diodes can handle a forward-biased current of 120 mA max. This condition could eventually occur when the input buffer’s U1 or U2 supplies are different from AVDD. In such a case, an input buffer with a short-circuit current limitation can be used to protect the part. lumped components made up of a serial resistor and the on resistance of the switches. CS is typically 60 pF and mainly consists of the ADC sampling capacitor. This 1-pole filter with a –3 dB cutoff frequency of 26 MHz typ reduces any undesirable aliasing effect and limits the noise coming from the inputs. Because the input impedance of the AD7674 is very high, the part can be driven directly by a low impedance source without gain error. This allows the user to put an external 1-pole RC filter between the amplifier output and the ADC analog inputs, as shown in Figure 27, to improve the noise filtering done by the AD7674 analog input circuit. However, the source impedance has to be kept low because it affects the ac performance, especially the total harmonic distortion (THD). The maximum source impedance depends on the amount of THD that can be tolerated. The THD degrades as a function of source impedance and the maximum input frequency, as shown in Figure 30. AVDD –95 20kHz –100 R+ = 102Ω IN+ CS –105 THD (dB) CS IN– R– = 102Ω 10kHz –110 AGND 2kHz 03083-0-028 –115 Figure 28. Simplified Analog Input –120 15 This analog input structure is a true differential structure. By using these differential inputs, signals common to both inputs are rejected as shown in Figure 29, which represents typical CMRR over frequency. 45 75 INPUT RESISTANCE (Ω) 105 03083-0-030 Figure 30. THD vs. Analog Input Frequency and Source Resistance Driver Amplifier Choice 66 Although the AD7674 is easy to drive, the driver amplifier needs to meet the following requirements: 64 CMRR (dB) 62 • The driver amplifier and the AD7674 analog input circuit have to be able to settle for a full-scale step of the capacitor array at an 18-bit level (0.0004%). In the amplifier’s data sheet, settling at 0.1% or 0.01% is more commonly specified. This could differ significantly from the settling time at an 18-bit level and, therefore, should be verified prior to driver selection. The tiny op amp AD8021, which combines ultralow noise and high gain-bandwidth, meets this settling time requirement. • The noise generated by the driver amplifier needs to be kept as low as possible in order to preserve the SNR and transition noise performance of the AD7674. The noise coming from the driver is filtered by the AD7674 analog input circuit 1-pole low-pass filter made by R+, R–, and CS. 60 58 56 54 52 50 1 10 100 FREQUECY (kHz) 1000 10000 03083-0-029 Figure 29. Analog Input CMRR vs. Frequency During the acquisition phase for ac signals, the AD7674 behaves like a 1-pole RC filter consisting of the equivalent resistance R+, R–, and CS. The resistors R+ and R– are typically 102 Ω and are Rev. 0 | Page 18 of 28 AD7674 The SNR degradation due to the amplifier is SNRLOSS = 20 log 25 625 + π f –3dB (Ne N )2 ANALOG INPUT (UNIPOLAR 0V TO 4.096V) where: f–3dB is the –3 dB input bandwidth in MHz of the AD7674 (26 MHz) or the cutoff frequency of the input filter, if used. U1 AD8021 10pF 15Ω 590Ω 2.7nF AD8021 100nF IN+ AD7674 15Ω U2 1.82kΩ 8.25kΩ 590Ω 10pF 2.7nF IN– REF REFBUFIN 10µF N is the noise factor of the amplifiers (1 if in buffer configuration). 2.5V 03083-0-031 eN is the equivalent input noise voltage of each op amp in nV/√Hz. For instance, for a driver with an equivalent input noise of 2 nV/√Hz (e.g., AD8021) configured as a buffer, thus with a noise gain of +1, the SNR degrades by only 0.34 dB with the filter in Figure 27, and by 1.8 dB without it. • The driver needs to have a THD performance suitable to that of the AD7674. The AD8021 meets these requirements and is usually appropriate for almost all applications. The AD8021 needs a 10 pF external compensation capacitor, which should have good linearity as an NPO ceramic or mica type. The AD8022 could be used if a dual version is needed and gain of 1 is present. The AD829 is an alternative in applications where high frequency (above 100 kHz) performance is not required. In gain of 1 applications, it requires an 82 pF compensation capacitor. The AD8610 is another option when low bias current is needed in low frequency applications. Single-to-Differential Driver For applications using unipolar analog signals, a single-endedto-differential driver will allow for a differential input into the part. The schematic is shown in Figure 31. When provided an input signal of 0 to VREF, this configuration will produce a differential ±VREF with midscale at VREF/2. If the application can tolerate more noise, the AD8138 differential driver can be used. Figure 31. Single-Ended-to-Differential Driver Circuit (Internal Reference Buffer Used) Voltage Reference The AD7674 allows the use of an external voltage reference either with or without the internal reference buffer. Using the internal reference buffer is recommended when sharing a common reference voltage between multiple ADCs is desired. However, the advantages of using the external reference voltage directly are: • The SNR and dynamic range improvement (about 1.7 dB) resulting from the use of a reference voltage very close to the supply (5 V) instead of a typical 4.096 V reference when the internal buffer is used • The power saving when the internal reference buffer is powered down (PDBUF High) To use the internal reference buffer, PDBUF should be LOW. A 2.5 V reference voltage applied on the REFBUFIN input will result in a 4.096 V reference on the REF pin. In both cases, the voltage reference input REF has a dynamic input impedance and therefore requires an efficient decoupling between REF and REFGND inputs, The decoupling consists of a low ESR 47 µF tantalum capacitor connected to the REF and REFGND inputs with minimum parasitic inductance. Care should also be taken with the reference temperature coefficient of the voltage reference, which directly affects the full-scale accuracy if this parameter matters. For instance, a ±4 ppm/°C temperature coefficient of the reference changes the full scale by ±1 LSB/°C. Rev. 0 | Page 19 of 28 AD7674 1000000 Power Supply WARP/NORMAL 100000 POWER DISSAPATION (µW) The AD7674 uses three sets of power supply pins: an analog 5 V supply (AVDD), a digital 5 V core supply (DVDD), and a digital output interface supply (OVDD). The OVDD supply defines the output logic level and allows direct interface with any logic working between 2.7 V and DVDD + 0.3 V. To reduce the number of supplies needed, the digital core (DVDD) can be supplied through a simple RC filter from the analog supply, as shown in Figure 27. The AD7674 is independent of power supply sequencing once OVDD does not exceed DVDD by more than 0.3 V, and is therefore free from supply voltage induced latch-up. Additionally, it is very insensitive to power supply variations over a wide frequency range, as shown in Figure 32. 10000 1000 100 IMPULSE 10 PDBUF HIGH 1 0.1 1 100 1k 10k SAMPLING RATE (SPS) 10 100k 1M 03083-0-033 Figure 33. Power Dissipation vs. Sample Rate 70 CONVERSION CONTROL Figure 34 shows the detailed timing diagrams of the conversion process. The AD7674 is controlled by the CNVST signal, which initiates conversion. Once initiated, it cannot be restarted or aborted, even by PD, until the conversion is complete. The CNVST signal operates independently of CS and RD signals. 65 PSRR (dB) 60 55 50 t2 t1 CNVST 45 40 1 BUSY 10 100 FREQUECY (kHz) 1000 10000 t4 t3 03083-0-032 t6 t5 Figure 32. PSRR vs. Frequency MODE ACQUIRE CONVERT ACQUIRE t7 t8 CONVERT 03083-0-034 POWER DISSIPATION VERSUS THROUGHPUT Figure 34. Basic Conversion Timing In Impulse mode, the AD7674 automatically reduces its power consumption at the end of each conversion phase. During the acquisition phase, the operating currents are very low, which allows for a significant power savings when the conversion rate is reduced, as shown in Figure 33. This feature makes the AD7674 ideal for very low power battery applications. It should be noted that the digital interface remains active even during the acquisition phase. To reduce the operating digital supply currents even further, the digital inputs need to be driven close to the power rails (DVDD and DGND), and OVDD should not exceed DVDD by more than 0.3 V. Although CNVST is a digital signal, it should be designed with special care with fast, clean edges and levels with minimum overshoot and undershoot or ringing. For applications where SNR is critical, the CNVST signal should have very low jitter. This may be achieved by using a dedicated oscillator for CNVST generation, or to clock it with a high frequency low jitter clock, as shown in Figure 27. In Impulse mode, conversions can be initiated automatically. If CNVST is held low when BUSY goes low, the AD7674 controls the acquisition phase and automatically initiates a new conversion. By keeping CNVST low, the AD7674 keeps the conversion process running by itself. Note that the analog input has to be settled when BUSY goes low. Also, at power-up, CNVST should be brought low once to initiate the conversion process. In this mode, the AD7674 could sometimes run slightly faster than the guaranteed limits of 570 kSPS in Impulse mode. This feature does not exist in Warp or Normal modes. Rev. 0 | Page 20 of 28 AD7674 DIGITAL INTERFACE The AD7674 has a versatile digital interface; it can be interfaced with the host system by using either a serial or parallel interface. The serial interface is multiplexed on the parallel data bus. The AD7674 digital interface also accommodates both 3 V and 5 V logic by simply connecting the AD7674’s OVDD supply pin to the host system interface digital supply. Finally, by using the OB/2C input pin in any mode but 18-bit interface mode, both twos complement and straight binary coding can be used. The two signals, CS and RD, control the interface. When at least one of these signals is high, the interface outputs are in high impedance. Usually, CS allows the selection of each AD7674 in multicircuit applications, and is held low in a single AD7674 design. RD is generally used to enable the conversion result on the data bus. t9 that it is read only during the first half of the conversion phase. This avoids any potential feedthrough between voltage transients on the digital interface and the most critical analog conversion circuitry. Refer to Table 7 for a detailed description of the different options available. CS RD BUSY DATA BUS CURRENT CONVERSION t12 t13 03083-0-037 Figure 37. Slave Parallel Data Timing for Reading (Read after Convert) RESET CS = 0 t1 CNVST, RD BUSY t4 BUSY DATA BUS t3 PREVIOUS CONVERSION DATA BUS t8 t12 t13 03083-0-038 CNVST 03083-0-035 Figure 38. Slave Parallel Data Timing for Reading (Read during Convert) Figure 35. RESET Timing CS = RD = 0 CS t1 CNVST RD t10 A0, A1 t4 BUSY t3 t11 PINS D[15:8] DATA BUS PREVIOUS CONVERSION DATA HI-Z NEW DATA 03083-0-036 HIGH BYTE t12 PINS D[7:0] HI-Z LOW BYTE LOW BYTE t12 HIGH BYTE HI-Z t13 HI-Z 03083-0-039 Figure 36. Master Parallel Data Timing for Reading (Continuous Read) Figure 39. 8-Bit and 16-Bit Parallel Interface PARALLEL INTERFACE SERIAL INTERFACE The AD7674 is configured to use the parallel interface with an 18-bit, a 16-bit, or an 8-bit bus width, according to Table 7. The data can be read either after each conversion, which is during the next acquisition phase, or during the following conversion, as shown in Figure 37 and Figure 38, respectively. When the data is read during the conversion, however, it is recommended The AD7674 is configured to use the serial interface when MODE0 and MODE1 are held high. The AD7674 outputs 18 bits of data, MSB first, on the SDOUT pin. This data is synchronized with the 18 clock pulses provided on the SCLK pin. The output data is valid on both the rising and falling edge of the data clock. Rev. 0 | Page 21 of 28 AD7674 In Read during Conversion mode, the serial clock and data toggle at appropriate instants, minimizing potential feedthrough between digital activity and critical conversion decisions. MASTER SERIAL INTERFACE Internal Clock The AD7674 is configured to generate and provide the serial data clock SCLK when the EXT/INT pin is held low. The AD7674 also generates a SYNC signal to indicate to the host when the serial data is valid. The serial clock SCLK and the SYNC signal can be inverted if desired. Depending on the RDC/SDIN input, the data can be read after each conversion or during the following conversion. Figure 40 and Figure 41 show the detailed timing diagrams of these two modes. In Read after Conversion mode, it should be noted that unlike in other modes, the BUSY signal returns low after the 18 data bits are pulsed out and not at the end of the conversion phase, which results in a longer BUSY width. To accommodate slow digital hosts, the serial clock can be slowed down by using DIVSCLK. Usually, because the AD7674 is used with a fast throughput, the Master Read during Conversion mode is the most recommended serial mode. RDC/SDIN = 0 EXT/INT = 0 CS, RD INVSCLK = INVSYNC = 0 t3 CNVST t28 BUSY t30 t29 t25 SYNC t18 t19 t14 t20 1 SCLK t24 t21 2 3 16 17 t26 18 t15 t27 X SDOUT t16 t22 D17 D16 D2 D1 D0 t23 03083-0-040 Figure 40. Master Serial Data Timing for Reading (Read after Convert) Rev. 0 | Page 22 of 28 AD7674 RDC/SDIN = 1 EXT/INT = 0 CS, RD INVSCLK = INVSYNC = 0 t1 CNVST t3 BUSY t17 t25 SYNC t14 t19 t20 t21 t15 SCLK 1 t24 2 3 16 17 t18 X SDOUT t16 t27 D17 t22 t26 18 D16 D2 D1 D0 t23 03083-0-046 Figure 41. Master Serial Data Timing for Reading (Read Previous Conversion during Convert) External Discontinuous Clock Data Read after Conversion SLAVE SERIAL INTERFACE External Clock The AD7674 is configured to accept an externally supplied serial data clock on the SCLK pin when the EXT/INT pin is held high. In this mode, several methods can be used to read the data. The external serial clock is gated by CS. When CS and RD are both low, the data can be read after each conversion or during the following conversion. The external clock can be either a continuous or a discontinuous clock. A discontinuous clock can be either normally high or normally low when inactive. Figure 42 and Figure 43 show the detailed timing diagrams of these methods. While the AD7674 is performing a bit decision, it is important that voltage transients not occur on digital input/output pins or degradation of the conversion result could occur. This is particularly important during the second half of the conversion phase because the AD7674 provides error correction circuitry that can correct for an improper bit decision made during the first half of the conversion phase. For this reason, it is recommended that when an external clock is being provided, it is a discontinuous clock that only toggles when BUSY is low or, more importantly, that it does not transition during the latter half of BUSY high. Though maximum throughput cannot be achieved using this mode, it is the most recommended of the serial slave modes. Figure 42 shows the detailed timing diagrams of this method. After a conversion is complete, indicated by BUSY returning low, the result of this conversion can be read while both CS and RD are low. Data is shifted out MSB first with 18 clock pulses, and is valid on the rising and falling edge of the clock. Among the advantages of this method, the conversion performance is not degraded because there are no voltage transients on the digital interface during the conversion process. Also, data can be read at speeds up to 40 MHz, accommodating both slow digital host interface and the fastest serial reading. Finally, in this mode only, the AD7674 provides a daisy-chain feature using the RDC/SDIN input pin to cascade multiple converters together. This feature is useful for reducing component count and wiring connections when desired (for instance, in isolated multiconverter applications). An example of the concatenation of two devices is shown in Figure 44. Simultaneous sampling is possible by using a common CNVST signal. It should be noted that the RDC/SDIN input is latched on the edge of SCLK opposite the one used to shift out data on SDOUT. Thus, the MSB of the upstream converter follows the LSB of the downstream converter on the next SCLK cycle. Rev. 0 | Page 23 of 28 AD7674 INVSCLK = 0 EXT/INT = 1 CS RD = 0 BUSY t36 SCLK t35 t37 1 2 t31 3 16 17 18 19 20 t32 SDOUT X D17 t16 D16 D15 D1 D0 X17 X16 X16 X15 X1 X0 Y17 Y16 t34 SDIN X17 t33 03083-0-042 Figure 42. Slave Serial Data Timing for Reading (Read after Convert) EXT/INT = 1 INVSCLK = 0 RD = 0 CS CNVST BUSY t3 t35 t36 SCLK t37 1 2 t31 SDOUT 3 16 17 18 t32 X D17 D16 D15 D1 D0 t16 03083-0-043 Figure 43. Slave Serial Data Timing for Reading (Read Previous Conversion during Convert) Rev. 0 | Page 24 of 28 AD7674 BUSY OUT BUSY BUSY AD7674 AD7674 #2 (UPSTREAM) RDC/SDIN MICROPROCESSOR INTERFACING The AD7674 is ideally suited for traditional dc measurement applications supporting a microprocessor, and for ac signal processing applications interfacing to a digital signal processor. The AD7674 is designed to interface either with a parallel 8-bit or 16-bit wide interface, or with a general-purpose serial port or I/O ports on a microcontroller. A variety of external buffers can be used with the AD7674 to prevent digital noise from coupling into the ADC. The following section illustrates the use of the AD7674 with an SPI equipped DSP, the ADSP-219x. #1 (DOWNSTREAM) SDOUT CNVST RDC/SDIN DATA OUT SDOUT CNVST CS CS SCLK SCLK SCLK IN CS IN CNVST IN 03083-0-044 SPI Interface (ADSP-219x) Figure 44. Two AD7674s in a Daisy-Chain Configuration External Clock Data Read during Conversion Figure 43 shows the detailed timing diagrams of this method. During a conversion, while both CS and RD are low, the result of the previous conversion can be read. The data is shifted out MSB first with 18 clock pulses, and is valid on both the rising and falling edge of the clock. The 18 bits have to be read before the current conversion is complete. If that is not done, RDERROR is pulsed high and can be used to interrupt the host interface to prevent incomplete data reading. There is no daisychain feature in this mode, and the RDC/SDIN input should always be tied either high or low. To reduce performance degradation due to digital activity, a fast discontinuous clock is recommended to ensure that all bits are read during the first half of the conversion phase. It is also possible to begin to read the data after conversion and continue to read the last bits even after a new conversion has been initiated. Figure 45 shows an interface diagram between the AD7674 and the SPI equipped ADSP-219x. To accommodate the slower speed of the DSP, the AD7674 acts as a slave device, and data must be read after conversion. This mode also allows the daisychain feature. The convert command could be initiated in response to an internal timer interrupt. The 18-bit output data are read with 3-byte SPI access. The reading process could be initiated in response to the end-of-conversion signal (BUSY going low) using an interrupt line of the DSP. The serial interface (SPI) on the ADSP-219x is configured for master mode (MSTR) = 1, Clock Polarity Bit (CPOL) = 0, Clock Phase Bit (CPHA) = 1, and SPI interrupt enable (TIMOD) = 00, by writing to the SPI Control register (SPICLTx). It should be noted that to meet all timing requirements, the SPI clock should be limited to 17 Mbps, which allows it to read an ADC result in about 1.1 µs. When a higher sampling rate is desired, use of one of the parallel interface modes is recommended. DVDD AD7674* ADSP-219x* SER/PAR EXT/INT BUSY CS RD INVSCLK SDOUT SCLK CNVST PFx SPIxSEL (PFx) MISOx SCKx PFx or TFSx * ADDITIONAL PINS OMITTED FOR CLARITY 03083-0-045 Figure 45. Interfacing the AD7674 to an SPI Interface Rev. 0 | Page 25 of 28 AD7674 APPLICATION HINTS LAYOUT The AD7674 has very good immunity to noise on the power supplies. However, care should still be taken with regard to grounding layout. The printed circuit board that houses the AD7674 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. This calls for the use of ground planes, which can be easily separated. Digital and analog ground planes should be joined in only one place, preferably underneath the AD7674, or at least as close to the AD7674 as possible. If the AD7674 is in a system where multiple devices require analog-to-digital ground connections, the connection should still be made at one point only, a star ground point that should be established as close to the AD7674 as possible. The user should avoid running digital lines under the device, as these will couple noise onto the die. The analog ground plane should be allowed to run under the AD7674 to avoid noise coupling. Fast switching signals like CNVST or clocks should be shielded with digital ground to avoid radiating noise to other sections of the board, and should never run near analog signal paths. Crossover of digital and analog signals should be avoided. Traces on different but close layers of the board should run at right angles to each other. This will reduce the effect of feedthrough through the board. The power supply lines to the AD7674 should use as large a trace as possible to provide low impedance paths and reduce the effect of glitches on the power supply lines. Good decoupling is also important to lower the supply’s impedance presented to the AD7674 and to reduce the magnitude of the supply spikes. Decoupling ceramic capacitors, typically 100 nF, should be placed close to and ideally right up against each power supply pin (AVDD, DVDD, and OVDD) and their corresponding ground pins. Additionally, low ESR 10 µF capacitors should be located near the ADC to further reduce low frequency ripple. The DVDD supply of the AD7674 can be a separate supply or can come from the analog supply, AVDD, or the digital interface supply, OVDD. When the system digital supply is noisy or when fast switching digital signals are present, and if no separate supply is available, the user should connect the DVDD digital supply to the analog supply AVDD through an RC filter, (see Figure 27), and connect the system supply to the interface digital supply OVDD and the remaining digital circuitry. When DVDD is powered from the system supply, it is useful to insert a bead to further reduce high frequency spikes. The AD7674 has four different ground pins: REFGND, AGND, DGND, and OGND. REFGND senses the reference voltage and should be a low impedance return to the reference because it carries pulsed currents. AGND is the ground to which most internal ADC analog signals are referenced. This ground must be connected with the least resistance to the analog ground plane. DGND must be tied to the analog or digital ground plane depending on the configuration. OGND is connected to the digital system ground. The layout of the decoupling of the reference voltage is important. The decoupling capacitor should be close to the ADC and should be connected with short and large traces to minimize parasitic inductances. EVALUATING THE AD7674’S PERFORMANCE A recommended layout for the AD7674 is outlined in the documentation of the EVAL-AD7674CB evaluation board for the AD7674. The evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a PC via the EVALCONTROL BRD2. Rev. 0 | Page 26 of 28 AD7674 OUTLINE DIMENSIONS 0.75 0.60 0.45 9.00 BSC SQ 1.60 MAX 37 48 36 1 10° 6° 2° 1.45 1.40 1.35 0.15 0.05 SEATING PLANE PIN 1 SEATING PLANE 7.00 BSC SQ TOP VIEW 0.20 0.09 (PINS DOWN ) VIEW A 7° 3.5° 0° 0.10 MAX COPLANARITY 12 24 13 0.50 BSC VIEW A 25 0.27 0.22 0.17 ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026BBC Figure 46. 48-Lead Quad Flatpack (LQFP)(ST-48) 7.00 BSC SQ 0.60 MAX 0.60 MAX 37 36 PIN 1 INDICATOR 0.20 REF 12° MAX 25 24 12 13 5.50 REF 0.80 MAX 0.65 NOM 0.50 BSC 1 5.25 5.10 SQ 4.95 PADDLE CONNECTED TO AGND. THIS CONNECTION IS NOT REQUIRED TO MEET THE ELECTRICAL PERFORMANCE 0.05 MAX 0.02 NOM SEATING PLANE PIN 1 INDICATOR BOTTOM VIEW 0.50 0.40 0.30 1.00 0.90 0.80 48 6.75 BSC SQ TOP VIEW 0.30 0.23 0.18 COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2 Figure 47. 48-Lead Frame Chip Scale Package (LFCSP) (CP-48)) ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7674 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ORDERING GUIDE Model AD7674AST AD7674ASTRL AD7674ACP AD7674ACPRL EVAL-AD7674CB1 EVAL-CONTROL BRD22 Temperature Range –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C Package Description Quad Flatpack (LQFP) Quad Flatpack (LQFP) Lead Frame Chip Scale (LFCSP) Lead Frame Chip Scale (LFCSP) Evaluation Board Controller Board 1 Package Option ST-48 ST-48 CP-48 CP-48 This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD2 for evaluation/demonstration purposes. This board allows a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators. 2 Rev. 0 | Page 27 of 28 AD7674 NOTES © 2003 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective companies. C03083–0–7/03(0) Rev. 0 | Page 28 of 28