Cypress CY7C4282-10ASI 64k/128k x 9 deep sync fifos with retransmit and depth expansion Datasheet

CY7C4282
CY7C4292
64K/128K x 9 Deep Sync FIFOs with
Retransmit and Depth Expansion
Features
Functional Description
• High-speed, low-power, first-in first-out (FIFO)
memories
• 64K × 9 (CY7C4282)
• 128K × 9 (CY7C4292)
• 0.5-micron CMOS for optimum speed/power
• High-speed, near-zero latency (true dual-ported
memory cell), 100-MHz operation (10-ns read/write
cycle times)
• Low power
— ICC=40 mA
The CY7C4282/CY7C4292 are high-speed, low-power, FIFO
memories with clocked read and write interfaces. All devices
are nine bits wide. The CY7C4282/CY7C4292 can be
cascaded to increase FIFO depth. Programmable features
include Almost Full/Almost Empty flags. These FIFOs provide
solutions for a wide variety of data buffering needs, including
high-speed data acquisition, multiprocessor interfaces, video
and communications buffering.
These FIFOs have 9-bit input and output ports that are
controlled by separate clock and enable signals. The input port
is controlled by a free-running clock (WCLK) and a
write-enable pin (WEN).
— ISB = 2 mA
• Fully asynchronous and simultaneous read and write
operation
• Empty, Full, and Programmable Almost Empty and
Almost Full status flags
• TTL-compatible
• Retransmit function
• Output Enable (OE) pin
• Independent read and write enable pins
• Supports free-running 50% duty cycle clock inputs
• Width-Expansion Capability
• Depth-Expansion Capability through token-passing
scheme (no external logic required)
• 64-pin 10 × 10 STQFP
Retransmit and Synchronous Almost Full/Almost Empty flag
features are available on these devices.
Depth expansion is possible using the cascade input (XI),
cascade output (XO), and First Load (FL) pins. The XO pin is
connected to the XI pin of the next device, and the XO pin of
the last device should be connected to the XI pin of the first
device. The FL pin of the first device is tied to VSS and the FL
pin of all the remaining devices should be tied to VCC.
When WEN is asserted, data is written into the FIFO on the
rising edge of the WCLK signal. While WEN is held active, data
is continually written into the FIFO on each cycle. The output
port is controlled in a similar manner by a free-running read
clock (RCLK) and a read enable pin (REN). In addition, the
CY7C4282/92 have an output enable pin (OE). The read and
write clocks may be tied together for single-clock operation or
the two clocks may be run independently for asynchronous
read/write applications. Clock frequencies up to 100 MHz are
achievable.
D0-8
Logic Block Diagram
INPUT
REGISTER
WCLK WEN
FLAG
PROGRAM
REGISTER
WRITE
CONTROL
FF
FLAG
LOGIC
Dual Port
RAM Array
64K x 9
128K x 9
WRITE
POINTER
RS
PAF/XO
RESET
LOGIC
EXPANSION
LOGIC
THREE-STATE
OUTPUT REGISTER
PAF/XO
READ
CONTROL
OE
Q0 − 8
Cypress Semiconductor Corporation
Document #: 38-06009 Rev. *B
PAE
READ
POINTER
FL/RT
XI/LD
EF
•
3901 North First Street
RCLK REN
•
San Jose, CA 95134
•
408-943-2600
Revised August 21, 2003
CY7C4282
CY7C4292
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CY7C4282
CY7C4292
Q5
Q4
GND
Q3
Q2
VCC
Q1
Q0
GND
N/C
FF
EF
OE
GND
FL/RT
N/C
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
D1
D0
N/C
N/C
N/C
VCC
PAF/XO
PAE
N/C
N/C
N/C
N/C
N/C
GND
REN
RCLK
WEN
RS
D8
D7
D6
N/C
N/C
N/C
N/C
N/C
N/C
N/C
D5
D4
D3
D2
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Pin Configuration
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
WCLK
XI/LD
GND
N/C
N/C
N/C
N/C
N/C
VCC
N/C
N/C
Q8
Q7
GND
Q6
N/C
STQFP
Top View
Selection Guide
7C4282/92-10
7C4282/92-15
Maximum Frequency
7C4282/92-25
Unit
100
66.7
40
MHz
Maximum Access Time
8
10
15
ns
Minimum Cycle Time
10
15
25
ns
Minimum Data or Enable Set-up
3
4
6
ns
Minimum Data or Enable Hold
0.5
1
1
ns
8
10
15
ns
Commercial
40
40
40
mA
Industrial
45
Maximum Flag Delay
Active Power Supply Current (ICC)
CY7C4282
CY7C4292
Density
64k x 9
128k x 9
Package
64-pin 10x10 STQFP
64-pin 10x10 STQFP
Pin Definitions
Signal
Name
Description
I/O
D0 − 8
Data Inputs
I Data Inputs for 9-bit bus.
Description
Q0 − 8
Data Outputs
O Data Outputs for 9-bit bus.
WEN
Write Enable
I The only write enable when device is configured to have programmable flags. Data is
written on a LOW-to-HIGH transition of WCLK when WEN is asserted and FF is HIGH.
REN
Read Enable
I Enables the device for Read operation. REN must be asserted LOW to allow a read
operation.
WCLK
Write Clock
I The rising edge clocks data into the FIFO when WEN is LOW and the FIFO is not Full. When
LD is asserted, WCLK writes data into the programmable flag-offset register.
Document #: 38-06009 Rev. *B
Page 2 of 16
CY7C4282
CY7C4292
Pin Definitions
Signal
Name
Description
RCLK
Read Clock
I/O
Description
I The rising edge clocks data out of the FIFO when REN is LOW and the FIFO is not Empty.
When LD is LOW, RCLK reads data out of the programmable flag-offset register.
EF
Empty Flag
O When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
FF
Full Flag
O When FF is LOW, the FIFO is full. FF is synchronized to WCLK.
PAE
Programmable
Almost Empty
O When PAE is LOW, the FIFO is almost empty based on the almost empty offset value
programmed into the FIFO. PAE is synchronized to RCLK.
PAF/XO
Programmable
O Dual-Mode Pin. Cascaded – Connected to XI of next device. Not Cascaded – When PAF is
Almost Full/
LOW, the FIFO is almost full based on the almost full offset value programmed into the FIFO.
Expansion Output
PAF is synchronized to WCLK.
FL/RT
First Load/
Retransmit
I Dual-Mode Pin. Cascaded – The first device in the daisy chain will have FL tied to VSS; all
other devices will have FL tied to VCC. In standard mode or width expansion, FL is tied
to VSS on all devices. Not Cascaded – Retransmit function is available in stand-alone mode
by strobing RT.
XI/LD
Expansion
Input/Load
I Dual-Mode Pin. Cascaded – Connected to XO of previous device. Not Cascaded – LD is
used to write or read the programmable flag offset registers. LD must be asserted low during
reset to enable standalone or width expansion operation. If programmable offset register
access is not required, LD can be tied to RS directly.
OE
Output Enable
I When OE is LOW, the FIFO’s data outputs drive the bus to which they are connected. If
OE is HIGH, the FIFO’s outputs are in High Z (high-impedance) state.
RS
Reset
I Resets device to empty condition. A reset is required before an initial read or write operation
after power-up.
Functional Description (continued)
The CY7C4282/92 provides four status pins: Empty, Full,
Programmable Almost Empty, and Programmable Almost Full.
The Almost Empty/Almost Full flags are programmable to
single word granularity. The programmable flags default to
Empty+7 and Full-7.
The flags are synchronous, i.e., they change state relative to
either the read clock (RCLK) or the write clock (WCLK). When
entering or exiting the Empty and Almost Empty states, the
flags are updated exclusively by the RCLK. The flags denoting
Almost Full, and Full states are updated exclusively by WCLK.
The synchronous flag architecture guarantees that the flags
maintain their status for at least one cycle
All configurations are fabricated using an advanced 0.5µ
CMOS technology. Input ESD protection is greater than
2001V, and latch-up is prevented by the use of guard rings.
Architecture
The CY7C4282/92 consists of an array of 64K to 128K words
of 9 bits each (implemented by a dual-port array of SRAM
cells), a read pointer, a write pointer, control signals (RCLK,
WCLK, REN, WEN, RS), and flags (EF, PAE, PAF, FF).
Resetting the FIFO
Upon power-up, the FIFO must be reset with a Reset (RS)
cycle. This causes the FIFO to enter the Empty condition
signified by EF being LOW. All data outputs (Q0−8) go LOW
tRSF after the rising edge of RS. In order for the FIFO to reset
to its default state, the user must not read or write while RS is
LOW. All flags are guaranteed to be valid tRSF after RS is taken
LOW.
Document #: 38-06009 Rev. *B
During reset of the FIFO, the state of the XI/LD pin determines
if depth expansion operation is used. For depth expansion
operation, XI/LD is tied to XO of the next device. See “Depth
Expansion Configuration” and Figure 3. For standalone or
width-expansion configuration, the XI/LD pin must be asserted
low during reset.
There is a 0-ns hold time requirement for the XI/LD configuration at the RS deassertion edge. This allows the user to tie
XI/LD to RS directly for applications that do not require access
to the flag offset registers.
FIFO Operation
When the WEN is asserted LOW and FF is HIGH, data present
on the D0–8 pins is written into the FIFO on each rising edge
of the WCLK signal. Similarly, when the REN is asserted LOW
and EF is HIGH, data in the FIFO memory will be presented
on the Q0–8 outputs. New data will be presented on each rising
edge of RCLK while REN is active. REN must set up tENS
before RCLK for it to be a valid read function. WEN must occur
tENS before WCLK for it to be a valid write function.
An output enable (OE) pin is provided to three-state the Q0–8
outputs when OE is asserted. When OE is enabled (LOW),
data in the output register will be available to the Q0–8 outputs
after tOE. If devices are cascaded, the OE function will only
output data on the FIFO that is read enabled.
The FIFO contains overflow circuitry to disallow additional
writes when the FIFO is full, and underflow circuitry to disallow
additional reads when the FIFO is empty. An empty FIFO
maintains the data of the last valid read on its Q0–8 outputs
even after additional reads occur.
Page 3 of 16
CY7C4282
CY7C4292
Programming
When LD is held LOW during Reset, this pin is the load (LD)
enable for flag offset programming. In this configuration, LD
can be used to access the four 9-bit offset registers contained
in the CY7C4282/CY7C4292 for writing or reading data to
these registers.
When the device is configured for programmable flags and
both LD and WEN are LOW, the first LOW-to-HIGH transition
of WCLK writes data from the data inputs to the empty offset
least significant bit (LSB) register. The second, third, and
fourth LOW-to-HIGH transitions of WCLK store data in the
empty offset most significant bit (MSB) register, full offset LSB
register, and full offset MSB register, respectively, when LD
and WEN are LOW. The fifth LOW-to-HIGH transition of
WCLK while LD and WEN are LOW writes data to the empty
LSB register again. Figure 1 shows the registers sizes and
default values for the various device types.
64K × 9
8
8
Empty Offset (LSB) Reg.
Default Value = 007h
0
7
0
8
(MSB)
Default Value = 000h
8
0
7
(MSB)
Default Value = 000h
8
Full Offset (LSB) Reg
Default Value = 007h
8
7
WEN
0
0
0
1
No Operation
1
0
Write Into FIFO
1
1
No Operation
WCLK[1]
Selection
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
0
7
Empty Offset (LSB) Reg.
Default Value = 007h
8
LD
128K × 9
0
7
sponding offset registers and the difference between the read
and write pointers.
Table 1. Writing the Offset Registers
0
7
Full Offset (LSB) Reg
Default Value = 007h
0
8
(MSB)
Default Value = 000h
0
(MSB)
Default Value = 000h
Figure 1. Offset Register Location and Default Values
It is not necessary to write to all the offset registers at one time.
A subset of the offset registers can be written; then by bringing
the LD input HIGH, the FIFO is returned to normal read and
write operation. The next time LD is brought LOW, a write
operation stores data in the next offset register in sequence.
The contents of the offset registers can be read to the data
outputs when LD is LOW and REN is LOW. LOW-to-HIGH
transitions of RCLK read register contents to the data outputs.
Writes and reads should not be performed simultaneously on
the offset registers.
Programmable Flag (PAE, PAF) Operation
Whether the flag offset registers are programmed as
described in Table 1 or the default values are used, the
programmable almost-empty flag (PAE) and programmable
almost-full flag (PAF) states are determined by their corre-
The number formed by the empty offset least significant bit
register and empty offset most significant bit register is
referred to as n and determines the operation of PAE. PAE is
synchronized to the LOW-to-HIGH transition of RCLK by one
flip-flop and is LOW when the FIFO contains n or fewer unread
words. PAE is set HIGH by the LOW-to-HIGH transition of
RCLK when the FIFO contains (n + 1) or greater unread words.
The number formed by the full offset least significant bit
register and full offset most significant bit register is referred to
as m and determines the operation of PAF. PAF is synchronized to the LOW-to-HIGH transition of WCLK by one flip-flop
and is set LOW when the number of unread words in the FIFO
is greater than or equal to CY7C4282 (64K – m) and
CY7C4292 (128K – m). PAF is set HIGH by the LOW-to-HIGH
transition of WCLK when the number of available memory
locations is greater than m.
Flag Operation
The CY7C4282/CY7C4292 devices provide four flag pins to
indicate the condition of the FIFO contents. All flags operate
synchronously.
Full Flag
The Full Flag (FF) will go LOW when device is Full. Write
operations are inhibited whenever FF is LOW regardless of the
state of WEN. FF is synchronized to WCLK, i.e., it is exclusively updated by each rising edge of WCLK.
Empty Flag
The Empty Flag (EF) will go LOW when the device is empty.
Read operations are inhibited whenever EF is LOW,
regardless of the state of REN. EF is synchronized to RCLK,
i.e., it is exclusively updated by each rising edge of RCLK.
Note:
1. The same selection sequence applies to reading from the registers. REN is enabled and a read is performed on the LOW-to-HIGH transition of RCLK.
Document #: 38-06009 Rev. *B
Page 4 of 16
CY7C4282
CY7C4292
Programmable Almost Empty/Almost Full Flag
The CY7C4282/CY7C4292 features programmable Almost
Empty and Almost Full Flags. Each flag can be programmed
(described in the Programming section) a specific distance
from the corresponding boundary flags (Empty or Full). When
the FIFO contains the number of words or fewer for which the
flags have been programmed, the PAF or PAE will be
asserted, signifying that the FIFO is either Almost Full or
Almost Empty. See Table 2 for a description of programmable
flags.
Table 2. Status Flags
Number of Words in FIFO
CY7C4282
0
1 to
CY7C4292
0
n[2]
1 to
n[2]
FF
PAF
PAE
EF
H
H
L
L
H
H
L
H
(n + 1) to (65536 − (m + 1))
(n + 1) to (131072 − (m + 1))
H
H
H
H
(65536 − m)
(131072 −
H
L
H
H
L
L
H
H
[3] to 65535
65536
m)[3] to 131071
131072
Retransmit
mitted also. The full depth of the FIFO can be repeatedly
retransmitted.
The retransmit feature is beneficial when transferring packets
of data. It enables the receipt of data to be acknowledged by
the receiver and retransmitted if necessary.
Width-Expansion Configuration
The Retransmit (RT) input is active in the stand-alone and
width expansion modes. The retransmit feature is intended for
use when a number of writes equal to or less than the depth
of the FIFO have occurred and at least one word has been
read since the last RS cycle. A HIGH pulse on RT resets the
internal read pointer to the first physical location of the FIFO.
WCLK and RCLK may be free running but must be disabled
during and tRTR after the retransmit pulse. With every valid
read cycle after retransmit, previously accessed data is read
and the read pointer is incriminated until it is equal to the write
pointer. Flags are governed by the relative locations of the
read and write pointers and are updated during a retransmit
cycle. Data written to the FIFO after activation of RT are trans-
Word width may be increased simply by connecting the corresponding input controls signals of multiple devices.
A composite flag should be created for each of the end-point
status flags (EF and FF). The partial status flags (PAE and
PAF) can be detected from any one device. Figure 2 demonstrates a 18-bit word width by using two CY7C4282/92. Any
word width can be attained by adding additional
CY7C4282/92.
When the CY7C4282/92 is in a Width-Expansion Configuration, the Read Enable (REN) control input can be grounded
(see Figure 2). In this configuration, the Load (LD) pin is set to
LOW at Reset so that the pin operates as a control to load and
read the programmable flag offsets.
Notes:
2. n = Empty Offset (n = 7 default value).
3. m = Full Offset (m = 7 default value).
Document #: 38-06009 Rev. *B
Page 5 of 16
CY7C4282
CY7C4292
RESET (RS)
DATA IN (D) 18
RESET (RS)
9
9
READ CLOCK (RCLK)
WRITE CLOCK (WCLK)
READ ENABLE (REN)
WRITE ENABLE (WEN)
OUTPUT ENABLE (OE)
LOAD (LD)
PROGRAMMABLE(PAE)
PROGRAMMABLE (PAF)
CY7C4282/92
CY7C4282/92
HALF FULL FLAG (HF)
EMPTY FLAG (EF)
FF
FF
EF
EF
9
FULL FLAG (FF)
DATA OUT (Q)
18
9
FIRST LOAD (FL)
EXPANSION IN (XI)
FIRST LOAD (FL)
EXPANSION IN (XI)
Figure 2. Block Diagram of 64K × 9/128K × 9 1M Deep Sync FIFO Memory Used
in a Width Expansion Configuration
Document #: 38-06009 Rev. *B
Page 6 of 16
CY7C4282
CY7C4292
Depth Expansion Configuration
The CY7C4282/92 can easily be adapted to applications
requiring more than 64K/128K words of buffering. Figure 3
shows Depth Expansion using three CY7C4282/92s. Maximum
depth is limited only by signal loading. Follow these steps:
1. The first device must be designated by grounding the First
Load (FL) control input.
2. All other devices must have FL in the HIGH state.
3. The Expansion Out (XO) pin of each device must be tied to
the Expansion In (XI) pin of the next device.
4. EF and FF composite flags are created by O-Ring together
each individual respective flag.
XO
RCLK
WCLK
REN
WEN
OE
RS
7C4282
D 7C4292
Q
VCC
FL
FF
EF
XI
XO
RCLK
WCLK
REN
WEN
OE
RS
7C4282
D
7C4292 Q
DATAIN (D)
DATA OUT (Q)
VCC
FL
FF
EF
XI
WRITECLOCK (WCLK)
WCLK
WRITEENABLE (WEN)
XO
RCLK
WEN
READ CLOCK (RCLK)
READ ENABLE (REN)
REN
RESET (RS)
OUTPUTENABLE (OE)
RS 7C4282 OE
7C4292 Q
D
FF
FF
FL
EF
EF
XI
FIRST LOAD (FL)
Figure 3. Block Diagram of 64Kx9/128Kx9 One Meg Deep Sync FIFO Memory
with Programmable Flags used in Depth Expansion Configuration
Document #: 38-06009 Rev. *B
Page 7 of 16
CY7C4282
CY7C4292
DC Input Voltage .........................................−0.5V to VCC +0.5V
Maximum Ratings[4]
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ....................................... −65°C to +150°C
Ambient Temperature with
Power Applied.................................................... −55°C to +125°C
Supply Voltage to Ground Potential .................−0.5V to +7.0V
DC Voltage Applied to Outputs
in High-Z State ..............................................−0.5V to VCC+0.5V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage........................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current..................................................... > 200 mA
Operating Range
Range
Ambient Temperature
VCC
Commercial
0°C to +70°C
5V ± 10%
Industrial[5]
−40°C to +85°C
5V ± 10%
Electrical Characteristics Over the Operating Range[6]
7C4282/92−10 7C4282/92−15 7C4282/92−25
Parameter
Description
Test Conditions
Min.
Max.
VOH
Output HIGH Voltage
VCC = Min.,
IOH = −2.0 mA
VOL
Output LOW Voltage
VCC = Min.,
IOL = 8.0 mA
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
IIX
Input Leakage Current
VCC = Max.
IOZL
IOZH
Output OFF,
High Z Current
OE > VIH,
VSS < VO< VCC
ICC1[7]
Active Power Supply
Current
Com’l
40
Ind
45
Average Standby
Current
Com’l
2
Ind
2
ISB[8]
2.4
Min.
Max.
2.4
0.4
2.0
Min.
Max.
2.4
V
0.4
VCC
2.0
−0.5
0.8
−10
+10
−10
+10
Unit
0.4
V
VCC
V
VCC
2.0
−0.5
0.8
−0.5
0.8
V
−10
+10
−10
+10
µA
−10
+10
−10
+10
µA
40
40
mA
mA
2
2
mA
mA
Capacitance[9]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 5.0V
Max.
Unit
5
pF
7
pF
AC Test Loads and Waveforms[10, 11]
R11.1K Ω
ALL INPUT PULSES
5V
OUTPUT
CL
INCLUDING
JIG AND
SCOPE
Equivalent to:
THÉVENIN EQUIVALENT
410 Ω
OUTPUT
3.0V
R2
680Ω
90%
10%
GND
≤ 3 ns
90%
10%
≤ 3 ns
1.91V
Notes:
4. The voltage on any input or I/O pin cannot exceed the power pin during power-up.
5. TA is the “instant on” case temperature.
6. See the last page of this specification for Group A subgroup testing information.
7. Input signals switch from 0V to 3V with a rise/fall time of less than 3 ns, clocks and clock enables switch at maximum frequency 20Mhz, while data inputs switch
at 10 MHz. Outputs are unloaded.
8. All inputs = VCC − 0.2V, except WCLK and RCLK (which are switching at frequency = 0 MHz). All outputs are unloaded.
9. Tested initially and after any design or process changes that may affect these parameters.
10. CL = 30 pF for all AC parameters except for tOHZ.
11. CL = 5 pF for tOHZ.
Document #: 38-06009 Rev. *B
Page 8 of 16
CY7C4282
CY7C4292
Switching Characteristics Over the Operating Range
Parameter
Description
7C4282/92-10
7C4282/92-15
7C4282/92-25
Min.
Min.
Min.
Max.
Max.
Max.
Unit
40
MHz
15
ns
tS
Clock Cycle Frequency
tA
Data Access Time
2
tCLK
Clock Cycle Time
10
15
25
ns
tCLKH
Clock HIGH Time
4.5
6
10
ns
tCLKL
Clock LOW Time
4.5
6
10
ns
tDS
Data Set-up Time
3
4
6
ns
tDH
Data Hold Time
0.5
1
1
ns
tENS
Enable Set-up Time
3
4
6
ns
tENH
Enable Hold Time
0.5
1
1
ns
tRS
Reset Pulse Width[12]
10
15
25
ns
tRSS
Reset Set-up Time
8
10
15
ns
tRSR
Reset Recovery Time
8
tRSF
Reset to Flag and Output Time
tPRT
Retransmit Pulse Width
60
60
60
ns
tRTR
Retransmit Recovery Time
90
90
90
ns
tOLZ
Output Enable to Output in Low
tOE
Output Enable to Output Valid
100
8
66.7
2
10
10
Z[13]
0
3
[13]
10
2
15
15
0
7
3
7
3
ns
25
0
8
3
8
3
ns
ns
12
ns
tOHZ
Output Enable to Output in High Z
tWFF
Write Clock to Full Flag
tREF
Read Clock to Empty Flag
8
10
15
ns
tPAF
Clock to Programmable Almost-Full Flag
8
10
15
ns
tPAE
Clock to Programmable Almost-Full Flag
tSKEW1
Skew Time between Read Clock and Write Clock
for Empty Flag and Full Flag
5
6
10
ns
tSKEW2
Skew Time between Read Clock and Write Clock
for Almost-Empty Flag and Almost-Full Flag
10
15
18
ns
3
8
10
8
10
12
ns
15
ns
15
ns
Notes:
12. Pulse widths less than minimum values are not allowed.
13. Values guaranteed by design, not currently tested.
Document #: 38-06009 Rev. *B
Page 9 of 16
CY7C4282
CY7C4292
Switching Waveforms
Write Cycle Timing
tCLK
tCLKH
tCLKL
WCLK
tDS
tDH
D0 –D17
tENS
tENH
WEN
NO OPERATION
tWFF
tWFF
FF
tSKEW1 [14]
RCLK
REN
Read Cycle Timing
tCLK
tCLKH
tCLKL
RCLK
tENS
tENH
REN
NO OPERATION
tREF
tREF
EF
tA
VALID DATA
Q0 –Q17
tOLZ
tOHZ
tOE
OE
tSKEW1
[15]
WCLK
WEN
Notes:
14. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time between the rising
edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK rising edge.
15. tSKEW1 is also the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. It the time between the
rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then EF may not change state until the next RCLK rising edge.
Document #: 38-06009 Rev. *B
Page 10 of 16
CY7C4282
CY7C4292
Switching Waveforms (continued)
Reset Timing [16]
tRSS
[17]
LD
tRS
RS
tRSR
REN, WEN
tRSF
EF,PAE
tRSF
FF,PAF
tRSF
[18]
OE=1
Q0 – Q8
OE=0
First Data Word Latency after Reset with Simultaneous Read and Write
WCLK
tDS
D0 –D8
D0 (FIRSTVALID WRITE)
D1
D2
D3
D4
tENS
[19]
tFRL
WEN
tSKEW1
RCLK
tREF
EF
REN
tA
Q0 –Q8
[20]
tA
D0
D1
tOLZ
tOE
OE
4282–9
Note:
16. The clocks (RCLK, WCLK) can be free-running during reset.
17. For standalone or width expansion configuration only.
18. After reset, the outputs will be LOW if OE = 0 and three-state if OE=1.
19. When tSKEW1 > minimum specification, tFRL (maximum) = tCLK + tSKEW2. When tSKEW1 < minimum specification, tFRL (maximum) = either 2*tCLK + tSKEW1 or tCLK + tSKEW1.
The Latency Timing applies only at the Empty Boundary (EF = LOW).
20. The first word is available the cycle after EF goes HIGH, always.
Document #: 38-06009 Rev. *B
Page 11 of 16
CY7C4282
CY7C4292
Switching Waveforms (continued)
Empty Flag Timing
WCLK
tDS
tDS
DATA WRITE 2
DATA WRITE 1
D0 –D8
tENH
tENS
tENH
tENS
WEN
tFRL
[19]
tFRL
[19]
RCLK
tREF
tREF
tSKEW1
tREF
tSKEW1
EF
REN
LOW
OE
tA
DATA IN OUTPUT REGISTER
Q0 –Q8
Full Flag Timing
DATA READ
NO WRITE
NO WRITE
WCLK
tSKEW1[14]
[14]
tDS
DATA WRITE
tSKEW1
DATA WRITE
D0 –D8
tWFF
tWFF
tWFF
FF
WEN
RCLK
tENH
REN
OE
tENH
tENS
tENS
LOW
tA
Q0 –Q8
DATA IN OUTPUT REGISTER
Document #: 38-06009 Rev. *B
tA
DATA READ
NEXT DATA READ
Page 12 of 16
CY7C4282
CY7C4292
Switching Waveforms (continued)
Programmable Almost Empty Flag Timing
tCLKL
tCLKH
WCLK
tENS tENH
WEN
PAE
N + 1 WORDS
IN FIFO
Note [22]
tSKEW2
[21]
tPAE
Note 23 t
PAE
RCLK
tENS
tENS tENH
REN
Programmable Almost Full Flag Timing
tCLKL
tCLKH
Note 24
WCLK
tENS tENH
WEN
tPAF
PAF
FULL − M WORDS
IN FIFO [25]
FULL − (M+1)WORDS
IN FIFO
tSKEW2 [26]
tPAF
RCLK
tENS
tENS tENH
REN
Note:
21. tSKEW2 is the minimum time between a rising WCLK and a rising RCLK edge for PAE to change state during that clock cycle. If the time between the edge of WCLK and the rising
RCLK is less than tSKEW2, then PAE may not change state until the next RCLK.
22. PAE offset = n.
23. If a read is preformed on this rising edge of the read clock, there will be Empty + (n−1) words in the FIFO when PAE goes LOW
24. If a write is performed on this rising edge of the write clock, there will be Full − (m−1) words of the FIFO when PAF goes LOW.
25. 16,384 − m words for CY7C4282, 32,768 − m words for CY4292.
26. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to change during that clock cycle. If the time between the rising edge of RCLK and
the rising edge of WCLK is less than tSKEW2, then PAF may not change state until the next WCLK.
Document #: 38-06009 Rev. *B
Page 13 of 16
CY7C4282
CY7C4292
Switching Waveforms (continued)
Write Programmable Registers
tCLK
tCLKL
tCLKH
WCLK
tENS
tENH
LD
tENS
WEN
tDS
tDH
D0 –D8
PAE OFFSET
LSB
PAE OFFSET
MSB
PAF OFFSET
LSB
PAF OFFSET
MSB
Read Programmable Registers
tCLK
tCLKL
tCLKH
RCLK
tENS
LD
tENH
tENS
PAF OFFSET
MSB
REN
tA
UNKNOWN
Q0 –Q15
Retransmit Timing
PAE OFFSET LSB
PAE OFFSET MSB
PAF OFFSET
LSB
[27, 28, 29]
FL/RT
tPRT
tRTR
REN/WEN
EF/FF
Notes:
27. Clocks are free running in this case.
28. The flags may change state during Retransmit as a result of the offset of the read and write pointers, but flags will be valid at tRTR.
29. For the synchronous PAE and PAF flags, an appropriate clock cycle is necessary after tRTR to update these flags.
Document #: 38-06009 Rev. *B
Page 14 of 16
CY7C4282
CY7C4292
Ordering Information
64K x 9 Deep Sync FIFO
Speed
(ns)
10
Ordering Code
Package
Name
Package Type
Operating
Range
CY7C4282-10ASC
A64
64-Lead 10x10 Thin Quad Flatpack
Commercial
CY7C4282-10ASI
A64
64-Lead 10x10 Thin Quad Flatpack
Industrial
15
CY7C4282-15ASC
A64
64-Lead 10x10 Thin Quad Flatpack
Commercial
25
CY7C4282-25ASC
A64
64-Lead 10x10 Thin Quad Flatpack
Commercial
128K x 9 Deep Sync FIFO
Speed
(ns)
10
Ordering Code
CY7C4292-10ASC
Package
Name
A64
Package Type
64-Lead 10x10 Thin Quad Flatpack
Operating
Range
Commercial
CY7C4292-10ASI
A64
64-Lead 10x10 Thin Quad Flatpack
Industrial
15
CY7C4292-15ASC
A64
64-Lead 10x10 Thin Quad Flatpack
Commercial
25
CY7C4292-25ASC
A64
64-Lead 10x10 Thin Quad Flatpack
Commercial
Package Diagram
64-Pin Thin Plastic Quad Flat Pack (10 x 10 x 1.4 mm) A64
51-85051-*A
All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-06009 Rev. *B
Page 15 of 16
© Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C4282
CY7C4292
Document History Page
Document Title: CY7C4282/CY7C4292 64K/128K × 9 Deep Sync FIFOs with Retransmit and Depth Expansion
Document Number: 38-06009
REV.
ECN NO.
Issue Date
Orig. of
Change
Description of Change
**
106470
07/17/01
SZV
Changed from Spec Number: 38-00594 to 38-06009
*A
122261
12/26/02
RBI
Added power-up requirements to Maximum Ratings Information
*B
127855
08/25/03
FSG
Removed Preliminary
Switching Waveforms section: “Empty Flag Timing” tSKEW2 changed to
tSKEW1 (typo)
Document #: 38-06009 Rev. *B
Page 16 of 16