Intersil EL5170IYZ 100mhz differential twisted-pair driver Datasheet

EL5170, EL5370
®
Data Sheet
May 7, 2007
100MHz Differential Twisted-Pair Drivers
Features
The EL5170 and EL5370 are single and triple high bandwidth
amplifiers with a fixed gain of 2. They are primarily targeted for
applications such as driving twisted-pair lines in component
video applications. The inputs signal can be in either singleended or differential form but the outputs are always in
differential form.
• Fully differential inputs and outputs
FN7309.7
• Differential input range ±2.3V typ.
• 100MHz 3dB bandwidth at fixed gain of 2
• 1100V/µs slew rate
• Single 5V or dual ±5V supplies
The output common mode level for each channel is set by
the associated VREF pin, which have a -3dB bandwidth of
over 70MHz. Generally, these pins are grounded but can be
tied to any voltage reference.
All outputs are short circuit protected to withstand temporary
overload condition.
The EL5170 and EL5370 are specified for operation over the
full -40°C to +85°C temperature range.
• 50mA maximum output current
• Low power - 7.4mA per channel
• Pb-free plus anneal available (RoHS compliant)
Applications
• Twisted-pair drivers
• Differential line drivers
• VGA over twisted-pairs
Pinouts
• ADSL/HDSL drivers
EL5370
(24 LD QSOP)
TOP VIEW
EL5170
(8 LD SOIC, MSOP)
TOP VIEW
IN+ 1
EN 2
IN- 3
REF 4
EN 1
8 OUT+
+
-
INP1 2
7 VS6 VS+
5 OUT-
+
-
• Transmission of analog signals in a noisy environment
24 OUT1
23 OUT1B
INN1 3
22 NC
REF1 4
21 VSP
NC 5
20 VSN
19 NC
INP2 6
INN2 7
REF2 8
+
-
NC 9
INP3 10
INN3 11
REF3 12
1
• Single ended to differential amplification
18 OUT2
17 OUT2B
16 NC
+
-
15 OUT3
14 OUT3B
13 NC
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002, 2003, 2004, 2006, 2007. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
EL5170, EL5370
Ordering Information
PART NUMBER
PART MARKING
TAPE & REEL
PACKAGE
PKG. DWG. #
EL5170IS
5170IS
-
8 Ld SOIC (150 mil)
MDP0027
EL5170IS-T7
5170IS
7”
8 Ld SOIC (150 mil)
MDP0027
EL5170IS-T13
5170IS
13”
8 Ld SOIC (150 mil)
MDP0027
EL5170ISZ (Note)
5170ISZ
-
8 Ld SOIC (150 mil) (Pb-free)
MDP0027
EL5170ISZ-T7 (Note)
5170ISZ
7”
8 Ld SOIC (150 mil) (Pb-free)
MDP0027
EL5170ISZ-T13 (Note)
5170ISZ
13”
8 Ld SOIC (150 mil) (Pb-free)
MDP0027
EL5170IY
g
-
8 Ld MSOP (3.0mm)
MDP0043
EL5170IY-T7
g
7”
8 Ld MSOP (3.0mm)
MDP0043
EL5170IY-T13
g
13”
8 Ld MSOP (3.0mm)
MDP0043
EL5170IYZ (Note)
BAAVA
-
8 Ld MSOP (3.0mm) (Pb-free)
MDP0043
EL5170IYZ-T7 (Note)
BAAVA
7”
8 Ld MSOP (3.0mm) (Pb-free)
MDP0043
EL5170IYZ-T13 (Note)
BAAVA
13”
8 Ld MSOP (3.0mm) (Pb-free)
MDP0043
EL5370IU
EL5370IU
-
24 Ld QSOP (150 mil)
MDP0040
EL5370IU-T7
EL5370IU
7”
24 Ld QSOP (150 mil)
MDP0040
EL5370IU-T13
EL5370IU
13”
24 Ld QSOP (150 mil)
MDP0040
EL5370IUZ (Note)
EL5370IUZ
-
24 Ld QSOP (150 mil) (Pb-free)
MDP0040
EL5370IUZ-T7 (Note)
EL5370IUZ
7”
24 Ld QSOP (150 mil) (Pb-free)
MDP0040
EL5370IUZ-T13 (Note)
EL5370IUZ
13”
24 Ld QSOP (150 mil) (Pb-free)
MDP0040
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2
FN7309.7
May 7, 2007
EL5170, EL5370
Absolute Maximum Ratings (TA = +25°C)
Thermal Information
Supply Voltage (VS+ to VS-) . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6V
Maximum Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . ±60mA
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +135°C
Recommended Operating Temperature . . . . . . . . . .-40°C to +85°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER
VS+ = +5V, VS- = -5V, TA = +25°C, VIN = 0V, AV = 2, RLD = 200Ω, CLD = 1pF, Unless Otherwise Specified.
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
AC PERFORMANCE
BW
-3dB Bandwidth
100
MHz
BW
± 0.1dB Bandwidth
12
MHz
SR
Slew Rate
VOUT = 2VP-P, 20% to 80%
1100
V/µs
TSTL
Settling Time to 0.1%
VOUT = 2VP-P
20
ns
TOVR
Output Overdrive Recovery time
40
ns
800
VREFBW (-3dB) VREF -3dB Bandwidth
AV =1, CLD = 2.7pF
70
MHz
VREFSR+
VREF Slew Rate - Rise
VOUT = 2VP-P, 20% to 80%
125
V/µs
VREFSR-
VREF Slew Rate - Fall
VOUT = 2VP-P, 20% to 80%
65
V/µs
VN
Input Voltage Noise
f = 10kHz
28
nV/√Hz
HD2
Second Harmonic Distortion
VOUT = 2VP-P, 1MHz
-79
dBc
HD2
Second Harmonic Distortion
VOUT = 2VP-P, 10MHz
-65
dBc
HD3
Third Harmonic Distortion
VOUT = 2VP-P, 1MHz
-62
dBc
HD3
Third Harmonic Distortion
VOUT = 2VP-P, 10MHz
-43
dBc
dG
Differential Gain at 3.58MHz
RLD = 300Ω, AV = 2
0.14
%
dθ
Differential Phase at 3.58MHz
RLD = 300Ω, AV = 2
0.38
°
eS
Channel Separation - For EL5370 only
at f = 1MHz
85
dB
INPUT CHARACTERISTICS
VOS
Input Referred Offset Voltage
IIN
Input Bias Current (VIN, VINB)
IREF
Input Bias Current at REF Pin
±6
±25
mV
-10
-6
-2
µA
VREF = +3.2V
0.5
1.25
3
µA
VREF = -3.2V
-1
0
+1
µA
1.98
2
2.02
V
Gain
Gain Accuracy
VIN = ±1V
RIN
Differential Input Resistance
300
kΩ
CIN
Differential Input Capacitance
1
pF
DMIR
Differential Mode Input Range
±2.1
±2.3
V
CMIR+
Common Mode Positive Input Range at
VIN+, VIN-
3.2
3.4
V
CMIR-
Common Mode Negative Input Range at
VIN+, VIN-
3
-4.5
-4.2
V
FN7309.7
May 7, 2007
EL5170, EL5370
Electrical Specifications
PARAMETER
VREFIN
VS+ = +5V, VS- = -5V, TA = +25°C, VIN = 0V, AV = 2, RLD = 200Ω, CLD = 1pF, Unless Otherwise Specified.
(Continued)
DESCRIPTION
CONDITIONS
Reference Input Voltage Range - Positive VIN+ = VIN- = 0V
MIN
TYP
3.4
3.8
Reference Input Voltage Range Negative
VREFOS
Output Offset Relative to VREF
CMRR
Input Common Mode Rejection Ratio
MAX
UNIT
V
-3.3
-3
V
-140
60
+140
mV
VIN = ±2.5V
65
84
dB
RLD = 200Ω
3.3
3.6
V
OUTPUT CHARACTERISTICS
VOUT
Positive Output Voltage Swing
Negative Output Voltage Swing
IOUT(Max)
ROUT
-3.3
Maximum Output Current
-3
V
RL = 10Ω (EL5170)
±50
±80
mA
RL = 10Ω (EL5370)
±70
±85
mA
60
mΩ
Output Impedance
SUPPLY
VSUPPLY
Supply Operating Range
IS(ON)
Power Supply Current - Per channel
6
IS(OFF)+
Positive Power Supply Current - Disabled EN pin tied to 4.8V (EL5170)
IS(OFF)-
Negative Power Supply Current Disabled
IS(OFF)+
Positive Power Supply Current - Disabled EN pin tied to 4.8V (EL5370)
IS(OFF)-
Negative Power Supply Current Disabled
PSRR
Power Supply Rejection Ratio
VS+ to VS-
4.75
11
V
7.4
8.4
mA
60
80
100
µA
-150
-120
-90
µA
0.5
2
5
µA
-150
-120
-90
µA
VS from ±4.5V to ±5.5V (EL5170)
70
83
dB
VS from ±4.5V to ±5.5V (EL5370)
65
83
dB
ENABLE
tEN
Enable Time
200
ns
tDS
Disable Time
1
µs
VIH
EN Pin Voltage for Power-up
VIL
EN Pin Voltage for Shut-down
IIH-EN
EN Pin Input Current High - per channel
At VEN = 5V
IIL-EN
EN Pin Input Current Low - per channel
At VEN = 0V
VS+ 1.5
VS+ 0.5
V
40
-6
V
-3
50
µA
µA
Pin Descriptions
EL5170
EL5370
PIN NAME
1
2, 6, 10
IN+, INP1, 2, 3
PIN FUNCTION
Non-inverting inputs
Enable
2
1
EN
3
3, 7, 11
IN-, INN1, 2, 3
4
4, 8, 12
REF1, 2, 3
5
14, 17, 23
6
21
VS+, VSP
Positive supply
7
20
VS-, VSN
Negative supply
8
15, 18, 24
OUT+, OUT1, 2, 3
5, 9, 13, 16, 19, 22
NC
4
Inverting inputs
Reference input, sets common-mode output voltage
OUT-, OUT1B, 2B, 3B Inverting outputs
Non-inverting outputs
No connects, grounded for best crosstalk performance
FN7309.7
May 7, 2007
Connection Diagrams
EL5170
RS1
50Ω
-5V
RRT2
1 INP
INP
LOADP
OUT 8
50Ω
EN
2 EN
VSN 7
INN
3 INN
VSP 6
REF
4 REF
OUTB 5
RRT2
5
RS2
50Ω
LOADN
50Ω
RS3
50Ω
+5V
+5V
RRT1
ENABLE
1 EN
LD1
OUT1 24
RRT1B
INP1
2 INP1
50Ω
LD1B
OUT1B 23
50Ω
INN1
3 INN1
NC 22
REF1
4 REF1
VSP 21
5 NC
VSN 20
INP2
6 INP2
NC 19
INN2
7 INN2
OUT2 18
RRT2
LD2
RRT2B
8 REF2
REF2
50Ω
LD2B
OUT2B 17
50Ω
9 NC
NC 16
RRT3
INP3
10 INP3
OUT3 15
RRT3B
INN3
11 INN3
OUT3B 14
50Ω
REF3
12 REF3
RSP1
50Ω
RSN1
50Ω
RSR1
50Ω
RSP2
50Ω
RSN2
50Ω
RSR2
50Ω
RSP3
50Ω
RSN3
50Ω
NC 13
RSR3
50Ω
-5V
LD3
50Ω
LD3B
EL5170, EL5370
EL5370
FN7309.7
May 7, 2007
EL5170, EL5370
Typical Performance Curves
CLD = 1pF, VODP-P = 200mV
10
9
9
8
8
7
7
6
VOP-P = 200mV
5
4
3
GAIN (dB)
GAIN (dB)
VS = ±5V, AV = 2, RLD = 200Ω, CLD = 1pF
10
RLD = 500Ω
6
5
4
RLD = 200Ω
3
VOP-P = 2V
2
RLD = 1kΩ
2
1
0
100K
1M
10M
100M
RLD = 100Ω
1
VOP-P = 1V
0
100K
1G
10M
1M
FREQUENCY (Hz)
VS = ±5V, RLD = 200Ω, VODP-P = 200mV
4
11
2
GAIN (dB)
CLD = 40pF
8
GAIN (dB)
3
CLD = 75pF
9
7
6
0
-1
VREF = 1VP-P
-3
4
CLD = 0pF
3
-4
-5
2
1
100K
VREF = 200mVP-P
1
-2
CLD = 20pF
5
1G
FIGURE 2. SMALL SIGNAL FREQUENCY RESPONSE vs RLD
FIGURE 1. FREQUENCY RESPONSE
10
100M
FREQUENCY (Hz)
1M
10M
100M
-6
1M
1G
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 4. FREQUENCY RESPONSE vs VREF
FIGURE 3. SMALL SIGNAL FREQUENCY RESPONSE vs CLD
100Ω
VINCM
+
-
VODM
VOCM
100Ω
0
COMMON MODE REJECTION (dB)
-10
-10
-20
PSRR (dB)
-30
-40
-50
PSRR-
-60
-70
PSRR+
-80
-90
100K
1M
10M
FREQUENCY (Hz)
FIGURE 5. POWER SUPPLY REJECTION RATIO vs
FREQUENCY
6
100M
-20
-30
-40
-50
VOCM/VINCM
-60
-70
VODM/VINCM
-80
-90
100K
1M
10M
100M
FREQUENCY (Hz)
FIGURE 6. COMMON MODE REJECTION vs FREQUENCY
FN7309.7
May 7, 2007
EL5170, EL5370
Typical Performance Curves
(Continued)
100Ω
VIN
+
-
RT
VCM
VODM
R
100Ω
1000
VOLTAGE NOISE (nV/√Hz)
0
BALANCE ERROR (dB)
-10
-20
-30
-40
VOCM/VODM
-50
-60
100K
1M
10M
100
10
10
100M
100
1K
1M
10M
FIGURE 8. INPUT VOLTAGE NOISE vs FREQUENCY
FIGURE 7. DIFFERENTIAL MODE OUTPUT BALANCE
ERROR vs FREQUENCY
RLD = 200Ω
-40
110
-50
CH2<=>CH1
CH3<=>CH2
-60
105
100
BW (MHz)
CH2<=>CH3
-70
CH1<=>CH2
-80
-90
95
90
CH3<=>CH1
-100
85
CH1<=>CH3
-110
100K
1M
10M
80
4
100M
6
5
8
7
FREQENCY (Hz)
-30
7.76
11
12
VS = ±5V, RLD = 200Ω, VOP-P = 2V
HD3
-40
DISTORTION (dB)
IS+
7.72
IS-
7.7
10
FIGURE 10. BANDWIDTH vs SUPPLY VOLTAGE
7.78
7.74
9
VS (V)
FIGURE 9. CHANNEL ISOLATION vs FREQUENCY
IS (mA)
100K
FREQENCY (Hz)
FREQUENCY (Hz)
CHANNEL ISOLATION (dB)
10K
7.68
7.66
7.64
7.62
-50
-60
HD2
-70
-80
7.6
-90
7.58
4
5
6
8
7
9
10
11
VS (V)
FIGURE 11. SUPPLY CURRENT vs SUPPLY VOLTAGE
7
0
2
4
6
8
10
12
14
16
18
20
FREQUENCY (MHz)
FIGURE 12. HARMONIC DISTORTION vs FREQUENCY
FN7309.7
May 7, 2007
EL5170, EL5370
Typical Performance Curves
(Continued)
500mV/DIV
0.5V/DIV
20ns/DIV
40ns/DIV
FIGURE 13. VCOM TRANSIENT RESPONSE
FIGURE 14. LARGE SIGNAL TRANSIENT RESPONSE
100mV/DIV
20ns/DIV
FIGURE 16. DISABLED RESPONSE
FIGURE 15. SMALL SIGNAL TRANSIENT RESPONSE
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
POWER DISSIPATION (W)
1.2
1
870mW
0.8
QSOP24
θJA=115°C/W
625mW
0.6
SO8
θJA=160°C/W
0.4 486mW
MSOP8
θJA=206°C/W
0.2
0
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 17. ENABLED RESPONSE
8
FIGURE 18. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FN7309.7
May 7, 2007
EL5170, EL5370
Typical Performance Curves
(Continued)
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
POWER DISSIPATION (W)
1.4
1.2
1.136W
1
909mW
0.8
QSOP24
θJA=88°C/W
SO8
θJA=110°C/W
870mW
0.6
MSOP8/10
θJA=115°C/W
0.4
0.2
0
0
25
75 85 100
50
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 19. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
Simplified Schematic
200Ω
VS+
R3
R1
R4
R2
R7
IN+
IN-
FBP
R8
FBN
VB1
OUT+
RCD
REF
RCD
OUT-
VB2
CC
R9
R10
CC
R5
R6
VS-
400Ω
Description of Operation and Application
Information
Product Description
The EL5170 and EL5370 are wide bandwidth, low power
and single/differential ended to differential output amplifiers.
They have a fixed gain of 2. The EL5170 is a single channel
differential amplifier. The EL5370 is a triple channel
differential amplifier. The EL5170 and EL5370 have a -3dB
bandwidth of 100MHz while driving a 200Ω differential load.
The EL5170 and EL5370 are available with a power down
feature to reduce the power while the amplifiers are
disabled.
9
200Ω
Input, Output and Supply Voltage Range
The EL5170 and EL5370 have been designed to operate
with a single supply voltage of 5V to 10V or a split supplies
with its total voltage from 5V to 10V. The amplifiers have an
input common mode voltage range from -4.5V to 3.4V for
±5V supply. The differential mode input range (DMIR)
between the two inputs is from -2.3V to +2.3V. The input
voltage range at the REF pin is from -3.3V to 3.8V. If the
input common mode or differential mode signal is outside the
above-specified ranges, it will cause the output signal
distorted.
The output of the EL5170 and EL5370 can swing from -3.3V
to 3.6V at 200Ω differential load at ±5V supply. As the load
resistance becomes lower, the output swing is reduced.
FN7309.7
May 7, 2007
EL5170, EL5370
Differential and Common Mode Gain Settings
As shown at the simplified schematic, since the feedback
resistors RF and the gain resistor are integrated with 200Ω
and 400Ω, the EL5170 and EL5370 have a fixed gain of 2.
The common mode gain is always one.
Driving Capacitive Loads and Cables
The EL5170 and EL5370 can drive 75pF differential
capacitor in parallel with 200Ω differential load with less than
3.5dB of peaking. If less peaking is desired in applications, a
small series resistor (usually between 5Ω to 50Ω) can be
placed in series with each output to eliminate most peaking.
However, this will reduce the gain slightly.
When used as a cable driver, double termination is always
recommended for reflection-free performance. For those
applications, a back-termination series resistor at the
amplifier’s output will isolate the amplifier from the cable and
allow extensive capacitive drive. However, other applications
may have high capacitive loads without a back-termination
resistor. Again, a small series resistor at the output can help
to reduce peaking.
Disable/Power-Down
The EL5170 and EL5370 can be disabled and placed their
outputs in a high impedance state. The turn off time is about
1µs and the turn on time is about 200ns. When disabled, the
amplifier’s supply current is reduced to 2µA for IS+ and
120µA for IS- typically, thereby effectively eliminating the
power consumption. The amplifier’s power down can be
controlled by standard CMOS signal levels at the ENABLE
pin. The applied logic signal is relative to VS+ pin. Letting the
EN pin float or applying a signal that is less than 1.5V below
VS+ will enable the amplifier. The amplifier will be disabled
when the signal at EN pin is above VS+ -0.5V.
Output Drive Capability
The EL5170 and EL5370 have internal short circuit
protection. Its typical short circuit current is ±80mA. If the
output is shorted indefinitely, the power dissipation could
easily increase such that the part will be destroyed.
Maximum reliability is maintained if the output current never
exceeds ±60mA. This limit is set by the design of the internal
metal interconnect.
Power Dissipation
With the high output drive capability of the EL5170 and
EL5370 it is possible to exceed the 125°C absolute
maximum junction temperature under certain load current
conditions. Therefore, it is important to calculate the
maximum junction temperature for the application to
determine if the load conditions or package types need to be
modified for the amplifier to remain in the safe operating
area.
The maximum power dissipation allowed in a package is
determined according to:
10
T JMAX – T AMAX
PD MAX = --------------------------------------------Θ JA
Where:
TJMAX = Maximum junction temperature
TAMAX = Maximum ambient temperature
θJA = Thermal resistance of the package
The maximum power dissipation actually produced by an IC
is the total quiescent supply current times the total power
supply voltage, plus the power in the IC due to the load, or:
ΔV O⎞
⎛
PD = i × ⎜ V S × I SMAX + V S × ------------⎟
R LD ⎠
⎝
Where:
VS = Total supply voltage
ISMAX = Maximum quiescent supply current per channel
ΔVO = Maximum differential output voltage of the
application
RLD = Differential load resistance
ILOAD = Load current
i = Number of channels
By setting the two PDMAX equations equal to each other, we
can solve the output current and RLOAD to avoid the device
overheat.
Power Supply Bypassing and Printed Circuit
Board Layout
As with any high frequency device, a good printed circuit
board layout is necessary for optimum performance. Lead
lengths should be as sort as possible. The power supply pin
must be well bypassed to reduce the risk of oscillation. For
normal single supply operation, where the VS- pin is
connected to the ground plane, a single 4.7µF tantalum
capacitor in parallel with a 0.1µF ceramic capacitor from VS+
to GND will suffice. This same capacitor combination should
be placed at each supply pin to ground if split supplies are to
be used. In this case, the VS- pin becomes the negative
supply rail.
For good AC performance, parasitic capacitance should be
kept to minimum. Use of wire wound resistors should be
avoided because of their additional series inductance. Use
of sockets should also be avoided if possible. Sockets add
parasitic inductance and capacitance that can result in
compromised performance. Minimizing parasitic capacitance
at the amplifier’s inverting input pin is very important. The
feedback resistor should be placed very close to the
inverting input pin. Strip line design techniques are
recommended for the signal traces.
FN7309.7
May 7, 2007
EL5170, EL5370
Typical Applications
0Ω
50
VFB
IN+
50Ω
VIN
EL5170/
EL5370
50
EL5172/
EL5372
VINB
INZO = 100Ω
VOUT
50Ω
VREF
FIGURE 20. TWISTED PAIR DRIVER
0Ω
VFB
+
EL5170/
EL5370
IN-
IN+
VIN
VINB
EL5172/
EL5372
VOUT
VREF
FIGURE 21. DUAL COAXIAL CABLE DRIVER
10V
VIN
IN+
EL5170/
EL5370
IN-
FIGURE 22. SINGLE SUPPLY TWISTED PAIR DRIVER
11
FN7309.7
May 7, 2007
EL5170, EL5370
EL5172/
EL5372
IN+
EL5170/
EL5370
INEL5172
FIGURE 23. DUAL SIGNAL TRANSMISSION CIRCUIT
12
FN7309.7
May 7, 2007
EL5170, EL5370
Small Outline Package Family (SO)
A
D
h X 45°
(N/2)+1
N
A
PIN #1
I.D. MARK
E1
E
c
SEE DETAIL “X”
1
(N/2)
B
L1
0.010 M C A B
e
H
C
A2
GAUGE
PLANE
SEATING
PLANE
A1
0.004 C
0.010 M C A B
L
b
0.010
4° ±4°
DETAIL X
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
INCHES
SYMBOL
SO-14
SO16 (0.300”)
(SOL-16)
SO20
(SOL-20)
SO24
(SOL-24)
SO28
(SOL-28)
TOLERANCE
NOTES
A
0.068
0.068
0.068
0.104
0.104
0.104
0.104
MAX
-
A1
0.006
0.006
0.006
0.007
0.007
0.007
0.007
±0.003
-
A2
0.057
0.057
0.057
0.092
0.092
0.092
0.092
±0.002
-
b
0.017
0.017
0.017
0.017
0.017
0.017
0.017
±0.003
-
c
0.009
0.009
0.009
0.011
0.011
0.011
0.011
±0.001
-
D
0.193
0.341
0.390
0.406
0.504
0.606
0.704
±0.004
1, 3
E
0.236
0.236
0.236
0.406
0.406
0.406
0.406
±0.008
-
E1
0.154
0.154
0.154
0.295
0.295
0.295
0.295
±0.004
2, 3
e
0.050
0.050
0.050
0.050
0.050
0.050
0.050
Basic
-
L
0.025
0.025
0.025
0.030
0.030
0.030
0.030
±0.009
-
L1
0.041
0.041
0.041
0.056
0.056
0.056
0.056
Basic
-
h
0.013
0.013
0.013
0.020
0.020
0.020
0.020
Reference
-
16
20
24
28
Reference
-
N
SO-8
SO16
(0.150”)
8
14
16
Rev. M 2/07
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
13
FN7309.7
May 7, 2007
EL5170, EL5370
Quarter Size Outline Plastic Packages Family (QSOP)
MDP0040
A
QUARTER SIZE OUTLINE PLASTIC PACKAGES FAMILY
D
(N/2)+1
N
INCHES
SYMBOL QSOP16 QSOP24 QSOP28 TOLERANCE NOTES
E
PIN #1
I.D. MARK
E1
1
(N/2)
A
0.068
0.068
0.068
Max.
-
A1
0.006
0.006
0.006
±0.002
-
A2
0.056
0.056
0.056
±0.004
-
b
0.010
0.010
0.010
±0.002
-
c
0.008
0.008
0.008
±0.001
-
D
0.193
0.341
0.390
±0.004
1, 3
E
0.236
0.236
0.236
±0.008
-
E1
0.154
0.154
0.154
±0.004
2, 3
e
0.025
0.025
0.025
Basic
-
L
0.025
0.025
0.025
±0.009
-
L1
0.041
0.041
0.041
Basic
-
N
16
24
28
Reference
-
B
0.010
C A B
e
H
C
SEATING
PLANE
0.007
0.004 C
b
C A B
Rev. F 2/07
NOTES:
L1
A
1. Plastic or metal protrusions of 0.006” maximum per side are not
included.
2. Plastic interlead protrusions of 0.010” maximum per side are not
included.
c
SEE DETAIL "X"
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
0.010
A2
GAUGE
PLANE
L
A1
4°±4°
DETAIL X
14
FN7309.7
May 7, 2007
EL5170, EL5370
Mini SO Package Family (MSOP)
0.25 M C A B
D
MINI SO PACKAGE FAMILY
(N/2)+1
N
E
MDP0043
A
E1
MILLIMETERS
PIN #1
I.D.
1
B
(N/2)
e
H
C
SEATING
PLANE
0.10 C
N LEADS
SYMBOL
MSOP8
MSOP10
TOLERANCE
NOTES
A
1.10
1.10
Max.
-
A1
0.10
0.10
±0.05
-
A2
0.86
0.86
±0.09
-
b
0.33
0.23
+0.07/-0.08
-
c
0.18
0.18
±0.05
-
D
3.00
3.00
±0.10
1, 3
E
4.90
4.90
±0.15
-
E1
3.00
3.00
±0.10
2, 3
e
0.65
0.50
Basic
-
L
0.55
0.55
±0.15
-
L1
0.95
0.95
Basic
-
N
8
10
Reference
-
0.08 M C A B
b
Rev. D 2/07
NOTES:
1. Plastic or metal protrusions of 0.15mm maximum per side are not
included.
L1
2. Plastic interlead protrusions of 0.25mm maximum per side are
not included.
A
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
c
SEE DETAIL "X"
A2
GAUGE
PLANE
L
A1
0.25
3° ±3°
DETAIL X
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Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
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reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
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15
FN7309.7
May 7, 2007
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