1CY74FCT162827T Data sheet acquired from Cypress Semiconductor Corporation. Data sheet modified to remove devices not offered. CY74FCT16827T CY74FCT162827T 20-Bit Buffers/Line Drivers SCCS064B - August 1994 - Revised September 2001 Features • Ioff Supports Partial-Power-Down Mode Operation • Edge-rate control circuitry for significantly improved noise characteristics • Typical output skew < 250 ps • ESD > 2000V • TSSOP (19.6-mil pitch) and SSOP (25-mil pitch) packages • Industrial temperature range of −40˚C to +85˚C • VCC = 5V ± 10% CY74FCT16827T Features: • 64 mA sink current, 32 mA source current • Typical VOLP (ground bounce) <1.0V at VCC = 5V, TA = 25˚C Functional Description The CY74FCT16827T 20-bit buffer/line driver and the CY74FCT162827T 20-bit buffer/line driver provide high-performance bus interface buffering for wide data/address paths or buses carrying parity. These parts can be used as a single 20-bit buffer or two 10-bit buffers. Each 10-bit buffer has a pair of NANDed OE for increased flexibility. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The CY74FCT16827T is ideally suited for driving high-capacitance loads and low-impedance backplanes. The CY74FCT162827T has 24-mA balanced output drivers with current-limiting resistors in the outputs. This reduces the need for external terminating resistors and provides for minimal undershoot and reduced ground bounce. The CY74FCT162827T is ideal for driving transmission lines. CY74FCT162827T Features: • Balanced 24 mA output drivers • Reduced system switching noise • Typical VOLP (ground bounce) <0.6V at VCC = 5V, TA = 25˚C Logic Block Diagrams Pin Configuration SSOP/TSSOP Top View 1OE1 1OE1 1 56 1OE2 1Y1 2 55 1A 1 1Y2 3 54 1A 2 GND 4 53 GND 1Y3 5 52 1A 3 1Y4 6 51 1A 4 VCC 7 50 VCC 8 49 1A 5 1Y6 9 48 1Y7 10 1A 7 GND 1Y8 11 47 46 45 1A 8 1Y9 12 13 44 1A 9 1Y10 14 43 1A 10 2OE1 2Y1 15 42 2A 1 2OE2 2Y2 16 41 2A 2 2Y3 17 40 2A 3 GND 18 39 GND 2Y4 19 38 2A 4 2Y5 20 37 2A 5 2Y6 21 36 2A 6 VCC 2Y7 22 35 VCC 23 34 2A 7 1OE2 1Y1 1A1 1Y5 TO 9 OTHER CHANNELS 2A1 FCT16827-1 2Y1 TO 9 OTHER CHANNELS FCT16827-2 1A 6 GND 2Y8 24 GND 25 33 32 2A 8 2Y9 26 31 2A 9 2Y10 27 30 2A10 2OE1 28 29 2OE2 GND FCT16827-3 Copyright © 2001, Texas Instruments Incorporated CY74FCT16827T CY74FCT162827T Maximum Ratings[2, 3] Pin Description Name (Above which the useful life may be impaired. For user guidelines, not tested.) Description OE Output Enable Inputs (Active LOW) A Data Inputs Y Three-State Outputs Storage Temperature ............................... −55°C to +125°C Ambient Temperature with Power Applied.......................................... −55°C to +125°C DC Input Voltage .................................................−0.5V to +7.0V Function Table[1] DC Output Voltage ..............................................−0.5V to +7.0V Inputs DC Output Current (Maximum Sink Current/Pin) ...........................−60 to +120 mA Outputs OE1 OE2 A Y L L L L L L H H H X X Z X H X Z Power Dissipation .......................................................... 1.0W Static Discharge Voltage............................................>2001V (per MIL-STD-883, Method 3015) Operating Range Range Industrial Ambient Temperature VCC −40°C to +85°C 5V ± 10% Electrical Characteristics Over the Operating Range Parameter Description Test Conditions VIH Input HIGH Voltage VIL Input LOW Voltage VH Input Hysteresis[5] VIK Input Clamp Diode Voltage VCC=Min., IIN=−18 mA IIH Input HIGH Current IIL Min. Typ.[4] Max. 2.0 Unit V 0.8 100 mV −1.2 V VCC=Max., VI=VCC ±1 µA Input LOW Current VCC=Max., VI=GND ±1 µA IOZH High Impedance Output Current (Three-State Output pins) VCC=Max., VOUT=2.7V ±1 µA IOZL High Impedance Output Current (Three-State Output pins) VCC=Max., VOUT=0.5V ±1 µA IOS Short Circuit Current[6] VCC=Max., VOUT=GND −80 −200 mA Current[6] VCC=Max., VOUT=2.5V −50 −180 mA ±1 µA Max. Unit IO Output Drive IOFF Power-Off Disable VCC=0V, VOUT −0.7 V −140 ≤4.5V[7] Output Drive Characteristics for CY74FCT16827T Parameter VOH VOL 1. 2. 3. 4. 5. 6. 7. Description Output HIGH Voltage Output LOW Voltage Min. Typ.[4] VCC=Min., IOH=−3 mA 2.5 3.5 VCC=Min., IOH=−15 mA 2.4 3.5 VCC=Min., IOH=−32 mA 2.0 3.0 Test Conditions VCC=Min., IOL=64 mA 0.2 V 0.55 V H = HIGH Voltage Level. L = LOW Voltage Level. X = Don’t Care.Z = HIGH Impedance. Operation beyond the limits set forth may impair the useful life of the device. Unless noted, these limits are over the operating free-air temperature range. Unused inputs must always be connected to an appropriate logic voltage level, preferably either VCC or ground. Typical values are at VCC= 5.0V, TA= +25˚C ambient. This parameter is specified but not tested. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter tests, IOS tests should be performed last. Tested at +25˚C. 2 CY74FCT16827T CY74FCT162827T Output Drive Characteristics for CY74FCT162827T Parameter Description Test Conditions Min. Typ.[4] Max. Unit Output LOW Current[6] VCC=5V, VIN=VIH or VIL, VOUT=1.5V 60 115 150 mA IODH Output HIGH Current[6] VCC=5V, VIN=VIH or VIL, VOUT=1.5V −60 −115 −150 mA VOH Output HIGH Voltage VCC=Min., IOH=−24 mA 2.4 3.3 VOL Output LOW Voltage VCC=Min., IOL=24 mA IODL 0.3 V 0.55 V Capacitance[5] (TA = +25˚C, f = 1.0 MHz) Parameter Description Test Conditions Typ.[4] Max. Unit CIN Input Capacitance VIN = 0V 4.5 6.0 pF COUT Output Capacitance VOUT = 0V 5.5 8.0 pF Power Supply Characteristics Parameter Description Test Conditions Min. Typ.[4] Max. Unit ICC Quiescent Power Supply Current VCC=Max. VIN<0.2V, VIN>VCC−0.2V — 5 500 µA ∆ICC Quiescent Power Supply Current (TTL inputs HIGH) VCC=Max. VIN=3.4V[8] — 0.5 1.5 mA ICCD Dynamic Power Supply Current[9] VCC=Max., One Input Toggling, 50% Duty Cycle, Outputs Open, OE1=OE2=GND, VIN=VCC or VIN=GND — 60 100 µA/MHz IC Total Power Supply Current[10] VCC=Max., f1=10 MHz, 50% Duty Cycle, Outputs Open, One Bit Toggling, OE1=OE2=GND VIN=VCC or VIN=GND — 0.6 1.5 mA VIN=3.4V or VIN=GND — 0.9 2.3 VIN=VCC or VIN=GND — 3.0 5.5[11] VIN=3.4V or VIN=GND — 8.0 20.5[11] VCC=Max., f1=2.5 MHz, 50% Duty Cycle, Outputs Open, Twenty Bits Toggling, OE1=OE2=GND Notes: 8. Per TTL driven input (VIN=3.4V); all other inputs at VCC or GND. 9. This parameter is not directly testable, but is derived for use in Total Power Supply calculations. = IQUIESCENT + IINPUTS + IDYNAMIC 10. IC IC = ICC+∆ICCDHNT+ICCD(f0/2 + f1N1) ICC = Quiescent Current with CMOS input levels ∆ICC = Power Supply Current for a TTL HIGH input (VIN=3.4V) = Duty Cycle for TTL inputs HIGH DH = Number of TTL inputs at DH NT ICCD = Dynamic Current caused by an input transition pair (HLH or LHL) = Clock frequency for registered devices, otherwise zero f0 = Input signal frequency f1 = Number of inputs changing at f1 N1 All currents are in milliamps and all frequencies are in megahertz. 11. Values for these conditions are examples of the ICC formula. These limits are specified but not tested. 3 CY74FCT16827T CY74FCT162827T Switching Characteristics Over the Operating Range[12] CY74FCT16827AT CY74FCT162827AT Parameter tPLH tPHL tPZH tPZL tPHZ tPLZ tSK(O) Description Propagation Delay A to Y Output Enable Time OE to Y Output Disable Time OE to Y CY74FCT162827BT Condition[13] Min. Max. Min. Max. Unit Fig. No.[13] CL=50 pF RL=500Ω 1.5 8.0 1.5 5.0 ns 1, 3 CL=300 pF RL=500Ω 1.5 15.0 1.5 13.0 CL=50 pF RL=500Ω 1.5 12.0 1.5 8.0 ns 1, 7, 8 CL=300 pF RL=500Ω 1.5 23.0 1.5 15.0 CL=5 pF RL=500Ω 1.5 9.0 1.5 6.0 ns 1, 7, 8 CL=50 pF RL=500Ω 1.5 10.0 1.5 7.0 — 0.5 — 0.5 ns — Output Skew[14] CY74FCT16827CT CY74FCT162827CT Parameter tPLH tPHL tPZH tPZL tPHZ tPLZ tSK(O) Description Propagation Delay A to Y Output Enable Time OE to Y Output Disable Time OE to Y Output Skew[14] Condition[12] Min. Max. Unit Fig. No.[13] CL=50 pF RL=500Ω 1.5 4.2 ns 1, 3 CL=300 pF RL=500Ω 1.5 10.0 CL=50 pF RL=500Ω 1.5 5.6 ns 1, 7, 8 CL=300 pF RL=500Ω 1.5 14.0 CL=5 pF RL=500Ω 1.5 5.7 ns 1, 7, 8 CL=50 pF RL=500Ω 1.5 6.0 — 0.5 ns — Notes: 12. Minimum limits are specified but not tested on Propagation Delays. 13. See “Parameter Measurement Information” in the General Information section. 14. Skew between any two outputs of the same package switching in the same direction. This parameter is ensured by design. 4 CY74FCT16827T CY74FCT162827T Ordering Information CY74FCT16827 Speed (ns) 4.2 8.0 Ordering Code Package Name Package Type CY74FCT16827CTPACT Z56 56-Lead (240-Mil) TSSOP CY74FCT16827CTPVC/PVCT O56 56-Lead (300-Mil) SSOP CY74FCT16827ATPVC/PVCT Z56 56-Lead (240-Mil) SSOP Operating Range Industrial Industrial Document #: 38−00393–C Ordering Information CY74FCT162827 Speed (ns) 4.2 5.0 8.0 Ordering Code Package Name Package Type 74FCT162827CTPACT Z56 56-Lead (240-Mil) TSSOP CY74FCT162827CTPVC Z56 56-Lead (240-Mil) SSOP 74FCT162827CTPVCT Z56 56-Lead (240-Mil) SSOP CY74FCT162827BTPVC O56 56-Lead (300-Mil) SSOP 74FCT162827BTPVCT O56 56-Lead (300-Mil) SSOP CY74FCT162827ATPVC O56 56-Lead (300-Mil) SSOP 74FCT162827ATPVCT O56 56-Lead (300-Mil) SSOP 5 Operating Range Industrial Industrial Industrial CY74FCT16827T CY74FCT162827T Package Diagrams 56-Lead Shrunk Small Outline Package O56 56-Lead Thin Shrunk Small Outline Package Z56 6 PACKAGE OPTION ADDENDUM www.ti.com 24-Sep-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) 74FCT162827ATPACT ACTIVE TSSOP DGG 56 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 FCT162827A 74FCT162827CTPACT ACTIVE TSSOP DGG 56 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 FCT162827C 74FCT162827ETPACT OBSOLETE TSSOP DGG 56 TBD Call TI Call TI -40 to 85 74FCT162827ETPVCT OBSOLETE SSOP DL 56 TBD Call TI Call TI -40 to 85 CY74FCT162827ATPVC ACTIVE SSOP DL 56 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CY74FCT162827ETPAC OBSOLETE TSSOP DGG 56 TBD Call TI Call TI -40 to 85 CY74FCT162827ETPVC OBSOLETE SSOP DL 56 TBD Call TI Call TI -40 to 85 CY74FCT16827ATPVC ACTIVE SSOP DL 56 20 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 FCT16827A CY74FCT16827CTPACT ACTIVE TSSOP DGG 56 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 FCT16827C CY74FCT16827CTPVC ACTIVE SSOP DL 56 20 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 FCT16827C CY74FCT16827CTPVCT ACTIVE SSOP DL 56 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 FCT16827C 20 CY74FCT16827ETPAC OBSOLETE TSSOP DGG 56 TBD Call TI Call TI -40 to 85 CY74FCT16827ETPACT OBSOLETE TSSOP DGG 56 TBD Call TI Call TI -40 to 85 CY74FCT16827ETPVC OBSOLETE SSOP DL 56 TBD Call TI Call TI -40 to 85 CY74FCT16827ETPVCT OBSOLETE SSOP DL 56 TBD Call TI Call TI -40 to 85 FCT162827A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 24-Sep-2015 Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 2-Sep-2015 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 74FCT162827ATPACT TSSOP DGG 56 2000 330.0 24.4 8.6 15.6 1.8 12.0 24.0 Q1 74FCT162827CTPACT TSSOP DGG 56 2000 330.0 24.4 8.6 15.6 1.8 12.0 24.0 Q1 CY74FCT16827CTPACT TSSOP DGG 56 2000 330.0 24.4 8.6 15.6 1.8 12.0 24.0 Q1 CY74FCT16827CTPVCT SSOP DL 56 1000 330.0 32.4 11.35 18.67 3.1 16.0 32.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 2-Sep-2015 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) 74FCT162827ATPACT TSSOP DGG 56 2000 367.0 367.0 45.0 74FCT162827CTPACT TSSOP DGG 56 2000 367.0 367.0 45.0 CY74FCT16827CTPACT TSSOP DGG 56 2000 367.0 367.0 45.0 CY74FCT16827CTPVCT SSOP DL 56 1000 367.0 367.0 55.0 Pack Materials-Page 2 PACKAGE OUTLINE DGG0056A TSSOP - 1.2 mm max height SCALE 1.200 SMALL OUTLINE PACKAGE C 8.3 TYP 7.9 SEATING PLANE PIN 1 ID AREA A 0.1 C 54X 0.5 56 1 14.1 13.9 NOTE 3 2X 13.5 28 B 6.2 6.0 29 56X 0.27 0.17 0.08 1.2 MAX C A B (0.15) TYP SEE DETAIL A 0.25 GAGE PLANE 0 -8 0.15 0.05 0.75 0.50 DETAIL A TYPICAL 4222167/A 07/2015 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. Reference JEDEC registration MO-153. www.ti.com EXAMPLE BOARD LAYOUT DGG0056A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 56X (1.5) SYMM 1 56 56X (0.3) 54X (0.5) (R0.05) TYP SYMM 28 29 (7.5) LAND PATTERN EXAMPLE SCALE:6X SOLDER MASK OPENING METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK 0.05 MAX ALL AROUND 0.05 MIN ALL AROUND SOLDER MASK DEFINED NON SOLDER MASK DEFINED SOLDER MASK DETAILS 4222167/A 07/2015 NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN DGG0056A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 56X (1.5) SYMM 1 56 56X (0.3) 54X (0.5) (R0.05) TYP SYMM 29 28 (7.5) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:6X 4222167/A 07/2015 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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