Cypress CY7C43682-15AC 1k/4k/16k x36 x2 bidirectional synchronous fifo Datasheet

CY7C43642
CY7C43662
CY7C43682
1K/4K/16K x36 x2 Bidirectional
Synchronous FIFO
Features
• Low power
— ICC= 100 mA
• High-speed, low-power, bidirectional, First-In, First-Out
(FIFO) memories
• 1Kx36x2 (CY7C43642)
• 4Kx36x2 (CY7C43662)
• 16Kx36x2 (CY7C43682)
• 0.35-micron CMOS for optimum speed/power
• High speed 133-MHz operation (7.5-ns read/write cycle
times)
— ISB= 10 mA
• Fully asynchronous and simultaneous read and write
operation permitted
• Mailbox bypass register for each FIFO
• Parallel Programmable Almost Full and Almost Empty
flags
• Retransmit function
• Standard or FWFT mode user selectable
• 120-pin TQFP packaging
• Easily expandable in width and depth
Logic Block Diagram
MBF1
CLKA
CSA
Port A
Control
Logic
MBA
RT2
RST1
1K/4K/16K
x36
Dual Ported
Memory
Input
Register
ENA
FIFO1,
Mail1
Reset
Logic
Port B
Control
Logic
Status
Flag Logic
AFA
Programmable
Flag Offset
Registers
FS0
FS1
CLKB
CSB
W/RB
ENB
MBB
RT1
Read
Pointer
Write
Pointer
FFA/IRA
Output
W/RA
Register
Mail1
Register
EFB/ORB
AEB
B0–35
Timing
Mode
FWFT/STAN
A0–35
Status
Flag Logic
AEA
Read
Pointer
Write
Pointer
Output
Register
FFB/IRB
AFB
FIFO2,
Mail2
Reset
Logic
Input
Register
EFA/ORA
256/512/1K
4K/16K x36
Dual Ported
Memory
RST2
Mail2
Register
MBF2
Cypress Semiconductor Corporation
Document #: 38-06019 Rev. *B
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised December 26, 2002
Pin Configuration
A35
A34
A33
A32
VCC
A31
A30
GND
A29
A28
A27
A26
A25
A24
A23
FWFT/STAN
A22
VCC
A21
A20
A19
A18
GND
A17
A16
A15
A14
A13
RT2
RST2
MBB
MBF1
VCC
CY7C43642
CY7C43662
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C43682
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
B35
B34
B33
B32
GND
B31
B30
B29
B28
B27
B26
RT1
B25
B24
GND
B23
B22
B21
B20
B19
B18
GND
B17
B16
VCC
B15
B14
B13
B12
GND
Document #: 38-06019 Rev. *B
B4
B5
GND
B6
VCC
B7
B8
B9
B10
B11
B0
B1
B2
B3
A8
A7
A6
GND
A5
A4
A3
VCC
A2
A1
A0
GND
GND
A11
A10
A9
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
A12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
GND
CLKA
ENA
W/RA
CSA
FFA/IRA
EFA/ORA
VCC
AFA
AEA
MBF2
MBA
RST1
FS0
GND
FS1
TQFP
Top View
AEB
AFB
EFB/ORB
FFB/IRB
GND
CSB
W/RB
ENB
CLKB
VCC
CY7C43642
CY7C43662
CY7C43682
Page 2 of 30
CY7C43642
CY7C43662
CY7C43682
Functional Description
The CY7C436X2 is a monolithic, high-speed, low-power,
CMOS Bidirectional Synchronous (clocked) FIFO memory
which supports clock frequencies up to 133 MHz and has read
access times as fast as 6 ns. Two independent 1K/4K/16K x
36 dual-port SRAM FIFOs on board each chip buffer data in
opposite directions.
The CY7C436X2 is a synchronous (clocked) FIFO, meaning
each port employs a synchronous interface. All data transfers
through a port are gated to the LOW-to-HIGH transition of a
port clock by enable signals. The clocks for each port are
independent of one another and can be asynchronous or
coincident. The enables for each port are arranged to provide
a simple bidirectional interface between microprocessors
and/or buses with synchronous control.
Communication between each port may bypass the FIFOs via
two mailbox registers. The mailbox registers’ width matches
the selected Port B bus width. Each mailbox register has a flag
(MBF1 and MBF2) to signal when new mail has been stored.
Master Reset initializes the read and write pointers to the first
location of the memory array, and selects parallel flag
programming, or one of the three possible default flag offset
settings, 8, 16, or 64. Each FIFO has its own independent
Master Reset pin, RST1 and RST2.
The CY7C436X2 have two modes of operation: In the CY
Standard Mode, the first word written to an empty FIFO is
deposited into the memory array. A read operation is required
to access that word (along with all other words residing in
memory). In the First-Word Fall-Through Mode (FWFT), the
first word (36-bit wide) written to an empty FIFO appears
automatically on the outputs, no read operation required
(nevertheless, accessing subsequent words does necessitate
a formal read request). The state of the FWFT/STAN pin
during FIFO operation determines the mode in use.
Each FIFO has a combined Empty/Output Ready Flag
(EFA/ORA and EFB/ORB) and a combined Full/Input Ready
Flag (FFA/IRA and FFB/IRB). The EF and FF functions are
selected in the CY Standard Mode. EF indicates whether the
memory is full or not. The IR and OR functions are selected in
the First-Word Fall-Through Mode. IR indicates whether or not
the FIFO has available memory locations. OR shows whether
the FIFO has data available for reading or not. It marks the
presence of valid data on the outputs.[1]
Each FIFO has a programmable Almost Empty flag (AEA and
AEB) and a programmable Almost Full flag (AFA and AFB).
AEA and AEB indicate when a selected number of words
written to FIFO memory achieve a predetermined “almost
empty state.” AFA and AFB indicate when a selected number
of words written to the memory achieve a predetermined
“almost full state.”[2]
IRA, IRB, AFA, and AFB are synchronized to the port clock that
writes data into its array. ORA, ORB, AEA, and AEB are
synchronized to the port clock that reads data from its array.
Programmable offset for AEA, AEB, AFA, and AFB are loaded
in parallel using Port A. Three default offset settings are also
provided. The AEA and AEB threshold can be set at 8, 16, or
64 locations from the empty boundary and AFA and AFB
threshold can be set at 8, 16, or 64 locations from the full
boundary. All these choices are made using the FS0 and FS1
inputs during Master Reset.
Two or more devices may be used in parallel to create wider
data paths.
The CY7C436X2 are characterized for operation from 0°C to
70°C commercial, and from –40°C to 85°C industrial. Input
ESD protection is greater than 2001V, and latch-up is
prevented by the use of guard rings.
Selection Guide
CY7C43642/62/82
-7
CY7C43642/62/82
-10
CY7C43642/62/82
-15
Maximum Frequency (MHz)
133
100
66.7
Maximum Access Time (ns)
6
8
10
Minimum Cycle Time (ns)
7.5
10
15
Minimum Data or Enable Set-up (ns)
3
4
5
Minimum Data or Enable Hold (ns)
0
0
0
Maximum Flag Delay (ns)
6
8
8
100
100
100
Active Power Supply
Current (ICC1) (mA)
Commercial
Industrial
100
CY7C43642
CY7C43662
CY7C43682
Density
1K x 36
4K x 36
16K x 36
Package
120 TQFP
120 TQFP
120 TQFP
Notes:
1. When reading from the FIFO under FWFT, ORA/ORB signal should be included in the read logic to ensure proper operation. To read without gating the
boundary flag (e.g., in bursts), use CY standard mode.
2. When FIFO is operated at the almost empty/full boundary, there may be an uncertainty of up to 3 clock cycles for flag assertion and deassertion. Refer to
“Designing with CY7C436xx Synchronous FIFO” application notes for more details on flag uncertainties.
Document #: 38-06019 Rev. *B
Page 3 of 30
CY7C43642
CY7C43662
CY7C43682
Pin Definitions
Signal Name
Description
I/O
Function
A0–35
Port A Data
I/O 36-bit bidirectional data port for side A.
AEA
Port A Almost
Empty Flag
O
Programmable Almost Empty flag synchronized to CLKA. It is LOW when the number
of words in FIFO2 is less than or equal to the value in the Almost Empty A offset register,
X2.[2]
AEB
Port B Almost
Empty Flag
O
Programmable Almost Empty flag synchronized to CLKB. It is LOW when the number
of words in FIFO1 is less than or equal to the value in the Almost Empty B offset register,
X1.[2]
AFA
Port A Almost
Full Flag
O
Programmable Almost Full flag synchronized to CLKA. It is LOW when the number
of empty locations in FIFO1 is less than or equal to the value in the Almost Full A offset
register, Y1.[2]
AFB
Port B Almost
Full Flag
O
Programmable Almost Full flag synchronized to CLKB. It is LOW when the number
of empty locations in FIFO2 is less than or equal to the value in the Almost Full B offset
register, Y2.[2]
B0–35
Port B Data
I/O 36-bit bidirectional data port for side B.
FWFT/STAN Big
Endian/First-Wor
d Fall-Through
Select
I
During Master Reset. A HIGH on FWFT selects CY Standard mode, a LOW selects
First-Word Fall-Through mode. Once the timing mode has been selected, the level on
FWFT/STAN must be static throughout device operation.
CLKA
Port A Clock
I
CLKA is a continuous clock that synchronizes all data transfers through Port A and
can be asynchronous or coincident to CLKB. FFA/IRA, EFA/ORA, AFA, and AEA are all
synchronized to the LOW-to-HIGH transition of CLKA.
CLKB
Port B Clock
I
CLKB is a continuous clock that synchronizes all data transfers through Port B and
can be asynchronous or coincident to CLKA. FFB/IRB, EFB/ORB, AFB, and AEB are all
synchronized to the LOW-to-HIGH transition of CLKB.
CSA
Port A Chip
Select
I
CSA must be LOW to enable a LOW-to HIGH transition of CLKA to read or write on
Port A. The A0–35 outputs are in the high-impedance state when CSA is HIGH.
CSB
Port B Chip
Select
I
CSB must be LOW to enable a LOW-to HIGH transition of CLKB to read or write on
Port B. The B0–35 outputs are in the high-impedance state when CSB is HIGH.
EFA/ORA
Port A Empty/
Output Ready
Flag
O
This is a dual-function pin. In the CY Standard Mode, the EFA function is selected. EFA
indicates whether or not the FIFO2 memory is empty. In the FWFT mode, the ORA function
is selected. ORA indicates the presence of valid data on A0–35 outputs, available for
reading. EFA/ORA is synchronized to the LOW-to-HIGH transition of CLKA.[1]
EFB/ORB
Port B Empty/
Output Ready
Flag
O
This is a dual-function pin. In the CY Standard Mode, the EFB function is selected. EFB
indicates whether or not the FIFO1 memory is empty. In the FWFT mode, the ORB function
is selected. ORB indicates the presence of valid data on B0–35 outputs, available for
reading. EFB/ORB is synchronized to the LOW-to-HIGH transition of CLKB.[1]
ENA
Port A Enable
I
ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data
on Port A.
ENB
Port B Enable
I
ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data
on Port B.
FFA/IRA
Port A Full/Input
Ready Flag
O
This is a dual-function pin. In the CY Standard Mode, the FFA function is selected. FFA
indicates whether or not the FIFO1 memory is full. In the FWFT mode, the IRA function is
selected. IRA indicates whether or not there is space available for writing to the FIFO1
memory. FFA/IRA is synchronized to the LOW-to-HIGH transition of CLKA.
FFB/IRB
Port B Full/Input
Ready Flag
O
This is a dual-function pin. In the CY Standard Mode, the FFB function is selected. FFB
indicates whether or not the FIFO2 memory is full. In the FWFT mode, the IRB function is
selected. IRB indicates whether or not there is space available for writing to the FIFO2
memory. FFB/IRB is synchronized to the LOW-to-HIGH transition of CLKB.
Document #: 38-06019 Rev. *B
Page 4 of 30
CY7C43642
CY7C43662
CY7C43682
Pin Definitions (continued)
Signal Name
Description
I/O
Function
The LOW-to-HIGH transition of a FIFO’s reset input latches the values of FS0 and
FS1. If either FS0 or FS1 is HIGH when a reset input goes HIGH, one of the three preset
values (8, 16, or 64) is selected as the offset for the FIFO’s Almost Full and Almost Empty
flags. If both FIFOs are reset simultaneously and both FS0 and FS1 are LOW when RST1
and RST2 go HIGH, the first four writes to FIFO1 Almost Empty offsets for both FIFOs.
FS1
Flag Offset
Select 1
I
FS0
Flag Offset
Select 0
I
MBA
Port A Mailbox
Select
I
A HIGH level on MBA chooses a mailbox register for a Port A read or write operation.
When a read operation is performed on Port A, a HIGH level on MBA selects data from
the Mail2 register for output and a LOW level selects FIFO2 output register data for output.
When a write operation is performed on Port A, a HIGH level on MBA will write the data
into Mail1 register while a LOW level will write the data into FIFO1.
MBB
Port B Mailbox
Select
I
A HIGH level on MBB chooses a mailbox register for a Port B read or write operation.
When a read operation is performed on Port B, a HIGH level on MBB selects data from
the Mail1 register for output and a LOW level selects FIFO1 output register data for output.
When a write operation is performed on Port B, a HIGH level on MBB will write the data
into Mail2 register while a LOW level will write the data into FIFO2.
MBF1
Mail1 Register
Flag
O
MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the Mail1
register. Writes to the Mail1 register are inhibited while MBF1 is LOW. MBF1 is set HIGH
by a LOW-to-HIGH transition of CLKB when a Port B read is selected and MBB is HIGH.
MBF1 is set HIGH following either a Master or Partial Reset of FIFO1.
MBF2
Mail2 Register
Flag
O
MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the Mail2
register. Writes to the Mail2 register are inhibited while MBF2 is LOW. MBF2 is set HIGH
by a LOW-to-HIGH transition of CLKA when a Port A read is selected and MBA is HIGH.
MBF2 is set HIGH following either a Master or Partial Reset of FIFO2.
RT1
Retransmit
FIFO1
I
A LOW strobe on this pin will retransmit the data on FIFO1. This is achieved by
bringing the read pointer back to location zero. The user will still need to perform read
operations to retransmit the data. Retransmit function applies to CY standard mode only.
RT2
Retransmit
FIFO2
I
A LOW strobe on this pin will retransmit data on FIFO2. This is achieved by bringing
the read pointer back to location zero. The user will still need to perform read operations
to retransmit the data. Retransmit function applies to CY standard mode only.
W/RA
Port A Write/
Read Select
I
A HIGH selects a write operation and a LOW selects a read operation on Port A for
a LOW-to-HIGH transition of CLKA. The A0–35 outputs are in the HIGH impedance state
when W/RA is HIGH.
W/RB
Port B Write/
Read Select
I
A LOW selects a write operation and a HIGH selects a read operation on Port B for
a LOW-to-HIGH transition of CLKB. The B0–35 outputs are in the HIGH impedance state
when W/RB is LOW.
RST1
FIFO1 Master
Reset
I
A LOW on this pin initializes the FIFO1 read and write pointers to the first location of
memory and sets the Port B output register to all zeroes. A LOW pulse on RST1 selects
the programming method (serial or parallel) and one of three programmable flag default
offsets. It also configures Port A for bus size and endian arrangement. Four LOW-to-HIGH
transitions of CLKA and four LOW-to-HIGH transitions of CLKB must occur while RST1
is LOW.
RST2
FIFO2 Master
Reset
I
A LOW on this pin initializes the FIFO2 read and write pointers to the first location of
memory and sets the Port B output register to all zeroes. A LOW pulse on RST2 selects
the programming method (serial or parallel) and one of three programmable flag default
offsets. It also configures Port B for bus size and endian arrangement. Four LOW-to-HIGH
transitions of CLKA and four LOW-to-HIGH transitions of CLKB must occur while RST2
is LOW.
Signal Description
Reset (RST1, RST2)
Each of the two FIFO memories of the CY7C436X2 undergoes
a complete reset by taking its associated Master Reset (RST1,
RST2) input LOW for at least four Port A clock (CLKA) and four
Port B clock (CLKB) LOW-to-HIGH transitions. The Master
Reset inputs can switch asynchronously to the clocks. A
Document #: 38-06019 Rev. *B
Master Reset initializes the internal read and write pointers
and forces the Full/Input Ready flag (FFA/IRA, FFB/IRB) LOW,
the Empty/Output Ready flag (EFA/ORA, EFB/ORB) LOW, the
Almost Empty flag (AEA, AEB) LOW, and the Almost Full flag
(AFA, AFB) HIGH. A Master Reset also forces the Mailbox flag
(MBF1, MBF2) of the parallel mailbox register HIGH. After a
Master Reset, the FIFO’s Full/Input Ready flag is set HIGH
after two clock cycles to begin normal operation. A Master
Page 5 of 30
CY7C43642
CY7C43662
CY7C43682
Reset must be performed on the FIFO after power-up, before
data is written to its memory.
FS0 and FS1 function the same way in both CY Standard and
FWFT modes.
A LOW-to-HIGH transition on a FIFO reset (RST1, RST2)
input latches the values of the Flag select (FS0, FS1) for
choosing the Almost Full and Almost Empty offset
programming method (see Almost Empty and Almost Full flag
offset programming below).
FIFO Write/Read Operation
First-Word Fall-Through (FWFT/STAN)
After Master Reset, the FWFT select function is active,
permitting a choice between two possible timing modes: CY
Standard Mode or First-Word Fall-Through (FWFT) Mode.
Once the Master Reset (RST1, RST2) input is HIGH, a HIGH
on the FWFT/STAN input during the next LOW-to-HIGH
transition of CLKA (for FIFO1) and CLKB (for FIFO2) will select
CY Standard Mode. This mode uses the Empty Flag function
(EFA, EFB) to indicate whether or not there are any words
present in the FIFO memory. It uses the Full Flag function
(FFA, FFB) to indicate whether or not the FIFO memory has
any free space for writing. In CY Standard mode, every word
read from the FIFO, including the first, must be requested
using a formal read operation.
Once the Master Reset (RST1, RST2) input is HIGH, a LOW
on the FWFT/STAN input during the next LOW-to-HIGH
transition of CLKA (for FIFO1) and CLKB (for FIFO2) will select
FWFT Mode. This mode uses the Output Ready function
(ORA, ORB) to indicate whether or not there is valid data at
the data outputs (A0–35 or B0–35). (See footnote #1) It also
uses the Input Ready function (IRA, IRB) to indicate whether
or not the FIFO memory has any free space for writing. In the
FWFT mode, the first word written to an empty FIFO goes
directly to data outputs, no read request necessary. Subsequent words must be accessed by performing a formal read
operation.
Following Master Reset, the level applied to the FWFT/STD
input to choose the desired timing mode must remain static
throughout the FIFO operation.
Programming the Almost Empty and Almost Full Flags
Four registers in the CY7C436X2 are used to hold the offset
values for the Almost Empty and Almost Full flags. The Port B
Almost Empty flag (AEB) offset register is labeled X1 and the
Port A Almost Empty flag (AEA) offset register is labeled X2.
The Port A Almost Full flag (AFA) offset register is labeled Y1
and the Port B Almost Full flag (AFB) offset register is labeled
Y2. The index of each register name corresponds with preset
values during the reset of a FIFO, programmed in parallel
using the FIFO’s Port A data inputs (see Table 1).
To program the X1, X2, Y1, and Y2 registers from Port A,
perform a Master Reset on both FIFOs simultaneously with
FS0 and FS1 LOW during the LOW-to-HIGH transition of
RST1 and RST2. After this reset is complete, the first four
writes to FIFO1 do not store data in RAM but load the offset
registers in the order Y1, X1, Y2, X2. The Port A data inputs
used by the offset registers are (A0–9), (A0–11), or (A0–13), for
the CY7C436X2, respectively. The highest numbered input is
used as the most significant bit of the binary number in each
case. Valid programming values for the registers range from 0
to 1023 for the CY7C43642; 0 to 4095 for the CY7C43662; 0
to 16383 for the CY7C43682. (See footnote #2) After all the
offset registers are programmed from Port A, the Port B
Full/Input Ready (FFB/IRB) is set HIGH and both FIFOs begin
normal operation.
Document #: 38-06019 Rev. *B
The state of the Port A data (A0–35) lines is controlled by Port
A Chip Select (CSA) and Port A Write/Read Select (W/RA).
The A0–35 lines are in the high-impedance state when either
CSA or W/RA is HIGH. The A0–35 lines are active outputs
when both CSA and W/RA are LOW.
Data is loaded into FIFO1 from the A0–35 inputs on a
LOW-to-HIGH transition of CLKA when CSA is LOW, W/RA is
HIGH, ENA is HIGH, MBA is LOW, and FFA/IRA is HIGH. Data
is read from FIFO2 to the A0–35 outputs by a LOW-to-HIGH
transition of CLKA when CSA is LOW, W/RA is LOW, ENA is
HIGH, MBA is LOW, and EFA/ORA is HIGH (see Table 2).
FIFO reads and writes on Port A are independent of any
concurrent Port B operation.
The Port B control signals are identical to those of Port A with
the exception that the Port B Write/Read select (W/RB) is the
inverse of the Port A Write/Read Select (W/RA). The state of
the Port B data (B0–35) lines is controlled by the Port B Chip
Select (CSB) and Port B Write/Read Select (W/RB).The B0–35
lines are in the high-impedance state when either CSB is HIGH
or W/RB is LOW. The B0–35 lines are active outputs when CSB
is LOW and W/RB is HIGH.
Data is loaded into FIFO2 from the B0–35 inputs on a
LOW-to-HIGH transition of CLKB when CSB is LOW, W/RB is
LOW, ENB is HIGH, MBB is LOW, and FFB/IRB is HIGH. Data
is read from FIFO1 to the B0–35 outputs by a LOW-to-HIGH
transition of CLKB when CSB is LOW, W/RB is HIGH, ENB is
HIGH, MBB is LOW, and EFB/ORB is HIGH (see Table 3).
FIFO reads and writes on Port B are independent of any
concurrent Port A operation.
The set-up and hold time constraints to the port clocks for the
port Chip Selects and Write/Read Selects are only for enabling
write and read operations and are not related to
high-impedance control of the data outputs. If a port enable is
LOW during a clock cycle, the port’s Chip Select and
Write/Read select may change states during the set-up and
hold time window of the cycle.
When operating the FIFO in FWFT Mode and the Output
Ready flag is LOW, the next word written is automatically sent
to the FIFO’s output register by the LOW-to-HIGH transition of
the port clock that sets the Output Ready flag HIGH, data
residing in the FIFO’s memory array is clocked to the output
register only when a read is selected using the port’s Chip
Select, Write/Read Select, Enable, and Mailbox select.
When operating the FIFO in CY Standard Mode, regardless of
whether the Empty Flag is LOW or HIGH, data residing in the
FIFO’s memory array is clocked to the output register only
when a read is selected using the port’s Chip Select,
Write/Read Select, Enable, and Mailbox Select.
Synchronized FIFO Flags
Each FIFO is synchronized to its port clock through at least two
flip-flop stages. This is done to improve flag-signal reliability by
reducing the probability of the metastable events when CLKA
and CLKB operate asynchronously to one another. EFA/ORA,
AEA, FFA/IRA, and AFA are synchronized to CLKA.
EFB/ORB, AEB, FFB/IRB, and AFB are synchronized to
CLKB. Table 4 and Table 5 show the relationship of each port
flag to FIFO1 and FIFO2.
Page 6 of 30
CY7C43642
CY7C43662
CY7C43682
Empty/Output Ready Flags (EFA/ORA, EFB/ORB)
These are dual-purpose flags. In the FWFT Mode, the Output
Ready (ORA, ORB) function is selected. When the
Output-Ready flag is HIGH, new data is present in the FIFO
output register. When the Output Ready flag is LOW, the
previous data word is present in the FIFO output register and
attempted FIFO reads are ignored. (See footnote #1)
minimum of two cycles of the Full/Input Ready flag synchronizing clock. Therefore, an Full/Input Ready flag is LOW if less
than two cycles of the Full/Input Ready flag synchronizing
clock have elapsed since the next memory write location has
been read. The second LOW-to-HIGH transition on the
Full/Input Ready flag synchronizing clock after the read sets
the Full/Input Ready flag HIGH.
In the CY Standard Mode, the Empty Flag (EFA, EFB) function
is selected. When the Empty Flag is HIGH, data is available in
the FIFO’s RAM memory for reading to the output register.
When the Empty Flag is LOW, the previous data word is
present in the FIFO output register and attempted FIFO reads
are ignored.
A LOW-to-HIGH transition on a Full/Input Ready flag synchronizing clock begins the first synchronization cycle of a read if
the clock transition occurs at time tSKEW1 or greater after the
read. Otherwise, the subsequent clock cycle can be the first
synchronization cycle.
The Empty/Output Ready flag of a FIFO is synchronized to the
port clock that reads data from its array. For both the FWFT
and CY Standard modes, the FIFO read pointer is incremented
each time a new word is clocked to its output register. The
state machine that controls an Output Ready flag monitors a
write pointer and read pointer comparator that indicates when
the FIFO SRAM status is empty, or empty+1.
The Almost Empty flag of a FIFO is synchronized to the port
clock that reads data from its array. The state machine that
controls an Almost Empty flag monitors a write pointer and
read pointer comparator that indicates when the FIFO SRAM
status is almost empty, or almost empty+1. The Almost Empty
state is defined by the contents of register X1 for AEB and
register X2 for AEA. These registers are loaded with preset
values during a FIFO reset, programmed from Port A, or
programmed serially (see Almost Empty flag and Almost Full
flag offset programming above). An Almost Empty flag is LOW
when its FIFO contains X or less words and is HIGH when its
FIFO contains (X+1) or more words.[2]
In FWFT Mode, from the time a word is written to a FIFO, it
can be shifted to the FIFO output register in a minimum of
three cycles of the Output Ready flag synchronizing clock.
Therefore, an Output Ready flag is LOW if a word in memory
is the next data to be sent to the FIFO output register and three
cycles have not elapsed since the time the word was written.
The Output Ready flag of the FIFO remains LOW until the third
LOW-to-HIGH transition of the synchronizing clock occurs,
simultaneously forcing the Output Ready flag HIGH and
shifting the word to the FIFO output register.
In the CY Standard Mode, from the time a word is written to a
FIFO, the Empty flag will indicate the presence of data
available for reading in a minimum of two cycles of the Empty
flag synchronizing clock. Therefore, an Empty Flag is LOW if
a word in memory is the next data to be sent to the FIFO output
register and two cycles have not elapsed since the time the
word was written. The Empty flag of the FIFO remains LOW
until the second LOW-to-HIGH transition of the synchronizing
clock occurs, forcing the Empty flag HIGH; only then can data
be read.
A LOW-to-HIGH transition on an Empty/Output Ready flag
synchronizing clock begins the first synchronization cycle of a
write if the clock transition occurs at time tSKEW1 or greater
after the write. Otherwise, the subsequent clock cycle can be
the first synchronization cycle.
Full/Input Ready Flags (FFA/IRA, FFB/IRB)
This is a dual-purpose flag. In FWFT Mode, the Input Ready
(IRA and IRB) function is selected. In CY Standard Mode, the
Full Flag (FFA and FFB) function is selected. For both timing
modes, when the Full/Input Ready flag is HIGH, a memory
location is free in the SRAM to receive new data. No memory
locations are free when the Full/Input Ready flag is LOW and
attempted writes to the FIFO are ignored.
The Full/Input Ready flag of a FIFO is synchronized to the port
clock that writes data to its array. For both FWFT and CY
Standard modes, each time a word is written to a FIFO, its
write pointer is incremented. The state machine that controls
a Full/Input Ready flag monitors a write pointer and read
pointer comparator that indicates when the FIFO SRAM status
is full, or full–1. From the time a word is read from a FIFO, its
previous memory location is ready to be written to in a
Document #: 38-06019 Rev. *B
Almost Empty Flags (AEA, AEB)
Two LOW-to-HIGH transitions of the Almost Empty flag
synchronizing clock are required after a FIFO write for its
Almost Empty flag to reflect the new level of fill. Therefore, the
Almost Full flag of a FIFO containing (X+1) or more words
remains LOW if two cycles of its synchronizing clock have not
elapsed since the write that filled the memory to the (X+1)
level. An Almost Empty flag is set HIGH by the second
LOW-to-HIGH transition of its synchronizing clock after the
FIFO write that fills memory to the (X+1) level. A LOW-to-HIGH
transition of an Almost Empty flag synchronizing clock begins
the first synchronization cycle if it occurs at time tSKEW2 or
greater after the write that fills the FIFO to (X+1) words.
Otherwise, the subsequent synchronizing clock cycle may be
the first synchronization cycle.
Almost Full Flags (AFA, AFB)
The Almost Full flag of a FIFO is synchronized to the port clock
that writes data to its array. The state machine that controls an
Almost Full flag monitors a write pointer and read pointer
comparator that indicates when the FIFO SRAM status is
almost full, or almost full–1. The Almost Full state is defined by
the contents of register Y1 for AFA and register Y2 for AFB.
These registers are loaded with preset values during a FIFO
reset, programmed from Port A, or programmed serially (see
Almost Empty flag and Almost Full flag offset programming
above). An Almost Full flag is LOW when the number of words
in its FIFO is greater than or equal to (1024–Y), (4096–Y), or
(16384–Y) for the CY7C436X2 respectively. An Almost Full
flag is HIGH when the number of words in its FIFO is less than
or equal to [1024–(Y+1)], [4096–(Y+1)], or [16384–(Y+1)], for
the CY7C436X2 respectively. (See footnote #2)
Two LOW-to-HIGH transitions of the Almost Full flag synchronizing clock are required after a FIFO read for its Almost Full
flag to reflect the new level of fill. Therefore, the Almost Full
flag of a FIFO containing [1024/4096/16384–(Y+1)] or less
words remains LOW if two cycles of its synchronizing clock
have not elapsed since the read that reduced the number of
Page 7 of 30
CY7C43642
CY7C43662
CY7C43682
words in memory to [1024/4096/16384–(Y+1)]. An Almost Full
flag is set HIGH by the second LOW-to-HIGH transition of its
synchronizing clock after the FIFO read that reduces the
number of words in memory to [1024/4096/16384–(Y+1)]. A
LOW-to-HIGH transition of an Almost Full flag synchronizing
clock begins the first synchronization cycle if it occurs at time
tSKEW2 or greater after the read that reduces the number of
words in memory to [1024/4096/16384–(Y+1)]. Otherwise, the
subsequent synchronizing clock cycle may be the first
synchronization cycle.
Mailbox Registers
Each FIFO has a 36-bit bypass register to pass command and
control information between Port A and Port B without putting
it in queue. The Mailbox Select (MBA, MBB) inputs choose
between a mail register and a FIFO for a port data transfer
operation. The usable width of both the Mail1 and Mail2
registers matches the selected bus size for Port B.
A LOW-to-HIGH transition on CLKA writes A0-35 data to the
Mail1 Register when a Port A write is selected by CSA, W/RA,
and ENA with MBA HIGH. If the selected Port A bus size is
also 36 bits, then the usable width of the Mail1 Register
employs data lines A0-35. If the selected Port A bus size is 18
bits, then the usable width of the Mail1 Register employs data
lines A0-17. (In this case, A18-35 are don’t care inputs.) If the
selected Port A bus size is 9 bits, then the usable width of the
Mail1 Register employs data lines A0-8. (In this case, A9-35 are
don’t care inputs.)
A LOW-to-HIGH transition on CLKB writes B0–35 data to the
Mail2 Register when a Port B write is selected by CSB, W/RB,
and ENB with MBB HIGH. If the selected Port B bus size is
also 36 bits, then the usable width of the Mail2 Register
employs data lines B0–35. If the selected Port B bus size is 18
bits, then the usable width of the Mail2 Register employs data
lines B0–17. (In this case, B18–35 are don’t care inputs.) If the
selected Port B bus size is 9 bits, then the usable width of the
Mail2 Register employs data lines B0-8. (In this case, B9-35 are
don’t care inputs.)
Writing data to a mail register sets its corresponding flag
(MBF1 or MBF2) LOW. Attempted writes to a mail register are
ignored while the mail flag is LOW.
When data outputs of a port are active, the data on the bus
comes from the FIFO output register when the port Mailbox
Select input is LOW and from the mail register when the port
Mailbox Select input is HIGH.
The Mail1 Register flag (MBF1) is set HIGH by a
LOW-to-HIGH transition on CLKB when a Port B read is
selected by CSB, W/RB, and ENB with MBB HIGH. For a
36-bit bus size, 36 bits of mailbox data are placed on B0–35.
For an 18-bit bus size, 18 bits of mailbox data are placed on
B0–17. (In this case, B18–35 are indeterminate.) For a 9-bit bus
size, 9 bits of mailbox data are placed on B0–8. (In this case,
B9–35 are indeterminate.)
The Mail2 Register flag (MBF2) is set HIGH by a
LOW-to-HIGH transition on CLKA when a Port A read is
selected by CSA, W/RA, and ENA with MBA HIGH.
For a 36-bit bus size, 36 bits of mailbox data are placed on
A0–35. For an 18-bit bus size, 18 bits of mailbox data are
placed on A0–17. (In this case, A18–35 are indeterminate.) For
a 9-bit bus size, 9 bits of mailbox data are placed on A0–8. (In
this case, A9–35 are indeterminate.)
The data in a mail register remains intact after it is read and
changes only when new data is written to the register. The
Endian Select feature has no effect on the mailbox data.
Retransmit (RT1, RT2)
The retransmit feature is beneficial when transferring packets
of data. It enables the receipt of data to be acknowledged by
the receiver and retransmitted if necessary. Retransmit
function applies to CY standard mode only.
The number of 36-/18-/9-bit words written into the FIFO should
be less than full depth minus 2/4/8 words between the reset of
the FIFO (master or partial) and Retransmit setup.A LOW
pulse on RT1, (RT2) resets the internal read pointer to the first
physical location of the FIFO. CLKA and CLKB may be free
running but ENB (ENA) must be deasserted during and tRTR
after the retransmit pulse. With every valid read cycle after
retransmit, previously accessed data is read and the read
pointer is incremented until it is equal to the write pointer. Flags
are governed by the relative locations of the read and write
pointers and are updated during a retransmit cycle. Data
written to the FIFO after activation of RT1, (RT2) are transmitted also.
Table 1. Flag Programming[2]
FS1
FS0
RST1
RST2
X1 and Y1 Registers[3]
X2 and Y2 Registers[4]
H
H
↑
X
64
X
H
H
X
↑
X
64
H
L
↑
X
16
X
H
L
X
↑
X
16
L
H
↑
X
8
X
L
H
X
↑
X
8
L
L
↑
↑
Programming via Port A
Programming via Port A
Table 2. Port A Enable Function
CSA
W/RA
ENA
MBA
CLKA
H
X
X
X
X
In high-impedance state
None
L
H
L
X
X
In high-impedance state
None
Document #: 38-06019 Rev. *B
A0–35 Outputs
Port Function
Page 8 of 30
CY7C43642
CY7C43662
CY7C43682
Table 2. Port A Enable Function (continued)
L
H
H
L
↑
In high-impedance state
FIFO1 write
L
H
H
H
↑
In high-impedance state
Mail1 write
L
L
L
L
X
Active, FIFO2 output register
None
L
L
H
L
↑
Active, FIFO2 output register
FIFO2 read
L
L
L
H
X
Active, Mail2 register
None
L
L
H
H
↑
Active, Mail2 register
Mail2 read (set MBF2 HIGH)
Table 3. Port B Enable Function
CSB
W/RB
ENB
MBB
CLKB
B0–35 Outputs
Port Function
H
X
X
X
X
In high-impedance state
None
L
L
L
X
X
In high-impedance state
None
L
L
H
L
↑
In high-impedance state
FIFO2 write
L
L
H
H
↑
In high-impedance state
Mail2 write
L
H
L
L
X
Active, FIFO1 output register
None
L
H
H
L
↑
Active, FIFO1 output register
FIFO1 read
L
H
L
H
X
Active, Mail1 register
None
L
H
H
H
↑
Active, Mail1 register
Mail1 read (set MBF1 HIGH)
Table 4. FIFO1 Flag Operation (CY Standard and FWFT modes)[2]
Number of Words in FIFO Memory[5, 6, 7, 8]
CY7C43642
CY7C43662
CY7C43682
Synchronized to CLKB
Synchronized to CLKA
EFB/ORB
AEB
AFA
FFA/IRA
0
0
0
L
L
H
H
1 TO X1
1 TO X1
1 TO X1
H
L
H
H
(X1+1) to
[1024–(Y1+1)]
(X1+1) to
[4096–(Y1+1)]
(X1+1) to
[16384–(Y1+1)]
H
H
H
H
(1024–Y1) to 1023
(4096–Y1) to 4095
(16384–Y1) to 16383
H
H
L
H
1024
4096
16384
H
H
L
L
Table 5. FIFO2 Flag Operation (CY Standard and FWFT modes)[2]
Number of Words in FIFO Memory[6, 7, 8, 9]
CY7C43642
0
CY7C43662
0
Synchronized to CLKA
CY7C43682
0
Synchronized to CLKB
EFA/ORA
AEA
AFB
FFB/IRB
L
L
H
H
1 TO X2
1 TO X2
1 TO X2
H
L
H
H
(X2+1) to
[1024–(Y2+1)]
(X2+1) to
[4096–(Y2+1)]
(X2+1) to
[16384–(Y2+)1]
H
H
H
H
(1024–Y2) to 1023
(4096–Y2) to 4095
(16384–Y2) to 16383
H
H
L
H
1024
4096
16384
H
H
L
L
Notes:
3. X1 register holds the offset for AEB; Y1 register holds the offset for AFA.
4. X2 register holds the offset for AEA; Y2 register holds the offset for AFB.
5. X1 is the Almost Empty offset for FIFO1 used by AEB. Y1 is the Almost Full offset for FIFO1 used by AFA. Both X1 and Y1 are selected during a FIFO1 reset
or port A programming.
6. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.
7. Data in the output register does not count as a “word in FIFO memory.” Since in FWFT mode, the first word written to an empty FIFO goes unrequested to the
output register (no read operation necessary), it is not included in the FIFO memory count.
8. The ORA and IRB functions are active during FWFT mode; the EFA and FFB functions are active in CY Standard Mode.
9. X2 is the Almost Empty offset for FIFO2 used by AEA. Y2 is the Almost Full offset for FIFO2 used by AFB. Both X2 and Y2 are selected during a FIFO2 reset
or port A programming.
Document #: 38-06019 Rev. *B
Page 9 of 30
CY7C43642
CY7C43662
CY7C43682
Maximum Ratings[10,11]
Static Discharge Voltage........................................... > 2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guidelines, not tested.)
Latch-up Current...................................................... > 200mA
Storage Temperature ...................................–65°C to +150°C
Ambient Temperature with
Power Applied...............................................–55°C to +125°C
Operating Range
Supply Voltage to Ground Potential ............... –0.5V to +7.0V
Range
Ambient
Temperature
VCC[13]
DC Voltage Applied to Outputs
in High-Z State[12] ....................................–0.5V to VCC+0.5V
Commercial
0°C to +70°C
5.0V ± 0.5V
−40°C to +85°C
5.0V ± 0.5V
DC Input Voltage[12] .................................–0.5V to VCC+0.5V
Industrial
Output Current into Outputs (LOW) .............................20 mA
Electrical Characteristics Over the Operating Range
CY7C43642/62/82
Parameter
Description
Test Conditions
VOH
Output HIGH Voltage
VCC = 4.5V,
IOH = −4.0 mA
VOL
Output LOW Voltage
VCC = 4.5V,
IOL = 8.0 mA
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
IIX
Input Leakage Current
IOZL
IOZH
Output OFF, High-Z
Current
ICC1[14]
Active Power Supply Current
ISB[15]
Average Standby Current
Min.
Max.
Unit
2.4
V
0.5
V
2.0
VCC
V
–0.5
0.8
V
VCC = Max.
–10
+10
µA
OE > VIH,
VSS < VO< VCC
–10
+10
µA
Com’l
100
mA
Ind
100
mA
Com’l
10
mA
Ind
10
mA
Capacitance[16]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 3.3V
Max.
Unit
4
pF
8
pF
Notes:
10. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
11. The Voltage on any input or I/O pin cannot exceed the power pin during power-up.
12. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
13. Operating VCC Range for -7 speed is 5.0V ± 0.25V.
14. Input signals switch from 0V to 3V with a rise/fall time of less than 3 ns, clocks and clock enables switch at 20 MHz, while data inputs switch at 10 MHz.
Outputs are unloaded.
15. All inputs = VCC – 0.2V, except RCLK and WCLK (which are at frequency = 0 MHz). All outputs are unloaded.
16. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-06019 Rev. *B
Page 10 of 30
CY7C43642
CY7C43662
CY7C43682
AC Test Loads and Waveforms (-10 and -15)
R1 = 1.1kΩ
ALL INPUT PULSES
5V
OUTPUT
3.0V
CL = 30 pF
R2 = 680Ω
90%
10%
90%
10%
GND
≤ 3 ns
INCLUDING
JIG AND
SCOPE
≤ 3 ns
AC Test Loads and Waveforms (-7)
VCC/2
50Ω
I/O
ALL INPUT PULSES
3.0V
GND
Z0 = 50Ω
90%
10%
90%
10%
≤ 3 ns
≤ 3 ns
Switching Characteristics Over the Operating Range
CY7C43642/62/82 CY7C43642/62/82 CY7C43642/62/82
-7
-10
-15
Parameter
Description
Min.
Max.
Min.
133
Max.
Min.
100
Max.
Unit
67
MHz
fS
Clock Frequency, CLKA or CLKB
tCLK
Clock Cycle Time, CLKA or CLKB
7.5
10
15
ns
tCLKH
Pulse Duration, CLKA or CLKB HIGH
3.5
4
6
ns
tCLKL
Pulse Duration, CLKA or CLKB LOW
3.5
4
6
ns
tDS
Set-up Time, A0–35 before CLKA↑ and B0–35
before CLKB↑
3
4
5
ns
tENS
Set-up Time, CSA, W/RA, ENA, and MBA before
CLKA↑; CSB, W/RB, ENB, and MBB before
CLKB↑
3
4
5
ns
tRSTS
Set-up Time, RST1, RST2, RT1 or RT2 LOW
before CLKA↑ or CLKB↑[17]
2.5
4
5
ns
tFSS
Set-up Time, FS0 and FS1 before RST1 and
RST2 HIGH
6
7
7.5
ns
tSDS
Set-up Time, FS0 before CLKA↑
3
4
5
ns
tSENS
Set-up Time, FS1 before CLKA↑
3
4
5
ns
tFWS
Set-up Time, FWFT before CLKA↑
0
0
0
ns
tDH
Hold Time, A0–35 after CLKA↑ and B0–35 after
CLKB↑
0
0
0
ns
tENH
Hold Time, CSA, W/RA, ENA, and MBA after
CLKA↑; CSB, W/RB, ENB, and MBB after
CLKB↑
0
0
0
ns
tRSTH
Hold Time, RST1, RST2, RT1 or RT2 LOW after
CLKA↑ or CLKB↑[17]
1
2
4
ns
tFSH
Hold Time, FS0 and FS1 after RST1 and RST2
HIGH
1
1
2
ns
tSDH
Hold Time, FS0 after CLKA↑
0
0
0
ns
tSENH
Hold Time, FS1 after CLKA↑
0
0
0
ns
Note:
17. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between the CLKA cycle and the CLKB
cycle.
Document #: 38-06019 Rev. *B
Page 11 of 30
CY7C43642
CY7C43662
CY7C43682
Switching Characteristics Over the Operating Range (continued)
CY7C43642/62/82 CY7C43642/62/82 CY7C43642/62/82
-7
-10
-15
Parameter
tSPH
Description
Hold Time, FS1 HIGH after RST1 and RST2
HIGH
Min.
Max.
Min.
Max.
Min.
Max.
Unit
0
1
2
ns
tSKEW1[17] Skew Time between CLKA↑ and CLKB↑ for
EFA/ORA, EFB/ORB, FFA/IRA, and FFB/IRB
5
5
7.5
ns
tSKEW2[17] Skew Time between CLKA↑ and CLKB↑ for
AEA, AEB, AFA, AFB
7
8
12
ns
tA
Access Time, CLKA↑ to A0–35 and CLKB↑ to
B0–35
1
6
1
8
3
10
ns
tWFF
Propagation Delay Time, CLKA↑ to FFA/IRA
and CLKB↑ to FFB/IRB
1
6
1
8
2
8
ns
tREF
Propagation Delay Time, CLKA↑ to EFA/ORA
and CLKB↑ to EFB/ORB
1
6
1
8
1
8
ns
tPAE
Propagation Delay Time, CLKA↑ to AEA and
CLKB↑ to AEB
1
6
1
8
1
8
ns
tPAF
Propagation Delay Time, CLKA↑ to AFA and
CLKB↑ to AFB
1
6
1
8
1
8
ns
tPMF
Propagation Delay Time, CLKA↑ to MBF1 LOW
or MBF2 HIGH and CLKB↑ to MBF2 LOW or
MBF1 HIGH
0
6
0
8
0
12
ns
tPMR
Propagation Delay Time, CLKA↑ to B0–35[18] and
CLKB↑ to A0–35[19]
1
7
2
11
3
12
ns
tMDV
Propagation Delay Time, MBA to A0–35 valid and
MBB to B0–35 valid[20]
1
6
2
9
3
11
ns
tRSF
Propagation Delay Time, RST1 LOW to AEB
LOW, AFA HIGH, FFA/IRA Low, EFB/ORB
LOW, and MBF1 HIGH and RST2 LOW to AEA
LOW, AFB HIGH, FFB/IRB Low, EFA/ORA
LOW, and MBF2 HIGH
1
6
1
10
1
15
ns
tEN
Enable Time, CSA or W/RA LOW to A0–35 Active
and CSB LOW and W/RB HIGH to B0–35 Active
1
6
2
8
2
10
ns
tDIS
Disable Time, CSA or W/RA HIGH to A0–35 at
High Impedance and CSB HIGH or W/RB LOW
to B0–35 at High Impedance
1
5
1
6
1
8
ns
tRTR
Retransmit Recovery Time
90
90
90
ns
Notes:
18. Writing data to the Mail1 register when the B0–35 outputs are active and MBB is HIGH.
19. Writing data to the Mail2 register when the A0–35 outputs are active and MBA is HIGH.
20. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
Document #: 38-06019 Rev. *B
Page 12 of 30
CY7C43642
CY7C43662
CY7C43682
Switching Waveforms
FIFO1 Reset Loading X1 and Y1 with a Preset Value of Eight [21]
CLKA
CLKB
RST1
tRSTH
tRSTS
tFWS
FWFT/STAN
tFSS
tFSH
FS1, FS0
tRSF
FFA/IRA
EFB/ORB
AEB
tWFF
tRSF
tRSF
tRSF
AFA
tRSF
MBF1
Note:
21. Reset is performed in the same manner for FIFO2 to load X2 and Y2 with a preset value.
Document #: 38-06019 Rev. *B
Page 13 of 30
CY7C43642
CY7C43662
CY7C43682
Switching Waveforms (continued)
Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset
(CY Standard and FWFT Modes) [22]
CLKA
RST1, RST2
tFSS
tFSH
FS1, FS0
tWFF
FFA/IRA
tENS
tENH
tSKEW1[23]
ENA
tDS
tDH
A0−35
AFA Offset (Y1)
AEB Offset (X1)AFB Offset (Y2)AEA Offset (X2)First Word to FIFO1
CLKB
tWFF
FFB/IRB
Port A Write Cycle Timing for FIFO1 (CY Standard and FWFT Modes)
tCLK
tCLKH
tCLKL
CLKA
FFA/IRA
HIGH
tENS tENH
CSA
tENS
tENH
W/RA[24]
tENS tENH
MBA
tENS
ENA
A0–35
tENH
tDS
tENS
tENH
tENS
tENH
tDH
W1[25]
W2[25]
Notes:
22. CSA = LOW, W/RA=HIGH, MBA=LOW. It is not necessary to program offset register on consecutive clock cycles.
23. tSKEW1 is the minimum time between the rising CLKA edge and a rising CLKB for FFB/IRB to transition HIGH in the next cycle. If the time between the rising
edge of CLKA and rising edge of CLKB is less than tSKEW1, then FFB/IRB may transition HIGH one cycle later than shown.
24. If W/RA switches from read to write before the assertion of CSA, tENS = tDIS+tENS.
25. Written to FIFO1.
Document #: 38-06019 Rev. *B
Page 14 of 30
CY7C43642
CY7C43662
CY7C43682
Switching Waveforms (continued)
Port B Write Cycle Timing for FIFO2 (CY Standard and FWFT Modes)
tCLK
tCLKL
tCLKH
CLKB
FFB/IRB
HIGH
tENS tENH
CSB
tENS
tENH
W/RB[26]
tENS tENH
MBB
tENS
ENB
tENH
tDS
B0−35
tENS
tENH
tENS
tENH
tDH
W2[27]
W1[27]
Port B Read Cycle Timing for FIFO1 (CY Standard and FWFT Modes)
[1]
tCLK
tCLKL
tCLKH
CLKB
EFB/ORB
HIGH
CSB
W/RB[26]
MBB
tENS
tENH
ENB
B0–35
(Standard Mode)
OR
tEN
tMDV
tEN
B0–35
(FWFT Mode)
tENS
No Operation
[28]
tA
W1
[28]
W2
tDIS
[28]
W2
tMDV
[28]
tENH
tA
tA
Previous Data
tENH
tENS
W2
tDIS
W3[28]
Notes:
26. If W/RB switches from read to write before the assertion of CSB, tENS = tDIS+tENS.
27. Written to FIFO2.
28. Read from FIFO1.
Document #: 38-06019 Rev. *B
Page 15 of 30
CY7C43642
CY7C43662
CY7C43682
Switching Waveforms (continued)
Port A Read Cycle Timing for FIFO2 (CY Standard and FWFT Modes)
[1]
tCLK
tCLKL
tCLKH
CLKA
EFA/ORA
HIGH
CSA
W/RA[24]
MBA
tENS
tENH
tENS
ENA
A0−35
(Standard Mode)
OR
tEN
tMDV
tEN
A0−35
(FWFT Mode)
No Operation
W2[29]
[29]
W2
tDIS
[29]
tA
tMDV
W1[29]
tENH
tA
tA
Previous Data
tENH
tENS
W2
tDIS
[29]
W3
Note:
29. Read From FIFO2.
Document #: 38-06019 Rev. *B
Page 16 of 30
CY7C43642
CY7C43662
CY7C43682
Switching Waveforms (continued)
[1]
ORB Flag Timing and First Data Word Fall Through when FIFO1 is Empty (FWFT Mode)
tCLK
tCLKL
tCLKH
CLKA
CSA
LOW
W/RA
HIGH
tENS tENH
MBA
tENH
tENS
ENA
FFA/IRA
HIGH
tDS
A0–35
W1
tSKEW1[30]
CLKB
EFB/ORB
CSB
W/RB
MBB
tDH
tCLKH
tCLKL
tCLK
tREF
tREF
FIFO1 Empty
LOW
HIGH
LOW
tENS
tENH
ENB
tA
B0–35
Old Data in FIFO1 Output Register
W1
Note:
30. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for ORB to transition HIGH and to clock the next word to the FIFO1 output
register in three CLKB cycles. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of ORB HIGH and load
of the first word to the output register may occur one CLKB cycle later than shown.
Document #: 38-06019 Rev. *B
Page 17 of 30
CY7C43642
CY7C43662
CY7C43682
Switching Waveforms (continued)
EFB Flag Timing and First Data Read Fall Through when FIFO1 is
Empty (CY Standard Mode)
tCLK
tCLKH tCLKL
CLKA
CSA
W/RA
LOW
HIGH
tENS tENH
MBA
tENH
tENS
ENA
FFA/IRA
HIGH
tDS
A0–35
tDH
W1
tSKEW1[31] tCLKH
CLKB
tCLKL
tCLK
EFB/ORB
CSB
W/RB
MBB
tREF
tREF
FIFO1 Empty
LOW
HIGH
LOW
tENS
tENH
ENB
tA
B0–35
W1
Note:
31. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for EFB to transition HIGH in the next CLKB cycle. If the time between the
rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of EFB HIGH may occur one CLKB cycle later than shown.
Document #: 38-06019 Rev. *B
Page 18 of 30
CY7C43642
CY7C43662
CY7C43682
Switching Waveforms (continued)
[1]
ORA Flag Timing and First Data Word Fall Through when FIFO2 is Empty
(FWFT Mode) [32]
tCLK
tCLKH tCLKL
CLKB
CSB
LOW
W/RB
LOW
tENH
tENS
MBB
tENS
tENH
ENB
FFB/IRB
HIGH
tDH
tDS
B0–35
W1
tSKEW1[33] tCLKH
tCLKL
CLKA
tCLK
EFA/ORA
FIFO2 Empty
CSA
LOW
W/RA
LOW
MBA
LOW
tREF
tENS
tREF
tENH
ENA
tA
A0–35
Old Data in FIFO2 Output Register
W1
Notes:
32. tSKEW1 is referenced to the rising CLKB edge that writes the last word or byte of the long word, respectively.
33. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for ORA to transition HIGH and to clock the next word to the FIFO2 output
register in three CLKA cycles. If the time between the rising CLKB edge and rising CLKA edge is less than tSKEW1, then the transition of ORA HIGH and load
of the first word to the output register may occur one CLKA cycle later than shown.
Document #: 38-06019 Rev. *B
Page 19 of 30
CY7C43642
CY7C43662
CY7C43682
Switching Waveforms (continued)
EFA Flag Timing and First Data Read when FIFO2 is Empty (CY Standard Mode)
tCLK
tCLKH
tCLKL
CLKB
CSB
LOW
W/RB
LOW
tENS
tENH
tENS
tENH
MBB
ENB
FFB/IRB
HIGH
tDS
B0–35
tDH
W1
tSKEW1[34] tCLKH
tCLKL
CLKA
tCLK
EFA/ORA
FIFO2 Empty
CSA
LOW
W/RA
LOW
MBA
LOW
tREF
tREF
tENS
tENH
ENA
tA
A0–35
W1
Note:
34. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for EFA to transition HIGH in the next CLKA cycle. If the time between the
rising CLKB edge and rising CLKA edge is less than tSKEW1, then the transition of EFA HIGH may occur one CLKA cycle later than shown.
Document #: 38-06019 Rev. *B
Page 20 of 30
CY7C43642
CY7C43662
CY7C43682
Switching Waveforms (continued)
IRA Flag Timing and First Available Write when FIFO1 is Full (FWFT Mode)
tCLK
tCLKH tCLKL
CLKB
CSB
LOW
W/RB
HIGH
MBB
LOW
tENH
tENS
ENB
EFB/ORB
HIGH
tA
B0–35
CLKA
Previous Word in FIFO1
Next Word From FIFO1
Output Register
tCLKL
[35] tCLKH
tSKEW1
tCLK
FFA/IRA
FIFO1 Full
CSA
LOW
W/RA
HIGH
tWFF
tWFF
tENS
tENH
MBA
tENS
tENH
tDS
tDH
ENA
A0–35
To FIFO1
Note:
35. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for IRA to transition HIGH in the next CLKA cycle. If the time between the
rising CLKB edge and rising CLKA edge is less than tSKEW1, then IRA may transition HIGH one CLKA cycle later than shown.
Document #: 38-06019 Rev. *B
Page 21 of 30
CY7C43642
CY7C43662
CY7C43682
Switching Waveforms (continued)
FFA Flag Timing and First Available Write when FIFO1 is Full (CY Standard Mode)
tCLK
tCLKH tCLKL
CLKB
CSB
LOW
W/RB
HIGH
MBB
LOW
tENS
tENH
ENB
EFB/ORB
HIGH
tA
B0–35
Previous Word in FIFO1
Output Register
t
Next Word From FIFO1
tCLKH tCLKL
[36]
SKEW1
CLKA
tCLK
FFA/IRA
FIFO1 Full
CSA
LOW
W/RA
HIGH
tWFF
tWFF
tENS tENH
MBA
tENS
tENH
tDS
tDH
ENA
A0−35
Note:
36. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for FFA to transition HIGH in the next CLKA cycle. If the time between the
rising CLKB edge and rising CLKA edge is less than tSKEW1, then the transition of FFA HIGH may occur one CLKA cycle later than shown.
Document #: 38-06019 Rev. *B
Page 22 of 30
CY7C43642
CY7C43662
CY7C43682
Switching Waveforms (continued)
IRB Flag Timing and First Available Write when FIFO2 is Full (FWFT Mode)
tCLK
tCLKH tCLKL
CLKA
CSA
LOW
W/RA
LOW
MBA
LOW
tENS
tENH
ENA
EFA/ORA
HIGH
tA
A0–35
Previous Word in FIFO2 Out- Next Word From FIFO2
put Register
tCLKH tCLKL
tSKEW1[37]
CLKB
tCLK
FFB/IRB
FIFO2 Full
CSB
LOW
W/RB
LOW
tWFF
tWFF
tENS
tENH
tENS
tENH
tDS
tDH
MBB
ENB
B0–35
To FIFO2
Note:
37. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for IRB to transition HIGH in the next CLKB cycle. If the time between the
rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of IRB HIGH may occur one CLKB cycle later than shown.
Document #: 38-06019 Rev. *B
Page 23 of 30
CY7C43642
CY7C43662
CY7C43682
Switching Waveforms (continued)
FFB Flag Timing and First Available Write when FIFO2 is Full (CY Standard Mode)
tCLK
tCLKH tCLKL
CLKA
CSA
LOW
W/RA
LOW
MBA
LOW
tENS
tENH
ENA
EFA/ORA
HIGH
tA
A0–35
Previous Word in FIFO2
Output Register
t
[38
SKEW1
Next Word From FIFO2
tCLKH tCLKL
CLKB
tCLK
FFB/IRB
FIFO2 Full
CSB
LOW
W/RB
LOW
tWFF
tENS
tWFF
tENH
MBB
tENS
tENH
tDS
tDH
ENB
B0–35
To FIFO2
Note:
38. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for FFB to transition HIGH in the next CLKB cycle. If the time between the
rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of FFB HIGH may occur one CLKB cycle later than shown.
Document #: 38-06019 Rev. *B
Page 24 of 30
CY7C43642
CY7C43662
CY7C43682
Switching Waveforms (continued)
Timing for AEB when FIFO1 is Almost Empty (CY Standard and FWFT Modes) [39, 40,2]
CLKA
tENS
tENH
ENA
tSKEW2[41]
CLKB
tPAE
tPAE
AEB
X1 Word in FIFO1
(X1+1)Words in FIFO1
tENS
(X1+1) Words in FIFO1
tENH
ENB
Timing for AEA when FIFO2 is Almost Empty (CY Standard and FWFT Modes)[42, 43,2]
CLKB
ENB
tENS
tENH
tSKEW2[44]
CLKA
tPAE
tPAE
AEA
X2 Word in FIFO2
(X2+1) Words in FIFO2
(X2+1) Words in FIFO2
tENS
tENH
ENA
Notes:
39. FIFO1 Write (CSA = LOW, W/RA = LOW, MBA = LOW), FIFO1 Read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has been
read from the FIFO.
40. If Port B size is word or byte, AEB is set LOW by the last word or byte read from FIFO1, respectively.
41. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AEB to transition HIGH in the next CLKB cycle. If the time between the
rising CLKA edge and rising CLKB edge is less than tSKEW2, then AEB may transition HIGH one CLKB cycle later than shown.
42. FIFO2 Write (CSB = LOW, W/RB = LOW, MBB = LOW), FIFO2 Read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been
read from the FIFO.
43. If Port B size is word or byte, tSKEW2 is referenced to the rising CLKB edge that writes the last word or byte of the long word, respectively.
44. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AEA to transition HIGH in the next CLKA cycle. If the time between the
rising CLKB edge and rising CLKA edge is less than tSKEW2, then AEA may transition HIGH one CLKA cycle later than shown.
Document #: 38-06019 Rev. *B
Page 25 of 30
CY7C43642
CY7C43662
CY7C43682
Switching Waveforms (continued)
Timing for AFA when FIFO1 is Almost Full (CY Standard and FWFT Modes) [43,2,45, 46]
tSKEW2[47]
CLKA
tENS
tENH
ENA
AFA
tPAF
[D–(Y1+1)] Words in FIFO1
tPAF
(D–Y1)Words in FIFO1
CLKB
tENS
tENH
ENB
Timing for AFB when FIFO2 is Almost Full (CY Standard and FWFT Modes) [42,2, 46]
tSKEW2[48]
CLKB
ENB
tENS
tENH
tPAF
AFB
[D–(Y2+1)] Words in FIFO2
tPAF
(D–Y2)Words in FIFO2
CLKA
tENS
tENH
ENA
Notes:
45. FIFO1 Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 Read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has been
read from the FIFO.
46. D = Maximum FIFO Depth 1K for the CY7C43642, 4K for the CY7C43662, and 16K for the CY7C43682.
47. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AFA to transition HIGH in the next CLKA cycle. If the time between the
rising CLKA edge and rising CLKB edge is less than tSKEW2, then AFA may transition HIGH one CLKB cycle later than shown.
48. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AFB to transition HIGH in the next CLKB cycle. If the time between the
rising CLKB edge and rising CLKA edge is less than tSKEW2, then AFB may transition HIGH one CLKA cycle later than shown.
Document #: 38-06019 Rev. *B
Page 26 of 30
CY7C43642
CY7C43662
CY7C43682
Switching Waveforms (continued)
Timing for Mail1 Register and MBF1 Flag (CY Standard and FWFT Modes) [49]
CLKA
tENS
tENH
CSA
tENS
tENH
tENS
tENH
tENS
tENH
tDS
tDH
W/RA[24]
MBA
ENA
A0–35
W1
CLKB
tPMF
tPMF
MBF1
CSB
W/RB[26]
MBB
tENS
tENH
ENB
B0-35
tEN
tMDV
tPMR
FIFO1 Output Register
tDIS
W1 (Remains valid in Mail1 Register after read)
49. Simultaneous writing to and reading from mailbox register is not allowed.
Document #: 38-06019 Rev. *B
Page 27 of 30
CY7C43642
CY7C43662
CY7C43682
Switching Waveforms (continued)
Timing for Mail2 Register and MBF2 Flag (CY Standard and FWFT Modes)
[49]
CLKB
tENS
tENH
CSB
tENS
tENH
W/RB[26]
tENS
tENH
tENS
tENH
tDS
tDH
MBB
ENB
B0–35
W1
CLKA
tPMF
tPMF
MBF2
CSA
W/RA[24]
MBA
tENS
tENH
ENA
tMDV
tEN
A0−35
FIFO2 Output Register
tPMR
tDIS
W1 (Remains valid in Mail2 Register after read)
FIFO1 Retransmit Timing [50,51,52,53,54]
CLKA
CLKB
tRSTS
tRSTH
RT1
tRTR
ENB
EFB/FFA
Notes:
50. Retransmit is performed in the same manner for FIFO2.
51. Clocks are free-running in this case. CY standard mode only. Write operation should be prohibited one write clock cycle before the falling edge of RT1, and
during the retransmit operation, i.e. when RT1 is LOW and tRTR after the RT1 rising edge.
52. The Empty and Full flags may change state during Retransmit as a result of the offset of the read and write pointers, but flags will be valid at tRTR.
53. For the AEA, AEB, AFA, and AFB flags, two clock cycle are necessary after tRTR to update these flags.
54. The number of 36-/18-/9-bit words written into the FIFO should be less than full depth minus 2/4/8 words between the reset of the FIFO (master or partial) and
the Retransmit setup.
Document #: 38-06019 Rev. *B
Page 28 of 30
CY7C43642
CY7C43662
CY7C43682
Ordering Information
1K x36 x2 Bidirectional Synchronous FIFO
Speed
(ns)
Ordering Code
Package
Name
Package
Type
Operating
Range
7
CY7C43642–7AC
A120
120-lead Thin Quad Flat Package
Commercial
10
CY7C43642–10AC
A120
120-lead Thin Quad Flat Package
Commercial
15
CY7C43642–15AC
A120
120-lead Thin Quad Flat Package
Commercial
4K x36 x2 Bidirectional Synchronous FIFO
Speed
(ns)
Ordering Code
Package
Name
Package
Type
Operating
Range
7
CY7C43662–7AC
A120
120-lead Thin Quad Flat Package
Commercial
10
CY7C43662–10AC
A120
120-lead Thin Quad Flat Package
Commercial
15
CY7C43662–15AC
A120
120-lead Thin Quad Flat Package
Commercial
16K x36 x2 Bidirectional Synchronous FIFO
Speed
(ns)
Ordering Code
Package
Name
Package
Type
Operating
Range
7
CY7C43682–7AC
A120
120-lead Thin Quad Flat Package
Commercial
10
CY7C43682–10AC
A120
120-lead Thin Quad Flat Package
Commercial
15
CY7C43682–15AC
A120
120-lead Thin Quad Flat Package
Commercial
15
CY7C43682–15AI
A120
120-lead Thin Quad Flat Package
Industrial
Package Diagram
120-pin Thin Quad Flatpack (14 x 14 x 1.4 mm) A120
51-85100
All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-06019 Rev. *B
Page 29 of 30
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C43642
CY7C43662
CY7C43682
Document Title: CY7C43642, CY7C43662, CY7C43682 1K/4K/16K x36 x2 Bidirectional Synchronous FIFO
Document Number: 38-06019
REV.
ECN NO.
Issue Date
Orig. of
Change
Description of Change
**
106556
06/08/01
SZV
Change from Spec #: 38-00698 to 38-06019
*A
117171
08/23/02
OOR
Added footnote to retransmit timing
Added note to retransmit section
*B
122271
12/26/02
RBI
Document #: 38-06019 Rev. *B
Power up requirements added to Maximum Ratings Information
Page 30 of 30