Cypress CY7C038V-20AXC 3.3v 32k/64k x 16/18 dual-port static ram Datasheet

CY7C027V/027VN/027AV/028V
CY7C037V/037AV/038V
3.3V 32K/64K x 16/18 Dual-Port Static
RAM
Features
■
■
■
True Dual-Ported memory cells which allow
simultaneous access of the same memory location
[1]
■ 32K x 16 organization (CY7C027V/027VN/027AV
)
■ 64K x 16 organization (CY7C028V)
[2]
■ 32K x 18 organization (CY7C037V/037AV )
■ 64K x 18 organization (CY7C038V)
■ 0.35 micron CMOS for optimum speed and power
■ High speed access: 15, 20, and 25 ns
■ Low operating power
■ Active: ICC = 115 mA (typical)
■ Standby: ISB3 = 10 μA (typical)
■
■
■
■
■
■
■
■
■
Fully asynchronous operation
Automatic power down
Expandable data bus to 32/36 bits or more using Master/Slave
chip select when using more than one device
On-chip arbitration logic
Semaphores included to permit software handshaking
between ports
INT flag for port-to-port communication
Separate upper-byte and lower-byte control
Dual chip enables
Pin select for Master or Slave
Commercial and Industrial temperature ranges
100-pin Pb-free TQFP and 100-pin TQFP
Logic Block Diagram
R/WL
UBL
R/WR
UBR
CE0L
CE1L
CEL
CE0R
CE1R
CER
LBL
LBR
OEL
OER
[3]
I/O8/9L–I/O15/17L
[4]
8/9
8/9
8/9
8/9
I/O
Control
I/O0L–I/O7/8L
[5]
A0L–A14/15L
[5]
15/16
Address
Decode
15/16
[4]
I/O0L–I/O7/8R
Address
Decode
True Dual-Ported
RAM Array
15/16
[5]
A0R–A14/15R
15/16
A0L–A14/15L
CEL
OEL
R/WL
SEML
BUSYL
INTL
UBL
LBL
I/O
Control
[3]
I/O8/9L–I/O15/17R
[5]
A0R–A14/15R
CER
OER
R/WR
SEMR
Interrupt
Semaphore
Arbitration
[6]
[6]
M/S
BUSYR
INTR
UBR
LBR
Notes
1. CY7C027V, CY7C027VN and CY7C027AV are functionally identical.
2. CY7C037V and CY7C037AV are functionally identical.
3. I/O8–I/O15 for x16 devices; I/O9–I/O17 for x18 devices.
4. I/O0–I/O7 for x16 devices; I/O0–I/O8 for x18 devices.
5. A0–A14 for 32K; A0–A15 for 64K devices.
6. BUSY is an output in master mode and an input in slave mode.
Cypress Semiconductor Corporation
Document #: 38-06078 Rev. *B
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised December 09, 2008
[+] Feedback
CY7C027V/027VN/027AV/028V
CY7C037V/037AV/038V
Pin Configurations
A8R
A7R
A6R
A5R
A4R
A3R
A2R
A1R
A0R
INTR
BUSYR
M/S
GND
BUSYL
INTL
NC
A0L
A1L
A2L
A3L
A4L
A5L
A6L
A7L
A8L
Figure 1. 100-Pin TQFP (Top View)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
A9L
1
75
A9R
A10L
2
74
A10R
A11L
3
73
A11R
A12L
4
72
A12R
A13L
5
71
A13R
A14L
6
70
A14R
[1] A15L
7
69
A15R [1]
NC
8
68
NC
NC
9
67
NC
LBL
10
66
LBR
UBL
11
65
UBR
64
CE0R
63
CE1R
62
SEMR
CY7C028V (64K x 16)
CY7C027V/027VN/027AV (32K x 16)
CE0L
12
CE1L
13
SEML
14
VCC
15
61
GND
R/WL
16
60
R/WR
OEL
17
59
OER
GND
18
58
GND
GND
19
57
GND
I/O15L
20
56
I/O15R
I/O14L
21
55
I/O14R
I/O13L
22
54
I/O13R
I/O12L
23
53
I/O12R
I/O11L
24
52
I/O11R
I/O10L
25
51
I/O10R
NC
I/O9R
I/O8R
I/O7R
VCC
I/O6R
I/O5R
I/O4R
I/O3R
I/O2R
I/01R
I/O0R
GND
I/O0L
I/O1L
GND
I/O2L
I/O3L
I/O4L
I/O5L
I/O6L
I/O7L
VCC
I/O8L
I/O9L
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Note
1. This pin is NC for CY7C027V/027VN/027AV.
Document #: 38-06078 Rev. *B
Page 2 of 18
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CY7C027V/027VN/027AV/028V
CY7C037V/037AV/038V
Pin Configurations (continued)
A7R
A6R
A5R
A4R
A3R
A2R
A1R
A0R
INTR
BUSYR
M/S
VCC
GND
GND
BUSYL
INTL
A0L
A1L
A2L
A3L
A4L
A5L
A6L
A7L
A8L
Figure 2. 100-Pin TQFP (Top View)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
[2]
A9L
1
75
A8R
A10L
2
74
A9R
A11L
3
73
A10R
A12L
4
72
A11R
A13L
5
71
A12R
A14L
6
70
A13R
A15L
7
69
A14R
LBL
8
68
A15R [2]
UBL
9
67
LBR
CE0L
10
66
UBR
CE1L
11
65
CE0R
SEML
12
64
CE1R
R/WL
13
63
SEMR
OEL
14
62
R/WR
VCC
15
61
GND
GND
16
60
OER
I/O17L
17
59
GND
I/O16L
18
58
I/O17R
GND
19
57
GND
I/O15L
20
56
I/O16R
I/O14L
21
55
I/O15R
I/O13L
22
54
I/O14R
I/O12L
23
53
I/O13R
I/O11L
24
52
I/O12R
I/O10L
25
51
I/O11R
CY7C038V (64K x 18)
CY7C037V/037AV (32K x 18)
I/O10R
I/O9R
I/O8R
I/O7R
VCC
I/O6R
I/O5R
I/O4R
I/O3R
I/O2R
I/01R
I/O0R
GND
I/O0L
I/O1L
GND
I/O2L
I/O3L
I/O4L
I/O5L
I/O6L
I/O7L
VCC
I/O8L
I/O9L
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Selection Guide
-15
-20
-25
Unit
Maximum Access Time
Parameter
15
20
25
ns
Typical Operating Current
125
120
115
mA
Typical Standby Current for ISB1 (Both ports TTL level)
35
35
30
mA
10 μA
10 μA
10 μA
μA
Typical Standby Current for ISB3 (Both ports CMOS level)
Note
2. This pin is NC for CY7C037V/037AV.
Document #: 38-06078 Rev. *B
Page 3 of 18
[+] Feedback
CY7C027V/027VN/027AV/028V
CY7C037V/037AV/038V
Pin Definitions
Left Port
Right Port
Description
CE0L, CE1L
CE0R, CE1R
Chip Enable (CE is LOW when CE0 ≤ VIL and CE1 ≥ VIH)
R/WL
R/WR
Read/Write Enable
OEL
OER
Output Enable
A0L–A15L
A0R–A15R
Address (A0–A14 for 32K; A0–A15 for 64K devices)
I/O0L–I/O17L
I/O0R–I/O17R
Data Bus Input/Output (I/O0–I/O15 for x16 devices; I/O0–I/O17 for x18)
SEML
SEMR
Semaphore Enable
UBL
UBR
Upper Byte Select (I/O8–I/O15 for x16 devices; I/O9–I/O17 for x18 devices)
LBL
LBR
Lower Byte Select (I/O0–I/O7 for x16 devices; I/O0–I/O8 for x18 devices)
INTL
INTR
Interrupt Flag
BUSYL
BUSYR
Busy Flag
M/S
Master or Slave Select
VCC
Power
GND
Ground
NC
No Connect
Architecture
The
CY7C027V/027VN/027AV/028V
and
CY7037V/037AV/038V consist of an array of 32K and 64K words
of 16 and 18 bits each of dual-port RAM cells, I/O and address
lines, and control signals (CE, OE, R/W). These control pins permit
independent access for reads or writes to any location in memory. To
handle simultaneous writes/reads to the same location, a BUSY pin is
provided on each port. Two interrupt (INT) pins can be utilized for
port-to-port communication. Two semaphore (SEM) control pins are
used for allocating shared resources. With the M/S pin, the devices can
function as a master (BUSY pins are outputs) or as a slave (BUSY pins
are inputs). The devices also have an automatic power down feature
controlled by CE. Each port is provided with its own output enable
control (OE), which allows data to be read from the device.
Functional Description
The
CY7C027V/027VN/027AV/028V
and
CY7037V/037AV/038V are low power CMOS 32K, 64K x 16/18
dual-port static RAMs. Various arbitration schemes are included
on the devices to handle situations when multiple processors
access the same piece of data. Two ports are provided, permitting independent, asynchronous access for reads and writes to
any location in memory. The devices can be utilized as
stand-alone 16/18-bit dual-port static RAMs or multiple devices
can be combined to function as a 32/36-bit or wider master/slave
dual-port static RAM. An M/S pin is provided for implementing
32/36-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic. Application areas include interprocessor/multiprocessor designs,
communications status buffering, and dual-port video/graphics
memory.
Each port has independent control pins: chip enable (CE), read
or write enable (R/W), and output enable (OE). Two flags are provided
on each port (BUSY and INT). BUSY signals that the port is trying to
access the same location currently being accessed by the other port.
The interrupt flag (INT) permits communication between ports or
Document #: 38-06078 Rev. *B
systems by means of a mail box. The semaphores are used to pass a
flag, or token, from one port to the other to indicate that a shared
resource is in use. The semaphore logic is comprised of eight shared
latches. Only one side can control the latch (semaphore) at any time.
Control of a semaphore indicates that a shared resource is in use. An
automatic power down feature is controlled independently on each port
by a chip select (CE) pin.
The
CY7C027V/027VN/027AV/028V
and
CY7037V/037AV/038V are available in 100-pin Thin Quad Plastic Flatpacks (TQFP).
Write Operation
Data must be set up for a duration of tSD before the rising edge of
R/W to guarantee a valid write. A write operation is controlled by either
the R/W pin (see Figure 7) or the CE pin (see Figure 8). Required inputs
for non-contention operations are summarized in Table 1.
If a location is being written to by one port and the opposite port
attempts to read that location, a port-to-port flowthrough delay
must occur before the data is read on the output; otherwise the
data read is not deterministic. Data is valid on the port tDDD after
the data is presented on the other port.
Read Operation
When reading the device, the user must assert both the OE and
CE pins. Data is available tACE after CE or tDOE after OE is asserted. If
the user wishes to access a semaphore flag, then the SEM pin must be
asserted instead of the CE pin, and OE must also be asserted.
Interrupts
The upper two memory locations may be used for message
passing. The highest memory location (7FFF for the
CY7C027V/027VN/027AV/37V, FFFF for the CY7C028V/38V) is
the mailbox for the right port and the second-highest memory
location (7FFE for the CY7C027V/027VN/027AV/037V/037AV,
FFFE for the CY7C028V/38V) is the mailbox for the left port.
When one port writes to the other port’s mailbox, an interrupt is
Page 4 of 18
[+] Feedback
CY7C027V/027VN/027AV/028V
CY7C037V/037AV/038V
generated to the owner. The interrupt is reset when the owner
reads the contents of the mailbox. The message is user defined.
Each port can read the other port’s mailbox without resetting the
interrupt. The active state of the busy signal (to a port) prevents
the port from setting the interrupt to the winning port. Also, an
active busy to a port prevents that port from reading its own
mailbox and, thus, resetting the interrupt to it.
If an application does not require message passing, do not
connect the interrupt pin to the processor’s interrupt request
input pin.
The operation of the interrupts and their interaction with Busy are
summarized in Table 2.
Busy
The
CY7C027V/027VN/027AV/028V
and
CY7037V/037AV/038V provide on-chip arbitration to resolve
simultaneous memory location access (contention). If both ports’
CEs are asserted and an address match occurs within tPS of each other,
the busy logic determines which port has access. If tPS is violated, one
port definitely gains permission to the location, but it is not predictable
which port gets that permission. BUSY is asserted tBLA after an address
match or tBLC after CE is taken LOW.
Master/Slave
A M/S pin is provided to expand the word width by configuring the
device as either a master or a slave. The BUSY output of the master is
connected to the BUSY input of the slave. This allows the device to
interface to a master device with no external components. Writing to
slave devices must be delayed until after the BUSY input has settled
(tBLC or tBLA), otherwise, the slave chip may begin a write cycle during
a contention situation. When tied HIGH, the M/S pin allows the device
to be used as a master and, therefore, the BUSY line is an output. BUSY
can then be used to send the arbitration outcome to a slave.
Semaphore Operation
The
CY7C027V/027VN/027AV/028V
and
CY7037V/037AV/038V provide eight semaphore latches, which
are separate from the dual-port memory locations. Semaphores
Document #: 38-06078 Rev. *B
are used to reserve resources that are shared between the two
ports.The state of the semaphore indicates that a resource is in
use. For example, if the left port wants to request a given
resource, it sets a latch by writing a zero to a semaphore location.
The left port then verifies its success in setting the latch by
reading it. After writing to the semaphore, SEM or OE must be
deasserted for tSOP before attempting to read the semaphore. The
semaphore value is available tSWRD + tDOE after the rising edge of the
semaphore write. If the left port was successful (reads a zero), it
assumes control of the shared resource, otherwise (reads a one) it
assumes the right port has control and continues to poll the semaphore.
When the right side has relinquished control of the semaphore (by
writing a one), the left side succeeds in gaining control of the
semaphore. If the left side no longer requires the semaphore, a one is
written to cancel its request.
Semaphores are accessed by asserting SEM LOW. The SEM pin
functions as a chip select for the semaphore latches (CE must remain
HIGH during SEM LOW). A0–2 represents the semaphore address. OE
and R/W are used in the same manner as a normal memory access.
When writing or reading a semaphore, the other address pins have no
effect.
When writing to the semaphore, only I/O0 is used. If a zero is written
to the left port of an available semaphore, a one appears at the same
semaphore address on the right port. That semaphore can now only be
modified by the side showing zero (the left port in this case). If the left
port now relinquishes control by writing a one to the semaphore, the
semaphore is set to one for both sides. However, if the right port had
requested the semaphore (written a zero) while the left port had control,
the right port would immediately own the semaphore as soon as the left
port released it. Table 3 shows sample semaphore operations.
When reading a semaphore, all sixteen/eighteen data lines
output the semaphore value. The read value is latched in an
output register to prevent the semaphore from changing state
during a write from the other port. If both ports attempt to access
the semaphore within tSPS of each other, the semaphore is definitely
obtained by one side or the other, but there is no guarantee which side
controls the semaphore.
Page 5 of 18
[+] Feedback
CY7C027V/027VN/027AV/028V
CY7C037V/037AV/038V
DC Input Voltage[2] .................................. –0.5V to VCC+0.5V
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage.......................................... > 1100V
Storage Temperature ................................. –65°C to +150°C
Latch-up Current.................................................... > 200 mA
Ambient Temperature with
Power Applied ............................................ –55°C to +125°C
Operating Range
Supply Voltage to Ground Potential................–0.5V to +4.6V
Range
Ambient
Temperature
VCC
DC Voltage Applied to
Outputs in High-Z State ........................... –0.5V to VCC+0.5V
Commercial
0°C to +70°C
3.3V ± 300 mV
Industrial[3]
–40°C to +85°C
3.3V ± 300 mV
Electrical Characteristics Over the Operating Range
CY7C027V/027VN/027AV/028V/CY7C037V/037AV/038V
Parameter
Description
VOH
Output HIGH Voltage
(VCC=Min., IOH= –4.0 mA)
VOL
Output LOW Voltage (VCC=Min., IOH= +4.0 mA)
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
IIX
Input Leakage Current
IOZ
Output Leakage Current
ICC
Operating Current (VCC=Max. IOUT=0
mA) Outputs Disabled
Com’l.
Standby Current (Both Ports TTL
Level) CEL & CER ≥ VIH, f=fMAX
Com’l.
ISB1
-15
-20
Min
Typ Max Min
Typ
2.4
2.4
−5
10
–10
125
185
35
50
Ind.[3]
Ind.[3]
−5
10
–10
120
175
140
195
35
45
45
55
Standby Current (One Port TTL Level) Com’l.
CEL | CER ≥ VIH, f=fMAX
Ind.[3]
80
120
75
110
85
120
ISB3
Standby Current (Both Ports CMOS
Level) CEL & CER ≥ VCC−0.2V, f=0
10
250
10
250
10
250
75
105
70
95
80
105
ISB4
Ind.
[3]
Standby Current (One Port CMOS Lev- Com’l.
el) CEL | CER ≥ VIH, f=fMAX[4]
Ind.[3]
0.4
5
ISB2
Com’l.
V
V
V
0.8
5
Unit
Max
2.2
0.8
–10
Typ
0.4
2.2
−5
Min
2.4
0.4
2.2
-25
Max
0.8
V
5
μA
10
μA
115
165
mA
30
40
mA
65
95
mA
10
250
μA
60
80
mA
mA
mA
mA
μA
mA
Capacitance[5]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 3.3V
Max
Unit
10
pF
10
pF
Notes
2. Pulse width < 20 ns.
3. Industrial parts are available in CY7C028V and CY7C038V only.
4. fMAX = 1/tRC = All inputs cycling at f = 1/tRC (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby ISB3.
5. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-06078 Rev. *B
Page 6 of 18
[+] Feedback
CY7C027V/027VN/027AV/028V
CY7C037V/037AV/038V
Figure 3. AC Test Loads and Waveforms
3.3V
3.3V
R1 = 590Ω
C = 30 pF
RTH = 250Ω
OUTPUT
OUTPUT
R1 = 590Ω
OUTPUT
C = 30 pF
R2 = 435Ω
C = 5 pF
R2 = 435Ω
VTH = 1.4V
(a) Normal Load (Load 1)
(c) Three-State Delay (Load 2)
(Used for tLZ, tHZ, tHZWE, & tLZWE
including scope and jig)
(b) Thévenin Equivalent (Load 1)
ALL INPUT PULSES
3.0V
10%
GND
90%
10%
90%
≤ 3 ns
≤ 3 ns
Switching Characteristics
Over the Operating Range[6]
CY7C027V/027VN/027AV/028V/
CY7C037V/037AV/038V
Parameter
Description
-15
Min
-20
Max
Min
Unit
-25
Max
Min
Max
Read Cycle
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Output Hold From Address Change
tACE[7]
CE LOW to Data Valid
tDOE
OE LOW to Data Valid
tLZOE[8, 9, 10]
OE LOW to Low Z
tHZOE[8, 9, 10]
OE HIGH to High Z
tLZCE[8, 9, 10]
tHZCE[8, 9, 10]
tPU[10]
tPD[10]
tABE[7]
CE LOW to Low Z
15
3
25
20
3
15
3
12
3
10
3
3
0
ns
ns
13
ns
ns
15
ns
15
ns
3
12
0
ns
25
3
12
10
ns
25
20
10
3
CE HIGH to High Z
CE LOW to Power Up
20
15
ns
0
ns
CE HIGH to Power Down
15
20
25
ns
Byte Enable Access Time
15
20
25
ns
Write Cycle
tWC
Write Cycle Time
15
20
25
tSCE[7]
CE LOW to Write End
12
16
20
ns
ns
tAW
Address Valid to Write End
12
16
20
ns
tHA
Address Hold From Write End
0
0
0
ns
tSA[7]
Address Setup to Write Start
0
0
0
ns
tPWE
Write Pulse Width
12
17
22
ns
tSD
Data Setup to Write End
10
12
15
ns
Notes
6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOI/IOH
and 30 pF load capacitance.
7. To access RAM, CE=L, UB=L, SEM=H. To access semaphore, CE=H and SEM=L. Either condition must be valid for the entire tSCE time.
8. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE.
9. Test conditions used are Load 2.
10. This parameter is guaranteed by design, but it is not production tested. For information on port-to-port delay through RAM cells from writing port to reading port,
refer to Figure 11.
Document #: 38-06078 Rev. *B
Page 7 of 18
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CY7C027V/027VN/027AV/028V
CY7C037V/037AV/038V
Switching Characteristics Over the Operating Range[6](continued)
CY7C027V/027VN/027AV/028V/
CY7C037V/037AV/038V
Parameter
Description
-15
Min
-20
Max
0
Min
Unit
-25
Max
Min
0
Max
tHD
Data Hold From Write End
tHZWE[9, 10]
R/W LOW to High Z
0
tLZWE[9 ,10]
R/W HIGH to Low Z
tWDD[36]
tDDD[36]
Write Pulse to Data Delay
30
40
50
ns
Write Data Valid to Read Data Valid
25
30
35
ns
tBLA
BUSY LOW from Address Match
15
20
20
ns
tBHA
BUSY HIGH from Address Mismatch
15
20
20
ns
tBLC
BUSY LOW from CE LOW
15
20
20
ns
tBHC
BUSY HIGH from CE HIGH
tPS
Port Setup for Priority
5
5
5
ns
tWB
R/W HIGH after BUSY (Slave)
0
0
0
ns
tWH
R/W HIGH after BUSY HIGH (Slave)
13
tBDD[13]
BUSY HIGH to Data Valid
10
3
12
ns
15
3
ns
3
ns
Busy Timing[11]
15
16
15
17
ns
17
ns
15
20
25
ns
[11]
Interrupt Timing
tINS
INT Set Time
15
20
20
ns
tINR
INT Reset Time
15
20
20
ns
Semaphore Timing
tSOP
SEM Flag Update Pulse (OE or SEM)
10
10
12
ns
tSWRD
SEM Flag Write to Read Time
5
5
5
ns
tSPS
SEM Flag Contention Window
5
5
5
ns
tSAA
SEM Address Access Time
Data Retention Mode
The
CY7C027V/027VN/027AV/028V
and
CY7037V/037AV/038V are designed with battery backup in
mind. Data retention voltage and supply current are guaranteed
over temperature. The following rules ensure data retention:
1. Chip enable (CE) must be held HIGH during data retention, within
VCC to VCC – 0.2V.
2. CE must be kept between VCC – 0.2V and 70% of VCC during
the power up and power down transitions.
3. The RAM can begin operation >tRC after VCC reaches the minimum operating voltage (3.0 volts).
15
20
25
ns
Timing
Data Retention Mode
VCC
3.0V
VCC > 2.0V
3.0V
VCC to VCC – 0.2V
CE
Parameter
ICCDR1
Test Conditions[14]
At VCCDR = 2V
tRC
V
IH
Max
Unit
50
μA
Notes
11. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Figure 11 waveform.
12. Test conditions used are Load 1.
13. tBDD is a calculated parameter and is the greater of tWDD–tPWE (actual) or tDDD–tSD (actual).
14. CE = VCC, Vin = GND to VCC, TA = 25° C. This parameter is guaranteed but not tested.
Document #: 38-06078 Rev. *B
Page 8 of 18
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CY7C037V/037AV/038V
Switching Waveforms
Figure 4. Read Cycle No. 1 (Either Port Address Access)[15, 16, 17]
tRC
ADDRESS
tOHA
DATA OUT
tAA
tOHA
PREVIOUS DATA VALID
DATA VALID
Figure 5. Read Cycle No. 2 (Either Port CE/OE Access)[15, 18, 19]
tACE
CE and
LB or UB
tHZCE
tDOE
OE
tHZOE
tLZOE
DATA VALID
DATA OUT
tLZCE
tPU
tPD
ICC
CURRENT
ISB
Figure 6. Read Cycle No. 3 (Either Port)[15, 17, 18, 19]
tRC
ADDRESS
tAA
tOHA
UB or LB
tHZCE
tLZCE
tABE
CE
tHZCE
tACE
tLZCE
DATA OUT
Notes
15. R/W is HIGH for read cycles.
16. Device is continuously selected CE = VIL and UB or LB = VIL. This waveform cannot be used for semaphore reads.
17. OE = VIL.
18. Address valid prior to or coincident with CE transition LOW.
19. To access RAM, CE = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH, SEM = VIL.
Document #: 38-06078 Rev. *B
Page 9 of 18
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CY7C037V/037AV/038V
Switching Waveforms(continued)
Figure 7. Write Cycle No. 1: R/W Controlled Timing[20, 21, 22, 23]
tWC
ADDRESS
tHZOE [26]
OE
tAW
CE
[24,25]
tPWE[23]
tSA
tHA
R/W
tHZWE[26]
DATA OUT
tLZWE
NOTE 27
NOTE 27
tSD
tHD
DATA IN
Figure 8. Write Cycle No. 2: CE Controlled Timing[20, 21, 22, 28]
tWC
ADDRESS
tAW
CE
[24,25]
tSA
tSCE
tHA
R/W
tSD
tHD
DATA IN
Notes
20. R/W must be HIGH during all address transitions.
21. A write occurs during the overlap (tSCE or tPWE) of a LOW CE or SEM and a LOW UB or LB.
22. tHA is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle.
23. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + tSD) to allow the I/O drivers to turn off and data to be placed on
the bus for the required tSD. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tPWE.
24. To access RAM, CE = VIL, SEM = VIH.
25. To access upper byte, CE = VIL, UB = VIL, SEM = VIH.
To access lower byte, CE = VIL, LB = VIL, SEM = VIH.
26. Transition is measured ±500 mV from steady state with a 5 pF load (including scope and jig). This parameter is sampled and not 100% tested.
27. During this period, the I/O pins are in the output state, and input signals must not be applied.
28. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high impedance state.
Document #: 38-06078 Rev. *B
Page 10 of 18
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CY7C037V/037AV/038V
Switching Waveforms(continued)
Figure 9. Semaphore Read After Write Timing, Either Side[29]
tSAA
A0–A 2
VALID ADRESS
VALID ADRESS
tAW
tACE
tHA
SEM
tOHA
tSCE
tSOP
tSD
I/O 0
DATAIN VALID
tSA
tPWE
DATAOUT VALID
tHD
R/W
tSWRD
tDOE
tSOP
OE
WRITE CYCLE
READ CYCLE
Figure 10. Timing Diagram of Semaphore Contention[30, 31, 32]
A0L –A2L
MATCH
R/WL
SEM L
tSPS
A 0R –A 2R
MATCH
R/WR
SEM R
Notes
29. CE = HIGH for the duration of the above timing (both write and read cycle).
30. I/O0R = I/O0L = LOW (request semaphore); CER = CEL = HIGH.
31. Semaphores are reset (available to both ports) at cycle start.
32. If tSPS is violated, the semaphore is definitely obtained by one side or the other, but which side gets the semaphore is unpredictable.
Document #: 38-06078 Rev. *B
Page 11 of 18
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CY7C037V/037AV/038V
Switching Waveforms(continued)
Figure 11. Timing Diagram of Read with BUSY (M/S=HIGH)[33]
tWC
ADDRESSR
MATCH
tPWE
R/WR
tSD
DATA INR
tHD
VALID
tPS
ADDRESSL
MATCH
tBLA
tBHA
BUSYL
tBDD
tDDD
DATA OUTL
VALID
tWDD
Figure 12. Write Timing with Busy Input (M/S=LOW)
tPWE
R/W
BUSY
tWB
tWH
Note
33. CEL = CER = LOW.
Document #: 38-06078 Rev. *B
Page 12 of 18
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CY7C037V/037AV/038V
Switching Waveforms(continued)
Figure 13. Busy Timing Diagram No. 1 (CE Arbitration)[34]
CELValid First:
ADDRESS L,R
ADDRESS MATCH
CEL
tPS
CER
tBLC
tBHC
BUSYR
CER Valid First:
ADDRESS L,R
ADDRESS MATCH
CER
tPS
CE L
tBLC
tBHC
BUSY L
Figure 14. Busy Timing Diagram No. 2 (Address Arbitration)[34]
Left Address Valid First:
tRC or tWC
ADDRESS L
ADDRESS MATCH
ADDRESS MISMATCH
tPS
ADDRESSR
tBLA
tBHA
BUSY R
Right Address Valid First:
tRC or tWC
ADDRESSR
ADDRESS MATCH
ADDRESS MISMATCH
tPS
ADDRESSL
tBLA
tBHA
BUSY L
Note
34. If tPS is violated, the busy signal is asserted on one side or the other, but there is no guarantee to which side BUSY is asserted.
Document #: 38-06078 Rev. *B
Page 13 of 18
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CY7C027V/027VN/027AV/028V
CY7C037V/037AV/038V
Switching Waveforms(continued)
Figure 15. Interrupt Timing Diagrams
Left Side Sets INTR :
ADDRESSL
tWC
WRITE 7FFF (FFFF for CY7C028V/38V)
tHA[35]
CE L
R/W L
INT R
tINS [36]
Right Side Clears INT R :
tRC
READ 7FFF
(FFFF for CY7C028V/38V)
ADDRESSR
CE R
tINR [36]
R/WR
OE R
INTR
Right Side Sets INT L:
tWC
ADDRESSR
WRITE 7FFE (FFFE for CY7C028V/38V)
tHA[35]
CE R
R/W R
INT L
[36]
tINS
Left Side Clears INT L:
tRC
READ 7FFE
(FFFF for CY7C028V/38V)
ADDRESSR
CE L
tINR[36]
R/W L
OE L
INT L
Notes
35. tHA depends on which enable pin (CEL or R/WL) is deasserted first.
36. tINS or tINR depends on which enable pin (CEL or R/WL) is asserted last.
Document #: 38-06078 Rev. *B
Page 14 of 18
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CY7C037V/037AV/038V
Table 1. Non-Contending Read/Write
Inputs
Outputs
CE
R/W
OE
UB
LB
SEM
I/O9–I/O17
I/O0–I/O8
H
X
X
X
X
H
X
X
X
H
H
H
High Z
High Z
Deselected: Power Down
L
L
X
L
H
H
Data In
High Z
Write to Upper Byte Only
L
L
X
H
L
H
High Z
Data In
Write to Lower Byte Only
L
L
X
L
L
H
Data In
Data In
Write to Both Bytes
L
H
L
L
H
H
Data Out
High Z
Read Upper Byte Only
L
H
L
H
L
H
High Z
Data Out
Read Lower Byte Only
L
H
L
L
L
H
Data Out
Data Out
Read Both Bytes
X
X
H
X
X
X
High Z
High Z
Outputs Disabled
H
H
L
X
X
L
Data Out
Data Out
Read Data in Semaphore Flag
X
H
L
H
H
L
Data Out
Data Out
Read Data in Semaphore Flag
H
X
X
X
L
Data In
Data In
Write DIN0 into Semaphore Flag
X
X
H
H
L
Data In
Data In
Write DIN0 into Semaphore Flag
High Z
Operation
High Z
Deselected: Power Down
L
X
X
L
X
L
Not Allowed
L
X
X
X
L
L
Not Allowed
Table 2. Interrupt Operation Example (assumes BUSYL=BUSYR=HIGH)[37]
Left Port
Function
Right Port
R/WL
CEL
OEL
A0L–14L
INTL
R/WR
CER
OER
A0R–14R
INTR
Set Right INTR Flag
L
L
X
7FFF
X
X
X
X
X
L[39]
Reset Right INTR Flag
X
X
X
X
X
X
L
L
7FFF
H[38]
X
L[38]
L
L
X
7FFE
X
7FFE
H[39]
X
X
X
X
X
Set Left INTL Flag
Reset Left INTL Flag
X
X
X
X
L
L
Table 3. Semaphore Operation Example
Function
No action
I/O0–I/O17 Left I/O0–I/O17 Right
1
1
Status
Semaphore free
Left port writes 0 to semaphore
0
1
Left port has semaphore token
Right port writes 0 to semaphore
0
1
No change. Right side has no write access to semaphore
Left port writes 1 to semaphore
1
0
Right port obtains semaphore token
Left port writes 0 to semaphore
1
0
No change. Left port has no write access to semaphore
Right port writes 1 to semaphore
0
1
Left port obtains semaphore token
Left port writes 1 to semaphore
1
1
Semaphore free
Right port writes 0 to semaphore
1
0
Right port has semaphore token
Right port writes 1 to semaphore
1
1
Semaphore free
Left port writes 0 to semaphore
0
1
Left port has semaphore token
Left port writes 1 to semaphore
1
1
Semaphore free
Notes
37. A0L–15L and A0R–15R,FFFF/FFFE for the CY7C028V/038V.
38. If BUSYR=L, then no change.
39. If BUSYL=L, then no change.
Document #: 38-06078 Rev. *B
Page 15 of 18
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CY7C037V/037AV/038V
Ordering Information
32K x16 3.3V Asynchronous Dual-Port SRAM
Speed
(ns)
15
20
25
Ordering Code
Package
Name
Package Type
100-Pin Thin Quad Flat Pack
Operating
Range
CY7C027V-15AC
A100
Commercial
CY7C027V-15AXC
A100
100-Pin Pb-Free Thin Quad Flat Pack
Commercial
CY7C027VN-15AXC
A100
100-Pin Pb-Free Thin Quad Flat Pack
Commercial
CY7C027V-20AC
A100
100-Pin Thin Quad Flat Pack
Commercial
CY7C027V-20AXC
A100
100-Pin Pb-Free Thin Quad Flat Pack
Commercial
CY7C027V-25AC
A100
100-Pin Thin Quad Flat Pack
Commercial
CY7C027V-25AXC
A100
100-Pin Pb-Free Thin Quad Flat Pack
Commercial
CY7C027AV-25AXI
A100
100-Pin Pb-Free Thin Quad Flat Pack
Industrial
64K x16 3.3V Asynchronous Dual-Port SRAM
Speed
(ns)
15
20
25
Ordering Code
Package
Name
CY7C028V-15AC
A100
CY7C028V-15AXC
CY7C028V-20AC
Package Type
Operating
Range
100-Pin Thin Quad Flat Pack
Commercial
A100
100-Pin Pb-Free Thin Quad Flat Pack
Commercial
A100
100-Pin Thin Quad Flat Pack
Commercial
CY7C028V-20AXC
A100
100-Pin Pb-Free Thin Quad Flat Pack
Commercial
CY7C028V-20AI
A100
100-Pin Thin Quad Flat Pack
Industrial
CY7C028V-20AXI
A100
100-Pin Pb-Free Thin Quad Flat Pack
Industrial
CY7C028V-25AC
A100
100-Pin Thin Quad Flat Pack
Commercial
CY7C028V-25AXC
A100
100-Pin Pb-Free Thin Quad Flat Pack
Commercial
32K x18 3.3V Asynchronous Dual-Port SRAM
Speed
(ns)
15
20
25
Ordering Code
Package
Name
Package Type
Operating
Range
CY7C037V-15AC
A100
100-Pin Thin Quad Flat Pack
Commercial
CY7C037V-15AXC
A100
100-Pin Pb-Free Thin Quad Flat Pack
Commercial
CY7C037V-20AC
A100
100-Pin Thin Quad Flat Pack
Commercial
CY7C037AV-20AXC
A100
100-Pin Pb-Free Thin Quad Flat Pack
Commercial
CY7C037V-25AC
A100
100-Pin Thin Quad Flat Pack
Commercial
CY7C037V-25AXC
A100
100-Pin Pb-Free Thin Quad Flat Pack
Commercial
64K x18 3.3V Asynchronous Dual-Port SRAM
Speed
(ns)
15
20
25
Ordering Code
Package
Name
Package Type
Operating
Range
CY7C038V-15AC
A100
100-Pin Thin Quad Flat Pack
Commercial
CY7C038V-15AXC
A100
100-Pin Pb-Free Thin Quad Flat Pack
Commercial
CY7C038V-20AC
A100
100-Pin Thin Quad Flat Pack
Commercial
CY7C038V-20AXC
A100
100-Pin Pb-Free Thin Quad Flat Pack
Commercial
CY7C038V-20AI
A100
100-Pin Thin Quad Flat Pack
Industrial
CY7C038V-20AXI
A100
100-Pin Pb-Free Thin Quad Flat Pack
Industrial
CY7C038V-25AC
A100
100-Pin Thin Quad Flat Pack
Commercial
CY7C038V-25AXC
A100
100-Pin Pb-Free Thin Quad Flat Pack
Commercial
Document #: 38-06078 Rev. *B
Page 16 of 18
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CY7C037V/037AV/038V
Package Diagram
Figure 16. 100-Pin Pb-Free Thin Plastic Quad Flat Pack (TQFP) A100
51-85048-*C
Document #: 38-06078 Rev. *B
Page 17 of 18
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CY7C037V/037AV/038V
Document History Page
Document Title: CY7C027V/027VN/027AV/CY7C028V/037V/037AV/038V 3.3V 32K/64K x 16/18 Dual Port Static RAM
Document Number: 38-06078
Rev.
ECN No.
Orig. of
Change
Submission
Date
**
237626
YDT
6/30/04
*A
259110
JHX
See ECN
Added Pb-Free packaging information.
*B
2623540
VKN/PYRS
12/17/08
Added CY7C027VN, CY7C027AV and CY7C037AV parts
Updated Ordering information table
Description of Change
Converted data sheet from old spec 38-00670 to conform with new data
sheet. Removed cross information from features section
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© Cypress Semiconductor Corporation, 2001-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
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United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
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the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-06078 Rev. *B
Revised December 09, 2008
Page 18 of 18
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