ADC1410S065/080/105/125 Single 14-bit ADC 65, 80, 105 or 125 Msps CMOS or LVDS DDR digital outputs Rev. 02 — 4 June 2009 Objective data sheet 1. General description The ADC1410S is a single channel 14-bit Analog-to-Digital Converter (ADC) optimized for high dynamic performances and low power consumption at sample rates up to 125 Msps. Pipelined architecture and output error correction ensure the ADC1410S is accurate enough to guarantee zero missing codes over the entire operating range. Supplied from a single 3 V source, it can handle output logic levels from 1.8 V to 3.3 V in CMOS mode, thanks to a separate digital output supply. It supports the LVDS (Low Voltage Differential Signalling) DDR (Double Data Rate) output standard. An integrated SPI (Serial Peripheral Interface) allows the user to easily configure the ADC. The device also includes a programmable gain amplifier with a flexible input voltage range. With excellent dynamic performance from the baseband to input frequencies of 170 MHz or more, the ADC1410S is ideal for use in communications, imaging and medical applications. 005aaa040 1.5 005aaa042 0 005aaa041 1.5 dB 1 1 0.5 0.5 0 0 -0.5 -0.5 -1 -1 -40 -80 -120 -1.5 -1.5 0 Fig 1. 4000 8000 12000 16000 Integral Non-Linearity (INL) 0 0 Fig 2. 4000 8000 12000 16000 Differential Non-Linearity (DNL) 10 20 30 40 f (MHz) Fig 3. Output spectrum: −1 dBFS, 80 Msps, fi = 4.43 MHz 2. Features n n n n n n SNR, 73 dB SFDR, 90 dBc Sample rate up to 125 Msps 14-bit pipelined ADC core Single 3 V supply Flexible input voltage range: 1 V to 2 V p-p with 6 dB programmable fine gain n CMOS or LVDS DDR digital outputs n INL ±1 LSB, DNL ±0.5 LSB (typical) n n n n n n Input bandwidth, 600 MHz Power dissipation, 387 at 80 Msps SPI Interface Duty cycle stabilizer Fast OTR detection Offset binary, 2’s complement, gray code n Power-down and Sleep modes n HVQFN40 package ADC1410S065/080/105/125 NXP Semiconductors Single 14-bit ADC 65, 80, 105 or 125 Msps 3. Applications n Wireless and wired broadband communications n Spectral analysis n Portable instrumentation n Ultrasound equipment n Imaging systems 4. Ordering information Table 1. Ordering information Type number fs (Msps) Package Name Description Version ADC1410S125HN/C1 125 HVQFN40 plastic thermal enhanced very thin quad flat package; no leads; 40 terminals; body 6 × 6 × 0.85 mm SOT618-1 ADC1410S105HN/C1 105 HVQFN40 plastic thermal enhanced very thin quad flat package; no leads; 40 terminals; body 6 × 6 × 0.85 mm SOT618-1 ADC1410S080HN/C1 80 HVQFN40 plastic thermal enhanced very thin quad flat package; no leads; 40 terminals; body 6 × 6 × 0.85 mm SOT618-1 ADC1410S065HN/C1 65 HVQFN40 plastic thermal enhanced very thin quad flat package; no leads; 40 terminals; body 6 × 6 × 0.85 mm SOT618-1 ADC1410S065_080_105_125_2 Objective data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 June 2009 2 of 35 ADC1410S065/080/105/125 NXP Semiconductors Single 14-bit ADC 65, 80, 105 or 125 Msps CS SDIO/ODS SCLK/DFS 5. Block diagram ADC1410S ERROR CORRECTION AND DIGITAL PROCESSING SPI INTERFACE OTR PGA CMOS: DAV or LVDS/DDR: DAVP DAVM INP T/H INPUT STAGE ADC CORE 14-BIT PIPELINED OUTPUT DRIVERS INM PWD OE REFT REFB SENSE VCM SYSTEM REFERENCE AND POWER MANAGEMENT VREF CLKP CLKM VDDO OGND VDDA AGND CLOCK INPUT STAGE AND DUTY CYCLE CONTROL CMOS: D13 to D0 or LVDS/DDR: D13_M to D0_M D13_P to D0_P 005aaa036 Fig 4. Block diagram ADC1410S065_080_105_125_2 Objective data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 June 2009 3 of 35 ADC1410S065/080/105/125 NXP Semiconductors Single 14-bit ADC 65, 80, 105 or 125 Msps 6. Pinning information 5 AGND 6 INM 7 INP 8 23 D7 AGND 9 22 D8 VDDA 10 21 D9 26 D4 D10 20 D11 19 D12 18 D13 17 PWD 16 OE 15 DEC 14 CLKM 13 CLKP 12 VDDA 11 31 DAVM 32 DAVP 33 VDDO INM 7 24 D6_D7_P INP 8 23 D6_D7_M AGND 9 22 D8_D9_P VDDA 10 21 D8_D9_M 005aaa037 Transparent top view Fig 5. 34 OGND 6 25 D5 24 D6 35 OTR AGND 27 D2_D3_M 26 D4_D5_P ADC1410S HVQFN40 25 D4_D5_M D10_D11_P 20 VDDA 36 SCLK/DFS 5 D10_D11_M 19 27 D3 37 SDIO/ODS VDDA D12_D13_P 18 4 38 CS 4 D12_D13_M 17 VCM 39 SENSE 28 D2_D3_P VCM 28 D2 ADC1410S HVQFN40 40 VREF 31 DAV 32 n.c. 33 VDDO 34 OGND 35 OTR 36 SCLK/DFS 37 SDIO/ODS 3 PWD 16 3 29 D0_D1_M AGND OE 15 AGND 29 D1 30 D0_D1_P 2 DEC 14 2 1 REFT CLKM 13 REFT 30 D0 REFB CLKP 12 1 terminal 1 index area VDDA 11 REFB 38 CS terminal 1 index area 39 SENSE 40 VREF 6.1 Pinning 005aaa038 Transparent top view Pin configuration with CMOS digital outputs selected Fig 6. Pin configuration with LVDS/DDR digital outputs selected 6.2 Pin description Table 2. Symbol Pin description (CMOS digital outputs) Pin Type [2] Description REFB 1 O bottom reference REFT 2 O top reference AGND 3 G analog ground VCM 4 O common-mode output voltage VDDA 5 P analog power supply AGND 6 G analog ground INM 7 I complementary analog input INP 8 I analog input AGND 9 G analog ground VDDA 10 P analog power supply VDDA 11 P analog power supply CLKP 12 I clock input CLKM 13 I complementary clock input DEC 14 O regulator decoupling node OE 15 I output enable, active LOW PWD 16 I power down, active HIGH ADC1410S065_080_105_125_2 Objective data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 June 2009 4 of 35 ADC1410S065/080/105/125 NXP Semiconductors Single 14-bit ADC 65, 80, 105 or 125 Msps Table 2. Pin description (CMOS digital outputs) Symbol Pin Type [2] Description D13 17 O data output bit 13 (MSB) D12 18 O data output bit 12 D11 19 O data output bit 11 D10 20 O data output bit10 D9 21 O data output bit 9 D8 22 O data output bit 8 D7 23 O data output bit 7 D6 24 O data output bit 6 D5 25 O data output bit 5 D4 26 O data output bit 4 D3 27 O data output bit 3 D2 28 O data output bit 2 D1 29 O data output bit 1 D0 30 O data output bit 0 (LSB) DAV 31 O data valid output clock n.c. 32 - not connected VDDO 33 P output power supply OGND 34 G output ground OTR 35 O out of range SCLK/DFS 36 I SPI clock / data format select SDIO/ODS 37 I/O SPI data IO / output data standard CS 38 I SPI chip select SENSE 39 I reference programming pin VREF 40 I/O voltage reference input/output [1] P: power supply; G: ground; I: input; O: output; I/O: input/output. Table 3. Pin description (LVDS/DDR) digital outputs) Symbol Pin [1] Type [2] Description D12_D13_M 17 O differential output data D12 and D13 multiplexed, complement D12_D13_P 18 O differential output data D12 and D13 multiplexed, true D10_D11_M 19 O differential output data D10 and D11 multiplexed, complement D10_D11_P 20 O differential output data D10 and D11 multiplexed, true D8_D9_M 21 O differential output data D8 and D9 multiplexed, complement D8_D9_P 22 O differential output data D8 and D9 multiplexed, true D6_D7_M 23 O differential output data D6 and D7 multiplexed, complement D6_D7_P 24 O differential output data D6 and D7 multiplexed, true D4_D5_M 25 O differential output data D4 and D5 multiplexed, complement D4_D5_P 26 O differential output data D4 and D5 multiplexed, true D2_D3_M 27 O differential output data D2 and D3 multiplexed, complement D2_D3_P 28 O differential output data D2 and D3 multiplexed, true D0_D1_M 29 O differential output data D0 and D1 multiplexed, complement ADC1410S065_080_105_125_2 Objective data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 June 2009 5 of 35 ADC1410S065/080/105/125 NXP Semiconductors Single 14-bit ADC 65, 80, 105 or 125 Msps Table 3. Pin description …continued (LVDS/DDR) digital outputs) Symbol Pin [1] Type [2] Description D0_D1_P 30 O differential output data D0 and D1 multiplexed, true DAVM 31 O data valid output clock, complement DAVP 32 O data valid output clock, true [1] Pins 1 to 16 and pins 33 to 40 are the same for both CMOS and LVDS DDR outputs (see Table 2) [2] P: power supply; G: ground; I: input; O: output; I/O: input/output. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions VDDA analog supply voltage VDDO output supply voltage ∆VCC supply voltage difference Tstg Min Max Unit <tbd> <tbd> V <tbd> <tbd> V <tbd> <tbd> V storage temperature −55 +125 °C Tamb ambient temperature −40 +85 °C Tj junction temperature - <tbd> °C VDDA − VDDO 8. Thermal characteristics Table 5. Symbol Rth(j-a) Rth(j-c) [1] Thermal characteristics Parameter Conditions Typ Unit thermal resistance from junction to ambient [1] <tbd> K/W thermal resistance from junction to case [1] <tbd> K/W In compliance with JEDEC test board, in free air. ADC1410S065_080_105_125_2 Objective data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 June 2009 6 of 35 ADC1410S065/080/105/125 NXP Semiconductors Single 14-bit ADC 65, 80, 105 or 125 Msps 9. Static characteristics Table 6. Static characteristics Typical values measured at VDDA = 3 V, VDDO = 1.8 V, Tamb = 25 °C and CL = 5 pF; min and max values are across the full temperature range Tamb = −40 °C to +85 °C at VDDA = 3 V, VDDO = 1.8 V; VINP − VINM = −1 dBFS; internal reference mode; applied to CMOS and LVDS interface; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit 2.85 3.0 3.4 V 1.65 1.8 3.6 V Supplies VDDA analog supply voltage VDDO output supply voltage LVDS DDR mode 2.85 3.0 3.6 V IDDA analog supply current fclk = 125 Msps; fi =70 MHz - 185 - mA IDDO output supply current CMOS mode; fclk = 125 Msps; fi =70 MHz - 20 - mA LVDS DDR mode: fclk = 125 Msps; fi =70 MHz - 35 - mA ADC1410S125 - 557 - mW ADC1410S105 - 488 - mW ADC1410S080 - 387 - mW ADC1410S065 - 336 - mW Power-down mode - 2 - mW Sleep mode - 40 - mW peak-to-peak 0.2 0.8 <tbd> V 0.3VDDA - 0.7VDDA V P power dissipation CMOS mode Clock inputs: pins CLKP and CLKM AC coupled; LVPECL, LVDS and sine wave Vi(clk)dif differential clock input voltage LVCMOS VI input voltage Logic Inputs: pins PWD and OE VIL LOW-level input voltage 0 - 0.8 V VIH HIGH-level input voltage 2 - VDDA V IIL LOW-level input current <tbd> - <tbd> µA IIH HIGH-level input current −10 - +10 µA - 0.3VDDA V Serial Peripheral Interface: pins CS, SDIO/ODS, SCLK/DFS VIL LOW-level input voltage 0 VIH HIGH-level input voltage 0.7VDDA - VDDA V IIL LOW-level input current −10 - +10 µA IIH HIGH-level input current −50 - +50 µA CI input capacitance - 4 - pF Digital Outputs: CMOS mode - pins D13 to D0, OTR, DAV Output levels, VDDO = 3 V VOL LOW-level output voltage IOL = <tbd> OGND - 0.2VDDO V VOH HIGH-level output voltage IOH = <tbd> 0.8VDDO - VDDO IOL LOW-level output current 3-state; output level = 0 V - <tbd> - µA IOH HIGH-level output current 3-state; output level = VDDA - <tbd> - µA ADC1410S065_080_105_125_2 Objective data sheet V © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 June 2009 7 of 35 ADC1410S065/080/105/125 NXP Semiconductors Single 14-bit ADC 65, 80, 105 or 125 Msps Table 6. Static characteristics …continued Typical values measured at VDDA = 3 V, VDDO = 1.8 V, Tamb = 25 °C and CL = 5 pF; min and max values are across the full temperature range Tamb = −40 °C to +85 °C at VDDA = 3 V, VDDO = 1.8 V; VINP − VINM = −1 dBFS; internal reference mode; applied to CMOS and LVDS interface; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit CO output capacitance high impedance; OE = HIGH - 3 - pF Output levels, VDDO = 1.8 V VOL LOW-level output voltage IOL = <tbd> OGND - 0.2VDDO V VOH HIGH-level output voltage IOH = <tbd> 0.8VDDO - VDDO V Digital Outputs, LVDS mode - pins D13P, D13M to D0P, D0M, DAVP and DAVM Output levels, VDDO = 3 V only, Rload = 100 Ω VO(offset) output offset voltage output buffer current set to 3.5 mA - 1.2 - V VO(dif) differential output voltage output buffer current set to 3.5 mA - 350 - mV CO output capacitance - <tbd> - pF Analog inputs: pins INP and INM II Input current −5 - +5 µA RI Input resistance - <tbd> - Ω CI Input capacitance - 5 - pF VI(cm) common mode input voltage VINP = VINM 0.9 1.5 2 V Bi input bandwidth - 600 VI(dif) differential input voltage peak-to-peak 1 - MHz 2 V Common mode output voltage: pin VCM VO(cm) common-mode output voltage - VDDA/2 - V IO(cm) common-mode output current - <tbd> - µA output - 0.5 to 1 - V input 0.5 - 1 V −5 ±1 +5 LSB −0.95 ±0.5 +0.95 LSB - ±2 - mV I/O reference voltage: pin VREF VVREF voltage on pin VREF Accuracy INL integral non-linearity DNL differential non-linearity Eoffset offset error EG gain error guaranteed no missing codes ±0.5 %FS Supply PSRR power supply rejection ratio 100 mV (p-p) on VDDA ADC1410S065_080_105_125_2 Objective data sheet - 35 - dBc © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 June 2009 8 of 35 ADC1410S065/080/105/125 NXP Semiconductors Single 14-bit ADC 65, 80, 105 or 125 Msps 10. Dynamic characteristics 10.1 Dynamic characteristics Table 7. Dynamic characteristics Typical values measured at VDDA = 3 V, VDDO = 1.8 V, Tamb = 25 °C and CL = 5 pF; min and max values are across the full temperature range Tamb = −40 °C to +85 °C at VDDA = 3 V, VDDO = 1.8 V; VINP − VINM = −1 dBFS; internal reference mode; applied to CMOS at LVDS interface; unless otherwise specified. Symbol Parameter Conditions ADC1410S065 ADC1410S080 ADC1410S105 ADC1410S125 Unit Min Typ Max Min Typ Max Min Typ Max Min Typ Ma x fi = 3 MHz - 94 - - 94 - - 96 - - 96 - dBc fi = 30 MHz - 93 - - 93 - - 92 - - 93 - dBc fi = 70 MHz - 90 - - 91 - - 91 - - 91 - dBc Analog signal processing α2H α3H THD ENOB SNR SFDR second harmonic level third harmonic level total harmonic distortion effective number of bits signal-tonoise ratio spuriousfree dynamic range fi = 170 MHz - 88 - - 88 - - 85 - - 85 - dBc fi = 3 MHz - 92 - - 93 - - 91 - - 90 - dBc fi = 30 MHz - 91 - - 92 - - 91 - - 89 - dBc fi = 70 MHz - 90 - - 90 - - 90 - - 87 - dBc fi = 170 MHz - 88 - - 87 - - 88 - - 87 - dBc fi = 3 MHz - 88 - - 88 - - 87 - - 87 - dBc fi = 30 MHz - 87 - - 87 - - 87 - - 86 - dBc fi = 70 MHz - 86 - - 86 - - 85 - - 84 - dBc fi = 170 MHz - 83 - - 83 - - 82 - - 82 - dBc fi = 3 MHz - 11.9 - - 11.9 - - 11.8 - - 11.8 - bits fi = 30 MHz - 11.7 - - 11.7 - - 11.7 - - 11.7 - bits fi = 70 MHz - 11.6 - - 11.6 - - 11.6 - - 11.6 - bits fi = 170 MHz - 11.6 - - 11.5 - - 11.5 - - 11.5 - bits fi = 3 MHz - 73.2 - - 73.1 - - 72.9 - - 72.5 - dBFS fi = 30 MHz - 72.4 - - 72.3 - - 72.3 - - 72.2 - dBFS fi = 70 MHz - 71.8 - - 71.8 - - 71.7 - - 71.6 - dBFS fi = 170 MHz - 71.3 - - 71.2 - - 71.1 - - 71 - dBFS fi = 3 MHz - 91 - - 91 - - 90 - - 90 - dBc fi = 30 MHz - 90 - - 90 - - 90 - - 89 - dBc fi = 70 MHz - 89 - - 89 - - 88 - - 87 - dBc fi = 170 MHz IMD Intermodul- fi = 3 MHz ation fi = 30 MHz distortion fi = 70 MHz fi = 170 MHz - 86 - - 86 - - 85 - - 85 - dBc - 94 - - 94 - - 93 - - 93 - dBc - 93 - - 93 - - 93 - - 92 - dBc - 92 - - 92 - - 91 - - 90 - dBc - 89 - - 89 - - 88 - - 88 - dBc ADC1410S065_080_105_125_2 Objective data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 June 2009 9 of 35 ADC1410S065/080/105/125 NXP Semiconductors Single 14-bit ADC 65, 80, 105 or 125 Msps 10.2 Clock and digital output timing Table 8. Clock and digital output timing characteristics Typical values measured at VDDA = 3 V, VDDO = 1.8 V, Tamb = 25 °C and CL = 5 pF; min and max values are across the full temperature range Tamb = −40 °C to +85 °C at VDDA = 3 V, VDDO = 1.8 V ; VINP − VINM = −1 dBFS; unless otherwise specified. Symbol Parameter Conditions ADC1410S065 Min Typ ADC1410S080 Max Min 65 60 - - Typ ADC1410S105 Max Min 80 60 - - ADC1410S125 Unit Typ Max Min Typ Max - 105 60 - 125 MHz - - 14 - clk/cy Clock timing input: pins CLKP and CLKM fclk clock frequency 20 tlat(data) data latency time - δclk clock duty cycle 14 14 14 DCS_EN = 1 30 50 70 30 50 70 30 50 70 30 50 70 % DCS_EN = 0 45 50 55 45 50 55 45 50 55 45 50 55 % td(s) sampling delay time - 0.8 - - 0.8 - - 0.8 - - 0.8 - ns twake wake-up time - tbd - - tbd - - tbd - - tbd - ns CMOS Mode Timing output: pins D13 to D0 and DAV tPD propagation DATA delay DAV - 3.9 - - 3.9 - - 3.9 - - 3.9 - ns - 4.2 - - 4.2 - - 4.2 - - 4.2 - ns tsu set-up time - 7.7 - - 6.5 - - 4.7 - - 4.3 - ns th hold time - 6.7 - - 5.5 - - 3.8 - - 3.5 - ns DATA 0.5 - 2.4 0.5 - 2.4 0.5 - 2.4 0.5 - 2.4 ns DAV 0.5 - 2.4 0.5 - 2.4 0.5 - 2.4 0.5 - 2.4 ns DATA 0.5 - 2.4 0.5 - 2.4 0.5 - 2.4 0.5 - 2.4 ns time[1] tr rise tf fall time[1] LVDS DDR mode timing output: pins D13P, D13M to D0P, D0M, DAVP and DAVM tPD [1] propagation DATA delay DAV 3.9 3.9 3.9 3.9 ns 4.2 4.2 4.2 4.2 ns Measured between 20 % to 80 % of VDDO; rise time measured from −50 mV to +50 mV; fall time measured from +50 mV to −50 mV. ADC1410S065_080_105_125_2 Objective data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 June 2009 10 of 35 NXP Semiconductors ADC1410S065/080/105/125 Single 14-bit ADC 65, 80, 105 or 125 Msps 10.3 SPI Timings Table 9. Characteristics Typical values measured at VDDA = 3 V, VDDO = 1.8 V, Tamb = 25 °C and CL = 5 pF. Min and max values are across the full temperature range Tamb = −40 °C to +85 °C at VDDA = 3 V, VDDO = 1.8 V Symbol Parameter Conditions Min Typ Max Unit SPI timings tw(SCLK) SCLK pulse width 40 - - ns tw(SCLKH) SCLK HIGH pulse width 16 - - ns tw(SCLKL) SCLK LOW pulse width 16 - - ns tsu set-up time th fclk(max) hold time data to SCLKH 5 - - ns CS to SCLKH 5 - - ns data to SCLKH 2 - - ns CS to SCLKH 2 - - ns - - 25 MHz maximum clock frequency ADC1410S065_080_105_125_2 Objective data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 June 2009 11 of 35 ADC1410S065/080/105/125 NXP Semiconductors Single 14-bit ADC 65, 80, 105 or 125 Msps 11. Application information 11.1 Device control The ADC1410S can be controlled via the Serial Peripheral Interface (SPI control mode) or directly via the I/O pins (PIN control mode). 11.1.1 SPI and PIN control modes The device enters PIN control mode at power-up, and remains in this mode as long as pin CS is held HIGH. In PIN control mode, the SPI pins SDIO, CS and SCLK are used as static control pins. SPI settings are ignored. SPI control mode is enabled by forcing pin CS LOW. It is not possible to toggle between PIN control and SPI control modes. Once SPI control mode has been enabled, the device will remain in this mode until it is powered down. The transition from PIN control mode to SPI control mode is illustrated in Figure 7. CS PIN control mode SCLK/DFS Data Format 2's complement SDIO/ODS SPI control mode Data Format offset binary LVDS DDR CMOS R/W W1 W0 A12 005aaa039 Fig 7. Control mode selection. When the device enters SPI control mode, the output data standard (CMOS or LVD DDR) is not determined by the state of the relevant SPI control bit (LVDS/CMOS; see Table 21), but by the level on pin SDIO at the instant a transition is triggered by a falling edge on CS (SDIO = LOW = CMOS). 11.1.2 Operating mode selection The active ADC1410S operating mode (Power-up, Power-down or Sleep) can be selected via the SPI interface (see Table 18) or using pins PWD and OE in PIN control mode, as described in Table 10. Table 10. Operating mode selection via pin PWD and OE Pin PWD Pin OE Operating mode Output high-Z 0 0 Power-up no 0 1 Power-up yes 1 0 Sleep yes 1 1 Power-down yes 11.1.3 Selecting the output data standard The output data standard (CMOS or LVDS DDR) can be selected via the SPI interface (see Table 21) or using pin ODS in PIN control mode. LVDS DDR is selected when ODS is HIGH, otherwise CMOS is selected. ADC1410S065_080_105_125_2 Objective data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 June 2009 12 of 35 ADC1410S065/080/105/125 NXP Semiconductors Single 14-bit ADC 65, 80, 105 or 125 Msps 11.1.4 Selecting the output data format The output data format can be selected via the SPI interface (offset binary, 2’s complement or gray code; see Table 21) or using pin DFS in PIN control mode (offset binary or 2’s complement). Offset binary is selected when DFS is LOW. When DFS is HIGH, 2’s complement is selected. 11.2 Analog inputs 11.2.1 Input stage The analog input of the ADC1410S supports differential or single-ended input drive. Optimal performance is achieved using differential inputs with the common-mode input voltage (VI(cm)) on pins INP and INM set to 0.5VDDA. The full scale analog input voltage range is configurable between 1 V (p-p) and 2 V (p-p) via a programmable internal reference (see Section 11.3 and Table 20 further details). The equivalent circuit of the sample and hold input stage, including ESD protection and circuit and package parasitics, is shown in Figure 8. Package ESD Parasitics Switch INP Ron = 14 Ω 8 internal clock 4 pF Sampling Capacitor Switch INM Ron = 14 Ω 7 internal clock 4 pF Sampling Capacitor 005aaa043 Fig 8. Input sampling circuit The sample phase occurs when the internal clock (derived from the clock signal on pin CLKP/CLKM) is HIGH. The voltage is then held on the sampling capacitors. When the clock signal goes LOW, the stage enters the hold phase and the voltage information is transmitted to the ADC core. 11.2.2 Anti-kickback circuitry Anti-kickback circuitry (R-C filter in Figure 9) is needed to counteract the effects of charge injection generated by the sampling capacitance. ADC1410S065_080_105_125_2 Objective data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 June 2009 13 of 35 ADC1410S065/080/105/125 NXP Semiconductors Single 14-bit ADC 65, 80, 105 or 125 Msps The RC filter is also used to filter noise from the signal before it reaches the sampling stage. The value of the capacitor should be chosen to maximize noise attenuation without degrading the settling time excessively. R INP C R INM 005aaa073 Fig 9. Anti-kickback circuit The component values are determined by the input frequency and should be selected so as not to affect the input bandwidth. Table 11. RC coupling versus input frequency - recommended values Input frequency R C 3 MHz 25 Ω 12 pF 70 MHz 12 Ω 8 pF 170 MHz 12 Ω 8 pF 11.2.3 Transformer The configuration of the transformer circuit is determined by the input frequency. The configuration shown in Figure 10 would be suitable for a baseband application. ADT1-1WT 100 nF Analog lnput 25 Ω 100 nF INP 25 Ω 12 pF 100 nF 100 nF 25 Ω 25 Ω INM VCM 100 nF 100 nF 005aaa044 Fig 10. Single transformer configuration suitable for baseband applications The configuration shown in Figure 11 is recommended for high frequency applications. In both cases, the choice of transformer will be a compromise between cost and performance. ADC1410S065_080_105_125_2 Objective data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 June 2009 14 of 35 ADC1410S065/080/105/125 NXP Semiconductors Single 14-bit ADC 65, 80, 105 or 125 Msps ADT1-1WT Analog lnput ADT1-1WT 100 nF 50 Ω 12 Ω INP 50 Ω 8.2 pF 50 Ω 50 Ω 12 Ω 100 nF INM VCM 100 nF 100 nF 005aaa045 Fig 11. Dual transformer configuration suitable for high frequency application 11.3 System reference and power management 11.3.1 Internal/external references The ADC1410S has a stable and accurate built-in internal reference voltage. This reference voltage can be set internally, externally or via the SPI (programmable in 1 dB steps between 0 dB and −6 dB via control bits INTREF when bit INTREF_EN = 1; see Table 20). The equivalent reference circuit is shown in Figure 12. REFT REFERENCE AMP VREF BUFFER REFB BANDGAP REFERENCE ADC CORE SENSE SELECTION LOGIC 005aaa046 Fig 12. Single transformer configuration suitable for baseband applications If bit INTREF_EN is set to 0, the reference voltage will be determined either internally or externally as detailed in Table 12. ADC1410S065_080_105_125_2 Objective data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 June 2009 15 of 35 ADC1410S065/080/105/125 NXP Semiconductors Single 14-bit ADC 65, 80, 105 or 125 Msps Table 12. Reference selection Selection SPI bit INTREF_EN SENSE pin VREF pin full scale (p-p) internal 0 AGND 330 pF capacitor to AGND 2V internal 0 pin VREF connected to pin SENSE and via 1 V a 330 pF capacitor to AGND external 0 VDDA internal via SPI 1 pin VREF connected to pin SENSE and via 1 V to 2 V 330 pF capacitor to AGND [1] external voltage between 0.5 V and 1 V[1] 1 V to 2 V The voltage on pin VREF is doubled internally to generate the internal reference voltage. Figure 13 to Figure 16 illustrate how to connect the SENSE and VREF pins to select the required reference voltage source. VREF VREF REFT SENSE REFB REFT 330 pF 330 pF REFB SENSE 005aaa048 005aaa047 Fig 13. Internal reference, 2 V (p-p) full scale VREF Fig 14. Internal reference, 1 V (p-p) full scale REFT VREF V 330 pF SPI SETTINGS INTREF_EN = 1, active INTREF = XXX REFB SENSE 0.1 µF REFB SENSE VDDA 005aaa049 Fig 15. Internal reference via SPI, 1 V to 2 V (p-p) full scale REFT 005aaa050 Fig 16. External reference, 1 V to 2 V (p-p) full scale 11.3.2 Gain control The gain is programmable between 0 dB to −6 dB in 1 dB steps via the SPI (see Table 20). This makes it possible to improve the Spurious-Free Dynamic Range (SFDR) of the ADC1410S. The corresponding full scale input voltage range varies between 2 V (p-p) and 1 V (p-p), as shown in Table 13: ADC1410S065_080_105_125_2 Objective data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 June 2009 16 of 35 ADC1410S065/080/105/125 NXP Semiconductors Single 14-bit ADC 65, 80, 105 or 125 Msps Table 13. Reference SPI Gain Control INTREF Gain full scale (p-p) 000 0 dB 2V 001 −1 dB 1.78 V 010 −2 dB 1.59 V 011 −3 dB 1.42 V 100 −4 dB 1.26 V 101 −5 dB 1.12 V 110 −6 dB 1V 111 reserved x 11.3.3 Common-mode output voltage (VO(cm)) A 0.1 µF filter capacitor should be connected between pin VCM and ground to ensure a low-noise common-mode output voltage. When AC-coupled, pin VCM can then be used to set the common-mode reference for the analog inputs, for instance via a transformer middle point. PACKAGE ESD PARASITICS COMMON MODE REFERENCE 1.5 V VCM 0.1 µF ADC CORE 005aaa051 Fig 17. Equivalent schematic of the common-mode reference circuit 11.3.4 Biasing The common-mode input voltage (VI(cm)) on pins INP and INM should be set externally to 0.5VDDA for optimal performance and should always be between 0.9 V and 2 V. The graph in Figure 18 illustrates how the SFDR and SNR characteristics vary with changes in the common-mode input voltage. ADC1410S065_080_105_125_2 Objective data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 June 2009 17 of 35 ADC1410S065/080/105/125 NXP Semiconductors Single 14-bit ADC 65, 80, 105 or 125 Msps dB SFDR (x MHz) SNR (x MHz) 2V 0.9 V VI(cm) 005aaa052 Fig 18. SFDR and SNR performances versus VI(cm) 11.4 Clock input 11.4.1 Drive modes The ADC1410S can be driven differentially (SINE, LVPECL or LVDS) without the performance being affected by the choice of configuration. It can also be driven by a single-ended LVCMOS signal connected to pin CLKP (CLKM should be connected to ground via a capacitor) or CLKM (CLKP should be connected to ground via a capacitor). LVCMOS Clock lnput CLKP CLKP CLKM LVCMOS Clock lnput CLKM 005aaa053 Fig 19. LVCMOS Single-ended clock input CLKP Sine Clock lnput Sine Clock lnput CLKM CLKP CLKM 005aaa054 Fig 20. Sine differential clock input ADC1410S065_080_105_125_2 Objective data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 June 2009 18 of 35 ADC1410S065/080/105/125 NXP Semiconductors Single 14-bit ADC 65, 80, 105 or 125 Msps CLKP LVDS Clock lnput CLKM 005aaa055 Fig 21. LVDS differential clock input 11.4.2 Equivalent input circuit The equivalent circuit of the input clock buffer is shown in Figure 22. The common-mode voltage of the differential input stage is set via internal 5 kΩ resistors. PACKAGE ESD PARASITICS CLKP Vcm(clk) SE_SEL SE_SEL 5k 5k CLKM 005aaa056 Fig 22. Equivalent input circuit Single-ended or differential clock inputs can be selected via the SPI interface (see Table 19). If single-ended is enabled, the input pin (CLKM or CLKP) is selected via control bit SE_SEL. If single-ended is implemented without setting SE_SEL to the appropriate value, the unused pin should be connected to ground via a capacitor. 11.4.3 Duty cycle stabilizer The duty cycle stabilizer can improve the overall performances of the ADC by compensating the duty cycle of the input clock signal. When the duty cycle stabilizer is active (bit DCS_EN = 1; see Table 19), the circuit can handle signals with duty cycles of between 30 % and 70 % (typical). When the duty cycle stabilizer is disabled (DCS_EN = 0), the input clock signal should have a duty cycle of between 45 % and 55 %. ADC1410S065_080_105_125_2 Objective data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 June 2009 19 of 35 ADC1410S065/080/105/125 NXP Semiconductors Single 14-bit ADC 65, 80, 105 or 125 Msps 11.4.4 Clock input divider The ADC1410S contains an input clock divider that divides the incoming clock by a factor of 2 (when bit CLKDIV = 1; see Table 19). This feature allows the user to deliver a higher clock frequency with better jitter performance, leading to a better SNR result once acquisition has been performed. 11.5 Digital outputs 11.5.1 Digital output buffers: CMOS mode The digital output buffers can be configured as CMOS by setting bit LVDS/CMOS to 0 (see Table 21). Each digital output has a dedicated output buffer. The equivalent circuit of the CMOS digital output buffer is shown in Figure 23. The buffer is powered by a separate OGND/VDDO to ensure 1.8 V to 3.4 V compatibility and is isolated from the ADC core. Each buffer can be loaded by a maximum of 10 pF. VDDO PARASITICS ESD PACKAGE 50 Ω LOGIC DRIVER Dx OGND 005aaa057 Fig 23. CMOS digital output buffer The output resistance is 50 Ω and is the combination of the an internal resistor and the equivalent output resistance of the buffer. There is no need for an external damping resistor. The drive strength of both data and DAV buffers can be programmed via the SPI in order to adjust the rise and fall times of the output digital signals (see Table 28): 11.5.2 Digital output buffers: LVDS DDR mode The digital output buffers can be configured as LVDS DDR by setting bit LVDS/CMOS to 1 (see Table 21). ADC1410S065_080_105_125_2 Objective data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 June 2009 20 of 35 ADC1410S065/080/105/125 NXP Semiconductors Single 14-bit ADC 65, 80, 105 or 125 Msps VCCO 3.5 mA typ − + DnP/Dn + 1P DnM/Dn + 1M 100 Ω RECEIVER − + OGND 005aaa058 Fig 24. LVDS DDR digital output buffer - externally terminated Each output should be terminated externally with a 100 Ω resistor (typical) at the receiver side (Figure 24) or internally via SPI control bits LVDS_INTTER (see Figure 25 and Table 30). VCCO 3.5 mA typ − + DxP/Dx + 1P 100 Ω + DxM/Dx + 1M RECEIVER − OGND 005aaa059 Fig 25. LVDS DDR digital output buffer - internally terminated The default LVDS DDR output buffer current is set to 3.5 mA. It can be programmed via the SPI (bits DAVI and DATAI; see Table 29) in order to adjust the output logic voltage levels. 11.5.3 Data valid (DAV) output clock A data valid output clock signal (DAV) is provided that can be used to capture the data delivered by the ADC1410S. Detailed timing diagrams for CMOS and LVDS DDR modes are provided in Figure 26 and Figure 27 respectively. 11.5.4 Out-of-Range (OTR) An out-of-range signal is provided on pin OTR. By default, pin OTR goes HIGH fourteen clock cycles after an OTR event has occurred. The OTR response can be speeded up by enabling Fast OTR (bit FASTOTR = 1; see Table 27). When Fast OTR is enabled, OTR goes HIGH four clock cycles after the OTR event. The Fast OTR detection threshold (below full scale) can be programmed via bits FASTOTR_DET. ADC1410S065_080_105_125_2 Objective data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 June 2009 21 of 35 ADC1410S065/080/105/125 NXP Semiconductors Single 14-bit ADC 65, 80, 105 or 125 Msps 11.5.5 Digital offset By default, the ADC1410S delivers output code that corresponds to the analog input. However it is possible to add a digital offset to the output code via the SPI (bits DIG_OFFSET; see Table 23). 11.5.6 Test patterns For test purposes, the ADC1410S can be configured to transmit one of a number of predefined test patterns (via bits TESTPAT_SEL; see Table 24). A custom test pattern can be defined by the user (TESTPAT_USER; see Table 25 and Table 26) and is selected when TESTPAT_SEL = 101. The selected test pattern will be transmitted regardless of the analog input. 11.5.7 Output codes versus input voltage Table 14. Output codes VINP − VINM Offset binary Two’s complement OTR pin < −1 00 0000 0000 0000 10 0000 0000 0000 1 −1 00 0000 0000 0000 10 0000 0000 0000 0 −0.9998779 00 0000 0000 0001 10 0000 0000 0001 0 −0.9997559 00 0000 0000 0010 10 0000 0000 0010 0 −0.9996338 00 0000 0000 0011 10 0000 0000 0011 0 −0.9995117 00 0000 0000 0100 10 0000 0000 0100 0 .... .... .... 0 −0.0002441 01 1111 1111 1110 11 1111 1111 1110 0 −0.0001221 01 1111 1111 1111 11 1111 1111 1111 0 0 10 0000 0000 0000 00 0000 0000 0000 0 +0.0001221 10 0000 0000 0001 00 0000 0000 0001 0 +0.0002441 10 0000 0000 0010 00 0000 0000 0010 0 .... .... .... 0 +0.9995117 11 1111 1111 1011 01 1111 1111 1011 0 +0.9996338 11 1111 1111 1100 01 1111 1111 1100 0 +0.9997559 11 1111 1111 1101 01 1111 1111 1101 0 +0.9998779 11 1111 1111 1110 01 1111 1111 1110 0 +1 11 1111 1111 1111 01 1111 1111 1111 0 > +1 11 1111 1111 1111 01 1111 1111 1111 1 ADC1410S065_080_105_125_2 Objective data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 June 2009 22 of 35 ADC1410S065/080/105/125 NXP Semiconductors Single 14-bit ADC 65, 80, 105 or 125 Msps 11.6 Timings summary 11.6.1 CMOS mode timings N N+1 td(s) N+2 tclk CLKP CLKM tPD (N − 14) (N − 13) (N − 12) (N − 11) DATA tsu tPD th DAV tclk 005aaa060 Fig 26. CMOS mode timing 11.6.2 LVDS DDR mode timing N N+1 td(s) N+2 tclk CLKP CLKM tPD (N − 14) (N − 13) (N − 12) (N − 11) Dx_Dx + 1_P Dx Dx + 1 Dx Dx + 1 Dx Dx + 1 Dx Dx + 1 Dx Dx + 1 Dx_Dx + 1_M tsu th tsu th tPD DAVP DAVM tclk 005aaa061 Fig 27. LDVS DDR mode timing ADC1410S065_080_105_125_2 Objective data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 June 2009 23 of 35 ADC1410S065/080/105/125 NXP Semiconductors Single 14-bit ADC 65, 80, 105 or 125 Msps 11.7 Serial Peripheral Interface (SPI) 11.7.1 Register description The ADC1410S serial interface is a synchronous serial communications port that allows for easy interfacing with many commonly-used microprocessors. It provides access to the registers that control the operation of the chip. This interface is configured as a 3-wire type (SDIO as bidirectional pin) Pin SCLK is the serial clock input and CS is the chip select pin. Each read/write operation is initiated by a LOW level on CS. A minimum of three bytes will be transmitted (two instruction bytes and at least one data byte). The number of data bytes is determined by the value of bits W1 and W2 (see Table 16). Table 15. Instruction bytes for the SPI MSB LSB Bit 7 6 5 4 3 2 1 0 Description R/W[1] W1[2] W0[2] A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 [1] Bit R/W indicates whether it is a read (1) or a write (0) operation. [2] Bits W1 and W0 indicate the number of bytes to be transferred after the instruction byte (see Table 16). Table 16. Number of data bytes to be transferred after the instruction bytes W1 W0 Number of bytes transmitted 0 0 1 byte 0 1 2 bytes 1 0 3 bytes 1 1 4 bytes or more Bits A12 to A0 indicate the address of the register being accessed. In the case of a multiple byte transfer, this address is the first register to be accessed. An address counter is incriminated to access subsequent addresses. The steps involved in a data transfer are as follows: 1. A falling edge on CS in combination with a rising edge on SCLK determine the start of communications. 2. The first phase is the transfer of the 2-byte instruction. 3. The second phase is the transfer of the data which can vary in length but will always be a multiple of 8 bits. The MSB is always sent first (for instruction and data bytes). 4. A rising edge on CS indicates the end on data transmission. ADC1410S065_080_105_125_2 Objective data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 June 2009 24 of 35 ADC1410S065/080/105/125 NXP Semiconductors Single 14-bit ADC 65, 80, 105 or 125 Msps CS SCLK SDIO R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 Instruction bytes A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Register N (data) Register N + 1 (data) 005aaa062 Fig 28. SPI mode timing 11.7.2 Default modes at start-up During circuit initialization, it doesn’t matter which output data standard has been selected. At power-up, the device defaults to PIN control mode. A falling edge on CS will trigger a transition to SPI control mode. When the ADC1410S enters SPI control mode, the output data standard (CMOS/LVDS DDR) is determined by the level on pin SDIO (see Figure 29). Once in SPI control mode, the output data standard can be changed via bit LVDS/CMOS in Table 21. When the ADC1410S enters SPI control mode, the output data format (2’s complement or offset binary) is determined by the level on pin SCLK (grey code can only be selected via the SPI). Once in SPI control mode, the output data format can be changed via bit DATA_FORMAT in Table 21. CS SCLK (Data Format) SDIO (CMOS LVDS DDR) Offset binary, LVDS DDR default mode at startup 005aaa063 Fig 29. Default mode at start-up: SCLK LOW = offset binary; SDIO HIGH = LVDS DDR CS SCLK (Data Format) SDIO (CMOS LVDS DDR) 2's complement, CMOS default mode at startup 005aaa064 Fig 30. Default mode at start-up: SCLK HIGH = 2’s complement; SDIO LOW = CMOS ADC1410S065_080_105_125_2 Objective data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 June 2009 25 of 35 ADC1410S065/080/105/125 NXP Semiconductors Single 14-bit ADC 65, 80, 105 or 125 Msps 11.7.3 Register allocation map Table 17. Register allocation map Addr Register name Hex R/W Bit definition 0005 Reset and operating mode Bit 7 Default Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 R/W SW_ RST - - - - - OP_MODE 0006 Clock R/W - - - SE_SEL DIFF/SE - CLKDIV 0008 Internal reference R/W - - - - INTREF_ EN INTREF 0011 Output data standard. R/W - - - LVDS/ CMOS OUTBUF - 0012 Output clock R/W - - - - DAVINV DAVPHASE 0013 Offset R/W - - DIG_OFFSET 0014 Test pattern 1 R/W - - - 0015 Test pattern 2 R/W TESTPAT_USER 0016 Test pattern 2 R/W TESTPAT_USER 0017 Fast OTR R/W - - - - FASTOTR 0020 CMOS output R/W - - - - DAV_DRV 0021 LVDS DDR O/P 1 R/W - - DAVI_ x2_EN DAVI 0022 LVDS DDR O/P 2 R/W - - Table 18. - Bit 0 Bin 0000 0000 DCS_EN 0000 0001 0000 0000 DATA_FORMAT 0000 0000 0000 1110 0000 0000 - TESTPAT_SEL 0000 0000 0000 0000 - - - - FASTOTR_DET 0000 0000 0000 0000 DATA_DRV 0000 1110 DATAI_x DATAI 2_EN 0000 0000 BIT/BYTE_ LVDS_INTTER WISE 0000 0000 Reset and operating mode control register (address 0005h) bit description Bit Symbol Access 7 SW_RST R/W Value Description reset digital section 0 no reset 1 performs a reset of the digital section 6 to 2 reserved 1 to 0 OP_MODE R/W operating mode 00 normal (Power-up) 01 Power-down 10 Sleep 11 normal (Power-up) ADC1410S065_080_105_125_2 Objective data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 June 2009 26 of 35 ADC1410S065/080/105/125 NXP Semiconductors Single 14-bit ADC 65, 80, 105 or 125 Msps Table 19. Bit Clock control register (address 0006h)bit description Symbol Access Value Description R/W single-ended clock input pin select 7 to 5 reserved 4 3 SE_SEL DIFF/SE 2 reserved 1 CLKDIV 0 DCS_EN Table 20. Bit 0 CLKM 1 CLKP R/W differential/single ended clock input select 0 fully differential 1 single-ended R/W clock input divide by 2 0 disabled 1 enabled R/W duty cycle stabilizer 0 disabled 1 enabled Internal reference control register (address 0008h) bit description Symbol Access Value Description 7 to 4 reserved 3 INTREF_EN 2 to 0 INTREF Table 21. Bit R/W programmable internal reference enable 0 disable 1 active R/W programmable internal reference 000 0 dB (FS = 2 V) 001 −1 dB (FS = 1.78 V) 010 −2 dB (FS = 1.59 V) 011 −3 dB (FS = 1.42 V) 100 −4 dB (FS = 1.26 V) 101 −5 dB (FS = 1.12 V) 110 −6 dB (FS = 1 V) 111 reserved Output data standard control register (address 0011h) bit description Symbol Access Value Description 7 to 5 reserved 4 3 2 LVDS/CMOS OUTBUF R/W output data standard: LVDS DDR or CMOS 0 CMOS 1 LVDS DDR R/W output buffers enable 0 output enabled 1 output disabled (high Z) reserved ADC1410S065_080_105_125_2 Objective data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 June 2009 27 of 35 ADC1410S065/080/105/125 NXP Semiconductors Single 14-bit ADC 65, 80, 105 or 125 Msps Table 21. Bit Output data standard control register (address 0011h) bit description …continued Symbol 1 to 0 DATA_FORMAT Table 22. Bit Access Value Description R/W output data format 00 offset binary 01 2’s complement 10 gray code 11 offset binary Output clock register (address 0012h) bit description Symbol Access Value Description 7 to 4 reserved 3 DAVINV 2 to 0 DAVPHASE Table 23. Bit R/W output clock data valid (DAV) polarity 0 normal 1 inverted R/W DAV phase select 000 output clock shifted (ahead) by 3 ns 001 output clock shifted (ahead) by 2.5 ns 010 output clock shifted (ahead) by 2 ns 011 output clock shifted (ahead) by 1.5 ns 100 output clock shifted (ahead) by 1 ns 101 output clock shifted (ahead) by 0.5 ns 110 default value as defined in timing section 111 output clock shifted (delayed) by 0.5 ns Offset register (address 0013h) bit description Symbol Access Value Description 7 to 6 reset 5 to 0 DIG_OFFSET R/W digital offset adjustment 011111 ... ... 000000 0 ... ... 100000 ADC1410S065_080_105_125_2 Objective data sheet +31 LSB −32 LSB © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 June 2009 28 of 35 ADC1410S065/080/105/125 NXP Semiconductors Single 14-bit ADC 65, 80, 105 or 125 Msps Table 24. Bit Test pattern register 1(address 0014h) bit description Symbol Access Value Description R/W digital test pattern select 7 to 3 reserved 2 to 0 TESTPAT_SEL Table 25. Bit 7 to 0 TESTPAT_USER Bit off 001 mid scale 010 −FS 011 +FS 100 toggle ‘1111..1111’/’0000..0000’ 101 custom test pattern 110 ‘1010..1010.’ 111 ‘010..1010’ Test pattern register 2 (address 0015h) bit description Symbol Table 26. 000 Access Value Description R/W custom digital test pattern (bits 13 to 6) Test pattern register 3 (address 0016h) bit description Symbol 7 to 2 TESTPAT_USER Access Value Description R/W custom digital test pattern (bits 5 to 0) 1 to 0 reserved Table 27. Bit Fast OTR register (address 0017h) bit description Symbol Access Value Description R/W fast Out-of-Range (OTR) detection 7 to 4 reset 3 FASTOTR 2 to 0 FASTOTR_DET 0 disabled 1 enabled R/W set fast OTR detect level 000 −20.56 dB 001 −16.12 dB 010 −11.02 dB 011 −7.82 dB 100 −5.49 dB 101 −3.66 dB 110 −2.14 dB 111 −0.86 dB ADC1410S065_080_105_125_2 Objective data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 June 2009 29 of 35 ADC1410S065/080/105/125 NXP Semiconductors Single 14-bit ADC 65, 80, 105 or 125 Msps Table 28. Bit CMOS output register (address 0020h) bit description Symbol Access Value Description 7 to 4 reserved 3 to 2 DAV_DRV R/W drive strength for DAV CMOS output buffer 00 low 01 medium 10 high 11 1 to 0 DATA_DRV Table 29. Bit R/W very high drive strength for DATA CMOS output buffer 00 low 01 medium 10 high 11 very high LVDS DDR output register 1 (address 0021h) bit description Symbol Access DAVI_x2_EN R/W Value Description 7 to 6 5 4 to 3 DAVI double LVDS current for DAV LVDS buffer 0 disabled 1 enabled R/W LVDS current for DAV LVDS buffer 00 3.5 mA 01 4.5 mA 10 1.25 mA 11 2 DATAI_x2_EN 1 to 0 DATAI Table 30. Bit R/W 2.5 mA double LVDS current for DATA LVDS buffer 0 disabled 1 enabled R/W LVDS current for DATA LVDS buffer 00 3.5 mA 01 4.5 mA 10 1.25 mA 11 2.5 mA LVDS DDR output register 2 (address 0022h) bit description Symbol Access Value Description 7 to 4 reserved 3 BIT/BYTE_WISE R/W DDR mode for LVDS output 0 bit wise (even data bits output on DAV rising edge / odd data bits output on DAV falling edge) 1 byte wise (MSB data bits output on DAV rising edge / LSB data bits output on DAV falling edge) ADC1410S065_080_105_125_2 Objective data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 June 2009 30 of 35 ADC1410S065/080/105/125 NXP Semiconductors Single 14-bit ADC 65, 80, 105 or 125 Msps Table 30. Bit LVDS DDR output register 2 (address 0022h) bit description …continued Symbol Access Value Description 2 to 0 LVDS_INTTER R/W internal termination for LVDS buffer (DAV and DATA) 000 no internal termination 001 300 Ω 010 180 Ω 011 110 Ω 100 150 Ω 101 100 Ω 110 81 Ω 111 60 Ω 11.7.4 Serial timing interface SPI timing is shown in Figure 31. tsu tsu th CS tw(SCLKL) th tw(SCLKH) tw(SCLK) SCLK SDIO R/W W1 W0 A12 A11 D2 D1 D0 005aaa065 Fig 31. SPI timing SPI timing characteristics are detailed in Table 9. ADC1410S065_080_105_125_2 Objective data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 June 2009 31 of 35 ADC1410S065/080/105/125 NXP Semiconductors Single 14-bit ADC 65, 80, 105 or 125 Msps 12. Package outline HVQFN40: plastic thermal enhanced very thin quad flat package; no leads; 40 terminals; body 6 x 6 x 0.85 mm A B D SOT618-1 terminal 1 index area A E A1 c detail X C e1 1/2 e e 20 y y1 C v M C A B w M C b 11 L 21 10 e e2 Eh 1/2 e 1 30 terminal 1 index area 40 31 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max. A1 b c D(1) Dh E(1) Eh e e1 e2 L v w y y1 mm 1 0.05 0.00 0.30 0.18 0.2 6.1 5.9 4.25 3.95 6.1 5.9 4.25 3.95 0.5 4.5 4.5 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT618-1 --- MO-220 --- EUROPEAN PROJECTION ISSUE DATE 01-08-08 02-10-22 Fig 32. Package outline SOT618-1 (HVQFN40) ADC1410S065_080_105_125_2 Objective data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 June 2009 32 of 35 ADC1410S065/080/105/125 NXP Semiconductors Single 14-bit ADC 65, 80, 105 or 125 Msps 13. Revision history Table 31. Revision history Document ID Release date Data sheet status Change notice Supersedes ADC1410S065_080_105_125_2 20090604 Objective data sheet - ADC1410S065_080_105_125_1 - - Modifications: ADC1410S065_080_105_125_1 • Values in Table 7 have been updated 20090528 Objective data sheet ADC1410S065_080_105_125_2 Objective data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 June 2009 33 of 35 ADC1410S065/080/105/125 NXP Semiconductors Single 14-bit ADC 65, 80, 105 or 125 Msps 14. Legal information 14.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 14.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. 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Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 14.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 15. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] ADC1410S065_080_105_125_2 Objective data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 June 2009 34 of 35 NXP Semiconductors ADC1410S065/080/105/125 Single 14-bit ADC 65, 80, 105 or 125 Msps 16. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 10.1 10.2 10.3 11 11.1 11.1.1 11.1.2 11.1.3 11.1.4 11.2 11.2.1 11.2.2 11.2.3 11.3 11.3.1 11.3.2 11.3.3 11.3.4 11.4 11.4.1 11.4.2 11.4.3 11.4.4 11.5 11.5.1 11.5.2 11.5.3 11.5.4 11.5.5 11.5.6 11.5.7 11.6 11.6.1 11.6.2 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 Thermal characteristics. . . . . . . . . . . . . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7 Dynamic characteristics . . . . . . . . . . . . . . . . . . 9 Dynamic characteristics . . . . . . . . . . . . . . . . . . 9 Clock and digital output timing . . . . . . . . . . . . 10 SPI Timings . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Application information. . . . . . . . . . . . . . . . . . 12 Device control . . . . . . . . . . . . . . . . . . . . . . . . . 12 SPI and PIN control modes . . . . . . . . . . . . . . 12 Operating mode selection. . . . . . . . . . . . . . . . 12 Selecting the output data standard . . . . . . . . . 12 Selecting the output data format. . . . . . . . . . . 13 Analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . 13 Input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Anti-kickback circuitry . . . . . . . . . . . . . . . . . . . 13 Transformer. . . . . . . . . . . . . . . . . . . . . . . . . . . 14 System reference and power management . . 15 Internal/external references . . . . . . . . . . . . . . 15 Gain control . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Common-mode output voltage (VO(cm)) . . . . . 17 Biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Drive modes . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Equivalent input circuit . . . . . . . . . . . . . . . . . . 19 Duty cycle stabilizer . . . . . . . . . . . . . . . . . . . . 19 Clock input divider . . . . . . . . . . . . . . . . . . . . . 20 Digital outputs . . . . . . . . . . . . . . . . . . . . . . . . . 20 Digital output buffers: CMOS mode . . . . . . . . 20 Digital output buffers: LVDS DDR mode . . . . . 20 Data valid (DAV) output clock . . . . . . . . . . . . . 21 Out-of-Range (OTR) . . . . . . . . . . . . . . . . . . . . 21 Digital offset . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Test patterns . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Output codes versus input voltage . . . . . . . . . 22 Timings summary . . . . . . . . . . . . . . . . . . . . . . 23 CMOS mode timings. . . . . . . . . . . . . . . . . . . . 23 LVDS DDR mode timing . . . . . . . . . . . . . . . . . 23 11.7 11.7.1 11.7.2 11.7.3 11.7.4 12 13 14 14.1 14.2 14.3 14.4 15 16 Serial Peripheral Interface (SPI). . . . . . . . . . . Register description . . . . . . . . . . . . . . . . . . . . Default modes at start-up. . . . . . . . . . . . . . . . Register allocation map . . . . . . . . . . . . . . . . . Serial timing interface. . . . . . . . . . . . . . . . . . . Package outline . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 24 25 26 31 32 33 34 34 34 34 34 34 35 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 4 June 2009 Document identifier: ADC1410S065_080_105_125_2