STMicroelectronics EMIF08-VID01C2 8 line low capacitance emi filter and esd protection Datasheet

EMIF08-VID01C2
8 line low capacitance EMI filter and ESD protection
Main product characteristics
Where EMI filtering in ESD sensitive equipment is
required:
■
LCD and camera for mobile phones
■
Computers and printers
■
Communication systems
■
MCU Boards
Description
The EMIF08-VID01C2 is an 8 line highly
integrated device designed to suppress EMI/RFI
noise in all systems subjected to electromagnetic
interference. The Flip-Chip packaging means the
package size is equal to the die size.
Coated Flip-Chip package
Pin configuration (Bump side)
This filter includes ESD protection circuitry, which
prevents damage to the application when it is
subjected to ESD surges up to 15 kV.
9 8 7
6 5 4
3 2 1
I6
I4
I2
12 11 10
Benefits
■
High efficiency EMI filter (-33 dB @ 900 MHz)
■
Low line capacitance suitable for high speed
data bus
I8
I7
GND
O8
O7
I5
GND
GND
O6
O5
I3
O4
I1
GND
O3
O2
O1
■
Low serial resistance for camera impedance
adaptation
■
Optimized PCB space consuming:
1.29 mm x 3.92 mm
■
Very thin package: 0.695 mm
Complies with following standards:
■
Coating resin on back side and lead free
package
IEC 61000-4-2
■
High efficiency in ESD suppression on inputs
pins (IEC 61000-4-2 level 4).
■
High reliability offered by monolithic integration
■
High reducing of parasitic elements through
integration & wafer level packaging.
October 2006
level 4 input pins
level 1 output pins
15 kV
(air discharge)
8 kV
(contact discharge
2 kV
(air discharge)
2 kV
(contact discharge
A
B
C
MIL STD 883E - Method 3015-6 Class 3
Rev 4
1/6
www.st.com
Characteristics
1
EMIF08-VID01C2
Characteristics
Figure 1.
Basic cell configuration
Input
Output
R
R = 100 Ω
Cline = 16 pF typ. @ 3 V
Table 1.
Absolute ratings (limiting values)
Symbol
Parameter
Value
Unit
ESD discharge IEC 61000-4-2 air discharge
ESD discharge IEC 61000-4-2 contact discharge
15
8
kV
kV
Tj
Maximum junction temperature
125
°C
Top
Operating temperature range
-40 to +85
°C
Tstg
Storage temperature range
-55 to +150
°C
Vpp
Table 2.
Electrical characteristics (Tamb = 25° C)
Symbol
Parameters
I
VBR
Breakdown voltage
IRM
Leakage current @ VRM
IRM
VRM
R
VBR
Series resistance between input and output
Cline
Input capacitance per line
Symbol
2/6
V
VRM
Stand-off voltage
Test conditions
VBR
IR = 1 mA
IRM
VRM = 3 V per line
RI/O
I = 10 mA
Cline
VR = 3 V DC, 1 MHz
Min
Typ
Max
Unit
6
8
10
V
500
nA
100
120
Ω
16
19
pF
80
EMIF08-VID01C2
Figure 2.
Characteristics
S21 (dB) attenuation measurement Figure 3.
Analog crosstalk measurement
dB
dB
0
0
-5
-10
-20
-10
--30
-15
--40
-20
--50
-25
--60
-30
--70
-35
--80
--90
-40
F (Hz)
100k
Figure 4.
1M
10M
F (Hz)
--100
-45
100M
100k
1G
ESD response to IEC 61000-4-2
(+15 kV air discharge) on one
input Vin and one output Vout
Figure 5.
1M
10M
100M
1G
ESD response to IEC 61000-4-2
(- 15 kV air discharge) on one
input Vin and one output Vout
Input
Input
10V/d
10V/d
Output
10V/d
Output
10V/d
200ns/d
200ns/d
Figure 6.
Line capacitance versus applied
voltage
CLINE (pF)
28
26
24
22
20
18
16
14
12
VLINE (V)
10
0
1
2
3
4
5
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Ordering information scheme
2
EMIF08-VID01C2
Ordering information scheme
EMIF
vv
-
xxx zz
C
y
EMI Filter
Number of lines
X: resistance (Ohms)
Z: capacitance value / 10 pF
or
Application (3 letters) and
Version (2 digits)
C: Coated flip chip
1: Pitch = 500 µm, Bump = 315 µm
2: Lead free Pitch = 500 µm, Bump = 315 µm
Package information
Figure 7.
Flip-Chip Dimensions
500µm +/-50
-
315 µm +/- 50
435 µm +/-50
3
695µm +/-- 70
50
1µ
m
+/ 50
1.29
.29 mm +/-50µm
250µm +/-50
-
3.92 mm +/-50µm
-
Figure 8.
Marking
Dot, ST logo
xx = marking
z = manufacturing location
yww = date code
(y = year
ww = week)
4/6
Figure 9.
Footprint recommendation
Copper pad Diameter:
250µm recommended, 300µm max
E
®
x x
x
x z
z
y w
y
w w
w
Solder stencil opening: 330µm
Solder mask opening recommendation:
340µm min for 300µm copper pad diameter
EMIF08-VID01C2
Ordering information
Figure 10. Flip-Chip tape and reel specification
Dot identifying Pin A1 location
Ø 1.5 +/- 0.1
1.75 +/- 0.1
4 +/- 0.1
3.5 +/- 0.1
ST E
xxx
yww
ST E
xxx
yww
ST E
xxx
yww
8 +/- 0.3
0.78 max
4 +/- 0.1
User direction of unreeling
All dimensions in mm
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a lead-free second level interconnect. The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
4
5
Ordering information
Ordering code
Marking
Package
Weight
Base qty
Delivery mode
EMIF08-VID01C2
GS
Flip-Chip
7.4mg
4000
7” Tape and reel
Revision history
Date
Revision
Changes
13-Jul-2005
1
Initial release.
11-Aug-2005
2
Fonts changed in Figures 7, 8, and 9.
31-May-2006
3
Reformatted to current standards. Depth dimension changed in
Figure 10.
26-Oct-2006
4
Base quantity changed to 4000 in Ordering information
5/6
EMIF08-VID01C2
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