Cypress CY7C344B 32-macrocell maxâ® epld Datasheet

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FOR ALL NEW DESIGNS
CY7C344B
32-Macrocell MAX® EPLD
Features
densest EPLD of this size. Eight dedicated inputs and 16
bidirectional I/O pins communicate to one logic array block. In
the CY7C344B LAB there are 32 macrocells and 64 expander
product terms. When an I/O macrocell is used as an input, two
expanders are used to create an input path. Even if all of the
I/O pins are driven by macrocell registers, there are still 16
“buried” registers available. All inputs, macrocells, and I/O pins
are interconnected within the LAB.
• High-performance, high-density replacement for TTL,
74HC, and custom logic
• 32 macrocells, 64 expander product terms in one LAB
• 8 dedicated inputs, 16 I/O pins
• Advanced 0.65-micron CMOS EPROM technology to
increase performance
The speed and density of the CY7C344B makes it a natural
for all types of applications. With just this one device, the
designer can implement complex state machines, registered
logic, and combinatorial “glue” logic, without using multiple
chips. This architectural flexibility allows the CY7C344B to
replace multichip TTL solutions, whether they are
synchronous, asynchronous, combinatorial, or all three.
• 28-pin, 300-mil DIP, cerDIP or 28-pin HLCC, PLCC
package
Functional Description
Available in a 28-pin, 300-mil DIP or windowed J-leaded
ceramic chip carrier (HLCC), the CY7C344B represents the
Logic Block Diagram [1]
Pin Configurations
HLCC
Top View
INPUT
15(23)
INPUT
INPUT/CLK 2(9)
27(6)
INPUT
INPUT
13(20)
28(7)
INPUT
INPUT
14(21)
MACROCELL 4
MACROCELL 6
MACROCELL 8
MACROCELL 10
MACROCELL 12
MACROCELL 14
MACROCELL 16
MACROCELL 18
MACROCELL 20
MACROCELL 22
I/O
I/O
I/O
VCC
GND
I/O
I/O
4 3 2 1 28 27 26
MACROCELL 1
G
L
O
B
A
L
I/O
3(10)
I/O
4(11)
MACROCELL 5
I
I/O
5(12)
MACROCELL 7
O
I/O
6(13)
MACROCELL 3
I/O
9(16)
C
O
I/O
10(17)
I/O
11(18)
N
T
I/O
12(19)
I/O
17(24)
R
I/O
18(25)
O
L
I/O
19(26)
I/O
20(27)
MACROCELL 9
MACROCELL 11
MACROCELL 13
MACROCELL 15
B
MACROCELL 17
U
S
MACROCELL 19
MACROCELL 21
MACROCELL 24
MACROCELL 23
MACROCELL 26
MACROCELL 25
I/O
23(2)
MACROCELL 28
MACROCELL 27
I/O
24(3)
MACROCELL 30
MACROCELL 29
I/O
25(4)
MACROCELL 32
MACROCELL 31
I/O
26(5)
32
64 EXPANDER PRODUCT TERM ARRAY
I/O
INPUT
INPUT
INPUT
INPUT/CLK
I/O
I/O
5
6
7
8
9
10
11
12 13 14 1516 1718
I/O
I/O
MACROCELL 2
1(8)
25
24
23
22
21
20
19
I/O
I/O
INPUT
INPUT
INPUT
INPUT
I/O
I/O
INPUT
VCC
GND
I/O
I/O
15(22)
CerDIP
Top View
INPUT
INPUT/CLK
I/O
I/O
I/O
I/O
VCC
GND
I/O
I/O
I/O
I/O
INPUT
INPUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
INPUT
INPUT
I/O
I/O
I/O
I/O
VCC
GND
I/O
I/O
I/O
I/O
INPUT
INPUT
Selection Guide
7C344B-15
7C344B-20
7C344B-25
Unit
15
20
25
ns
Maximum Access Time
Note:
1. Number in () refers to J-leaded packages.
Cypress Semiconductor Corporation
Document #: 38-03036 Rev. *D
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised June 6, 2005
USE ULTRA37000™ FOR
ALL NEW DESIGNS
CY7C344B
DC Output Current, per Pin[2] ...................–25 mA to +25 mA
Maximum Ratings
DC Input Voltage[2] .........................................–2.0V to +7.0V
(Above which the useful life may be impaired. For user guidelines, not tested.)
Operating Range[3]
Storage Temperature ................................. –65°C to +135°C
Ambient Temperature with
Power Applied..............................................-65°C to +135°C
Ambient
Temperature
Range
Maximum Junction Temperature (Under Bias)............. 150°C
Supply Voltage to Ground Potential[2] ............ –2.0V to +7.0V
VCC
Commercial
–0°C to +70°C
5V ±5%
Industrial
–40°C to +85°C
5V ±10%
Electrical Characteristics Over the Operating Range
Parameter
Description
VCC
Test Conditions
Supply Voltage
VOH
Maximum VCC rise time is 10 ms
Output HIGH Voltage
IOH = –4.0 mA
IOL = 8 mA
Min.
Max.
Unit
4.75(4.5)
5.25(5.5)
V
DC[4]
2.4
V
DC[4]
VOL
Output LOW Voltage
0.45
V
VIH
Input HIGH Level
VIL
Input LOW Level
2.0
VCC+0.3
V
–0.3
0.8
V
IIX
Input Current
GND ≤ VIN ≤ VCC
–10
+10
µA
IOZ
Output Leakage Current
VO = VCC or GND
–40
+40
µA
tR
tF
Recommended Input Rise Time
100
ns
Recommended Input Fall Time
100
ns
Capacitance
Parameter
Description
Test Conditions
Max.
Unit
CIN
Input Capacitance
VIN = 0V, f = 1.0 MHz
10
pF
COUT
Output Capacitance
VOUT = 0V, f = 1.0 MHz
12
pF
AC Test Loads and Waveforms
R1 464Ω
5V
R1 464Ω
5V
OUTPUT
ALL INPUT PULSES
OUTPUT
R2
250Ω
50 pF
INCLUDING
JIGAND
SCOPE
Equivalent to:
(a)
3.0V
R2
250Ω
5 pF
GND
≤ 6 ns
90%
10%
90%
10%
tR
tf
tF
≤ 6 ns
(b)
THÉVENIN EQUIVALENT (commercial)
163Ω
OUTPUT
1.75V
Notes:
2. Minimum DC input is –0.3V. During transactions, the inputs may undershoot to –2.0V or overshoot to 7.0V for input currents less then 100 mA and periods
shorter than 20 ns.
3. The Voltage on any input or I/O pin cannot exceed the power pin during power-up.
4. The IOH parameter refers to high-level TTL output current; the IOL parameter refers to low-level TTL output current.
Document #: 38-03036 Rev. *D
Page 2 of 12
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Operation of the devices described herein with conditions
above those listed under “Absolute Maximum Ratings” may
cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any
other conditions above those indicated in the operational
sections of this data sheet is not implied. Exposure to absolute
maximum ratings conditions for extended periods of time may
affect device reliability. The CY7C344B contains circuitry to
protect device pins from high-static voltages or electric fields;
however, normal precautions should be taken to avoid
applying any voltage higher than maximum rated voltages.
For proper operation, input and output pins must be
constrained to the range GND ≤ (VIN or VOUT) ≤ VCC. Unused
inputs must always be tied to an appropriate logic level (either
VCC or GND). Each set of VCC and GND pins must be
connected together directly at the device. Power supply
decoupling capacitors of at least 0.2 µF must be connected
between VCC and GND. For the most effective decoupling,
each VCC pin should be separately decoupled.
are guaranteed to function properly with a common
synchronous clock under worst-case environmental and
supply voltage conditions.
Typical ICC vs. fMAX
240
ICC ACTIVE (mA) Typ.
Design Recommendations
When calculating external asynchronous frequencies, use
tAS1 if all inputs are on dedicated input pins.
When expander logic is used in the data path, add the appropriate maximum expander delay, tEXP to tAS1. Determine
which of 1/(tAWH + tAWL), 1/tACO1, or 1/(tEXP + tAS1) is the
lowest frequency. The lowest of these frequencies is the
maximum data-path frequency for the asynchronous configuration.
The parameter tOH indicates the system compatibility of this
device when driving other synchronous logic with positive
input hold times, which is controlled by the same synchronous
clock. If tOH is greater than the minimum required input hold
time of the subsequent synchronous logic, then the devices
Document #: 38-03036 Rev. *D
VCC =5.0V
Room Temp.
120
60
1 kHz
10 kHz
100 kHz
1 MHz 10 MHz
50 MHz
MAXIMUM FREQUENCY
Output Drive Current
IO OUTPUT CURRENT (mA) TYPICAL
When calculating synchronous frequencies, use tSU if all
inputs are on the input pins. When expander logic is used in
the data path, add the appropriate maximum expander delay,
tEXP to tSU. Determine which of 1/(tWH + tWL), 1/tCO1, or 1/(tEXP
+ tSU) is the lowest frequency. The lowest of these frequencies
is the maximum data-path frequency for the synchronous
configuration.
180
0
100 Hz
Timing Considerations
Unless otherwise stated, propagation delays do not include
expanders. When using expanders, add the maximum
expander delay tEXP to the overall delay.
CY7C344B
250
IOL
200
VCC =5.0V
Room Temp.
150
100
IOH
50
0
1
2
3
4
5
VO OUTPUT VOLTAGE (V)
Page 3 of 12
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EXPANDER
DELAY
t EXP
CY7C344B
REGISTER
LOGIC ARRAY
CONTROLDELAY tCLR
tLAC
tPRE
INPUT
INPUT
DELAY
tIN
LOGIC ARRAY tRSU
DELAY
tRH
tLAD
OUTPUT
DELAY
OUTPUT
tOD
tXZ
tZX
tRD
tCOMB
tLATCH
SYSTEM CLOCK DELAYtICS
I/O
CLOCK
DELAY
tIC
I/O
I/O DELAY
tIO
FEEDBACK
DELAY
tFD
Figure 1. CY7C344B Timing Model
External Synchronous Switching Characteristics Over Operating Range
7C344B-15
Parameter
tPD1
Description
Min.
Dedicated Input to Combinatorial Output Delay[5] Com’l/Ind
tPD2
I/O Input to Combinatorial Output
tSU
Global Clock Set-up Time
Delay[5]
Com’l/Ind
Com’l/Ind
Delay[5]
Max.
Min.
Max.
7C344B-25
Max.
Unit
15
20
25
ns
15
20
25
ns
9
12
15
Synchronous Clock Input to Output
Input Hold Time from Synchronous Clock Input
Com’l/Ind
0
0
0
ns
tWH
Synchronous Clock Input HIGH Time
Com’l/Ind
6
7
8
ns
tWL
Synchronous Clock Input LOW Time
Com’l/Ind
6
7
8
ns
Com’l/Ind
83.3
Maximum Register Toggle
tCNT
Minimum Global Clock Period
tODH
Output Data Hold Time After Clock
fCNT
Maximum Internal Global Clock
Com’l/Ind
Frequency[7]
12
ns
tH
fMAX
10
Min.
tCO1
Frequency[6]
Com’l/Ind
7C344B-20
13
15
ns
71.4
62.5
MHz
16
20
ns
Com’l/Ind
1
1
1
ns
Com’l/Ind
76.9
62.5
50
MHz
Notes:
5. C1 = 35 pF
6. The fMAX values represent the highest frequency for pipeline data.
7. This parameter is measured with a 32-bit counter programmed into each LAB.
Document #: 38-03036 Rev. *D
Page 4 of 12
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CY7C344B
External Asynchronous Switching Characteristics Over Operating Range
Parameter
Description
7C344B-15
7C344B-20
7C344B-25
Min.
Min.
Min.
Max.
Max.
Max.
Unit
22
ns
tACO1
[5]
Asynchronous Clock Input to Output Delay
Com’l/Ind
tAS1
Dedicated Input or Feedback Set-Up Time to
Asynchronous Clock Input
Com’l/Ind
5
6
8
ns
tAH
Input Hold Time from Asynchronous Clock Input
tAWH
18
Com’l/Ind
5
6
8
ns
[8]
Com’l/Ind
6
7
9
ns
[8]
7
Asynchronous Clock Input HIGH Time
tAWL
Asynchronous Clock Input LOW Time
Com’l/Ind
tACNT
Minimum Internal Array Clock Frequency
Com’l/Ind
fACNT
15
[7]
Maximum Internal Array Clock Frequency
Com’l/Ind
9
13
76.9
11
16
62.5
ns
20
50
ns
MHz
Typical Internal Switching Characteristics Over Operating Range
7C344B-15
Parameter
Description
Min.
Max.
7C344B-20
Min.
Max.
7C344B-25
Min.
Max.
Unit
tIN
Dedicated Input Pad and Buffer Delay
Com’l/Ind
3
5
7
ns
tIO
I/O Input Pad and Buffer Delay
Com’l/Ind
3
5
7
ns
tEXP
Expander Array Delay
Com’l/Ind
8
10
15
ns
tLAD
Logic Array Data Delay
Com’l/Ind
7
10
13
ns
tLAC
Logic Array Control Delay
Com’l/Ind
4
4
4
ns
tOD
Output Buffer and Pad Delay[5]
Com’l/Ind
4
4
4
ns
Output Buffer Enable
Delay[5]
Com’l /Ind
7
7
7
ns
tXZ
Output Buffer Disable
Delay[5]
Com’l/Ind
7
7
7
ns
tRSU
Register Set-Up Time Relative to Clock Signal
at Register
Com’l/Ind
4
4
5
ns
tRH
Register Hold Time Relative to Clock Signal at
Register
Com’l/Ind
5
8
10
ns
tLATCH
Flow-Through Latch Delay
Com’l/Ind
1
1
1
ns
tRD
Register Delay
Com’l/Ind
1
1
1
ns
tCOMB
Transparent Mode Delay
Com’l/Ind
1
1
1
ns
tIC
Asynchronous Clock Logic Delay
Com’l/Ind
7
8
10
ns
tICS
Synchronous Clock Delay
Com’l/Ind
2
2
3
ns
tFD
Feedback Delay
Com’l/Ind
1
1
1
ns
tPRE
Asynchronous Register Preset Time
Com’l/Ind
5
6
9
ns
tCLR
Asynchronous Register Clear Time
Com’l/Ind
5
6
9
ns
tZX
Note:
8. This parameter is measured with a positive-edge-triggered clock at the register. For the negative-edge clocking, the tACH and tACL parameter must be swapped.
Document #: 38-03036 Rev. *D
Page 5 of 12
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CY7C344B
Switching Waveforms
External Combinatorial
DEDICATED INPUT/
I/O INPUT
tPD1/tPD2
COMBINATORIAL
OUTPUT
External Synchronous
tWH
tWL
SYNCHRONOUS
CLOCK PIN
SYNCHRONOUS
CLOCK AT REGISTER
tH
tSU
DATA FROM
LOGIC ARRAY
tCO1
REGISTERED
OUTPUTS
External Asynchronous
DEDICATED INPUTS OR
REGISTERED FEEDBACK
tAS1
tAH
tAWH
tAWL
ASYNCHRONOUS
CLOCK INPUT
Internal Synchronous
CLOCK FROM
LOGIC ARRAY
tRD
tOD
DATA FROM
LOGIC ARRAY
tXZ
OUTPUT PIN
Document #: 38-03036 Rev. *D
tZX
HIGH IMPEDANCE
STATE
Page 6 of 12
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CY7C344B
Switching Waveforms (continued)
Internal Combinatorial
tIN
INPUT PIN
t IO
I/O PIN
tEXP
EXPANDER
ARRAY DELAY
tLAC, tLAD
LOGIC ARRAY
INPUT
LOGIC ARRAY
OUTPUT
tCOMB
tOD
OUTPUT
PIN
Internal Asynchronous
tAWH
tIOtR
tAWL
tF
CLOCK PIN
tIN
CLOCK INTO
LOGIC ARRAY
CLOCK FROM
LOGIC ARRAY
tIC
tRSU
tRH
DATA FROM
LOGIC ARRAY
tRD,tLATCH
REGISTER OUTPUT
TO LOCAL LAB
LOGIC ARRAY
tFD
tCLR,tPRE
tFD
tPIA
REGISTER OUTPUT
TO ANOTHER LAB
Document #: 38-03036 Rev. *D
Page 7 of 12
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CY7C344B
Switching Waveforms (continued)
Internal Synchronous
SYSTEM CLOCK PIN
SYSTEM CLOCK
AT REGISTER
tIN
tICS
tRSU
tRH
DATA FROM
LOGIC ARRAY
Ordering Information
Speed
(ns)
15
20
25
Ordering Code
CY7C344B-15HC/HI
Package
Name
Package Type
H64
28-Lead Windowed Leaded Chip Carrier
CY7C344B-15JC/JI
J64
28-Lead Plastic Leaded Chip Carrier
CY7C344B-15PC/PI
P21
28-Lead (300-Mil) Molded DIP
CY7C344B-15WC/WI
W22
28-Lead Windowed CerDIP
CY7C344B-20HC/HI
H64
28-Lead Windowed Leaded Chip Carrier
CY7C344B-20JC/JI
J64
28-Lead Plastic Leaded Chip Carrier
CY7C344B-20PC/PI
P21
28-Lead (300-Mil) Molded DIP
CY7C344B-20WC/WI
W22
28-Lead Windowed CerDIP
CY7C344B-25HC/HI
H64
28-Lead Windowed Leaded Chip Carrier
CY7C344B-25JC/JI
J64
28-Lead Plastic Leaded Chip Carrier
CY7C344B-25PC/PI
P21
28-Lead (300-Mil) Molded DIP
Document #: 38-03036 Rev. *D
Operating
Range
Commercial/Industrial
Commercial/Industrial
Commercial/Industrial
Page 8 of 12
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CY7C344B
Package Diagrams
28-Pin Windowed Leaded Chip Carrier H64
51-80077-**
Document #: 38-03036 Rev. *D
Page 9 of 12
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CY7C344B
Package Diagrams (continued)
28-Lead Plastic Leaded Chip Carrier J64
51-85001-*A
28-Lead (300-Mil) PDIP P21
SEE LEAD END OPTION
14
1
DIMENSIONS IN INCHES [MM] MIN.
MAX.
REFERENCE JEDEC MO-095
0.260[6.60]
0.295[7.49]
15
28
PACKAGE WEIGHT: 2.15 gms
0.030[0.76]
0.080[2.03]
SEATING PLANE
1.345[34.16]
1.385[35.18]
0.290[7.36]
0.325[8.25]
0.120[3.05]
0.140[3.55]
0.140[3.55]
0.190[4.82]
0.115[2.92]
0.160[4.06]
0.015[0.38]
0.060[1.52]
0.090[2.28]
0.110[2.79]
0.009[0.23]
0.012[0.30]
0.055[1.39]
0.065[1.65]
0.015[0.38]
0.020[0.50]
LEAD END OPTION
3° MIN.
0.310[7.87]
0.385[9.78]
SEE LEAD END OPTION
51-85014-*D
(LEAD #1, 14, 15 & 28)
Document #: 38-03036 Rev. *D
Page 10 of 12
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CY7C344B
Package Diagrams (continued)
28-Lead (300-Mil) Windowed CerDIP W22
MIL-STD-1835 D-15 Config. A
51-80087-**
MAX is a registered trademark and Ultra37000 is a trademark of Cypress Semiconductor Corporation. All products and company
names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-03036 Rev. *D
Page 11 of 12
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
USE ULTRA37000™ FOR
ALL NEW DESIGNS
CY7C344B
Document History Page
Document Title: CY7C344 32-Macrocell MAX® EPLD
Document Number: 38-03036
REV.
ECN NO.
Issue Date
Orig. of
Change
Description of Change
**
106381
06/15/01
SZV
Change from Spec #: 38-00860 to 38-03036
*A
122235
12/28/02
RBI
Power-up requirements added to Operating Range Information
*B
213375
See ECN
FSG
Added note to title page: “Use Ultra37000 For All New Designs”
*C
238565
See ECN
KKV
Minor change: fixed error in part number in header
*D
373715
See ECN
PCX
Corrected header information
Document #: 38-03036 Rev. *D
Page 12 of 12
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