Agere DNC5X3125 Gigabit ethernet transceiver macrocell Datasheet

Advance Data Sheet
March 2000
DNC5X3125
Gigabit Ethernet Transceiver Macrocell
Overview
Features
The DNC5X3125 is a low-cost, low-power transceiver
macrocell. It is used for data transmission over fiber
or coaxial media in conformance with IEEE* 802.3z
Gigabit Ethernet specification and Fibre Channel
ANSI† X3T11 at 1.0 Gbits/s and 1.25 Gbits/s.
■
Designed to operate in Ethernet, fibre channel,
FireWire‡ or backplane applications.
■
Operationally compliant to IEEE 802.3z Gigabit
Ethernet specification.
■
Operationally compliant to Fibre Channel ANSI
X3T11. Provides FC-0 services at 1.0 Gbits/s—
1.25 Gbits/s (10-bit encoded data rate).
■
100 MHz—125 MHz differential or single-ended
reference clock.
■
10-bit parallel interface.
■
8b/10b encoded data.
■
High-speed comma character recognition (K28.1,
K28.5, K28.7) for latency-sensitive applications
and alignment to word boundary.
■
Two 50.0 MHz—62.5 MHz receive-byte clocks.
■
Single analog PLL design requires no external
components for the frequency synthesizer.
■
Novel digital data lock in receiver avoids the need
for multiple analog PLLs.
■
Expandable beyond single-channel SERDES.
■
PECL high-speed interface I/O for use with optical
transceiver or coaxial copper media.
■
Requires one external resistor for PECL output reference level definition.
■
Low-power digital 0.25 µm CMOS technology.
■
3.3 V ± 5% power supply.
■
0 °C—70 °C ambient temperature.
The transmitter section accepts parallel 10-bit
8b/10b encoded data that is latched on the rising
edge of TBC. It also accepts the low-speed, TTL
compatible system clock, REFCLK, and uses this
clock to synthesize the internal high-speed serial bit
clock. The serialized data is then available at the differential PECL outputs, terminated in 50 Ω or 75 Ω to
drive either an optical transmitter or coaxial media.
The receive section receives high-speed serial data
at its differential PECL input port. This data is fed to
the digital clock recovery section, which generates a
recovered clock and retimes the data. The retimed
data is deserialized and presented as 10-bit parallel
data on the output port. A divided-down version of
the recovered clock, synchronous with parallel data
bytes, is also available as a TTL compatible output.
The receive section recognizes the comma character
and aligns the comma-containing byte on the word
boundary, when ENCDET = 1.
* IEEE is a registered trademark of The Institute of Electrical and
Electronics Engineers, Inc.
† ANSI is a registered trademark of American National Standards
Institute.
‡ FireWire is a registered trademark of Apple Computer, Inc.
DNC5X3125
Gigabit Ethernet Transceiver Macrocell
Advance Data Sheet
March 2000
Table of Contents
Contents
Page
Overview .....................................................................1
Features.......................................................................1
Functional Description ................................................3
Transmitter Section.................................................. 3
Receiver Section..................................................... 3
Lock to Reference ....................................................3
Byte Alignment .........................................................4
Parallel Output Port ................................................. 4
Loopback Mode Operation ......................................4
Powerup Sequence .................................................5
Macrocell Reset .......................................................5
Sleep Mode ..............................................................5
Block Diagrams ........................................................6
Input/Output Information .............................................8
Electrical Specifications ..............................................9
Transmitter ...............................................................9
Receiver .................................................................10
Timing Characteristics ..............................................11
Serial Timing ..........................................................11
Receiver Section Timing ........................................12
Receiver Port Timing ..............................................12
Transmitter Section Timing.................................... 13
Application Information ............................................. 14
Test Modes ...............................................................16
Figure
Table
Page
Table 1. Receive Circuit Operating Modes .................. 3
Table 2. Definition of Bit Transmission/
Reception Order ............................................ 4
Table 3a. I/O Channel Interface .................................. 8
Table 3b. I/O Control/PLL Interface Connections ....... 8
Table 3c. Power Connections ..................................... 9
Table 4. Reference Clock Specifications (REFCLK
and REFCLKN) ............................................. 9
Table 5. PLL Specifications ........................................ 9
Table 6. Output Jitter at 1.0 Gbits/s—1.25 Gbits/s ..... 9
Table 7. Receive Input Data Rate ............................. 10
Table 8. Data Lock Characteristics ........................... 10
Table 9. Power Dissipation ....................................... 10
Table 10. dc Electrical Specifications ....................... 10
Table 11. Absolute Maximum Ratings ...................... 10
Table 12. Serial Output Timing Levels ...................... 11
Table 13. Serial Input Interface Timing ..................... 11
Table 14. Receiver Parallel Port Timing ................... 12
Table 15. Transmitter Timing at Parallel Interface ..... 13
Table 16. External Resistor Value vs. Differential
Output Level Viewing ................................ 15
Table 17. Test Modes ............................................... 16
Page
Figure 1. Quad Gigabit Ethernet Transceiver
Block Diagram.............................................. 6
Figure 2. DNC5X3125 Single-Channel Transceiver
Functional Block Diagram ........................... 7
Figure 3. Serial Interface Timing ............................... 11
Figure 4. Receiver Section Timing ............................ 12
Figure 5. Receiver Port Timing ................................ 12
Figure 6. Parallel Interface Transmit Timing ............. 13
Figure 7. Reference Clock Connections with
Single-Ended Source ................................. 14
Figure 8. Typical Termination for a Single-Channel,
High-Speed, Serial Transmit and Receive
Port in a 50 Ω Backplane Application ........ 14
Figure 9. Typical Termination for a Single-Channel,
High-Speed Serial Transmit/Receive Port
Interfacing a 5 V GBIC Transceiver............ 15
2
Lucent Technologies Inc.
Advance Data Sheet
March 2000
DNC5X3125
Gigabit Ethernet Transceiver Macrocell
Functional Description
Receiver Section
The DNC5X3125 transceiver provides for data transmission over fiber or coaxial media at 1.0 Gbits/s to
1.25 Gbits/s. The block diagram of the macrocell used
as a quad-channel transceiver is shown in Figure 1 and
the single-channel macrocell design is shown in
Figure 2. The input/output designations are given in
Table 3.
The receiver circuit extracts clock from and retimes the
serial input data. The data are input to the receiver on
differential PECL buffers. External termination resistors
are supplied by the user in accordance with ANSI standard, X3T11. The serial differential inputs, HDINP and
HDINN, are ac-coupled to the device and internally
biased to the PECL input common-mode range center.
Transmitter Section
The typical transmit and receive, high-speed I/O interfacing for single-channel applications is shown in
Figures 8 and 9.
The transmitter brings in 8b/10b encoded bits in 10-bit
parallel form for up to 1.25 Gbits/s transmission and
converts the data to serial format. The serial nonreturn
to zero (NRZ) bits are then shifted out of the device at a
maximum rate of 1.25 Gbits/s. Internally, the device
uses two parallel shift registers that operate at half rate
(i.e., a maximum of 625 MHz) for reduced power consumption. The two shift registers drive the PECL output
buffer in an interleaved manner to construct the
1.25 Gbit/s output data stream.
The transmit shift register and other circuits are driven
with clocks generated from a 625 MHz internal clock.
This internal clock is sourced from a voltage controlled
oscillator (VCO) that is locked to the external reference
of 100 MHz—125 MHz. The internal transmit phaselock loop multiplies the frequency of the input reference
clock by a factor of 5, and controls the transmit jitter
bandwidth with appropriate design of the jitter transfer
function. The transmit phase-lock loop generates multiple clock phases that are all used by each of the four
receiver circuits. The clock phases are derived from the
transmit VCO.
The receiver data-retiming circuit uses a digital timing
recovery loop that compares the phase of the input
data to multiple phases of the on-device VCO in the
transmit section. One of the phases is chosen to retime
the receive data. A digital low-pass filter is used in the
timing recovery loop to reject jitter from the data input.
A novel phase interpolation circuit permits the retiming
clock’s phase to be stepped with fine resolution for precise alignment of the sampling clock within the data
eye. Use of this digital data-locking scheme for each
receiver advantageously avoids the use of multiple
analog phase-lock loops on-device that can potentially
injection lock to one another. Additionally, the digital
data-locking loop maintains precise loop dynamics,
hence the jitter transfer function is process and temperature independent.
Lock to Reference
The receive circuit has two modes of operation, lock to
reference, and lock to data with retiming. When no data
or invalid data is present on the HDINP and HDINN
input nodes, the user can program the device to ignore
the input data by setting LCKREFN equal to logic 0. In
this mode, neither the PECL input buffer nor the RX
parallel data bus toggles. In normal operations, LCKREFN is a logic 1 and the receiver attempts to lock to
the incoming data. If the input data is invalid or outside
the nominal ± frequency range, the receive digital PLL
will simply ramp the phase of the output clock until it
locks to data.
Table 1. Receiver Circuit Operating Modes*
Mode
Lock to Reference
LCKREFN = 1 (normal operation) Not applicable
LCKREFN = 0
Lock to clock, output data does not
toggle. Disable PECL input buffer.
Lock to Receive Data
Continually attempts to lock to data.
Not applicable.
* REFCLK requirements are given in Table 4.
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DNC5X3125
Gigabit Ethernet Transceiver Macrocell
Advance Data Sheet
March 2000
Functional Description (continued)
Parallel Output Port
Byte Alignment
Timing for the parallel output data and the 50 MHz to
62.5 MHz receive-byte clock is given in Table 14.
When ENCDET = 1, the DNC5X3125 recognizes the
comma character and aligns this 10-bit character to the
word boundary, bits RX[0:9].
Two low data-rate, receive-byte clocks are available as
outputs during use of the parallel output port in 10-bit
mode. RXCLK1 is the receive-byte clock used by the
protocol device to register bytes 0 and 2. RXCLK0 is
the receive-byte clock used by the protocol device to
register bytes 1 and 3, and it is 180 degrees out of
phase with RXCLK1. Both RXCLK1 and RXCLK0 can
be stretched during byte alignment but not truncated or
slivered. The maximum allowable frequency of these
two clocks under all circumstances, excluding start-up,
will not exceed 80 MHz. The start-up time is specified
as 1 ms.
COMDET = 1 when the parallel output word contains a
byte-aligned comma character. The COMDET flag will
continue to pulse a logic 1 whenever a byte aligned
comma character is at the parallel output port, independent of ENCDET. When ENCDET = 0, there are two
possible scenarios depending upon when the comma
character is received:
1. If byte-alignment had been previously achieved
when ENCDET had been a logic 1, the COMDET
flag will continue to pulse a logic 1 whenever a bytealigned comma character is at the parallel output
port. If a comma character occurs that is not on the
word boundary, no attempt will be made to align this
comma character, and the COMDET flag will remain
at a logic 0.
2. If byte-alignment had not been previously achieved
when ENCDET had been a logic 1, then the first
(and only the first) comma character received will be
aligned to the word boundary. COMDET will pulse
when the comma character is aligned to the word
boundary.
Loopback Mode Operation
A control signal input, EWRAP, selects between two
possible sets of inputs: normal data (HDINP, HDINN) or
internal loopback data. When EWRAP = 1, the serial
output ports, HDOUTP and HDOUTN, remain active.
The serial transmit data prior to the PECL output driver
is directed to the data recovery circuit, where the clock
is recovered and data is resynchronized to the recovered clock. Retimed data and clock then go to the
serial-to-parallel converter.
Table 2. Definition of Bit Transmission/Reception Order
Serial Transmit/Receive Rate
1.0 Gbits/s to 1.25 Gbits/s
4
TX[9:0]
TX[0] bit serially transmitted first at
HDOUTP, HDOUTN
RX[9:0]
RX[0] bit received first at serial inputs,
HDINP, HDINN
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DNC5X3125
Gigabit Ethernet Transceiver Macrocell
Functional Description (continued)
Powerup Sequence
An appropriate powerup reset (PUR) standard cell must be placed in the ASIC to hold the transceiver in reset until
full power is supplied to the macrocell. REFCLK must be active at the time the PUR output goes low and must stay
active while powered up, unless in Reset.
When PUR and signals RESET, BYPPLL, and LPWR are all low, the following start-up sequence occurs:
1. 0 µs—32 µs, the analog PLL is held at minimum frequency to allow dc bias to settle.
2. 32 µs—262 µs, the analog PLL has locked in and receiver analog circuits start to lock in.
3. 262 µs—326 µs, the receiver analog circuits are locked; receiver starts to lock onto incoming data.
4. After 358 µs, receiver is locked onto incoming data and can be viewed at the parallel output ports. The comma
detect circuit is enabled at this point allowing byte alignment if ENCDET = 1.
If LCKREFN goes low after the 358 µs, the receiver will sit idle. When LCKREFN goes high, the receiver will be
locked onto data after 2 µs.
Macrocell Reset
The RESET input to the macrocell is an active-high. When activated with a pulse duration of 1 µs, the RESET signal globally resets the macrocell and the following is performed:
1. The single analog PLL is forced to operate at the minimum frequency possible for its VCO. The PLL will not be
locked in this condition.
2. The high-speed serial output HDOUTP is forced to a PECL logic 0, HDOUTN to logic 1.
3. The deserializer clocks are reset, input data at HDINP, HDINN is ignored and the RX[9:0] signals remain in their
previous state.
4. The phase interpolation/selection circuits are deactivated and the selected phase is reset.
5. The receiver digital low-pass filter in the DPLL is reset. Normally, a reset is not necessary for correct operation,
although a reset can aid rapid lock-in of the internal PLL circuitry.
Sleep Mode
The DNC5X3125 has a sleep mode that is activated by enabling LPWR. In this mode, a divided-down version of
the REFCLK is used to refresh the dynamic circuits within the transceiver. The PLL is powered down in this mode
also. LCKREFN can also be activated to reduce the power even further. Note that complete power down for IDDQ
testing is not supported due to the dynamic logic used in the high-speed sections of the transceiver. The lock-in
sequence timing is needed when coming out of sleep mode.
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Gigabit Ethernet Transceiver Macrocell
Advance Data Sheet
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Functional Description (continued)
HDINAP
HDINAN
2
HDOUTAP
HDOUTAN
2
HDINBP
HDINBN
2
HDOUTBP
HDOUTBN
2
LCKREFN[A:D]
EWRAP[A:D]
COMDET[A:D]
RESET
ENCDET[A:D]
LPWR
TBC[A:D]
Block Diagrams
OLREF OLRVS
RXA[9:0]
TXA[9:0]
TRANSCEIVER A
RXB[9:0]
TXB[9:0]
TRANSCEIVER B
TEST CIRCUITS
REFCLK
REFCLKN
2
ANALOG PLL
TEST[5:1]
LDST[A:D]
BYPPLL
RXCLK0[A:D]
RXCLK1[A:D]
HDINCP
HDINCN
TRANSCEIVER C
RXC[9:0]
TXC[9:0]
TRANSCEIVER D
RXD[9:0]
TXD[9:0]
2
2
HDOUTCP
HDOUTCN
HDINDP
HDINDN
HDOUTDP
HDOUTDN
2
2
5-8808(F)
Figure 1. Quad Gigabit Ethernet Transceiver Block Diagram
6
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DNC5X3125
Gigabit Ethernet Transceiver Macrocell
Functional Description (continued)
Block Diagrams (continued)
OLREF* OLRVS*
TX[9:0]
DATA IN
HDOUTP*
SERIALIZER
†
TBC
SERIAL DATA
OUT
PECL
HDOUTN*
LOAD
TEST[5:1] / LDST
BYPPLL
RESET
REFCLK*
REFCLKN*
GLOBAL
CONTROL
ANALOG PLL
LPWR
PUR
EWRAP
ENPLLO
PLLFB
DESERIALIZER
PHASE SELECT/
INTERPOLATION
HDINP*
DIGITAL
LOW-PASS FILTER
PECL
PHASE
DETECTOR
HDINN*
RX[9:0]
RXCLK0
DATA-RETIMING, SERIAL-TO-PARALLEL
CONVERSION AND COMMA DETECTION
RXCLK1
SERIAL
DATA
IN
COMDET
5-8809(F)
* These signals brought to I/O pads for SERDES integration.
† Synchronous with REFCLKN.
Figure 2. DNC5X3125 Single-Channel Transceiver Functional Block Diagram
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DNC5X3125
Gigabit Ethernet Transceiver Macrocell
Advance Data Sheet
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Input/Output Information
Table 3a. I/O Channel Interface
Name
I/O
Level
Description
TX[9:0]
Input
CMOS
RX[9:0]
Output
CMOS
TBC
Input
TTL/CMOS
RXCLK0
RXCLK1
ENCDET
COMDET
EWRAP
LCKREFN
HDINP, HDINN
HDOUTP, HDOUTN
LDST
Output
Output
Input
Output
Input
Input
Input
Output
Input
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
PECL
PECL
CMOS
Transmit Data [9:0]. Parallel input bits [9:0], one 10-bit, 8b/
10b encoded data byte, clocked-in on the rising edge of TBC.
TX0 is the least significant bit.
Receive Data [9:0]. Parallel output bits [9:0], one 10-bit data
type, clocked-out on the alternate rising edges of RXCLK0,
RXCLK1. RX0 is the least significant bit.
Transmit Byte Clock (100 MHz—125 MHz). Synchronous
with REFCLKN.
Receive Byte Clock 0.
Receive Byte Clock 1.
Enable Comma Detection.
Byte-Aligned Comma Detect.
Loopback at Serial I/O.
Lock Receiver to Clock.
Differential Serial Inputs.
Differential Serial Outputs.
Load TEST[5:1] Inputs.
Table 3b. I/O Control/PLL Interface Connections
8
Name
I/O
Level
Description
OLREF
OLRVS
LPWR
RESET
TEST5
TEST4
TEST3
TEST2
TEST1
BYPPLL
REFCLK, REFCLKN
Input/Output
Input/Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
PECL Level Set Resistor Terminal 1.
PECL Level Set Resistor Terminal 2.
Macrocell Low-Power Mode.
Macrocell Reset (Active-High).
Global Test Control Input.
Local Test Control Input.
Local Test Control Input.
Local Test Control Input.
Local Test Control Input.
Test Control—PLL Bypass Mode.
Reference Clock Input (100 MHz—125 MHz).
PUR
PLLFB
ENPLLO
Input
Output
Output
Analog
Analog
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
PECL or TTL/
CMOS
CMOS
CMOS
CMOS
Powerup Reset.
PLL Feedback Clock.
Enable PLL Feedback.
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Advance Data Sheet
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DNC5X3125
Gigabit Ethernet Transceiver Macrocell
Input/Output Information (continued)
Table 3c. Power Connections
Name
Description
Global Digital Power.
High-Speed Receive Power.
High-Speed Transmit Power.
PLL Power.
Power.
Global Digital Ground.
High-Speed Receive Ground.
High-Speed Transmit Ground
PLL Ground.
Ground.
VDDG
VDDR
VDDT
VDDP
VDD
VSSG
VSSR
VSST
VSSP
VSS
Electrical Specifications
Transmitter
Table 4. Reference Clock Specifications (REFCLK and REFCLKN)
Parameter
Minimum
Maximum
Unit
100
–100
40
—
—
—
—
—
—
125
100
60
0.8
0.8
1.5
1.5
30
50
MHz
ppm
%
ns
ns
ns
ns
ps p-p
ps p-p
Frequency Range
Frequency Tolerance
Duty Cycle*
Rise Time (PECL)
Fall Time (PECL)
Rise Time (TTL/CMOS)
Fall Time (TTL/CMOS)
In-band Jitter 1 Gbits/s—1.25 Gbits/s
Out-of-Band Jitter
* Measured at 50% amplitude point.
Table 5. PLL Specifications
Parameter
Bandwidth
Jitter Peaking
Lock Time
Minimum
Typical
Maximum
Unit
—
—
—
1.5
0.5
—
—
—
230
MHz
dB
µs
Table 6. Output Jitter at 1.0 Gbits/s—1.25 Gbits/s
Parameter
Deterministic
Random
Total
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Minimum
Maximum
Unit
—
—
—
0.08
0.12
0.2
UI p-p
UI p-p
UI p-p
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DNC5X3125
Gigabit Ethernet Transceiver Macrocell
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Electrical Specifications (continued)
Receiver
Table 7. Receiver Input Data Rate
Parameter
Minimum
Maximum
Unit
1.0
–100
1.25
100
Gbits/s
ppm
Data Rate
Frequency Tolerance with REFCLK
Table 8. Data Lock Characteristics
Parameter
Minimum
Typical
Maximum
Unit
†
0.3 *
—
1
MHz
Jitter Peaking
—
0.5
—
dB
Lock time*
—
—
2
µs
Bandwidth
†
* Data pattern: 111110000 . . .
† Data pattern: 101010 . . .
Table 9. Power Dissipation*
Parameter
Minimum
Maximum
Unit
—
—
750
TBD
mW
mW
Power
Sleep Mode
* Depending on application (PCB layout, etc.)
Table 10. dc Electrical Specifications
Parameter
Supply Voltage
Diff. PECL Output
Diff. PECL Input
Symbol
Condition
Minimum
Typical
Maximum
Unit
VDD,VDDA
—
—
—
Load, as in Figure 8
Source configuration,
as in Figure 8
3.135
800
400
3.3
—
—
3.465
—
1600
V
mV
mV
Table 11. Absolute Maximum Ratings
Parameter
Supply Voltage
TTL High Input Voltage
PECL Output Current
Junction Operating Temperature
Storage Temperature
10
Minimum
Maximum
Unit
3.135
3.0
—
0
–65
3.465
3.6
16
125
150
V
V
mA
°C
°C
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DNC5X3125
Gigabit Ethernet Transceiver Macrocell
Timing Characteristics
Serial Timing
Table 12. Serial Output Timing Levels
Description
Rise Time 20%—80%
Fall Time 80%—20%
Common Mode
Differential Swing
Load (See Table 16.)
Minimum
Typical
Maximum
Unit
0.17
0.17
VDD/2 – 0.1
0.8
50
0.2
0.2
VDD/2
—
—
0.22
0.22
VDD/2 + 0.1
1.6
75
ns
ns
V
V p-p
Ω
DWIN
tF/tR
VDIFF
Figure 3. Serial Interface Timing
5-8812(F)
Table 13. Serial Input Interface Timing
Description
Minimum
Maximum
Unit
Rise Time (tR)
150
225
ps
Fall Time (tF)
150
225
ps
Differential Swing (VDIFF)
0.4
1.6
V p-p
Source Impedance
50
75
Ω
320
—
ps
Data Eye Opening (DWIN)
.
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Gigabit Ethernet Transceiver Macrocell
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Timing Characteristics (continued)
Receiver Section Timing
HDNIP
K28.5
D7.2
D0.0
D1.0
RECOVERED CLOCK
(INTERNAL)
RXCLK1
RXCLK0
K28.5
RX[9:0]
D7.2
COMDET
5-8813(F)
Figure 4. Receiver Section Timing
Receiver Port Timing
RXCLK PERIOD
RXCLK1 LOW
RXCLK1 HIGH
RXCLK1
RXCLK0
tSKEW
RX
RX0
tS
RX1
RX3
RX2
tH
tS
tH
5-8814(F)
Figure 5. Receiver Port Timing
Table 14. Receiver Parallel Port Timing
Symbol
—
—
—
tR/F
tR/F
tS
tH
tSKEW
Parameter
RXCLK[1:0] Frequency*
RXCLK[1:0] Low
RXCLK[1:0] High
RXCLK[1:0] (0.4 V to 2.6 V)†
Data Output (0.4 V to 2.6 V)†
Setup Time
Hold Time
Skew
Min
Max
Unit
—
7.0
7.0
0.2
0.2
3.0
2.0
—
62.5
9.0
9.0
0.5
0.5
—
—
1.0
MHz
ns
ns
ns
ns
ns
ns
ns
* 1.25 Gbits/s.
† 0.5 pF load.
12
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DNC5X3125
Gigabit Ethernet Transceiver Macrocell
Timing Characteristics (continued)
Transmitter Section Timing
TBC*
TX[9:0]
155
126
375
155
126
34A
375
SERIALIZED DATA
SYNTHESIZED CLOCK
5-8815(F)
* Synchronous with REFCLKN.
Figure 6. Parallel Interface Transmit Timing
Table 15. Transmitter Timing at Parallel Interface
Description
Minimum
Maximum
Unit
Conditions
2
2
—
—
—
—
1
1
ns
ns
ns
ns
With Positive Edge TBC
With Positive Edge TBC
—
—
Data Setup
Data Hold
Rise Time
Fall Time
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Gigabit Ethernet Transceiver Macrocell
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Application Information
BIAS
REFCLK
CLOCK
SOURCE
INTERNAL
CLOCK
REFCLKN
BIAS
DNC5X3125
5-8010(F)(F
Figure 7. Reference Clock Connections with Single-Ended Source
10 Ω†
ZO = 50 Ω
0.01 µF
HDINP
HDOUTP
50 Ω
RX[9:0]
TXA[9:0]
100 Ω
TRANSMIT
DNC5X3125
RECEIVE
DNC5X3125
0.1 µF
50 Ω
RXCLK1
ZO = 50 Ω
TBC
RXCLK0
HDINN
HDOUTN
10 Ω†
0.01 µF
OLRVS
OLREF
*
* External resistor connected between OLREF and OLRVS. See Table 16 for external resistor value required for differential output swing.
† Damping resistor, maximum = 10 Ω.
Figure 8. Typical Termination for a Single-Channel, High-Speed Serial
Transmit-and-Receive Port in a 50 Ω Backplane Application
14
5-8811(F).c
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DNC5X3125
Gigabit Ethernet Transceiver Macrocell
Application Information (continued)
5V
68 Ω
10 Ω†
ZO = 50 Ω
0.01 µF
TX (+)
HDOUTP
50 Ω
TXA[9:0]
191 Ω
TRANSMIT
LU5X31FT
TRANSMIT
GBIC
0.1 µF
50 Ω
191 Ω
ZO = 50 Ω
TBC
TX (–)
HDOUTN
10 Ω†
0.01 µF
68 Ω
OLVRVS
OLREF
5V
*
5-8811(F)b
* External resistor connected between OLREF and OLRVS. See Table 16 for resistor value vs. termination impedance and output swing.
† Damping resistor, maximum = 10 Ω.
Figure 9. Typical Termination for a Single-Channel, High-Speed Serial
Transmit Port Interfacing a 5 V GBIC Transceiver
Table 16. External Resistor Value vs. Differential Output Level Viewing
Resistor Value (Ω)
7.5 K/11.25 K
Termination Impedance (Ω)
Differential Output Voltage (V)
50/75
0.8
5 K/7.5 K
1.2
4 K/6 K
1.6
Lucent Technologies Inc.
15
DNC5X3125
Gigabit Ethernet Transceiver Macrocell
Advance Data Sheet
March 2000
Test Modes
Note: Test modes are intended for manufacture test only and are not guaranteed to be operational. They may be
modified or eliminated without prior notice.
The device has per-channel test modes as well as global test modes. The bypass PLL, BYPPLL, is a global test
input because it modifies the operation of the analog PLL. Test bits TEST[4:1] generally operate in the localized
mode. The LDST[A:D] inputs are enable signals that permit the TEST[4:1] signals to be injected into a particular
channel.
For example, if LDST = 1, the TEST[4:1] signals directly control the test modes in the A channel. Once LDST = 0,
the previous values of TEST[4:1] are held for the A channel. The TEST[4:1] signals control the four channels (A, B,
C, D) via level sense latches that are gated with the LDST[A:D] inputs. TEST[5] is a global test node used for both
injection of signals as well as for monitoring points within the device.
Table 17. Test Modes
Global
16
Local Test Configuration
Global
BYPPLL
Test1
Test2
Test3
Test4
Test5
0
0
1
1
1
1
1
1
1
0
X
Output
0
1
1
0
1
X
0
1
1
0
0
Output
0
1
0
1
P
P
0
1
0
0
P
P
0
0
1
1
1
X
0
0
1
1
0
Output
0
0
1
0
1
X
0
0
1
0
0
Output
0
0
0
1
1
X
Operation
Normal operation.
Analog PLL feedback signal viewed at
TEST5.
Transceiver operates normally except
RX[9:0] output is from digital filter, not
the serial data.
Transceiver operates normally except
RX[9:0] output is from digital filter and
the analog PLL feedback signal is
viewed at TEST5.
Digital filter forced to count. Pulses
applied at TEST4 increments accumulator, pulses at TEST5 decrements
accumulator.
RX[9:0] output is from digital filter, not
the serial data. Digital filter forced to
count. Pulses applied at TEST4 increments accumulator, pulses at TEST5
decrements accumulator.
Parallel loopback. TX[9:0] = RX[9:0].
RX[9:0] remains active.
Parallel loopback. TX[9:0] = RX[9:0]
and analog PLL feedback signal viewed
at TEST5. RX[9:0] remains active.
RX[9:0] output is from digital filter, not
the serial data. Receive channel is held
in reset. BYPPLL overrides this reset.
RX[9:0] output is from digital filter, not
the serial data. Receive channel is held
in reset. BYPPLL overrides this reset.
Analog PLL feedback signal viewed at
TEST5.
Transmitter is held in reset. BYPPLL
overrides this reset.
Lucent Technologies Inc.
Advance Data Sheet
March 2000
DNC5X3125
Gigabit Ethernet Transceiver Macrocell
Test Modes (continued)
Table 17. Test Modes (continued)
Global
Local Test Configuration
Global
BYPPLL
Test1
Test2
Test3
Test4
Test5
0
0
0
1
0
Output
0
0
0
0
1
X
0
0
0
0
0
Output
1
X
X
1
C-0
C-90
1
X
X
0
C-0
C-90
Lucent Technologies Inc.
Operation
Transmitter is held in reset. BYPPLL
overrides this reset. Analog PLL feedback signal viewed at TEST5.
Transmitter and receiver are held in
reset. RX[9:0] output is from digital filter, not the serial data.
Transmitter and receiver are held in
reset. RX[9:0] output is from digital filter, not the serial data. Analog PLL
feedback signal viewed at TEST5.
Analog PLL is bypassed for low speed
functional test. A low speed clock is
input to TEST4, and a quadrature clock
is applied to TEST5. Frequency of
clocks is 5 x REFCLK, but here REFCLK is lowered to about 1 MHz.
Analog PLL is bypassed for low speed
functional test. A low speed clock is
input to TEST4, and a quadrature clock
is applied to TEST5. Frequency of
clocks is 5 x REFCLK, but here REFCLK is lowered to about 1 MHz.
RX[9:0] output is from digital filter, not
the serial data.
17
DNC5X3125
Gigabit Ethernet Transceiver Macrocell
Advance Data Sheet
March 2000
For additional information, contact your Microelectronics Group Account Manager or the following:
INTERNET:
http://www.lucent.com/micro
E-MAIL:
[email protected]
N. AMERICA: Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18103
1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106)
ASIA PACIFIC: Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256
Tel. (65) 778 8833, FAX (65) 777 7495
CHINA:
Microelectronics Group, Lucent Technologies (China) Co., Ltd., A-F2, 23/F, Zao Fong Universe Building, 1800 Zhong Shan Xi Road, Shanghai
200233 P. R. China Tel. (86) 21 6440 0468, ext. 316, FAX (86) 21 6440 0652
JAPAN:
Microelectronics Group, Lucent Technologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan
Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700
EUROPE:
Data Requests: MICROELECTRONICS GROUP DATALINE: Tel. (44) 7000 582 368, FAX (44) 1189 328 148
Technical Inquiries: GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Ascot),
FRANCE: (33) 1 40 83 68 00 (Paris), SWEDEN: (46) 8 594 607 00 (Stockholm), FINLAND: (358) 9 4354 2800 (Helsinki),
ITALY: (39) 02 6608131 (Milan), SPAIN: (34) 1 807 1441 (Madrid)
Lucent Technologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No
rights under any patent accompany the sale of any such product(s) or information.
Copyright © 2000 Lucent Technologies Inc.
All Rights Reserved
March 2000
DS99-398LAN