Cypress CY7C1308CV25-100BZC 9-mbit 4-word burst sram with ddr-i architecture Datasheet

PRELIMINARY
CY7C1308CV25
9-Mbit 4-Word Burst SRAM with DDR-I Architecture
Features
Functional Description
• 9-Mbit density (256 Kbit x 36)
• 167-MHz clock for high bandwidth
• 4-Word Burst for reducing address bus frequency
• Double Data Rate (DDR) interfaces (data transferred at
333 MHz @ 167 MHz)
• Two input clocks (K and K) for precise DDR timing—SRAM uses rising edges only
• Two output clocks (C and C) account for clock skew
and flight time mismatching
• Separate Port Selects for depth expansion
• Synchronous internally self-timed writes
• 2.5V core power supply with HSTL inputs and outputs
• Variable drive HSTL output buffers
• Expanded HSTL output voltage (1.4V–1.9V)
• 13 x 15 x 1.4 mm 1.0-mm pitch fBGA package, 165 ball
(11 x 15 matrix)
• JTAG 1149.1 compatible test access port
The CY7C1308CV25 is a 2.5V Synchronous Pipelined SRAM
equipped with DDR-I (Double Data Rate) architecture. The
DDR-I architecture consists of an SRAM core with advanced
synchronous peripheral circuitry and a 2-bit burst counter.
Addresses for Read and Write are latched on alternate rising
edges of the input (K) clock. Write data is registered on the
rising edges of both K and K. Read data is driven on the rising
edges of C and C if provided, or on the rising edge of K and K
if C/C are not provided. Every Read or Write operation is
associated with four words that burst sequentially into or out
of the device. The burst counter takes in the least two significant bits of the external address and bursts four 36-bit words.
Depth expansion is accomplished with Port Selects for each
port. Port Selects allow each port to operate independently.
Asynchronous inputs include impedance match (ZQ).
Synchronous data outputs (Q, sharing the same physical pins
as the data inputs D) are tightly matched to the two output echo
clocks CQ/CQ, eliminating the need for separately capturing
data from each individual DDR SRAM in the system design.
Output data clocks (C/C) are also provided for maximum
system clocking and data synchronization flexibility.
All synchronous inputs pass through input registers controlled
by the K or K input clocks. All data outputs pass through output
registers controlled by the C or C input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
Configuration
CY7C1308CV25 – 256K x 36
Logic Block Diagram (CY7C1308CV25)
Burst
Logic
16
18
Write Write Write Write
Reg
Reg
Reg Reg
Address
A(17:2) Register
Write Add. Decode
A(17:0)
LD
K
K
CLK
Gen.
Read Add. Decode
A(1:0)
256K x 36 Array
36
Output
Logic
Control
C
C
Read Data Reg.
Vref
R/W
BWS[3:0]
144
CQ
72
Reg.
Control
Logic
72
Reg.
36
Reg.
36
Cypress Semiconductor Corporation
Document #: 38-05502 Rev. *A
•
3901 North First Street
CQ
•
DQ[35:0]
San Jose, CA 95134
•
408-943-2600
Revised June 1, 2004
PRELIMINARY
CY7C1308CV25
Selection Guide
167 MHz
133 MHz
100 MHz
Unit
Maximum Operating Frequency
167
133
100
MHz
Maximum Operating Current
650
620
590
mA
Pin Configuration
CY7C1308CV25 (256K × 36) – 11 × 15 FBGA
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
CQ
R
2
3
GND/144M NC/36M
4
5
6
7
8
9
10
11
R/W
BWS2
K
BWS1
LD
NC
DQ27
DQ18
A
BWS3
K
BWS0
A
NC
NC
DQ8
NC
NC
NC
DQ29
DQ28
DQ19
VSS
VSS
A
VSS
A0
VSS
A1
VSS
VSS
VSS
NC
NC
DQ17
NC
DQ7
DQ16
NC
NC
DQ20
VDDQ
VSS
VSS
VSS
VDDQ
NC
DQ15
DQ6
NC
NC/18M GND/72M
CQ
NC
DQ30
VDD
VSS
VDD
VDDQ
DQ31
VREF
NC
DQ21
DQ22
VDDQ
DQ32
VDDQ
NC
NC
NC
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VSS
VSS
VSS
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
NC
NC
VDDQ
NC
NC
VREF
DQ13
DQ5
DQ14
ZQ
DQ4
NC
NC
DQ23
VDDQ
VDD
VSS
VDD
VDDQ
NC
DQ12
DQ3
NC
DQ33
DQ24
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
DQ2
NC
NC
NC
DQ35
DQ34
DQ25
VSS
VSS
VSS
A
VSS
A
VSS
A
VSS
VSS
NC
NC
DQ11
NC
DQ1
DQ10
NC
NC
DQ26
A
A
C
A
A
NC
DQ9
DQ0
TDO
TCK
A
A
A
C
A
A
A
TMS
TDI
Pin Definitions
I/O
Description
DQ[35:0]
Name
Input/OutputSynchronous
Data Input/Output Signals. Inputs are sampled on the rising edge of K and K clocks
during valid Write operations. These pins drive out the requested data during a Read
operation. Valid data is driven out on the rising edge of both the C and C clocks during
Read operations or K and K when in single clock mode. When Read access is deselected,
Q[35:0] are automatically three-stated.
LD
InputSynchronous
Synchronous Load. This input is brought LOW when a bus cycle sequence is to be
defined. This definition includes address and Read/Write direction. All transactions
operate on a burst of 4 data (two clock periods of bus activity).
BWS0, BWS1,
BWS2, BWS3
InputSynchronous
Byte Write Select 0, 1, 2 and 3 − active LOW. Sampled on the rising edge of the K and
K clocks during Write operations. Used to select which byte is written into the device
during the current portion of the Write operations. Bytes not written remain unaltered.
CY7C1308CV25 − BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18]
and BWS3 controls D[35:27]
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte
Write Select will cause the corresponding byte of data to be ignored and not written into
the device.
A, A0, A1
InputSynchronous
Address Inputs. These address inputs are multiplexed for both Read and Write operations. A0 and A1 are the inputs to the burst counter. These are incremented in a linear
fashion internally. 18 address inputs are needed to access the entire memory array.
All the address inputs are ignored when the part is deselected.
R/W
InputSynchronous
Synchronous Read/Write Input. When LD is LOW, this input designates the access
type (Read when R/W is HIGH, Write when R/W is LOW) for loaded address. R/W must
meet the set-up and hold times around edge of K.
Document #: 38-05502 Rev. *A
Page 2 of 18
PRELIMINARY
CY7C1308CV25
Pin Definitions (continued)
I/O
Description
C
Name
Input-Clock
Positive Output Clock Input. C is used in conjunction with C to clock out the Read data
from the device. C and C can be used together to deskew the flight times of various
devices on the board back to the controller. See application example for further details.
C
Input-Clock
Negative Output Clock Input. C is used in conjunction with C to clock out the Read data
from the device. C and C can be used together to deskew the flight times of various
devices on the board back to the controller. See application example for further details.
K
Input-Clock
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs
to the device and to drive out data through Q[35:0] when in single clock mode. All accesses
are initiated on the rising edge of K.
K
Input-Clock
Negative Input Clock Input. K is used to capture synchronous inputs being presented
to the device and to drive out data through Q[35:0] when in single clock mode.
CQ
Echo Clock
CQ is referenced with respect to C. This is a free running clock and is synchronized
to the output clock (C) of the DDR-I. In the single clock mode, CQ is generated with
respect to K. The timings for the echo clocks are shown in the AC timing table.
CQ
Echo Clock
CQ is referenced with respect to C. This is a free running clock and is synchronized
to the output clock (C) of the DDR-I. In the single clock mode, CQ is generated with
respect to K. The timings for the echo clocks are shown in the AC timing table.
ZQ
Input
Output Impedance Matching Input. This input is used to tune the device outputs to the
system data bus impedance. CQ, CQ and Q[35:0] output impedance are set to 0.2 x RQ,
where RQ is a resistor connected between ZQ and ground. Alternately, this pin can be
connected directly to VDD, which enables the minimum impedance mode. This pin cannot
be connected directly to GND or left unconnected.
TDO
Output
TCK
Input
TCK pin for JTAG.
TDI
Input
TDI pin for JTAG.
TMS
Input
TMS pin for JTAG.
NC
N/A
Not connected to the die. Can be tied to any voltage level.
NC/18M
N/A
Address expansion for 18M. This is not connected to the die.
NC/36M
N/A
Address expansion for 36M. This is not connected to the die.
GND/72M
Input
Address expansion for 72M. This should be tied LOW.
GND/144M
Input
Address expansion for 144M. This should be tied LOW.
VREF
InputReference
VDD
Power Supply
VSS
Ground
VDDQ
Power Supply
TDO for JTAG.
Reference Voltage Input. Static input used to set the reference level for HSTL inputs
and outputs as well as AC measurement points.
Power supply inputs to the core of the device.
Ground for the device.
Power supply inputs for the outputs of the device.
Introduction
Functional Overview
The CY7C1308CV25 is a synchronous pipelined Burst SRAM
equipped with DDR interface.
Accesses are initiated on the positive input clock (K). All
synchronous input timing is referenced from the rising edge of
the input clocks (K and K) and all output timing is referenced
to the rising edge of output clocks (C and C or K and K when
in single clock mode).
All synchronous data inputs (D[35:0]) pass through input
registers controlled by the input clocks (K and K). All
synchronous data outputs (Q[35:0]) pass through output
registers controlled by the rising edge of the output clocks (C
and C or K and K when in single clock mode).
Document #: 38-05502 Rev. *A
All synchronous control (R/W, LD, BWS0, BWS1, BWS2,
BWS3) inputs pass through input registers controlled by the
rising edge of the input clocks (K and K).
Read Operations
The CY7C1308CV25 is organized internally as an array of
256K x 36. Accesses are completed in a burst of four
sequential 36-bit data words. Read operations are initiated by
asserting R/W HIGH and LD LOW at the rising edge of the
Positive Input Clock (K). The address presented to Address
inputs are stored in the Read address register and the least
two significant bits of the address are presented to the burst
counter. The burst counter increments the address in a linear
fashion. Following the next K clock rise the corresponding
36-bit word of data from this address location is driven onto the
Q[35:0] using C as the output timing reference. On the subsequent rising edge of C the next 36-bit data word from the
Page 3 of 18
PRELIMINARY
address location generated by the burst counter is driven onto
the Q[35:0]. This process continues until all four 36-bit data
words have been driven out onto Q[35:0]. The requested data
will be valid 3 ns from the rising edge of the output clock (C or
C, 167-MHz device). In order to maintain the internal logic,
each Read access must be allowed to complete. Each Read
access consists of four 36-bit data words and takes two clock
cycles to complete. Therefore, Read accesses to the device
can not be initiated on two consecutive K clock rises. The
internal logic of the device will ignore the second Read
request. Read accesses can be initiated on every other K
clock rise. Doing so will pipeline the data flow such that data
is transferred out of the device on every rising edge of the
output clocks (C and C or K and K when in single clock mode).
When the read port is deselected, the CY7C1308CV25 will
first complete the pending read transactions. Synchronous
internal circuitry will automatically three-state the outputs
following the next rising edge of the positive output clock (C).
This will allow for a seamless transition between devices
without the insertion of wait states in a depth expanded
memory.
Write Operations
Write operations are initiated by asserting R/W LOW and LD
LOW at the rising edge of the positive input clock (K). The
address presented to Address inputs are stored in the Write
address register and the least two significant bits of the
address are presented to the burst counter. The burst counter
increments the address in a linear fashion. On the following K
clock rise the data presented to D[35:0] is latched and stored
into the 36-bit Write Data register provided BWS[3:0] are
asserted active. On the subsequent rising edge of the
Negative Input Clock (K) the information presented to D[35:0]
is also stored into the Write Data Register provided BWS[3:0]
are asserted active. This process continues for one more cycle
until four 36-bit words (a total of 144 bits) of data are stored in
the SRAM. The 144 bits of data are then written into the
memory array at the specified location. Therefore, Write
accesses to the device can not be initiated on two consecutive
K clock rises. The internal logic of the device will ignore the
second Write request. Write accesses can be initiated on
every other rising edge of the positive input clock (K). Doing
so will pipeline the data flow such that 36-bits of data can be
transferred into the device on every rising edge of the input
clocks (K and K).
When deselected, the Write port will ignore all inputs after the
pending Write operations have been completed.
Byte Write Operations
Byte Write operations are supported by the CY7C1308CV25.
A Write operation is initiated as described in the Write
Operation section above. The bytes that are written are determined by BWS[3:0] which are sampled with each set of 36-bit
data word. Asserting the appropriate Byte Write Select input
during the data portion of a write will allow the data being
presented to be latched and written into the device.
Deasserting the Byte Write Select input during the data portion
Document #: 38-05502 Rev. *A
CY7C1308CV25
of a Write will allow the data stored in the device for that byte
to remain unaltered. This feature can be used to simplify
Read/Modify/Write operations to a Byte Write operation.
Single Clock Mode
The CY7C1308CV25 can be used with a single clock that
controls both the input and output registers. In this mode the
device will recognize only a single pair of input clocks (K and
K) that control both the input and output registers. This
operation is identical to the operation if the device had zero
skew between the K/K and C/C clocks. All timing parameters
remain the same in this mode. To use this mode of operation,
the user must tie C and C HIGH at power-on. This function is
a strap option and not alterable during device operation.
DDR Operation
The CY7C1308CV25 enables high-performance operation
through high clock frequencies (achieved through pipelining)
and double data rate mode of operation. At slower
frequencies, the CY7C1308CV25 requires a single No
Operation (NOP) cycle when transitioning from a Read to a
Write cycle. At higher frequencies, a second NOP cycle may
be required to prevent bus contention.
If a Read occurs after a Write cycle, address and data for the
Write are stored in registers. The Write information must be
stored because the SRAM can not perform the last word Write
to the array without conflicting with the Read. The data stays
in this register until the next Write cycle occurs. On the first
Write cycle after the Read(s), the stored data from the earlier
Write will be written into the SRAM array. This is called a
Posted Write.
Depth Expansion
Depth expansion requires replicating the LD control signal for
each bank. All other control signals can be common between
banks as appropriate.
Echo Clocks
Echo clocks are provided on the DDR-I to simplify data capture
on high-speed systems. Two echo clocks are generated by the
DDR-I. CQ is referenced with respect to C and CQ is referenced with respect to C. These are free-running clocks and
are synchronized to the output clock of the DDR-I. In the single
clock mode, CQ is generated with respect to K and CQ is
generated with respect to K. The timings for the echo clocks
are shown in the AC Timing table.
Programmable Impedance
An external resistor, RQ must be connected between the ZQ
pin on the SRAM and VSS to allow the SRAM to adjust its
output driver impedance. The value of RQ must be 5X the
value of the intended line impedance driven by the SRAM, The
allowable range of RQ to guarantee impedance matching with
a tolerance of ±15% is between 175Ω and 350Ω, with
VDDQ=1.5V. The output impedance is adjusted every 1024
cycles to adjust for drifts in supply voltage and temperature.
Page 4 of 18
PRELIMINARY
CY7C1308CV25
Application Example[1]
DQ
A
DQ
Addresses
Cycle Start#
R/W#
Return CLK
Source CLK
Return CLK#
Source CLK#
Echo Clock1/Echo Clock#1
Echo Clock2/Echo Clock#2
BUS
MASTER
(CPU
or
ASIC)
ZQ
CQ/CQ#
LD# R/W# C C# K K#
SRAM#1
R = 250ohms
ZQ
CQ/CQ#
LD# R/W# C C# K K#
SRAM#2
DQ
A
R = 250ohms
Vterm = 0.75V
R = 50ohms
Vterm = 0.75V
Truth Table[2,3,4,5,6,7]
Operation
K
LD
R/W
DQ
D(A1)at
K(t+1)↑
DQ
DQ
DQ
D(A2) at
K(t+1)↑
D(A3) at
K(t+2) ↑
D(A4) at
K(t+2) ↑
Q(A1) at
C(t+1)↑
Q(A2) at
C(t+1) ↑
Q(A3) at
C(t+2)↑
Q(A4) at
C(t+2) ↑
High-Z
High-Z)
High-Z
Write Cycle:
Load address; wait one cycle; input
write data on 2 consecutive K and K
rising edges.
L-H
L
L[8]
Read Cycle:
Load address; wait one cycle; read data
on 2 consecutive C and C rising edges.
L-H
L
H[9]
NOP: No Operation
L-H
H
X
High-Z
Stopped
X
X
Previous State Previous State Previous State Previous State
Standby: Clock Stopped
Linear Burst Address Table
First Address (External)
Second Address (Internal)
Third Address (Internal)
Fourth Address (Internal)
X..X00
X..X01
X..X10
X..X11
X..X01
X..X10
X..X11
X..X00
X..X10
X..X11
X..X00
X..X01
X..X11
X..X00
X..X01
X..X10
Notes:
1. The above application shows 2 DDR-I being used.
2. X = “Don't Care“, H = Logic HIGH, L = Logic LOW, ↑represents rising edge.
3. Device will power-up deselected and the outputs in a three-state condition.
4. “A1” represents address location latched by the devices when transaction was initiated. A2, A3 and A4 represents the internal address sequence in the burst.
5. “t” represents the cycle at which a Read/Write operation is started. t+1 and t+2 are the first and second clock cycles succeeding the “t” clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
7. It is recommended that K = K and C = C when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging
symmetrically.
8. This signal was HIGH on previous K clock rise. Initiating consecutive Write operations on consecutive K clock rises is not permitted. The device will ignore the
second Write request.
9. This signal was LOW on previous K clock rise. Initiating consecutive Read operations on consecutive K clock rises is not permitted.The device will ignore the
second Read request.
Document #: 38-05502 Rev. *A
Page 5 of 18
PRELIMINARY
CY7C1308CV25
Write Cycle Descriptions[2,10]
BWS0 BWS1 BWS2 BWS3
K
K
Comments
-
During the Data portion of a Write sequence, all four bytes (D[35:0]) are written into
the device.
L
L
L
L
L-H
L
L
L
L
-
L
H
H
H
L-H
L
H
H
H
-
H
L
H
H
L-H
H
L
H
H
-
H
H
L
H
L-H
H
H
L
H
-
H
H
H
L
L-H
H
H
H
L
-
H
H
H
H
L-H
H
H
H
H
-
L-H During the Data portion of a Write sequence, all four bytes (D[35:0]) are written into
the device.
-
During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] will remain unaltered.
L-H During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] will remain unaltered.
-
During the Data portion of a Write sequence, only the byte (D[17:9]) is written into
the device. D[8:0] and D[35:18] will remain unaltered.
L-H During the Data portion of a Write sequence, only the byte (D[17:9]) is written into
the device. D[8:0] and D[35:18] will remain unaltered.
-
During the Data portion of a Write sequence, only the byte (D[26:18]) is written into
the device. D[17:0] and D[35:27] will remain unaltered.
L-H During the Data portion of a Write sequence, only the byte (D[26:18]) is written into
the device. D[17:0] and D[35:27] will remain unaltered.
During the Data portion of a Write sequence, only the byte (D[35:27]) is written into
the device. D[26:0] will remain unaltered.
L-H During the Data portion of a Write sequence, only the byte (D[35:27]) is written into
the device. D[26:0] will remain unaltered.
-
No data is written into the device during this portion of a Write operation.
L-H No data is written into the device during this portion of a Write operation.
Note:
10. Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table. BWS0, BWS1, BWS2, BWS3 can be altered on different portions of a Write
cycle, as long as the set-up and hold requirements are achieved.
Document #: 38-05502 Rev. *A
Page 6 of 18
PRELIMINARY
CY7C1308CV25
Maximum Ratings
Current into Outputs (LOW)......................................... 20 mA
(Above which the useful life may be impaired.)
Static Discharge Voltage.......................................... >2 001V
(per MIL-STD-883, Method 3015)
Storage Temperature ..................................... −65°C to +150°C
Ambient Temperature with
Power Applied.................................................. −55°C to +125°C
Supply Voltage on VDD Relative to GND.........−0.5V to +3.6V
DC Applied to Outputs in High-Z...........−0.5V to VDDQ + 0.5V
DC Input Voltage[12] ................................−0.5V to VDDQ + 0.5V
Latch-up Current.................................................... > 200 mA
Operating Range
Range
Ambient
Temperature (TA)
VDD[13]
VDDQ[13]
0°C to +70°C
2.5 ± 0.1V
1.4V to 1.9V
Com’l
Electrical Characteristics Over the Operating Range [14]
DC Electrical Characteristics
Parameter
Description
Test Conditions
Min.
Typ.
Max.
Unit
VDD
Power Supply Voltage
2.4
2.5
2.6
V
VDDQ
I/O Supply Voltage
1.4
1.5
1.9
V
VOH
Output HIGH Voltage
Note 16
VDDQ/2 – 0.12
VDDQ/2 + 0.12
V
VOL
Output LOW Voltage
Note 17
VDDQ/2 – 0.12
VDDQ/2 + 0.12
V
VOH(LOW)
Output HIGH Voltage
IOH = –0.1 mA, Nominal Impedance
VDDQ – 0.2
VDDQ
V
VOL(LOW)
Output LOW Voltage
IOL = 0.1 mA, Nominal Impedance
VSS
0.2
V
VREF + 0.1
VDDQ + 0.3
V
–0.3
VREF – 0.1
V
–0.3
VDDQ + 0.3
V
–5
5
µA
Voltage[12]
VIH
Input HIGH
VIL
Input LOW Voltage[12,15]
VIN
Clock Input Voltage
IX
Input Load Current
GND ≤ VI ≤ VDDQ
IOZ
Output Leakage Current
GND ≤ VI ≤ VDDQ, Output Disabled
VREF
Input Reference Voltage[18] Typical Value = 0.75V
IDD
VDD Operating Supply
ISB1
Automatic Power-Down
5
µA
0.95
V
VDD = Max., IOUT = 0 mA, 100 MHz
f = fMAX = 1/tCYC
133 MHz
590
mA
620
mA
167 MHz
650
mA
Max. VDD, Both Ports
100 MHz
Deselected, VIN ≥ VIH or 133 MHz
VIN ≤ VIL f = fMAX = 1/tCYC,
167 MHz
Inputs Static
360
mA
380
mA
400
mA
Max.
Unit
–5
0.68
0.75
AC Input Requirements
Parameter
Description
Test Conditions
Min.
Typ.
VIH
Input High (Logic 1) Voltage
VREF + 0.2
–
–
V
VIL
Input Low (Logic 0) Voltage
–
–
VREF – 0.2
V
11.
Thermal Resistance[19]
Parameter
ΘJA
ΘJC
Description
Test Conditions
165 FBGA Package Unit
Thermal Resistance (Junction to Ambient) Test conditions follow standard test
methods and procedures for measuring
Thermal Resistance (Junction to Case)
thermal impedance, per EIA/JESD51.
16.7
°C/W
2.5
°C/W
Notes:
12. Overshoot: VIH(AC) < VDDQ + 0.85V (Pulse width less than tCYC/2). Undershoot: VIL(AC) > –1.5V (Pulse width less than tCYC/2).
13. Power-up: Assumes a linear ramp from 0V to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
14. All voltage referenced to ground.
15. This spec is for all inputs except C and C Clock. For C and C Clock, VIL(Max.) = VREF – 0.2V.
16. Output are impedance controlled. IOH = –(VDDQ/2)/(RQ/5) for values of 175Ω <= RQ <= 350Ω.
17. Output are impedance controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175Ω <= RQ <= 350Ω.
18. VREF (Min.) = 0.68V or 0.46VDDQ, whichever is larger, VREF (Max.) = 0.95V or 0.54VDDQ, whichever is smaller.
Document #: 38-05502 Rev. *A
Page 7 of 18
PRELIMINARY
CY7C1308CV25
Capacitance[19]
Parameter
Description
CIN
Input Capacitance
CCLK
Clock Input Capacitance
CO
Output Capacitance
Test Conditions
Max.
TA = 25°C, f = 1 MHz,
VDD = 2.5V
VDDQ = 1.5V
Unit
5
pF
6
pF
7
pF
AC Test Loads and Waveforms
VDDQ/2
VREF
VDDQ/2
VREF
OUTPUT
Z0 = 50Ω
Device
Under
Test
ZQ
(a)
RL = 50Ω
VREF = 0.75V
RQ =
250Ω
VDDQ/2
R = 50 Ω
ALL INPUT PULSES
1.25V
0.75V
OUTPUT
Device
Under ZQ
Test
5 pF
[20]
0.25V
RQ =
250Ω
INCLUDING
JIG AND
SCOPE
(b)
Switching Characteristics Over the Operating Range [20]
-167
Cypress Consortium
Parameter Parameter
tPower[21]
Description
Min.
Max.
-133
Min.
Max.
-100
Min.
Max.
Unit
VCC (typical) to the First Access Read or Write
10
10
10
µs
Cycle Time
tCYC
tKHKH
K Clock and C Clock Cycle Time
6.0
7.5
10.0
ns
tKH
tKHKL
Input Clock (K/K and C/C) HIGH
2.4
3.2
3.5
ns
tKL
tKLKH
Input Clock (K/K and C/C) LOW
2.4
3.2
3.5
ns
tKHKH
tKHKH
K/K Clock Rise to K/K Clock Rise and C/C to C/C
Rise (rising edge to rising edge)
2.8
3.2
3.4
4.1
4.4
5.4
ns
tKHCH
tKHCH
K/K Clock Rise to C/C Clock Rise (rising edge to
rising edge)
0.0
2.0
0.0
2.5
0.0
3.0
ns
Set-up Times
tSA
tSA
Address Set-up to Clock (K and K) Rise
0.7
0.8
1.0
ns
tSC
tSC
Control Set-up to Clock (K and K) Rise (RPS,
WPS, BWS0, BWS1)
0.7
0.8
1.0
ns
tSD
tSD
D[35:0] Set-up to Clock (K and K) Rise
0.7
0.8
1.0
ns
Hold Times
tHA
tHA
Address Hold after Clock (K and K) Rise
0.7
0.8
1.0
ns
tHC
tHC
Control Signals Hold after Clock (K and K) Rise
(RPS, WPS, BWS0, BWS1)
0.7
0.8
1.0
ns
tHD
tHD
D[35:0] Hold after Clock (K and K) Rise
0.7
0.8
1.0
ns
Output Times
tCO
tCHQV
C/C Clock Rise (or K/K in single clock mode) to
Data Valid
tDOH
tCHQX
Data Output Hold after Output C/C Clock Rise
(Active to Active)
3.0
0.8
3.4
0.8
3.8
0.8
ns
ns
Notes:
19. Tested initially and after any design or process change that may affect these parameters.
20. Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V,Vref = 0.75V, RQ = 250Ω, VDDQ = 1.5V, input
pulse levels of 0.25V to 1.25V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of AC test loads.
Document #: 38-05502 Rev. *A
Page 8 of 18
PRELIMINARY
CY7C1308CV25
Switching Characteristics Over the Operating Range (continued)[20]
-167
Cypress Consortium
Parameter Parameter
Description
Min.
tCHZ
tCHZ
Clock (C and C) Rise to High-Z (Active to
High-Z)[22, 23]
tCLZ
tCLZ
Clock (C and C) Rise to Low-Z[22, 23]
0.8
tCCQO
tCHCQV
C/C Clock Rise to Echo Clock Valid
0.8
tCQD
tCQHQV
Echo Clock High to Data Valid
tCQDOH
tCQHQX
Echo Clock High to Data Invalid
tCQHZ
tCHZ
Clock (CQ and CQ) Rise to High-Z (Active to
High-Z)[22, 23]
tCQLZ
tCLZ
Clock (CQ and CQ) Rise to Low-Z[22, 23]
Max.
-133
Min.
3.0
-100
Min.
3.4
0.8
3.2
0.8
0.40
–0.40
0.8
0.45
Unit
3.8
ns
ns
4.0
0.50
–0.50
0.45
–0.45
Max.
0.8
3.6
–0.45
0.40
–0.40
Max.
ns
ns
0.50
–0.50
ns
ns
ns
Switching Waveforms[24, 25, 26]
Notes:
21. This part has a voltage regulator that steps down the voltage internally; tPower is the time power needs to be supplied above VDD minimum initially before a Read
or Write operation can be initiated.
22. tCHZ, tCLZ, are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 100 mV from steady-state voltage.
23. At any given voltage and temperature tCHZ is less than tCLZ and, tCHZ less than tCO.
24. Q01 refers to output from address A0. Q02 refers to output from the next internal burst address following A0, i.e., A0+1.
25. Outputs are disabled (High-Z) one clock cycle after a NOP.
26. In this example, if address A4 = A3, then data Q41 = D31, Q42 = D32, Q43 = D33, and Q44 = D34. Write data is forwarded immediately as Read results.This
note applies to the whole diagram.
Document #: 38-05502 Rev. *A
Page 9 of 18
PRELIMINARY
IEEE 1149.1 Serial Boundary Scan (JTAG)
These SRAMs incorporate a serial boundary scan test access
port (TAP) in the FBGA package. This part is fully compliant
with IEEE Standard #1149.1-1900. The TAP operates using
JEDEC standard 2.5V I/O logic levels.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately
be connected to VDD through a pull-up resistor. TDO should
be left unconnected. Upon power-up, the device will come up
in a reset state which will not interfere with the operation of the
device.
Test Access Port—Test Clock
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Test Mode Select
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this pin unconnected if the TAP is not used. The pin is
pulled up internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI pin is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see the TAP
Controller State Diagram. TDI is internally pulled up and can
be unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) on any register.
Test Data-Out (TDO)
The TDO output pin is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine (see Instruction codes). The
output changes on the falling edge of TCK. TDO is connected
to the least significant bit (LSB) of any register.
Performing a TAP Reset
A Reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of
the SRAM and may be performed while the SRAM is
operating. At power-up, the TAP is reset internally to ensure
that TDO comes up in a high-Z state.
TAP Registers
Registers are connected between the TDI and TDO pins and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction registers. Data is serially loaded into the TDI pin
on the rising edge of TCK. Data is output on the TDO pin on
the falling edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
Document #: 38-05502 Rev. *A
CY7C1308CV25
TDI and TDO pins as shown in TAP Controller Block Diagram.
Upon power-up, the instruction register is loaded with the
IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
When the TAP controller is in the Capture IR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board level serial test path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all of the input and
output pins on the SRAM. Several no connect (NC) pins are
also included in the scan register to reserve pins for higher
density devices.
The boundary scan register is loaded with the contents of the
RAM Input and Output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and
TDO pins when the controller is moved to the Shift-DR state.
The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the Input and
Output ring.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.
TAP Instruction Set
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in the
Instruction Code table. Three of these instructions are listed
as RESERVED and should not be used. The other five instructions are described in detail below.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO pins.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO pins and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state. The IDCODE instruction
Page 10 of 18
PRELIMINARY
is loaded into the instruction register upon power-up or
whenever the TAP controller is given a test logic reset state.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. The SAMPLE Z command puts
the output bus into a High-Z state until the next command is
given during the “Update IR” state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 10 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is
possible that during the Capture-DR state, an input or output
will undergo a transition. The TAP may then try to capture a
signal while in transition (metastable state). This will not harm
the device, but there is no guarantee as to the value that will
be captured. Repeatable results may not be possible.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture set-up plus
hold times (tCS and tCH). The SRAM clock input might not be
captured correctly if there is no way in a design to stop (or
slow) the clock during a SAMPLE/PRELOAD instruction. If this
is an issue, it is still possible to capture all other signals and
simply ignore the value of the CK and CK captured in the
boundary scan register.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO pins.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells
prior to the selection of another boundary scan test operation.
CY7C1308CV25
The shifting of data for the SAMPLE and PRELOAD phases
can occur concurrently when required—that is, while data
captured is shifted out, the preloaded data can be shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO pins. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
EXTEST
The EXTEST instruction enables the preloaded data to be
driven out through the system output pins. This instruction also
selects the boundary scan register to be connected for serial
access between the TDI and TDO in the shift-DR controller
state.
EXTEST Output Bus Three-state
IEEE Standard 1149.1 mandates that the TAP controller be
able to put the output bus into a three-state mode.
The boundary scan register has a special bit located at bit #47.
When this scan cell, called the “extest output bus three-state”,
is latched into the preload register during the “Update-DR”
state in the TAP controller, it will directly control the state of the
output (Q-bus) pins, when the EXTEST is entered as the
current instruction. When HIGH, it will enable the output
buffers to drive the output bus. When LOW, this bit will place
the output bus into a High-Z condition.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that
cell, during the “Shift-DR” state. During “Update-DR”, the value
loaded into that shift-register cell will latch into the preload
register. When the EXTEST instruction is entered, this bit will
directly control the output Q-bus pins. Note that this bit is
pre-set HIGH to enable the output when the device is
powered-up, and also when the TAP controller is in the
“Test-Logic-Reset” state.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Document #: 38-05502 Rev. *A
Page 11 of 18
PRELIMINARY
CY7C1308CV25
TAP Controller State Diagram[27]
1
TEST-LOGIC
RESET
0
0
TEST-LOGIC/
IDLE
1
1
SELECT
DR-SCAN
0
0
1
1
CAPTURE-DR
CAPTURE-DR
0
0
0
SHIFT-DR
1
1
EXIT1-DR
1
EXIT1-IR
0
0
PAUSE-DR
0
0
PAUSE-IR
1
1
0
EXIT2-DR
EXIT2-IR
1
1
UPDATE-DR
1
0
SHIFT-IR
1
0
1
SELECT
IR-SCAN
0
UPDATE-IR
1
0
Note:
27. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
Document #: 38-05502 Rev. *A
Page 12 of 18
PRELIMINARY
CY7C1308CV25
TAP Controller Block Diagram
0
Bypass Register
Selection
Circuitry
TDI
2
1
0
1
0
Selection
Circuitry
Instruction Register
31 30 29
.
.
2
TDO
Identification Register
106 .
.
.
.
2
1
0
Boundary Scan Register
TCK
TMS
TAP Controller
TAP Electrical Characteristics Over the Operating Range [12, 14, 28]
Parameter
Description
Test Conditions
Min.
VOH1
Output HIGH Voltage
IOH = −2.0 mA
1.7
VOH2
Output HIGH Voltage
IOH = −100 µA
2.1
VOL1
Output LOW Voltage
IOL = 2.0 mA
VOL2
Output LOW Voltage
IOL = 100 µA
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
IX
Input and Output Load Current
GND ≤ VI ≤ VDDQ
Max.
Unit
V
V
0.7
V
0.2
V
1.7
VDD + 0.3
V
–0.3
0.7
V
–5
5
µA
TAP AC Switching Characteristics Over the Operating Range[29, 30]
Parameter
Description
Min.
Max.
Unit
10
MHz
tTCYC
TCK Clock Cycle Time
tTF
TCK Clock Frequency
tTH
TCK Clock HIGH
40
ns
tTL
TCK Clock LOW
40
ns
tTMSS
TMS Set-up to TCK Clock Rise
10
ns
tTDIS
TDI Set-up to TCK Clock Rise
10
ns
tCS
Capture Set-up to TCK Rise
10
ns
tTMSH
TMS Hold after TCK Clock Rise
10
ns
tTDIH
TDI Hold after Clock Rise
10
ns
tCH
Capture Hold after Clock Rise
10
ns
100
ns
Set-up Times
Hold Times
Notes:
28. These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics table.
29. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.
30. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns.
Document #: 38-05502 Rev. *A
Page 13 of 18
PRELIMINARY
CY7C1308CV25
TAP AC Switching Characteristics Over the Operating Range[29, 30]
Parameter
Description
Min.
Max.
Unit
Output Times
tTDOV
TCK Clock LOW to TDO Valid
tTDOX
TCK Clock LOW to TDO Invalid
20
ns
0
ns
TAP Timing and Test Conditions[30]
1.25V
ALL INPUT PULSES
2.5V
50Ω
1.25V
TDO
0V
Z0 = 50Ω
(a)
CL = 20 pF
GND
tTH
tTL
Test Clock
TCK
tTCYC
tTMSS
tTMSH
Test Mode Select
TMS
tTDIS
tTDIH
Test Data-In
TDI
Test Data-Out
TDO
tTDOX
tTDOV
Identification Register Definitions
Value
Instruction Field
Revision Number (31:29)
CY7C1308CV25
001
Cypress Device ID (28:12)
01011111011100110
Cypress JEDEC ID (11:1)
00000110100
ID Register Presence (0)
1
Document #: 38-05502 Rev. *A
Description
Version number.
Defines the type of SRAM.
Allows unique identification of SRAM vendor.
Indicate the presence of an ID register.
Page 14 of 18
PRELIMINARY
CY7C1308CV25
Scan Register Sizes
Register Name
Bit Size
Instruction
3
Bypass
1
ID
32
Boundary Scan
107
Instruction Codes
Instruction
Code
Description
EXTEST
000
Captures the Input/Output ring contents.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operation.
SAMPLE Z
010
Captures the Input/Output contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
RESERVED
011
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
100
Captures the Input/Output ring contents. Places the boundary scan register between TDI and
TDO. Does not affect the SRAM operation.
RESERVED
101
Do Not Use: This instruction is reserved for future use.
RESERVED
110
Do Not Use: This instruction is reserved for future use.
BYPASS
111
Places the bypass register between TDI and TDO. This operation does not affect SRAM operation.
Boundary Scan Order (continued)
Boundary Scan Order
Bit #
Bump ID
Bit #
0
6R
24
9K
1
6P
25
10J
2
6N
26
11J
3
7P
27
11H
4
7N
28
10G
5
7R
29
9G
6
8R
30
11F
7
8P
31
11G
8
9R
32
9F
9
11P
33
10F
10
10P
34
11E
11
10N
35
10E
12
9P
36
10D
13
10M
37
9E
14
11N
38
10C
15
9M
39
11D
16
9N
40
9C
17
11L
41
9D
18
11M
42
11B
19
9L
43
11C
20
10L
44
9B
21
11K
45
10B
22
10K
46
11A
9J
47
Internal
23
Document #: 38-05502 Rev. *A
Bump ID
Page 15 of 18
PRELIMINARY
Boundary Scan Order (continued)
CY7C1308CV25
Boundary Scan Order (continued)
Bit #
Bump ID
Bit #
Bump ID
48
9A
92
1L
49
8B
93
3N
50
7C
94
3M
51
6C
95
1N
52
8A
96
2M
53
7A
97
3P
54
7B
98
2N
55
6B
99
2P
56
6A
100
1P
57
5B
101
3R
58
5A
102
4R
59
4A
103
4P
60
5C
104
5P
61
4B
105
5N
62
3A
106
5R
63
1H
64
1A
65
2B
66
3B
67
1C
68
1B
69
3D
70
3C
71
1D
72
2C
73
3E
74
2D
75
2E
76
1E
77
2F
78
3F
79
1G
80
1F
81
3G
82
2G
83
1J
84
2J
85
3K
86
3J
87
2K
88
1K
89
2L
90
3L
91
1M
Document #: 38-05502 Rev. *A
Page 16 of 18
PRELIMINARY
CY7C1308CV25
Ordering Information
Speed
(MHz)
Ordering Code
167
CY7C1308CV25-167BZC
133
CY7C1308CV25-133BZC
100
CY7C1308CV25-100BZC
Package
Name
BB165D
Operating
Range
Package Type
13 x 15 x 1.4 mm FBGA
Commercial
Package Diagram
165 FBGA 13 x 15 x 1.40 mm BB165D
51-85180-**
All products and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05502 Rev. *A
Page 17 of 18
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
PRELIMINARY
CY7C1308CV25
Document History Page
Document Title: CY7C1308CV25 9-Mbit 4-Word Burst SRAM with DDR-I Architecture
Document Number: 38-05502
REV.
ECN NO.
ISSUE DATE
ORIG. OF
CHANGE
DESCRIPTION OF CHANGE
**
208404
see ECN
DIM
New Data Sheet
*A
230396
see ECN
VBL
Upload datasheet to the internet
Document #: 38-05502 Rev. *A
Page 18 of 18