EC24C512C 512K bits Two-wire Serial EEPROM General Description The EC24C512C are EEPROM devices that use the industrial standard 2-wire interface for communications. The EC24C512C contains a memory array of 512K-bits (65,536x8), which is organized in 128byte per page. The EEPROM can operate in a wide voltage range from 1.7V to 5.5V which fits most application. This product can provide a low- power 2-wire EEPROM solution. The device is offered in Lead-free, RoHS, halogen free or Green. The available package types are 8-pin SOP, TSSOP, DFN. The EC24C512C is compatible with the industrial standard 2-wire bus protocol. If in case the bus is not responded, a new sent Op-code command will reset the bus and the device will respond correctly. The simple bus consists of the Serial Clock wire (SCL) and the Serial Data wire (SDA). Utilizing such bus protocol, a Master device, such as a microcontroller, can usually control one or more Slave devices, alike this EC24C512C. The bit stream over the SDA line includes a series of bytes, which identifies a particular Slave device, an instruction, an address within that Slave device, and a series of data, if appropriate. The EC24C512C also has a Write Protect pin (WP) to allow blocking any write operations over specified memory area. The EC24C512C also offers an additional page, named the Identification Page (128 bytes) which can be written and (later) permanently locked in Read-only mode. This Identification Page offers flexibility in the application board production line, as the Identification Page can be used to store unique identification parameters and/or parameters specific to the production line. Under no circumstance, the device will be hung up. In order to refrain the state machine entering into a wrong state during power-up sequence or a power toggle off-on condition, a power on reset circuit is embedded. During power-up, the device does not respond to any instructions until the supply voltage (VCC) has reached an acceptable stable level above the reset threshold voltage. Once VCC passes the power on reset threshold, the device is reset and enters into the Standby mode. This would also avoid any inadvertent Write operations during power-up stage. During power-down process, the device will enter into standby mode, once VCC drops below the power on reset threshold voltage. In addition, the device will be in standby mode after receiving the Stop command, provided that no internal write operation is in progress. Nevertheless, it is illegal to send a command unless the VCC is within its operating level. Features 2 ● Two-Wire Serial Interface, I C TM Compatible – Bi-directional data transfer protocol ● Wide-voltage Operation – VCC = 1.7V to 5.5V ● Page Size: 128 bytes ● Page write mode – Up to 128 bytes per page write - offer an 128 bytes additional page ● Speed: 400 KHz (1.7V) and 1 MHz (2.5V~5.5V) ● Self timed write cycle with auto clear: 5ms (max.) uA, 1.7V ● Operating current (max.): 0.5mA, 1.7V ● Hardware Data Protection ● Filtered inputs for noise suppression – Write Protect Pin ● Sequential & Random Read Features ● Memory organization: 65,536 x 8 bits ● High-reliability – Endurance: 1 million cycles – Data retention: 100 years ● Industrial temperature grades ● Packages: SOP,TSSOP,DFN ● Lead-free, RoHS, Halogen free, Green E-CMOS Corp. (www.ecmos.com.tw) Page 1 of 16 5C26N-Rev.F001 EC24C512C 512K bits Two-wire Serial EEPROM Ordering Information & Marking Information EC24C XXXC XX X X R：Tape & Reel T：Tube Device Function 512＝512Kbit (65536×8) G：Green M1：SOP 8L E1：TSSOP 8L F2：DFN 8L Functional Block Diagram E-CMOS Corp. (www.ecmos.com.tw) Page 2 of 16 5C26N-Rev.F001 EC24C512C 512K bits Two-wire Serial EEPROM Pin Configuration (SOP 8L / TSSOP 8L) (DFN 8L) Pin Definition Pin No. 1 Pin Name A0 I/O I 2 A1 I Definition Device Address Input Device Address Input 3 A2 I Device Address Input 4 GND - Ground 5 SDA I/O 6 SCL I Serial Clock Input 7 WP I Write Protect Input 8 VCC - Power Supply Serial Address and Data input and Data out put Pin Descriptions SCL This input clock pin is used to synchronize the data transfer to and from the device. SDA The SDA is a bi-directional pin used to transfer addresses and data into and out of the device. The SDA pin is an open drain output and can be wired with other open drain or open collector outputs. However, the SDA pin requires a pull-up resistor connected to the power supply. A0, A1, A2 The A0, A1 and A2 are the device address inputs. Typically, the A0, A1, and A2 pins are for hardware addressing and a total of 8 devices can be connected on a single bus system. When A0, A1, and A2 are left floating, the inputs are defaulted to zero. WP WP is the Write Protect pin. While the WP pin is connected to the power supply of EC24C512C, the entire array becomes Write Protected (i.e. the device becomes Read only). When WP is tied to Ground or left floating, the normal write operations are allowed. VCC Supply voltage GND Ground of supply voltage E-CMOS Corp. (www.ecmos.com.tw) Page 3 of 16 5C26N-Rev.F001 EC24C512C 512K bits Two-wire Serial EEPROM Device Operation The EC24C512C serial interface supports Reset communications using industrial standard 2-wire bus The EC24C512C contains a reset function in case the 22 protocol, such as I C. wire bus transmission on is accidentally interrupted (e.g. a power loss), or needs to be terminated mid-stream. 2-WIRE Bus The reset is initiated when the Master device creates a The two-wire bus is defined as Serial Data (SDA), and Start condition. To do this, it may be necessary for the Serial Clock (SCL). The protocol defines any device that Master device to monitor the SDA line while cycling the sends data onto the SDA bus as a transmitter, and the SCL up to nine times.(For each clock signal transition to receiving devices as receivers. The bus is controlled by High, the Master checks for a High level on SDA.) Master device that generates the SCL, controls the bus access, and generates the Start and Stop conditions. Standby Mode While in standby mode, the power consumption is The EC24C512C is the Slave device. minimal. The EC24C512C enters into standby mode during one of the following conditions: a) After Power-up, The Bus Protocol while no Op-code is sent; b) After the completion of an Data transfer may be initiated only when the bus is not operation and followed by the Stop signal, provided that busy. During a data transfer, the SDA line must remain the previous operation is not Write related; or c) After the stable whenever the SCL line is high. Any changes in the completion of any internal write operations. SDA line while the SCL line is high will be interpreted as a Start or Stop condition. Device Addressing The state of the SDA line represents valid data after a The Master begins a transmission on by sending a Start condition, then sends the address of the particular Slave devices to be communicated. The Slave device address is 8 bits format as shown in Figure. 5. The four most significant bits of the Slave address are fixed (1010) for EC24C512C. The next three bits, A0, A1 and A2, of the Slave address are specifically related to EEPROM. Up to eight EC24C512C units can be connected to the 2-wire bus. The last bit of the Slave address specifies whether a Read or Write operation is to be performed. When this bit is set to 1, Read operation is selected. While it is set to 0, Write operation is selected. After the Master transmits the Start condition and Slave address byte appropriately, the associated 2-wire Slave device,EC24C512C, will respond with ACK on the SDA line. Then EC24C512C will pull down the SDA on the ninth clock cycle, signaling that it received the eight bits of data. The EC24C512C then prepares for a Read or Write operation by monitoring the bus. Start condition. The SDA line must be stable for the duration of the High period of the clock signal. The data on the SDA line may be changed during the Low period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a Start condition and terminated by a Stop condition. Start Condition The Start condition precedes all commands to the device and is defined as a High to Low transition of SDA when SCL is High. The EEPROM monitors the SDA and SCL lines and will not respond until the Start condition is met. Stop Condition The Stop condition is defined as a Low to High transition of SDA when SCL is High. All operations must end with a Stop condition. Acknowledge After a successful data transfer, each receiving device is required to generate an ACK. The Acknowledging device pulls down the SDA line. E-CMOS Corp. (www.ecmos.com.tw) Page 4 of 16 5C26N-Rev.F001 EC24C512C 512K bits Two-wire Serial EEPROM Write Operation Byte Write This involves issuing the Start condition followed by the In the Byte Write mode, the Master device sends the Slave address for a Write operation. If the EEPROM is Start condition and the Slave address information (with still busy with the Write operation, no ACK will be the R/W set to Zero) to the Slave device. After the Slave returned. If the EC24C512C has completed the Write generates an ACK, the Master sends the byte address operation, an ACK will be returned and the host can then that is to be written into the address pointer of the proceed with the next Read or Write operation. EC24C512C. After receiving another ACK from the Slave, the Master device transmits the data byte to be Write Identification Page written into the address memory location. The The Identification Page(128 bytes) is an additional page EC24C512C acknowledges once more and the Master which can be written and (later) permanently locked in generates the Stop condition, at which time the device Read-only mode. It is written by issuing the Write begins its internal programming cycle. While this internal Identification Page instruction. This instruction uses the cycle is in progress, the device will not respond to any same protocol and format as Page Write (into memory request from the Master device. array), except for the following differences: ● Device type identifier=1011b Page Write ● MSB address bits A15/A7 are don’t care The EC24C512C is capable of 128-byte Page-Write except for address bit A10 which must be operation. A Page-Write is initiated in the same manner ‘0’. LSB address bits A6/A0 define the byte as a Byte Write, but instead of terminating the internal address inside the Identification page. Write cycle after the first data word is transferred, the If the Identification page is locked, the data bytes Master device can transmit up to 127 more bytes. After transferred during the Write Identification Page the receipt of each data word, the EEPROM responds instruction are not acknowledged (NoACK). immediately with an ACK on SDA line, and the seven lower order data word address bits are internally Lock Identification Page incremented by one, while the higher order bits of the The Lock Identification Page instruction (Lock ID) data word address remain constant. If a byte address is permanently locks the Identification page In Read-only incremented from the last byte of a page, it returns to the mode. The lock ID instruction is similar to Byte Write (into first byte of that page. If the Master device should memory array) with the following specific condition: transmit more than 128 bytes prior to issuing the Stop ● Device type identifier=1011b condition, the address counter will “roll over,” and the ● Address bit A10 must be ‘1’; all other address bits are previously written data will be overwritten. Once all 128 don’t care bytes are received and the Stop condition has been sent ● The data byte must be equal to the binary value xxxx by the Master, the internal programming cycle begins. At xx1x, where x is don’t care this point, all received data is written to the EC24C512C in a single Write cycle. All inputs are disabled until completion of the internal Write cycle. Acknowledge (ACK) Polling The disabling of the inputs can be used to take advantage of the typical Write cycle time. Once the Stop condition is issued to indicate the end of the host's Write operation, the EC24C512C initiates the internal Write cycle. ACK polling can be initiated immediately. E-CMOS Corp. (www.ecmos.com.tw) Page 5 of 16 5C26N-Rev.F001 EC24C512C 512K bits Two-wire Serial EEPROM Read Operation Read Operation Read operations are initiated in the same manner as Write operations, except that the (R/W) bit of the Slave address is set to “1”. There are three Read operation options: current address read, random address read and sequential read. Current Address Read The EC24C512C contains an internal address counter which maintains the address of the last byte accessed, incremented by one. For example, if the previous operation is either a Read or Write operation addressed to the address location n, the internal address counter would increment to address location n+1. When the EEPROM receives the Slave Addressing Byte with a Read operation (R/W bit set to “1”), it will respond an ACK and transmit the 8-bit data byte stored at address location n+1. The Master should not acknowledge the transfer but should generate a Stop condition so the EC24C512C discontinues transmission. If 'n' is the last byte of the memory, the data from location '0' will be transmitted. (Refer to Figure 8. Current Address Read Diagram.) Random Address Read Selective Read operations allow the Master device to select at random any memory location for a Read operation. The Master device first performs a 'dummy' Write operation by sending the Start condition, Slave address and byte address of the location it wishes to read. After the EC24C512C acknowledges the byte address, the Master device resends the Start condition and the Slave address, this time with the R/W bit set to one. The EEPROM then responds with its ACK and sends the data requested. The Master device does not send an ACK but will generate a Stop condition. (Refer to Figure 9. Random Address Read Diagram.) Sequential Read Sequential Reads can be initiated as either a Current Address Read or Random Address Read. After the EC24C512C sends the initial byte sequence, the Master device now responds with an ACK indicating it requires additional data from the EC24C512C. The EEPROM continues to output data for each ACK received. The Master device terminates the sequential Read operation by pulling SDA High (no ACK) indicating the last data word to be read, followed by a Stop condition. The data output is sequential, with the data from address n followed by the data from address n+1,n+2 ... etc. The address counter increments by one automatically, allowing the entire memory contents to be serially read during sequential Read operation. When the memory address boundary of the array is reached, the address counter “rolls over” to address 0, and the device continues to output data. (Refer to Figure 10. Sequential Read Diagram). Read Identification Page The Identification Page can be read by issuing an Read Identification Page instruction. This instruction uses the same protocol and format as the Random Address Read (from memory array) with device type identifier defined as 1011b.The MSB address bits A15/A7 are don’t care, the LSB address bits A6/A0 define the byte address inside the Identification Page. The number of bytes to read in the ID page must not exceed the page boundary (e.g.:when reading the Identification Page from location 100d, the number of bytes should be less than or equal to 28, as the ID page boundary is 128 bytes). Read the lock status The locked/unlocked status of the Identification page can be checked by transmitting a specific truncated command[Identification page is unlocked, otherwise a NoACK bit if the Identification page is locked. Right after this, it is recommended to transmit to the device a start followed by a Stop condition, so that: Start: the truncated command is not executed because the Start condition resets the device internal logic. Stop: the device is then set back into Standby mode by the Stop condition. E-CMOS Corp. (www.ecmos.com.tw) Page 6 of 16 5C26N-Rev.F001 EC24C512C 512K bits Two-wire Serial EEPROM Diagrams Figure 1. Typical System Bus Configuration EC24C512C Figure 2. output Acknowledge Figure 3. Start and Stop Conditions Figure 4. Data Validity Protocol E-CMOS Corp. (www.ecmos.com.tw) Page 7 of 16 5C26N-Rev.F001 EC24C512C 512K bits Two-wire Serial EEPROM Figure 5. Slave Address Figure 6. Byte Write Figure 7. Page Write Figure 8. Current Address Read E-CMOS Corp. (www.ecmos.com.tw) Page 8 of 16 5C26N-Rev.F001 EC24C512C 512K bits Two-wire Serial EEPROM Figure 9. Random Address Read Figure 10. Sequential Read E-CMOS Corp. (www.ecmos.com.tw) Page 9 of 16 5C26N-Rev.F001 EC24C512C 512K bits Two-wire Serial EEPROM Timing Diagrams Figure 11 .Bus Timing Figure 12. Write Cycle Timing E-CMOS Corp. (www.ecmos.com.tw) Page 10 of 16 5C26N-Rev.F001 EC24C512C 512K bits Two-wire Serial EEPROM Electrical Characteristics Absolute Maximum Ratings Symbol Parameter Value Unit VS Supply Voltage -0.5 to + 6.5 VP Voltage on Any Pin TBIAS Temperature Under Bias –55 to +125 TSTG Storage Temperature –65 to +150 –0.5 to VCC + 0.5 Output Current IOUT V V °C °C 5 mA Note: Stress greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condition outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Operating Range Range Industrial Ambient Temperature (TA) –40°C to +85°C VCC 1.7V to 5.5V Capacitance Symbol CIN CI/O Parameter [1,2] Input Capacitance Input / Output Capacitance Conditions Max. Unit VIN = 0V 6 pF VI/O = 0V 8 pF Note: (1) Tested initially and after any design or process changes that may affect these parameters and not 100% tested. (2) Test conditions: TA = 25°C, f = 1 MHz, VCC = 5.0V. E-CMOS Corp. (www.ecmos.com.tw) Page 11 of 16 5C26N-Rev.F001 EC24C512C 512K bits Two-wire Serial EEPROM DC Electrical Characteristic Industrial: TA = –40°C to +85°C, VCC = 1.7V ~ 5.5V Symbol Parameter [1] VCC Test Conditions Min. Typ. Max. Unit VCC Supply Voltage 1.7 -- 5.5 V VIH Input High Voltage 0.7*VCC -- VCC+1 V -1 -- 0.3* VCC V -- -- 2 μA -- -- 2 μA VIL Input Low Voltage ILI Input Leakage Current 5V ILO Output Leakage Current 5V VOL1 Output Low Voltage 1.7V IOL = 0.15 mA — -- 0.2 V VOL2 Output Low Voltage 3V IOL = 2.1 mA — -- 0.4 V ISB1 Standby Current 1.7V VIN = VCC or GND — 0.2 1 μA ISB2 Standby Current 2.5V VIN = VCC or GND — 0.3 1 μA ISB3 Standby Current 5V VIN = VCC or GND — 0.5 1 μA ICC1 Read Current 1.7V Read at 400 KHz — — 0.15 mA ICC1 Read Current 2.5V Read at 1 MHz — — 0.2 mA ICC1 Read Current 5.5V Read at 1 MHz — — 0.5 mA ICC2 Write Current 1.7V Write at 400 KHz — — 0.5 mA ICC2 Write Current 2.5V Write at 1 MHz — — 0.6 mA ICC2 Write Current 5.5V Write at 1 MHz — — 1 mA VIN = VCC max Note: The parameters are characterized but not 100% tested. E-CMOS Corp. (www.ecmos.com.tw) Page 12 of 16 5C26N-Rev.F001 EC24C512C 512K bits Two-wire Serial EEPROM AC Electrical Characteristic Industrial: TA = –40°C to +85°C, Supply voltage = 1.7V to 5.5V Symbol Parameter [1][2] 1.7V ≤ VCC<2.5V Min. Max. 2.5V ≤ VCC<4.5V 4.5V ≤ VCC ≤ 5.5V Min. Max. Unit 1000 KHz 400 — ns — 400 — ns — 300 — 300 ns 300 — 100 — 100 ns 400 Max. FSCL SCK Clock Frequency TLOW Clock Low Period 1200 — 400 — THIGH Clock High Period 600 — 400 TR Rise Time (SCL and SDA) — 300 TF Fall Time (SCL and SDA) — Min. Unit 1000 TSU:STA Start Condition Setup Time 600 — 200 — 200 — ns TSU:STO Stop Condition Setup Time 600 — 200 — 200 — ns THD:STA Start Condition Hold Time 600 — 200 — 200 — ns TSU:DAT Data In Setup Time 100 — 40 — 40 — ns THD:DAT Data In Hold Time 0 — 0 — 0 — ns 100 900 50 400 50 400 ns 100 — 50 — 50 — ns — 5 — 5 — 5 ms 1000 — 400 — 400 — ns TAA TDH TWR TBUF Clock to Output Access time (SCL Low to SDA Data Out Valid) Data Out Hold Time (SCL Low to SDA Data Out Change) Write Cycle Time Bus Free Time Before New Transmission TSU:WP WP pin Setup Time 600 — 400 — 400 THD:WP WP pin Hold Time 1200 — 1200 — 1200 — ns T Noise Suppression Time — 100 — 50 — 50 ns ns Note: (1)The parameters are characterized but not 100% tested. (2)AC measurement conditions: RL (connects to VCC): 1.3 kΩ (2.5V, 5.0V), 10 kΩ (1.7V) CL = 100 pF Input pulse voltages: 0.3*VCC to 0.7*VCC Input rise and fall times: ≤ 50 ns Timing reference voltages: half VCC level E-CMOS Corp. (www.ecmos.com.tw) Page 13 of 16 5C26N-Rev.F001 EC24C512C 512K bits Two-wire Serial EEPROM Package Information SOP 8L SYMBOLS DIMENSIONS IN MILLIMETERS DIMENSIONS IN INCHES A MIN 1.35 NOM -- MAX 1.75 MIN 0.053 NOM -- MAX 0.069 A1 b 0.10 0.33 --- 0.25 0.51 0.004 0.013 --- 0.010 0.020 D E 4.80 5.80 --- 5.00 6.20 0.189 0.228 --- 0.197 0.244 E1 e 3.80 4.00 0.150 L 0.38 1.27 0.015 L1 ZD Θ -1.27 BSC. -0.25 BSC. 0.545 REF. 0 -- -0.050 BSC. 0.157 0.050 0.010 BSC. 0.021 REF. 8° 0 -- 8° Note: 1. Controlling Dimension: MM 2. Dimension D and E1 do not include Mold protrusion 3. Dimension b does not include dambar protrusion/intrusion. 4. Refer to Jedec standard MS-012 5. Drawing is not to scale E-CMOS Corp. (www.ecmos.com.tw) Page 14 of 16 5C26N-Rev.F001 EC24C512C 512K bits Two-wire Serial EEPROM TSSOP 8L SYMBOLS DIMENSIONS IN MILLIMETERS DIMENSIONS IN INCHES MIN NOM MAX MIN NOM MAX A -- -- 1.20 -- -- 0.047 A1 0.05 -- 0.15 0.002 -- 0.006 A2 0.80 1.00 1.05 0.031 0.039 0.041 b 0.19 -- 0.30 0.007 -- 0.012 c 0.09 -- 0.20 0.004 -- 0.008 D 2.90 3.00 3.10 0.114 0.118 0.122 E 4.30 4.40 4.50 0.169 0.173 0.177 E1 6.4 BSC 0.252 BSC e 0.65 BSC 0.026 BSC L 0.45 0.60 0.75 0.018 0.024 0.030 Θ 0 -- 8° 0 -- 8° Note: 1. Controlling Dimension: MM 2. Dimension D and E do not include Mold protrusion 3. Dimension b does not include dambar protrusion/intrusion. 4. Refer to Jedec standard MO-153 AA 5. Drawing is not to scale 6. Package may have exposed tie bar. E-CMOS Corp. (www.ecmos.com.tw) Page 15 of 16 5C26N-Rev.F001 EC24C512C 512K bits Two-wire Serial EEPROM DFN 8L SYMBOLS A A1 b A2 D D2 E E2 e K L DIMENSIONS IN MILLIMETERS MIN NOM MAX 0.50 0.55 0.60 0.00 -0.05 0.18 0.25 0.30 0.152 REF 2.00 BSC 1.25 1.40 1.50 3.00 BSC 1.15 1.30 1.40 0.50 BSC. 0.40 --0.20 0.30 0.40 DIMENSIONS IN INCHES MIN NOM MAX 0.020 0.022 0.024 0.000 -0.002 0.007 0.010 0.012 0.006 REF 0.079 BSC 0.049 0.055 0.059 0.118 BSC 0.045 0.051 0.055 0.020 BSC. 0.016 --0.008 0.012 0.016 Note: 1. Controlling Dimension: MM 2. Drawing is not to scale E-CMOS Corp. (www.ecmos.com.tw) Page 16 of 16 5C26N-Rev.F001