ADC1443D series Dual channel 14-bit ADC; 125, 160 or 200 Msps; JESD204B-compliant CGVxpress serial outputs Rev. 3.4 — 10 October 2012 Data sheet 1. General description The ADC1443D is a dual channel 14-bit Analog-to-Digital Converter (ADC) with JESD204B interface (which is backward compatible with the JESD204A interface) optimized for high dynamic performance and low power consumption at sample rates up to 200 Msps. Pipelined architecture and output error correction ensure that the ADC1443D is accurate enough to guarantee zero missing codes over the entire operating range. Supplied from a single 1.8 V source, the ADC1443D has serial outputs compliant with the JESD204B standard over a configurable number of lanes (1 or 2). Multiple Device Synchronization (MDS) allows sample-accurate synchronization of the data outputs of multiple ADC devices. It guarantees a maximum skew of one clock period between as many as 16 output lanes from up to eight ADC1443D devices. An integrated Serial Peripheral Interface (SPI) allows easy configuration of the ADC. The device also includes a programmable full-scale to allow a flexible input voltage range of 1 V (p-p) to 2 V (p-p). With excellent dynamic performance from the baseband to input frequencies of up to 1 GHz (typical), the ADC1443D is ideal for use in undersampled multi-carrier, multistandard communication system applications. Using a pipelined architecture, an output error correction scheme ensures that the ADC1443D is accurate enough to guarantee zero missing codes over the entire operating range. The ADC1443D is available in an HLQFN56 package (8 mm × 8 mm outline). It is supported with customer demo boards. This device is also available in a 12-bit resolution variant with a choice of maximum sampling frequency (125, 160 or 200 Msps). 2. Features and benefits Dual channel 14-bit resolution ADC SNR = 70.6 dBFS (typical); fs = 154 Msps; fi = 190 MHz Sampling rate up to 200 Msps SFDR = 86 dBc (typical); fs = 154 Msps; fi = 190 MHz JESD204B Device Subclass 0, 1 and 2 IMD3 = 88 dBc (typical); fs = 154 Msps; compliant with harmonic clocking and fi1 = 188.5 MHz; fi2 = 191.5 MHz deterministic latency support ADC Multiple Device Synchronization Analog input bandwidth of 1 GHz (MDS) (typical) Assured interworking/interoperability Pin to pin compatible with ADC1413D with SerDes based FPGAs series ® ADC1443D series Integrated Device Technology Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs Two JESD204B serial output lanes, up to 5 Gbps typical Single 1.8 V supply Flexible input voltage range from 1 V (p-p) to 2 V (p-p) by 1 dB steps Clock input divider from 1 to 8 supports harmonic clocking Duty Cycle Stabilizer (DCS) Offset binary, two’s complement and Gray output data Typical power dissipation = 0.9 W; fs = 154 Msps Power-down and sleep modes Industrial temperature range from −40 °C to +85 °C Serial Peripheral Interface (SPI) for configuration control and status monitoring HLQFN56 package; 8 × 8 mm 3. Applications Wireless infrastructure: LTE, TD-LTE, WiMAX, MC-GSM, CDMA, WCDMA, TD-SCDMA Software defined radio Medical non-invasive scanners Scientific particle detectors Microwave backhaul transceivers Aerospace and defense communications and radar systems Industrial signal analysis instruments General-purpose high-speed applications 4. Ordering information Table 1. Ordering information Type number fs (Msps) Package Name Description ADC1443D200HD 200 HLQFN56 plastic thermal enhanced low profile quad flat package; SOT935-2 no leads; 56 terminals; resin based; body 8 × 8 × 1.35 mm ADC1443D160HD 160 HLQFN56 plastic thermal enhanced low profile quad flat package; SOT935-2 no leads; 56 terminals; resin based; body 8 × 8 × 1.35 mm ADC1443D125HD 125 HLQFN56 plastic thermal enhanced low profile quad flat package; SOT935-2 no leads; 56 terminals; resin based; body 8 × 8 × 1.35 mm ADC1443D_SER Data sheet Version © IDT 2012. All rights reserved. Rev. 3.4 — 10 October 2012 2 of 50 ADC1443D series Integrated Device Technology Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs 5. Block diagram SDIO OTRA OTRB SCLK SCS_N ADC1443D SPI T/H INPUT STAGE ADC B CORE PIPELINED 14-bit INAM INBP 8-bit INBM REFERENCE AND POWER MANAGEMENT VCMA Fig 1. VCMB 8-bit 10-bit SERIALIZER A CMLAP OUTPUT BUFFER A CMLAN SERIALIZER B CMLBP OUTPUT BUFFER B CMLBN 10-bit CLOCK DIVIDER AND DUTY CYCLE STABILIZER VDDA AGND VDDO OGND SYSREF CLKP CLKM Block diagram ADC1443D_SER Data sheet 8-bit ENCODER 8-bit/10-bit A 14-bit FRAME ASSEMBLY ADC A CORE PIPELINED ENCODER 8-bit/10-bit B 8-bit T/H INPUT STAGE SCRAMBLER B INAP SCRAMBLER A SYNCBP SYNCBN © IDT 2012. All rights reserved. Rev. 3.4 — 10 October 2012 3 of 50 ADC1443D series Integrated Device Technology Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs 6. Pinning information %& ;A+#87 %% ;A+#8+ %, !4+" $ %. 34+" 9+!7 . %$ 34+" 5#6! & %/ 5""3 "+# % &0 #6(!7 "+# , &1 #6(!+ !4+" - &2 5""3 #(:7 2 &- 34+" #(:6 1 &, 34+" !4+" 0 &% 5""3 "+# $/ && #6(8+ "+# $$ &. #6(87 5#68 $. &$ 5""3 9+87 $& &/ 34+" 9+86 $% .0 34+" .. .& .% ., .- .2 #*4/?3@=! #*4$?3@=8 #*4. #*4& 5""3 !4+" .1 .$ $0 ;#;<+ "+# $1 ;"93 ;#=<>+ $2 ;#(: ./ $5""! !4+" $, 5""! !"#$%%&" '()*+,- BBBC///%.% Pin configuration (SOT935-2) ADC1443D_SER Data sheet %- 5""3 9+!6 @DBEFGBDHEIJIKGJLMHN Fig 2. %2 "+# %1 ;A;=>*7 %0 ;A;=>*+ ,/ 5""! ,$ !4+" ,. !4+" ,& 5""! ,% "+# ,- 5""! IHDOMEBPJ$ MEQHRJBDHB ,, "+# 6.1 Pinning © IDT 2012. All rights reserved. Rev. 3.4 — 10 October 2012 4 of 50 ADC1443D series Integrated Device Technology Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs 6.2 Pin description Table 2. Pin description Symbol Pin Type[1] Description INAM 1 I channel A complementary analog input INAP 2 I channel A analog input VCMA 3 O channel A output common voltage DNC 4 - do not connect DNC 5 - do not connect AGND 6 G analog ground CLKP 7 I clock input CLKN 8 I complementary clock input AGND 9 G analog ground DNC 10 - do not connect DNC 11 - do not connect VCMB 12 O channel B output common voltage INBP 13 I channel B analog input INBM 14 I channel B complementary analog input VDDA 15 P analog power supply VDDA 16 P analog power supply SCLK 17 I SPI clock SDIO 18 I/O SPI data IO SCS_N 19 I SPI chip select AGND 20 G analog ground DNC 21 - do not connect SCR_EN 22 I scrambler enable CFG0/OTRA 23 I/O configuration pin 0/OuT of Range A (OTRA) CFG1/OTRB 24 I/O configuration pin 1/OuT of Range B (OTRB) CFG2 25 I/O configuration pin 2 CFG3 26 I/O configuration pin 3 VDDO 27 P digital output power supply AGND 28 G analog ground OGND 29 G digital output ground OGND 30 G digital output ground VDDO 31 P digital output power supply CMLBP 32 O channel B output CMLBN 33 O channel B complementary output VDDO 34 P digital output power supply OGND 35 G digital output ground OGND 36 G digital output ground VDDO 37 P digital output power supply CMLAN 38 O channel A complementary output CMLAP 39 O channel A output ADC1443D_SER Data sheet © IDT 2012. All rights reserved. Rev. 3.4 — 10 October 2012 5 of 50 ADC1443D series Integrated Device Technology Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs Table 2. Pin description …continued Symbol Pin Type[1] Description VDDO 40 P digital output power supply OGND 41 G digital output ground OGND 42 G digital output ground SYNCBP 43 I JESD204B SYNC synchronization signal from receiver SYNCBN 44 I complementary SYNC from receiver AGND 45 G analog ground VDDO 46 P digital power DNC 47 - do not connect SYSREFP 48 I positive clock synchronization SYSREFN 49 I negative clock synchronization VDDA 50 P analog power supply AGND 51 G analog ground AGND 52 G analog ground VDDA 53 P analog power supply DNC 54 - do not connect DNC 55 - do not connect VDDA 56 P analog power supply AGND EXP G Expose PAD [1] P: power supply; G: ground; I: input; O: output; I/O: input/output. ADC1443D_SER Data sheet © IDT 2012. All rights reserved. Rev. 3.4 — 10 October 2012 6 of 50 ADC1443D series Integrated Device Technology Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs 7. Limiting values Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDDA Min Max Unit analog supply voltage −0.3 +2.1 V VDDO output supply voltage −0.3 +2.1 V ∆VDD supply voltage difference VDDA − VDDO −0.8 +0.8 V VI input voltage pins INP, INM, CLKP and CLKM; referenced to AGND −0.3 VDDA + 0.3 V pins OTR, SCS_N, SDIO, SCLK, CFG, SCR_EN, SYSREFP, SYSREFN, SYNCBP, and SYNCBN; referenced to AGND −0.3 VDDO + 0.3 V pin VCM; referenced to AGND −0.3 VDDA + 0.3 V pins CMLP, and CMLN; referenced to OGND −0.3 VDDO + 0.3 V VO Conditions output voltage Tstg storage temperature −55 +125 °C Tamb ambient temperature −40 +85 °C Tj junction temperature - 125 °C 8. Thermal characteristics Table 4. Symbol Rth(j-a) Rth(j-c) [1] Thermal characteristics Parameter Conditions Typ Unit thermal resistance from junction to ambient [1] 22.7 K/W thermal resistance from junction to case [1] 9.3 K/W In compliance with JEDEC test board, in free air. 9. Static characteristics Table 5. Symbol Static characteristics[1] Parameter Conditions Min Typ Max Unit 1.7 1.8 1.9 V Supplies VDDA analog supply voltage VDDO output supply voltage 1.7 1.8 1.9 V IDDA analog supply current fs = 185 Msps; fi = 190 MHz - 410 <tbd> mA IDDO output supply current fs = 185 Msps; fi = 190 MHz - 173 <tbd> mA ADC1443D_SER Data sheet © IDT 2012. All rights reserved. Rev. 3.4 — 10 October 2012 7 of 50 ADC1443D series Integrated Device Technology Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs Table 5. Static characteristics[1] …continued Symbol Parameter Conditions Min Typ Max Unit Ptot total power dissipation fi = 190 MHz ADC1443D125; fs = 125 Msps - 0.71 0.9 W ADC1443D160; fs = 154 Msps - 0.9 <tbd> W ADC1443D200; fs = 185 Msps - 1.05 <tbd> W Power-down mode - 10 - mW Sleep mode - 115 - mW LVPECL - ±0.8 - V LVDS - ±0.35 - V SINE differential ±0.5 ±1.5 - V LVCMOS single - VDDA - V - 1.2 - pF Clock inputs: pins CLKP and CLKM (AC-coupled; peak-to-peak) Vi(clk) CI clock input voltage input capacitance Logic inputs IIL LOW-level input current absolute value - 30 - µA IIH HIGH-level input current absolute value - 70 - µA CI input capacitance - 1.2 - pF pins SYSREFP, SYSREFN, SYNCBP, and SYNCBN Vi(cm) common-mode input voltage 0.925 1.2 1.475 V Vi(dif) differential input voltage 0.2 0.7 - V pins SCS_N, SDIO, SCLK, SCR_EN and CFG VIL LOW-level input voltage 0 - 0.3VDDO V VIH HIGH-level input voltage 0.7VDDO - VDDO V - Logic output: pins CFG and SDIO VOL LOW-level output voltage 0 0.2 V VOH HIGH-level output voltage VDDO-0.2 - VDDO V Digital outputs: pins CMLAP, CMLAN, CMLBP, and CMLBN VO(cm) common-mode output voltage default current - 1.4 - V VO(dif) differential output voltage default current; peak-to-peak - 800 - mV - ±5 - µA Analog inputs: pins INP and INM II input current RI input resistance fi = 190 MHz - <tbd> - Ω CI input capacitance fi = 190 MHz - 5 - pF VI(cm) common-mode input voltage VINP = VINM <tbd> 0.9 <tbd> V Bi input bandwidth - 1 - GHz VI(dif) differential input voltage 1 - 2 V - 0.9 - V - - 1 mA peak-to-peak; full-scale Common-mode output voltage: pins VCMA and VCMB VO(cm) common-mode output voltage IO(cm) common-mode output current Tamb = 25 °C ADC1443D_SER Data sheet © IDT 2012. All rights reserved. Rev. 3.4 — 10 October 2012 8 of 50 ADC1443D series Integrated Device Technology Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs Table 5. Symbol Static characteristics[1] …continued Parameter Conditions Min Typ Max Unit INL integral non-linearity fs = 185 Msps; fi = 4.43 MHz <tbd> 4.4 <tbd> LSB DNL differential non-linearity fs = 185 Msps; fi = 4.43 MHz; guaranteed no missing codes <tbd> −0.24 +0.48 <tbd> LSB Eoffset offset error - <tbd> - mV EG gain error - <tbd> - % MG(CTC) channel-to-channel gain matching - <tbd> - % - <tbd> - dB Accuracy full-scale Supply PSRR [1] power supply rejection ratio <tbd> mV (p-p) on VDDA Typical values measured at VDDA = VDDO = 1.8 V; Tamb = 25 °C. Minimum and maximum values are across the full temperature range Tamb = −40 °C to +85 °C at VDDA = VDDO = 1.8 V; VI(dif) = 2 V; VINP − VINM = −1 dBFS; unless otherwise specified. ADC1443D_SER Data sheet © IDT 2012. All rights reserved. Rev. 3.4 — 10 October 2012 9 of 50 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Integrated Device Technology Data sheet ADC1443D_SER 10. Dynamic characteristics 10.1 Dynamic characteristics Table 6. Dynamic characteristics[1] Symbol Parameter Conditions ADC1443D125 (fs = 125 Msps) Min α2H SFDR spurious-free dynamic range total harmonic distortion Unit Min Typ Max Min Typ Max fi = 5 MHz - -87 - - -84 - - <tbd> - dBc fi = 70 MHz - -85 - - -82 - - <tbd> - dBc fi = 140 MHz - -92 - - -85 - - <tbd> - dBc fi = 170 MHz - -83 - - -83 - - <tbd> - dBc fi = 190 MHz - -82 - - -86 - - <tbd> - dBc fi = 230 MHz - -78 - - -80 - - <tbd> - dBc fi = 5 MHz - -100 - - -88 - - <tbd> - dBc fi = 70 MHz - -97 - - -90 - - <tbd> - dBc fi = 140 MHz - -88 - - -89 - - <tbd> - dBc fi = 170 MHz - -94 - - -90 - - <tbd> - dBc fi = 190 MHz - -96 - - -87 - - <tbd> - dBc fi = 230 MHz - -95 - - -85 - - <tbd> - dBc fi = 5 MHz - 87 - - 84 - - <tbd> - dBc fi = 70 MHz - 85 - - 82 - - <tbd> - dBc fi = 140 MHz - 92 - - 85 - - <tbd> - dBc fi = 170 MHz - 83 - - 83 - - <tbd> - dBc fi = 190 MHz - 82 - - 86 - - <tbd> - dBc fi = 230 MHz - 78 - - 80 - - <tbd> - dBc 10 of 50 © IDT 2012. All rights reserved. fi = 5 MHz - -86.5 - - -82.3 - - <tbd> - dBc fi = 70 MHz - -84.2 - - -80 - - <tbd> - dBc fi = 140 MHz - -85.3 - - -82.8 - - <tbd> - dBc fi = 170 MHz - -81.8 - - -81.7 - - <tbd> - dBc fi = 190 MHz - -81.4 - - -81.9 - - <tbd> - dBc fi = 230 MHz - -77.5 - - -78.5 - - <tbd> - dBc ADC1443D series THD third harmonic level Max ADC1443D200 (fs = 185 Msps) Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs Rev. 3.4 — 10 October 2012 α3H second harmonic level Typ ADC1443D160 (fs = 154 Msps) xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Dynamic characteristics[1] …continued Symbol Parameter Conditions ADC1443D125 (fs = 125 Msps) Min IMD3 ENOB 11 of 50 © IDT 2012. All rights reserved. [1] effective number of bits channel crosstalk Unit Min Typ Max Min Typ Max fi1 = 3.5 MHz; fi2 = 6.5 MHz - 91 - - 90 - - <tbd> - dBc fi1 = 68.5 MHz; fi2 = 71.5 MHz - 90 - - 89 - - <tbd> - dBc fi1 = 138.5 MHz; fi2 = 141.5 MHz - 89 - - 88 - - <tbd> - dBc fi1 = 168.5 MHz; fi2 = 171.5 MHz - 91 - - 88 - - <tbd> - dBc fi1 = 188.5 MHz; fi2 = 191.5 MHz - 88 - - 87 - - <tbd> - dBc fi1 = 228.5 MHz; fi2 = 231.5 MHz - 87 - - 87 - - <tbd> - dBc fi = 5 MHz - 72.6 - - 71.9 - - <tbd> - dBFS fi = 70 MHz - 72.4 - - 71.7 - - <tbd> - dBFS fi = 140 MHz - 72.1 - - 71.3 - - <tbd> - dBFS fi = 170 MHz - 71.6 - - 70.8 - - <tbd> - dBFS fi = 190 MHz - 71.2 - - 70.6 - - <tbd> - dBFS fi = 230 MHz - 70.6 - - 70 - - <tbd> - dBFS fi = 5 MHz - 11.7 - - 11.4 - - <tbd> - bit fi = 70 MHz - 11.7 - - 11.4 - - <tbd> - bit fi = 140 MHz - 11.7 - - 11.3 - - <tbd> - bit fi = 170 MHz - 11.5 - - 11.3 - - <tbd> - bit fi = 190 MHz - 11.5 - - 11.2 - - <tbd> - bit fi = 230 MHz - 11.3 - - 11.1 - - <tbd> - bit fi = 140 MHz - 95 - - 95 - - <tbd> - dBc fi = 230 MHz - 90 - - 90 - - <tbd> - dBc Typical values measured at VDDA = VDDO = 1.8 V; Tamb = 25 °C. Minimum and maximum values are across the full temperature range Tamb = −40 °C to +85 °C at VDDA = VDDO = 1.8 V; VI(dif) = 2 V; VINP − VINM = −1 dBFS; unless otherwise specified. ADC1443D series αct(ch) signal-to-noise ratio Max ADC1443D200 (fs = 185 Msps) Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs Rev. 3.4 — 10 October 2012 SNR third-order intermodulation distortion Typ ADC1443D160 (fs = 154 Msps) Integrated Device Technology Data sheet ADC1443D_SER Table 6. ADC1443D series Integrated Device Technology Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs 10.2 Timing 10.2.1 Clock timing Clock and digital output timing characteristics[1] Table 7. Symbol Parameter Conditions tlat(data) data latency time twake wake-up time Min Typ Max Unit - 42 - clock cycles from Power-down mode - <tbd> - ns from Sleep mode - <tbd> - ns from high impedance - <tbd> - ns ADC1443D125 60 - 125 MHz ADC1443D160 125 - 160 MHz ADC1443D200 160 - 200 MHz Clock timing fs sampling rate fclk clock frequency 60 - 800 MHz δclk clock duty cycle 30 - 70 % td(s) sampling delay time - <tbd> - ns [1] Typical values measured at VDDA = VDDO = 1.8 V; Tamb = 25 °C. Minimum and maximum values are across the full temperature range Tamb = −40 °C to 85 °C at VDDA = VDDO = 1.8 V; VI(dif) = 2 V; VINP − VINM = −1 dBFS; unless otherwise specified. N+1 N td(s) N+2 ts CLKP CLKM tPD DATA D [A, C] D [B, D] (N - 31) D [A, C] tsu th (N - 30) D [B, D] tsu D [A, C] D [B, D] th (N - 29) D [A, C] D [B, D] (N - 28) D [A, C] D [B, D] tPD DAVP DAVM 1 / fs Fig 3. Clock and digital output timing ADC1443D_SER Data sheet © IDT 2012. All rights reserved. Rev. 3.4 — 10 October 2012 12 of 50 ADC1443D series Integrated Device Technology Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs 10.2.2 SYSREF timing Table 8. SYSREF timing Symbol Parameter tsu th Conditions Min Typ Max Unit set-up time <tbd> - - ns hold time <tbd> - - ns CLKP-CLKM 50 % th tsu 70 % SYSREF Fig 4. 70 % SYSREF timing 10.2.3 SPI timing Table 9. SPI timing characteristics Symbol Parameter tw(SCLK) SCLK pulse width [1] Conditions Min Typ Max Unit 40 - - ns tw(SCLKH) SCLK HIGH pulse width 16 - - ns tw(SCLKL) SCLK LOW pulse width 16 - - ns tsu set-up time SDIO to SCLK HIGH 5 - - ns SCS_N to SCLK HIGH 5 - - ns th hold time fclk [1] SDIO to SCLK HIGH 2 - - ns SCS_N to SCLK HIGH 2 - - ns - - 25 MHz clock frequency Typical values measured at VDDA = VDDO = 1.8 V; Tamb = 25 °C. Minimum and maximum values are across the full temperature range Tamb = −40 °C to +85 °C at VDDA = VDDO = 1.8 V tsu tsu th tw(SCLKL) th tw(SCLKH) tw(SCLK) SCS_N SCLK SDIO Fig 5. R/W W1 W0 A12 D2 D1 D0 SPI timing ADC1443D_SER Data sheet A11 © IDT 2012. All rights reserved. Rev. 3.4 — 10 October 2012 13 of 50 ADC1443D series Integrated Device Technology Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs 10.3 Typical dynamic performances1 10.3.1 Typical FFT at 122.88 Msps Fig 6. 1-tone FFT: −1 dBFS; fi = 50 MHz; fs = 122.88 Msps Fig 7. 1-tone FFT: −1 dBFS; fi = 155 MHz; fs = 122.88 Msps Fig 8. 1-tone FFT: −14 dBFS; fi = 155 MHz; fs = 122.88 Msps Fig 9. SNR as a function of full-scale amplitude: −1 dBFS; fi = 190 MHz; fs = 185 Msps 1. Typical values measured at VDDA = VDDO = 1.8 V; Tamb = 25 °C ADC1443D_SER Data sheet © IDT 2012. All rights reserved. Rev. 3.4 — 10 October 2012 14 of 50 ADC1443D series Integrated Device Technology Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs 10.3.2 Typical FFT at 153.6 Msps Fig 10. 1-tone FFT: −1 dBFS; fi = 50 MHz; fs = 153.6 Msps Fig 11. 1-tone FFT: −1 dBFS; fi = 190 MHz; fs = 153.6 Msps Fig 12. 1-tone FFT: −14 dBFS; fi = 190 MHz; fs = 153.6 Msps Fig 13. 2-tone FFT: −7 dBFS; fi1 = 188.5 MHz; fi2 = 191.5 MHz; fs = 153.6 Msps ADC1443D_SER Data sheet © IDT 2012. All rights reserved. Rev. 3.4 — 10 October 2012 15 of 50 ADC1443D series Integrated Device Technology Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs 10.3.3 Typical SNR performances Fig 14. SNR as a function of sampling frequency: −1 dBFS; fi = 170 MHz Fig 15. SNR as a function of input frequency: −1 dBFS Fig 16. SNR as a function of input amplitude: fi = 190 MHz; fs = 185 Msps; VI(dif) = 2 V Fig 17. SFDR as a function of full-scale amplitude: −1 dBFS; fi = 190 MHz; fs = 185 Msps ADC1443D_SER Data sheet © IDT 2012. All rights reserved. Rev. 3.4 — 10 October 2012 16 of 50 ADC1443D series Integrated Device Technology Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs 10.3.4 Typical SFDR performances Fig 18. SFDR as a function of sampling frequency: −1 dBFS; fi = 170 MHz Fig 19. SFDR as a function of input frequency: −1 dBFS Fig 20. SFDR as a function of input amplitude: VI(dif) = 2 V Fig 21. SFDR as a function of full-scale amplitude: −1 dBFS ADC1443D_SER Data sheet © IDT 2012. All rights reserved. Rev. 3.4 — 10 October 2012 17 of 50 ADC1443D series Integrated Device Technology Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs 10.3.5 Typical IMD3 performances Fig 22. IMD3 as a function of sampling frequency: −7 dBFS; fi1 = 168.5 MHz; fi2 = 171.5 MHz Fig 23. IMD3 as a function of input frequency: −7 dBFS; 3 MHz spacing Fig 24. IMD3 as a function of input amplitude: 3 MHz spacing; VI(dif) = 2 V Fig 25. IMD3 as a function of full-scale amplitude: −7 dBFS; 3 MHz spacing ADC1443D_SER Data sheet © IDT 2012. All rights reserved. Rev. 3.4 — 10 October 2012 18 of 50 ADC1443D series Integrated Device Technology Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs 11. Application information 11.1 Analog inputs 11.1.1 Input stage The analog input of the ADC1443D supports a differential or a single-ended input drive. Optimal performance is achieved using differential inputs with respect to the common-mode input voltage (VI(cm)) on pins INP and INM. The equivalent circuit of the sample and hold input stage, including ElectroStatic Discharge (ESD) protection and circuit and package parasitics, is shown in Figure 26. PACKAGE ESD PARASITICS SWITCH Ron = 15 Ω 4 pF INP SAMPLING INTERNAL CAPACITOR CLOCK SWITCH Ron = 15 Ω 4 pF INM SAMPLING INTERNAL CAPACITOR CLOCK Fig 26. Input sampling circuit The sample phase occurs when the internal sampling clock (derived from the clock signal on pin CLKP/CLKM) is HIGH. The voltage is then held on the sampling capacitors. When the sampling clock signal becomes LOW, the device enters the hold phase and the voltage information is transmitted to the ADC core. 11.1.2 Common-mode input voltage (VI(cm)) Set the common-mode input voltage (VI(cm)) on pins INP and INM externally to 0.9 V for optimal performance. 11.1.3 Pin VCM When the input stage is AC-coupled, pin VCM can be used to set the common-mode reference for the analog inputs, for instance, via a transformer middle point. Connect a 0.1 µF filter capacitor between pin VCM and ground to ensure a low-noise common-mode output voltage. ADC1443D_SER Data sheet © IDT 2012. All rights reserved. Rev. 3.4 — 10 October 2012 19 of 50 ADC1443D series Integrated Device Technology Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs PACKAGE ESD PARASITICS COMMON MODE REFERENCE VCM 0.1 µF ADC CORE Fig 27. Equivalent schematic of the common-mode reference circuit 11.1.4 Programmable full-scale The full-scale analog input voltage range is configurable between 1 V (p-p) and 2 V (p-p) by programming internal reference gain between 0 dB and −6 dB in 1 dB steps. The full-scale range can be set independently via bits INTREF[2:0] of the SPI local registers (see Table 10 and Table 24). Table 10. Reference gain control Default values are shown highlighted. INTREF[2:0] Level (dB) Full-scale (V (p-p)) 000 0 2 001 −1 1.78 010 −2 1.59 011 −3 1.42 100 −4 1.26 101 −5 1.12 110 −6 1 111 reserved x 11.1.5 Anti-kickback circuitry An anti-kickback circuitry (RC-filter in Figure 28) is required to counteract the effects of the charge injection generated by the sampling capacitance. The RC-filter is also used to filter noise from the signal before it reaches the sampling stage. It is recommended that the capacitor has a value that maximizes noise attenuation without degrading the settling time excessively. ADC1443D_SER Data sheet © IDT 2012. All rights reserved. Rev. 3.4 — 10 October 2012 20 of 50 ADC1443D series Integrated Device Technology Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs R INxP C R INxM Fig 28. Anti-kickback circuit The input frequency determines the component values. Select values that do not affect the input bandwidth. The value given in the following tablme are advised for 50Ω impedances system Table 11. RC coupling versus input frequency; typical values Input frequency range (MHz) R (Ω Ω) C (pF) 0 to 50 25 12 50 to 200 10 3.9 200 to 300 6.8 3 11.1.6 Transformer The input frequency determines the configuration of the transformer circuit. The configuration shown in Figure 29 is suitable for a baseband application. 100 nF analog input 25 Ω 100 nF INxP 25 Ω 12 pF 25 Ω 100 nF 100 nF 25 Ω INxM VCMx 100 nF 100 nF Fig 29. Single transformer configuration (baseband) ADC1443D_SER Data sheet © IDT 2012. All rights reserved. Rev. 3.4 — 10 October 2012 21 of 50 ADC1443D series Integrated Device Technology Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs The configuration shown in Figure 30 is recommended for high-frequency applications. In both cases, the choice of transformer is a compromise between cost and performance. 10 Ω analog input 100 nF 50 Ω INxP 50 Ω 3.9 pF 50 Ω 50 Ω 10 Ω 100 nF INxM VCMx 100 nF 100 nF Fig 30. Dual transformer configuration (high IF) 11.2 Clock input 11.2.1 Drive modes The ADC1443D series can be driven differentially (LVPECL, LVDS or SINE). A single-ended LVCMOS signal connected to either pin CLKP or pin CLKM can also drive the device (connect the complementary pin to ground using a capacitor). The LVPECL is recommended for an optimal performance. CLKP LVPECL / LVDS clock input CLKM Fig 31. LVPECL/LVDS differential clock input CLKP Sine clock input CLKM a. Differential sine clock input Sine clock input CLKP CLKM b. Single-ended sine clock input (with transformer) Fig 32. Sine clock input ADC1443D_SER Data sheet © IDT 2012. All rights reserved. Rev. 3.4 — 10 October 2012 22 of 50 ADC1443D series Integrated Device Technology Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs CLKP LVCMOS clock input CLKP CLKM LVCMOS clock input a. Rising edge LVCMOS CLKM b. Falling edge LVCMOS Fig 33. LVCMOS single-ended clock input Single-ended or differential clock inputs can be selected via bit DIFF_SE of SPI. If single-ended is enabled, the input pin (pin CLKM or pin CLKP) is selected using control bit SE_SEL (see Table 23). 11.2.2 Equivalent input circuit Figure 34 shows the equivalent circuit of the input clock buffer. The input signal must be AC-coupled and the common-mode voltage of the differential input stage is set via internal 5 kΩ resistors. PACKAGE ESD PARASITICS CLKP 5 kΩ Vcm(clk) 5 kΩ CLKM Fig 34. Equivalent input circuit 11.2.3 JESD204B harmonic clocking The ADC1443D contains an input clock divider that divides the incoming clock (clock frequency fclk) by a factor of 1 to 8. The output of this divider is the sampling clock (sampling frequency fs) (see bits CLK_DIV[1:0] in Table 23). This feature allows a higher clock frequency to be delivered to the ADC1443D and hence get a better jitter performance, leading to a better SNR result. The ADC1443D should not be fed with a clock higher than 250Msps if the clock divider is not enabled, otherwise there is a risk of metastability. ADC1443D_SER Data sheet © IDT 2012. All rights reserved. Rev. 3.4 — 10 October 2012 23 of 50 ADC1443D series Integrated Device Technology Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs Two options are allowed, either to program first the clock divider before enabling the Harmonic Clock, or to power-up the ADC1443 in « Power Down» mode by setting the CFG_SETUP[3:0] to «1111» see Table 16 , then program the clock divider to the wanted value and then «wake-up» the ADC using the SPI register IP_CFG_SETUP Table 36, with the wanted configuration. 11.2.4 JESD204B Deterministic Latency (pins SYSREFN and SYSREFP or SYNCBP and SYNCBN) In the JESD204B standard 3 subclasses have been defined. Subclass 0: No deterministic latency is required (equivalent to the JESD204A) Subclass 1: Deterministic latency is wanted and is realized through the dedicated SYSREF pins. The deterministic latency can be controlled with a single-ended or a differential SYSREF signal. When SYSREF is active (High by default), it resets the clock divider phase registers. In a multi-device application and when the clock divider factor is higher than 1, the ADC1443D synchronization aligns all sampling clock edges (see Table 8 and Figure 4). On top of this, the SYSREF pins launch an internal LMFC counter ( Local Multi-frame counter), which has a period of a multi-frame F*K (F: number of octets per frame, K: number of frames per multi-frame) see table Table 16 for examples. When a SYNC request occurs at SYNCBP/N , the ADC1443 will start the ILA sequence at an edge of the LMFC . At the receiver side, the different lanes are aligned using the ILA and the ADC1443D releases the data at an LMFC boundary. The receiver and the ADC1443D are nowboth starting an LMFC and ensuring an alignment based on this clock, which allow a deterministic latency. Subclass2 : Behaviour is similar to Subclass1, but, instead of using a dedicated SYSREF signal, the SYNCBP/N is used for both SYNC request and deterministic latency. The rising edge of the SYNCBP/N start the LMFC, while the falling edge set the SYNC request and hence start the Initial Lane Alignement according to the JEDEC JESD204B standard. 11.3 Digital outputs 11.3.1 Digital output buffers The JESD204A/JESD204B standard specifies that both the receiver and the transmitter must be provided by the same supply if they are connected in DC-coupling. ADC1443D_SER Data sheet © IDT 2012. All rights reserved. Rev. 3.4 — 10 October 2012 24 of 50 ADC1443D series Integrated Device Technology Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs VDDO VDDO 50 Ω CMLAP/CLMBP 100 Ω RECEIVER 100 Ω RECEIVER CMLAN/CLMBN - + 12 mA to 26 mA OGND Fig 35. JESD204A/JESD204B serial output - DC-coupled VDDO 50 Ω CMLAP/CLMBP 10 nF CMLAN/CLMBN 10 nF + 12 mA to 26 mA Fig 36. JESD204A/JESD204B serial output - AC-coupled 11.3.2 JESD204A/JESD204B serializer 11.3.2.1 Digital JESD204A/JESD204B formatter The block placed after the ADC1443D cores is used to implement all functionalities of the JESD204A/JESD204B standard. This ensures signal integrity and guarantees the clock and the data recovery at the receiver side. The block is highly parameterized and can be configured in various ways depending on the sampling frequency and the number of lanes used. ADC1443D_SER Data sheet © IDT 2012. All rights reserved. Rev. 3.4 — 10 October 2012 25 of 50 ADC1443D series Integrated Device Technology Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs M CONVERTERS L LANES N bits from Cr0 + CS bits for control FRAME TO OCTETS F octets TX transport layer ALIGNMENT CHARACTER GENERATOR SCRAMBLER 8-bit/ 10-bit SER LANE 0 8-bit/ 10-bit SER LANE 1 TX CONTROLLER SYNC~ samples stream to lane stream mapping N bits from CrM−1 + CS bits for control N' = N+CS S samples per frame cycle FRAME TO OCTETS F octets ALIGNMENT CHARACTER GENERATOR SCRAMBLER CF: position of control bits HD: frame boundary break Padding with Tail bits (TT) Mx(N'xS) bits Lx(F) octets L octets Fig 37. General overview of the JESD204A/JESD204B serializer ADC_MODE[1:0] PRBS DUMMY sync_request 11 14 + 1 10 LANE_POL 14 + 1 N AND CS 8 N + CS SCR 8-bit/ 10-bit SER 10 ADC_PD LANE_MODE[1:0] ADC A PLL AND DLL 14 + 1 ×1 frame CLK ×F character CLK × 10F ADC B 00 14 + 1 FSM (frame assembly, character replication; ILA, test mode) FRAME ASSEMBLY bit CLK 00 LANE_POL ADC_PD SER DUMMY PRBS 14 + 1 10 14 + 1 N AND CS N + CS 8 SCR 8-bit/ 10-bit 10 LANE_MODE[1:0] 11 ADC_MODE[1:0] Fig 38. Detailed view of the JESD204A/JESD204B serializer with debug functionalities ADC1443D_SER Data sheet © IDT 2012. All rights reserved. Rev. 3.4 — 10 October 2012 26 of 50 ADC1443D series Integrated Device Technology Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs 11.3.3 OuT-of-Range (OTR) An out-of-range signal is provided on pins OTRA and OTRAB. The latency of OTR is 31 clock cycles. The OTR response can be speeded up by enabling fast OTR using SPI local registers (bit FAST_OTR in Table 31). In this mode, the latency of OTR is reduced to only 11 clock cycles. The fast OTR detection threshold (below full-scale) can be programmed using the SPI local registers (bits FAST_OTR_DET[2:0] in Table 31). Table 12. Fast OTR register threshold FAST_OTR_DET[2:0] Detection level (dB) 000 −18.06 001 −14.54 010 −12.04 011 −8.52 100 −6.02 101 −4.08 110 −2.5 111 −1.16 11.3.4 Digital offset By default, the ADC1443D delivers an output code that corresponds to the analog input. However, it is possible to add a digital offset to the output code using the SPI local registers (bits DIG_OFFSET[5:0] in see Table 13 and Table 27). The digital offset adjustment is coded in two’s complement. Table 13. Digital offset adjustment Default values are shown highlighted. DIG_OFFSET[5:0] Digital offset adjustment (LSB) 10 0000 −32 10 0001 −31 ... ... 11 1111 −1 00 0000 0 00 0001 +1 ... ... 01 1110 +30 01 1111 +31 ADC1443D_SER Data sheet © IDT 2012. All rights reserved. Rev. 3.4 — 10 October 2012 27 of 50 ADC1443D series Integrated Device Technology Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs 11.3.5 Test patterns The ADC1443D can be configured to transmit a number of predefined test patterns using the SPI local registers (bits TEST_PAT_SEL[2:0] in Table 14 and Table 28). The selected test pattern is transmitted regardless of the analog input. Table 14. Digital test pattern selection Default values are shown highlighted. TEST_PAT_SEL[2:0] Digital test pattern 000 Off 001 Mid code 010 Min code 011 Max code 100 Toggle ‘1111..1111’/’0000..0000’ 101 Custom test pattern 110 ‘0101..0101’ 111 ‘1010..1010’ A custom test pattern can be defined using the SPI local registers (bits TEST_PAT_USER[13:6] in Table 29 and bits TEST_PAT_USER[5:0] in Table 30). 11.3.6 Output data format selection The ADC1443D output data format can be selected (offset binary, two’s complement or gray code) using the SPI local registers (bits DATA_FORMAT[1:0] in Table 26). 11.3.7 Output codes versus input voltage Table 15. Output codes VINP − VINM Offset binary Two’s complement Gray code OTR < −1 00 0000 0000 0000 10 0000 0000 0000 00 0000 0000 0000 1 −1 00 0000 0000 0000 10 0000 0000 0000 00 0000 0000 0000 0 −0.99987793 00 0000 0000 0001 10 0000 0000 0001 00 0000 0000 0001 0 −0.99975586 00 0000 0000 0010 00 0000 0000 0010 00 0000 0000 0011 0 ... ... ... ... 0 −0.00024414 01 1111 1111 1110 11 1111 1111 1110 01 0000 0000 0001 0 −0.00012207 01 1111 1111 1111 11 1111 1111 1111 01 0000 0000 0000 0 +0.00012207 10 0000 0000 0000 00 0000 0000 0000 11 0000 0000 0000 0 +0.0.00024414 10 0000 0000 0001 00 0000 0000 0001 11 0000 0000 0001 0 ... ... ... ... 0 +0.99975586 11 1111 1111 1101 01 1111 1111 1101 10 0000 0000 0011 0 +0.99987793 11 1111 1111 1110 01 1111 1111 1110 10 0000 0000 0001 0 +1 11 1111 1111 1111 01 1111 1111 1111 10 0000 0000 0000 0 > +1 11 1111 1111 1111 01 1111 1111 1111 10 0000 0000 0000 1 ADC1443D_SER Data sheet © IDT 2012. All rights reserved. Rev. 3.4 — 10 October 2012 28 of 50 ADC1443D series Integrated Device Technology Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs 11.4 Configuration pins (CFG0, CFG1, CFG2, CFG3) The configuration pins are only active as inputs at start-up. The values on those pins are read once to set up the device. Then the pins become outputs (OTRA and OTRB). SPI applies any change in the configuration. N.B: for harmonic clocking uses, the CFG pins must be set to «1111», to start the ADC in power down mode and hence avoid any issue that comes from delivering a high frequency clock before setting the clock division. Table 16. JESD204A/JESD204B configuration table CFG_SETUP[3:0] ADC A ADC B Lane 0 Lane 1 F[1] HD[1] K[1] M[1] L[1] Comment CS[1] CF[1] S[1] 0 0000 ON ON ON ON 2 0 9 2 2 (F × K) ≥ 17 1 0 1 1 0001 ON ON ON OFF 4 0 5 2 1 (F × K) ≥ 17 1 0 1 2 0010 ON ON OFF ON 4 0 5 2 1 (F × K) ≥ 17 1 0 1 3 0011 reserved 4 0100 reserved 5 0101 1 0 1 6 7 OFF 2 0 9 1 1 (F × K) ≥ 17 ON 2 0 9 1 1 (F × K) ≥ 17 1 0 1 2 0 9 1 1 (F × K) ≥ 17 1 0 1 ON 2 0 9 1 1 (F × K) ≥ 17 1 0 1 ON ON 1 1 17 1 2 (F × K) ≥ 17 1 0 1 ON ON 1 1 17 1 2 (F × K) ≥ 17 1 0 1 ON OFF ON 0110 ON OFF OFF 0111 OFF ON ON 8 1000 OFF ON OFF 9 1001 ON OFF 10 1010 OFF ON OFF ADC1443D_SER Data sheet © IDT 2012. All rights reserved. Rev. 3.4 — 10 October 2012 29 of 50 ADC1443D series Integrated Device Technology Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs Table 16. JESD204A/JESD204B configuration table …continued CFG_SETUP[3:0] ADC A ADC B Lane 0 Lane 1 F[1] HD[1] K[1] M[1] L[1] 11 1011 reserved 12 1100 reserved 13 1101 reserved 14 1110 reserved 15 1111 [1] OFF OFF OFF OFF 2 0 9 2 2 Comment CS[1] CF[1] S[1] chip power-down 1 0 1 F: Octets per frame clock cycle HD: High-density mode K: Frame per multi-frame M: Converters per device L: Lane per converter device CS: Number of control bits per conversion sample CF: Control words per frame clock cycle and link S: Number of samples transmitted per single converter per frame cycle 11.5 Serial Peripheral Interface (SPI) 11.5.1 Register description The ADC1443D serial interface is a synchronous serial communications port, which allows easy interfacing with many commonly used microprocessors. It provides access to the registers controlling the operation of the chip. The register bits are either global or local functions: • A global function operates over the full IC behavior. A local function operates on one or several previously selected channels only. If a channel is selected, the next WRITE command in the local registers applies to the selected channel. The WRITE command has no impact on channels that are not selected. This makes it possible to apply different configurations on each channel by first selecting a specific channel and then all the related settings. • Select only one channel during a READ operation of the local registers. If several channels are selected, the READ operation occurs on the channel A. Programming all registers at the same time is required: • The IC allows the storage of a set of settings for the addresses 06h to 23h, which enables the configuration of all registers simultaneously by setting bit TRANSFER to HIGH (see Table 33). This bit is autoclearing. This function can be disabled using SPI (bit TRANS_DIS in Table 33). The registers are then updated at each WRITE operation. • The transfer function does not apply to a READ operation. The SPI interface is configured as a 3-wire type: pin SDIO is the bidirectional pin, pin SCLK is the serial clock input and SCS_N is the chip select pin. A LOW level on pin SCS_N initiates each READ/WRITE operation. A minimum of 3 bytes is transmitted (two instruction bytes and at least 1 DATA byte; see Table 18). ADC1443D_SER Data sheet © IDT 2012. All rights reserved. Rev. 3.4 — 10 October 2012 30 of 50 ADC1443D series Integrated Device Technology Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs Table 17. Instruction bytes for the SPI Bit: Description 7 (MSB) 6 5 4 3 2 1 0 (LSB) R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 • Bit R/W indicates whether it is a READ (when HIGH) or a WRITE (when LOW) operation. • Bits W1 and W0 indicate the number of bytes to be transferred after both instruction bytes (see Table 18). Table 18. Number of data bytes transferred W1 W0 Number of bytes transferred 0 0 1 byte 0 1 2 bytes 1 0 3 bytes 1 1 4 or more bytes • Bits A12 to A0 indicate the address of the register being accessed. If it concerns a multiple byte transfer, this address is the first register accessed. An address counter is increased to access subsequent addresses. The steps for a data transfer are: 1. Communication starts with the first rising edge on pin SCLK after a falling edge on pin SCS_N. 2. The first phase is the transfer of the 2-byte instruction. 3. The second phase is the transfer of the data. Its length varies, but it is always a multiple of 8 bits. The MSB is always sent first (for instruction and data bytes). 4. A rising edge on pin SCS_N indicates the end on data transmission. SCS_N SCLK SDIO R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 Instruction bytes A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 Register N (data) D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Register N + 1 (data) Fig 39. SPI mode timing ADC1443D_SER Data sheet © IDT 2012. All rights reserved. Rev. 3.4 — 10 October 2012 31 of 50 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Integrated Device Technology Data sheet ADC1443D_SER 11.5.2 Register allocation map Table 19 shows an overview of all registers. Table 19. Addr. (hex) Register allocation map Register name R/W Bit definition Bit 7 Bit 6 Bit 5 Bit 4 Default Bit 3 Bit 2 Bit 1 Bit 0 ADC control registers 0000h CHIP_RST RW 0001h CHIP_ID R 0005h CHIP_RST R/W 0006h OP_MODE SW_RST - - SW_RST[7:0] 0000 0000 CHIP_ID[7:0][1] 0100 0011 - - - - - OP_MODE[1:0][3] - 0000 0000 R/W - - - - - 0000 0000 0007h CLK_CFG R/W - - - SE_SEL DIFF_SE CLK_DIV[2:0] 0000 0000 0008h INTERNAL_ REF R/W - - - - - INTREF[2:0] 0000 0000 0009h CHANNEL_ SEL R/W - - - - - - 0011h R/W - - - - - DATA_ SWAP [2] 0013h DIG_OFFSET R/W 0014h TEST_CFG_1 R/W 0015h TEST_CFG_2 R/W R/W 0017h OTR_CFG R/W 0043h DCS_CTRL R/W 00FFh TRANS_CFG R/W - - - - - - TEST_PAT_SEL[2:0] - - SYSREF_SE TRANS_ DIS TRANSFER - - RESERVED FAST_ OTR - - - FAST_OTR_DET[2:0] - - 0000 0000 0000 0000 TEST_PAT_USER[5:0] - 0000 0000 0000 0000 TEST_PAT_USER[13:6] - 0000 1111 0001 0100 DIV_RESET DIV_RESE _POL T_SEL - - 0000 0000 - 11000100 0000 0000 JESD204A/JESD204B control 32 of 50 © IDT 2012. All rights reserved. 0801h IP_STATUS R RXSYNC_ ERR_FLG RESERVED[5:0] 0802h IP_RST R/W SW_ RST - - - 0803h IP_CFG_ SETUP R/W - - - - ASSEMBLER_ SW_RST PLL_LOCK 0000 0000 CFG_STP[3:0] - - 0000 0000 0000 **** ADC1443D series 0016h TEST_CFG_3 DATA_FORMAT[1:0] DIG_OFFSET[5:0] - ADC_A Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs Rev. 3.4 — 10 October 2012 OUTPUT_ CFG ADC_B xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Addr. (hex) Register allocation map …continued Register name R/W Bit definition Bit 6 Bit 5 Bit 4 Bit 3 RESERVED TRISTATE_ CFG_PAD SYNC_ POL SYNC_SE EN_ RXSYNC_ERR R/W 0806h IP_CTRL2 R/W RESERVED[5:0] 080Bh R/W RESERVED[5:0] IP_PRBS_ CTRL Default Bit 7 0805h IP_CTRL1 Bit 2 Bit 1 Bit 0 RESERVED[2:0] SWP_ ‘LANE_1_2 0000 0000 SWP_ ADC_0_1 PRBS_TYPE[1:0] 0000 **** 0000 0000 LMFC_perio LMFC_reset_ dic_rst en - - - - - 0000 0000 0811h JESD204B_C TRL2 R/W DCS_periodi DCS_reset_e c_rst n - - - - - 0000 0000 0812h JESD204B_C TRL3 R/W - - sync_at_lmfc_e n sync_captur e_path - 0000 0000 0816h IP_DEBUG_ OUT1 R/W 0817h IP_DEBUG_ OUT2 R/W PAT_OUT[7:0] 1010 1010 0818h IP_DEBUG_ IN1 R/W PAT_IN[15:8] 1010 1010 0819h IP_DEBUG_ IN2 R/W PAT_IN[7:0] 0000 0010 081Bh IP_ TESTMODE R/W 081Ch IP_EXPERT_ DOOR R/W 081Eh SYSREF_CFG R/W - - RESERVED LOOP_ ALIGN - - DIS_REPL_ CHAR - BYP_ ALIGN - PAT_OUT[9:8] RESERVED[3:0] 0*00 0000 KEY[7:0] - - - SCR[0] - - 0000 0010 0000 0000 SYSREF_E SYSREF_S N E RESERVED[5:0] 0000 0000 33 of 50 © IDT 2012. All rights reserved. 0822h CFG_3_ SCR_L R/W L[0] 0000 0000(?) 086Bh OUTBUF00_ SWING R/W RESERVED[4:0] SWING[3:0] 0000 01** 086Ch OUTBUF03_ SWING R/W SWING_SPARE[2:0] SWING[3:0] 0000 01** ADC1443D series R/W Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs Rev. 3.4 — 10 October 2012 0810h JESD204B_C TRL1 - Integrated Device Technology Data sheet ADC1443D_SER Table 19. xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Addr. (hex) Register allocation map …continued Register name R/W Bit definition Bit 7 Bit 6 Bit 5 Bit 4 Default Bit 3 Bit 2 Bit 1 Bit 0 0871h LANE00_0_ CTRL R/W RESERVED[2:0] LANE_MODE[1:0] LANE_POL RESERVED LANE_ PD 0000 000* 0872h LANE01_0_ CTRL R/W RESERVED[2:0] LANE_MODE[1:0] LANE_POL RESERVED LANE_ PD 0000 000* 0890h ADC00_0_ CTRL R/W - - ADC_MODE[1:0] - - - ADC_ PD 0000 0000 0891h ADC01_0_ CTRL R/W - - ADC_MODE[1:0] - - - ADC_ PD 0000 0000 The READ-ONLY and RESERVED registers. [2] The registers influenced by the TRANSFER function. [3] The LOCAL registers. Rev. 3.4 — 10 October 2012 ADC1443D series 34 of 50 © IDT 2012. All rights reserved. Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs [1] Integrated Device Technology Data sheet ADC1443D_SER Table 19. ADC1443D series Integrated Device Technology Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs 11.5.3 Detailed register description The tables in this section contain detailed descriptions of the registers. 11.5.3.1 ADC control registers Table 20. CHIP_RESET register (address 0000h) bit description Default settings are shown highlighted. Bit Symbol Access Value Description 7 to 0 SW_RST R/W - resets global and local registers for any value “1” written at any bit (autoclear). Table 21. CHIP_RESET register (address 0005h) bit description Default settings are shown highlighted. Bit Symbol Access 7 SW_RST R/W Value resets global and local registers 0 1 6 to 0 - - Description - no reset performs a reset to the default values (autoclear) not used Table 22. OP_MODE register (address 0006h) bit description Default settings are shown highlighted. Bit Symbol Access Value Description 7 to 2 - - - not used 1 to 0 OP_MODE[1:0][1] R/W [1] operating mode for the selected channel 00 normal (power-up) 01 power-down 10 sleep 11 not used Local register. Table 23. CLK_CFG register (address 0007h) bit description Default settings are shown highlighted. Bit Symbol 7 to 5 4 3 Access Value - - - SE_SEL R/W DIFF_SE Description not used single-ended clock input pin selection 0 CLKP 1 CLKM R/W differential/single-ended clock input selection 0 fully differential 1 single-ended ADC1443D_SER Data sheet © IDT 2012. All rights reserved. Rev. 3.4 — 10 October 2012 35 of 50 ADC1443D series Integrated Device Technology Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs Table 23. CLK_CFG register (address 0007h) bit description …continued Default settings are shown highlighted. Bit Symbol Access 2 to 0 CLK_DIV[1:0] R/W Value Description clock divider selection 000 divide by 1 001 divide by 2 010 divide by 3 011 divide by 4 100 divide by 5 101 divide by 6 110 divide by 7 111 divide by 8 Table 24. INTERNAL_REF register (address 0008h) bit description Default settings are shown highlighted. Bit Symbol Access Value Description 7 to 3 - - - not used 2 to 0 INTREF[2:0][1] R/W - see Table 10 [1] Local register Table 25. CHANNEL_SEL register (address 0009h) bit description Default settings are shown highlighted. Bit Symbol Access Value Description 7 to 2 - - - not used 1 ADC_B R/W 0 ADC_A channel B selection for next SPI operation in local registers 0 not selected 1 selected R/W channel A selection for next SPI operation in local registers 0 not selected 1 selected Table 26. OUTPUT_CFG register (address 0011h) bit description Default settings are shown highlighted. Bit Symbol Access Value Description 7 to 3 - - - not used 2 DATA_SWAP[1] R/W output data bits swapped 0 no swapping 1 MSBs swapped with LSBs ADC1443D_SER Data sheet © IDT 2012. All rights reserved. Rev. 3.4 — 10 October 2012 36 of 50 ADC1443D series Integrated Device Technology Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs Table 26. OUTPUT_CFG register (address 0011h) bit description …continued Default settings are shown highlighted. Bit Symbol Access 1 to 0 DATA_FORMAT[1:0:][1] R/W [1] Value Description output data format 00 offset binary 01 two’s complement 10 gray code 11 offset binary Local register Table 27. DIG_OFFSET register (address 0013h) bit description Default settings are shown highlighted. Bit Symbol Access Value Description 7 to 2 DIG_OFFSET[7:0][1] R/W - see Table 13 1 to 0 - - - not used [1] Local register Table 28. TEST_CFG_1 register (address 0014h) bit description Default settings are shown highlighted. Bit Symbol 7 to 3 - - - not used 2 to 0 TEST_PAT_SEL[2:0][1] R/W - see Table 14 [1] Access Value Description Local register Table 29. TEST_CFG_2 register (address 0015h) bit description Default settings are shown highlighted. Bit Symbol Access Value Description 7 to 0 TEST_PAT_USER[13:6][1] R/W - custom digital test pattern (bits 13 to 6) [1] Local register Table 30. TEST_CFG_3 register (address 0016h) bit description Default settings are shown highlighted. Bit Symbol Access Value Description 7 to 2 TEST_PAT_USER[5:0][1] R/W - custom digital test pattern (bits 5 to 0) 1 to 0 - - - not used [1] Local register Table 31. OTR_CFG register (address 0017h) bit description Default settings are shown highlighted. Bit Symbol Access Value Description 7 to 5 - - - not used 4 RESERVED R/W 1 reserved ADC1443D_SER Data sheet © IDT 2012. All rights reserved. Rev. 3.4 — 10 October 2012 37 of 50 ADC1443D series Integrated Device Technology Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs Table 31. OTR_CFG register (address 0017h) bit description …continued Default settings are shown highlighted. Bit Symbol Access 3 FAST_OTR[1] R/W 2 to 0 [1] FAST_OTR_DET[2:0][1] R/W Value Description Selection OTR full-scale/ fast OTR 0 OTR full-scale 1 fast OTR - Local register Table 32. DCS_CTRL register (address 0043h) bit description Default settings are shown highlighted. Bit Symbol Access Value Description 7 - - 1 not used, set allways to 1 6 - - 1 not used, set allways to 1 5 to 2 - - - not used 1 DIV_RESET_POL R/W 0 [1] DIV_RESET_SEL Polarity of the DCS reset 1 Rising edge ( Subclass 1 ) 0 falling edge ( Subclass 2) R/W DCS reset selection 0 SYNCBP/N is used (Subclass2) 1 SYSREFP/N is used (Subclass1) Local register Table 33. TRANS_CFG register (address 00FFh) bit description Default settings are shown highlighted. Bit Symbol Access 7 TRANS_DIS R/W Value disable transfer function 0 1 6 5 to 0 TRANSFER - R/W - Description transfer function active registers updated on a WRITE command updates the registers with the written settings 0 settings are stored 1 registers updated (autoclear) - not used ADC1443D_SER Data sheet © IDT 2012. All rights reserved. Rev. 3.4 — 10 October 2012 38 of 50 ADC1443D series Integrated Device Technology Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs 11.5.3.2 JESD204A/JESD204B control registers Table 34. IP_STATUS register (address 0801h) bit description Default settings are shown highlighted. Bit Symbol Access Value Description 7 RXSYNC_ERR_FLG R 0 RX synchronization error 0: no error 1: synchronization error has occurred 6 to 1 RESERVED[5:0] R 000000 reserved 0 PLL_LOCK R 0 JEDEC PLL lock 0: unlocked 1: locked Table 35. IP_RESET register (address 0802h) bit description Default settings are shown highlighted. Bit Symbol Access Value Description 7 SW_RST R/W 0 software reset: All JESD subblocks and registers are reset 6 to 4 - - 000 not used 3 ASSEMBLER_SW_RST R/W 0 Only the RXSYNC_ERR_FLG register bit and the frame assembler subblock are reset 2 to 0 - - 000 not used Table 36. IP_CFG_SETUP register (address 0803h) bit description Default settings are shown highlighted. Bit Symbol Access Value Description 7 to 4 - - 0000 not used 3 to 0 CFG_SETUP[3:0] R/W **** see Table 38 Table 37. Serial frequency computation information CFG_SETUP ADC sampling frequency (Mbps) Lane 0 serial frequency (Gbps) Lane 1 serial frequency (Gbps) 0000 FS 20 × FS 20 × FS 0001 FS 40 × FS 0 0010 FS 0 40 × FS 0011 reserved 0100 reserved 0101 FS 20 × FS 0 0110 FS 0 20 × FS 0111 FS 20 × FS 0 1000 FS 0 20 × FS 1001 FS 10 × FS 10 × FS 1010 FS 10 × FS 10 × FS 1011 reserved 1100 reserved ADC1443D_SER Data sheet © IDT 2012. All rights reserved. Rev. 3.4 — 10 October 2012 39 of 50 ADC1443D series Integrated Device Technology Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs Table 37. Serial frequency computation information CFG_SETUP ADC sampling frequency (Mbps) Lane 0 serial frequency (Gbps) 1101 reserved 1110 reserved 1111 Table 38. Lane 1 serial frequency (Gbps) FS 0 0 JESD204A/JESD204B configuration table CFG_SETUP[3:0] ADC[0] ADC[1] Lane 0 Lane 1 F[1] HD[1] K[1] M[1] L[1] Comment CS[1] CF[1] S[1] 0 0000 ON ON ON ON 2 0 9 2 2 (F × K) ≥ 17 1 0 1 1 0001 ON ON ON OFF 4 0 5 2 1 (F × K) ≥ 17 1 0 1 ON ON OFF ON 4 0 5 2 1 (F × K) ≥ 17 1 0 1 1 1 (F × K) ≥ 17 0 1 2 0010 3 0011 reserved 4 0100 reserved 5 0101 ON OFF ON OFF 2 0 9 1 6 0110 ON OFF OFF ON 2 0 9 1 1 (F × K) ≥ 17 1 0 1 7 0111 OFF ON ON OFF 2 0 9 1 1 (F × K) ≥ 17 1 0 1 8 1000 OFF ON OFF ON 2 0 9 1 1 (F × K) ≥ 17 1 0 1 9 1001 ON OFF ON ON 1 1 17 1 2 (F × K) ≥ 17 1 0 1 10 1010 OFF ON ON ON 1 1 17 1 2 (F × K) ≥ 17 1 0 1 11 1011 reserved 12 1100 reserved 13 1101 reserved 14 1110 15 1111 2 2 chip power-down 1 0 1 [1] reserved OFF OFF OFF OFF 2 0 9 F: Octets per frame clock cycle HD: High-density mode K: Frame per multi-frame M: Converters per device L: Lane per converter device CS: Number of control bits per conversion sample CF: Control words per frame clock cycle and link S: Number of samples transmitted per single converter per frame cycle Table 39. IP_CTRL1 register (address 0805h) bit description Default settings are shown highlighted. Bit Symbol Access Value Description 7 RESERVED R/W 0 reserved 6 TRISTATE_CFG_PAD R/W (1 > 0) TriState configuration pad 0: CFG Pads in Output mode (debug feature) 1: CFG Pads in Input mode; operating at power-up (see Table 38) ADC1443D_SER Data sheet © IDT 2012. All rights reserved. Rev. 3.4 — 10 October 2012 40 of 50 ADC1443D series Integrated Device Technology Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs Table 39. IP_CTRL1 register (address 0805h) bit description …continued Default settings are shown highlighted. Bit Symbol Access Value Description 5 SYNC_POL R/W 0 synchronization polarity 0: default synchronization polarity used (active LOW) 1: polarity inversion (active HIGH) 4 SYNC_SE R/W 0 single-ended synchronization 0: differential synchronization 1: single-ended synchronization 3 EN_RXSYNC_ERR R/W 1 error reporting using synchronization interface 0: disabled 1: enabled 2 to 0 RESERVED R/W 001 reserved Table 40. IP_CTRL2 register (address 0806h) bit description Default settings are shown highlighted. Bit Symbol Access Value Description 7 to 2 RESERVED R/W 0000** reserved 1 SWP_LANE_1_2 R/W * swap lanes: if set to logic 1 the lanes are swapped symmetrically (L0 ↔ L1, L1 ↔ L0) 0 SWP_ADC_0_1 R/W * if set to logic 1, ADC 0 and ADC1 are swapped at the input of the frame assembler Table 41. IP_PRBS_CTRL register (address 080Bh) bit description Default settings are shown highlighted. Bit Symbol Access Value Description 7 to 2 RESERVED - 000000 reserved 1 to 0 PRBS_TYPE[1:0] R/W 00 defines the type of Pseudo-Random Binary Sequence (PRBS) generator to be used 00; PRBS-7; 1 + x6 + x1 10; PRBS-23; 1 + x18 + x23 Table 42. JESD204B_CTRL1 register (address 0810h) bit description Default settings are shown highlighted. Bit Symbol Access Value Description 7 LMFC_periodic_rst R/W 0 defines the LMFC modes 0;LMFC reset is done once 1; LMFC reset is donce at each SYSREF or SYNC 6 LMFC_periodic_rst R/W 0 enables the LMFC reset 0;LMFC reset is disabled 1; LMFC reset is enabled 5 to 0 - - 00000 reserved ADC1443D_SER Data sheet © IDT 2012. All rights reserved. Rev. 3.4 — 10 October 2012 41 of 50 ADC1443D series Integrated Device Technology Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs Table 43. JESD204B_CTRL2register (address 0811h) bit description Default settings are shown highlighted. Bit Symbol Access Value Description 7 DCS_periodic_rst R/W 0 defines the LMFC modes 0;DCS reset is done once 1; DCS reset is donce at each SYSREF or SYNC 6 DCS_periodic_rst R/W 0 enables the LMFC reset 0;DCS reset is disabled 1; DCS reset is enabled 5 to 0 - - 00000 reserved Table 44. JESD204B_CTRL3 register (address 0812h) bit description Default settings are shown highlighted. Bit Symbol Access Value Description 7 to 4 - - 0000 reserved 3 sync_at_lmfc_en R/W 0 define the relation between the SYNC and the LMFC 0;SYNC is fetched directely (JESD204A mode) 1; SYNC is taken at next LMFC boundary ( Subclass 1 and Subclass 2) 2 - - 0 reserved 1 sync_capture_path R/W 0 SYNC mode 0;JESD204A mode 1; Subclass 1 and Subclass 2 0 - - 0 reserved Table 45. IP_DEBUG_OUT1 register (address 0816h) bit description Default settings are shown highlighted. Bit Symbol Access Value Description 7 to 2 - - 000000 not used 1 to 0 PATTERN_OUT[9:8] R/W 10 2 most significant bits of output stage debug word (inserted just before serializer) Table 46. IP_DEBUG_OUT2 register (address 0817h) bit description Default settings are shown highlighted. Bit Symbol Access Value Description 7 to 0 PATTERN_OUT[7:0] R/W 1010 1010 8 least significant bits of output stage debug word (inserted just before serializer) Table 47. IP_DEBUG_IN1 register (address 0818h) bit description Default settings are shown highlighted. Bit Symbol Access Value Description 7 to 0 PATTERN_IN[15:8] R/W 1010 1010 8 most significant bits of input stage debug word (inserted in place of ADC data) ADC1443D_SER Data sheet © IDT 2012. All rights reserved. Rev. 3.4 — 10 October 2012 42 of 50 ADC1443D series Integrated Device Technology Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs Table 48. IP_DEBUG_IN2 register (address 0819h) bit description Default settings are shown highlighted. Bit Symbol Access Value Description 7 to 0 PATTERN_IN[7:0] R/W 0000 0010 8 least significant bits of input stage debug word (inserted in place of ADC data) Table 49. IP_TESTMODE register (address 081Bh) bit description Default settings are shown highlighted. Bit Symbol Access Value Description 7 RESERVED R/W 0 reserved ILA sequence is repeated infinitely 6 LOOP_ALIGN R/W *[1] 5 DIS_REPL_CHAR R/W 0 no replacement character is placed in the data flow 4 BYP_ALIGN R/W 0 ILA is bypassed 3 to 0 RESERVED R/W 0000 reserved [1] ILA = Initial Lane Alignment Sequence (see JESD204 JEDEC standard). Table 50. IP_EXPERT_DOOR register (address 081Ch) bit description Default settings are shown highlighted. Bit Symbol Access Value Description 7 KEY[7:0] R/W 0000 0000 8-bit key to enable Write access for JESD204 control register Table 51. SYSREF_CFG register (address 081Eh) bit description Default settings are shown highlighted. Bit Symbol Access Value Description 7 to 4 RESERVED R/W 0000 reserved 3 SYSREF_EN R/W 0 1 : Enable SYSREFP/N path 2 SYSREF_SE 1 to 0 RESERVED 0 : Disable SYSREFP/N path 1 : SYSREFP is used as single ended SYSREF input 0 : SYSREFP/SYREFN are used as differential pair R/W 00 reserved Table 52. CFG_3_SCR_L register (address 0822h) bit description Default settings are shown highlighted. Bit Symbol Access Value Description 7 SCR[0] R/W 0 scrambling enabler 6 to 1 RESERVED R/W 000000 reserved 0 L[0] R/W 0 lanes number minus 1 (for example, for two lanes L = 1) 0x4A must be written in the IP_EXPERT_DOOR registers to obtain write access to this register ADC1443D_SER Data sheet © IDT 2012. All rights reserved. Rev. 3.4 — 10 October 2012 43 of 50 ADC1443D series Integrated Device Technology Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs Table 53. IP_OUTBUF00_SWING register (address 086Bh) bit description Default settings are shown highlighted. Bit Symbol Access Value Description 7 to 3 RESERVED[4:0] R/W 00000 reserved 2 to 0 SWING[2:0] R/W Configurable lane 0 output current 000 12 mA; ±300 mV (p-p) 001 14 mA; ±350 mV (p-p) 010 16 mA; ±400 mV (p-p) 011 18 mA; ±450 mV (p-p) 100 20 mA; ±500 mV (p-p) 101 22 mA; ±550 mV (p-p) 110 24 mA; ±600 mV (p-p) 111 26 mA; ±650 mV (p-p) Table 54. IP_OUTBUF01_SWING register (address 086Ch) bit description Default settings are shown highlighted. Bit Symbol Access Value Description 7 to 3 RESERVED[4:0] R/W 00000 reserved 2 to 0 SWING[2:0] R/W Configurable lane 1 output current 000 12 mA; ±300 mV (p-p) 001 14 mA; ±350 mV (p-p) 010 16 mA; ±400 mV (p-p) 011 18 mA; ±450 mV (p-p) 100 20 mA; ±500 mV (p-p) 101 22 mA; ±550 mV (p-p) 110 24 mA; ±600 mV (p-p) 111 26 mA; ±650 mV (p-p) Table 55. IP_LANE00_0_CTRL register (address 0871h) bit description Default settings are shown highlighted. Bit Symbol Access Value Description 7 to 5 RESERVED[2:0] R/W 000 reserved 4 to 3 LANE_MODE[1:0] R/W 00 debug option directly before serializer 0: normal mode, ADC path 1: toggle (0/1 toggle sent over the lanes) 2: A constant (value in IP_DEBUG_OUT) is sent over the lanes 3: PRBS polynom is sent over the lane 2 LANE_POL R/W 0 if set to logic 1, lane P/N polarity is inverted 1 RESERVED R/W 0 reserved 0 LANE_PD R/W * if set to logic 1, lane enters power-down ADC1443D_SER Data sheet © IDT 2012. All rights reserved. Rev. 3.4 — 10 October 2012 44 of 50 ADC1443D series Integrated Device Technology Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs Table 56. IP_LANE01_0_CTRL register (address 0872h) bit description Default settings are shown highlighted. Bit Symbol Access Value Description 7 to 5 RESERVED[2:0] R/W 000 reserved 4 to 3 LANE_MODE[1:0] R/W 00 debug option directly before serializer 0: normal mode, ADC path 1: toggle (0/1 toggle sent over the lanes) 2: A constant (value in IP_DEBUG_OUT) is sent over the lanes 3: PRBS polynom is sent over the lane 2 LANE_POL R/W 0 if set to logic 1, lane P/N polarity is inverted 1 RESERVED R/W 0 reserved 0 LANE_PD R/W * if set to logic 1, lane enters power-down Table 57. IP_ADC00_0_CTRL register (address 0890h) bit description Default settings are shown highlighted. Bit Symbol Access Value Description 7 to 6 RESERVED R/W 00 reserved 5 to 4 ADC_MODE[1:0] R/W 00 debug option to replace ADC core 0, 1: normal mode, ADC path 2: a constant (value in IP_Debug_in) is sent instead of ADC conversion output 3: PRBS polynom is sent instead of ADC 3 to 1 RESERVED R/W 000 reserved 0 ADC_PD R/W 0 if set to logic 1, ADC enters power-down Table 58. IP_ADC01_0_CTRL register (address 0891h) bit description Default settings are shown highlighted. Bit Symbol Access Value Description 7 to 6 RESERVED R/W 00 reserved 5 to 4 ADC_MODE[1:0] R/W 00 debug option to replace ADC core 0, 1: normal mode, ADC path 2: a constant (value in IP_Debug_in) is sent instead of ADC conversion output 3: PRBS polynom is sent instead of ADC 3 to 1 RESERVED R/W 000 reserved 0 ADC_PD R/W 0 if set to logic 1, ADC enters power-down ADC1443D_SER Data sheet © IDT 2012. All rights reserved. Rev. 3.4 — 10 October 2012 45 of 50 ADC1443D series Integrated Device Technology Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs 12. Package outline HLQFN56R: plastic thermal enhanced low profile quad flat package; no leads; 56 terminals; resin based; body 8 x 8 x 1.35 mm B D SOT935-2 A terminal 1 index area E A detail X e1 C e b 1/2 e L1 L 15 28 14 C A B C v w y1 C y 29 e e2 Eh 1 terminal 1 index area 42 56 43 Dh X 0 10 mm scale Dimensions Unit A b max 1.40 0.30 nom 1.35 0.25 min 1.25 0.20 mm D Dh E Eh e e1 e2 8.1 8.0 7.9 5.85 5.80 5.75 8.1 8.0 7.9 6.45 6.40 6.35 0.5 6.5 6.5 L L1 0.55 0.10 0.50 0.05 0.45 0.00 v 0.1 w y 0.05 0.05 y1 0.1 sot935-2_po Outline version References IEC JEDEC JEITA European projection Issue date 11-08-16 11-08-18 SOT935-2 Fig 40. Package outline SOT935-2 (HLQFN56) ADC1443D_SER Data sheet © IDT 2012. All rights reserved. Rev. 3.4 — 10 October 2012 46 of 50 ADC1443D series Integrated Device Technology Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs 13. Abbreviations Table 59. Abbreviations Acronym Description ADC Analog-to-Digital Converter CDMA Code Division Multiple Access DAV DAta Valid ESD ElectroStatic Discharge FFT Fast Fourier Transform GSM Global System for Mobile communications ILA Initial Lane Alignment IMD3 third order InterMoDulation product LSB Least Significant Bit LTE Long-Term Evolution LVDS DDR Low Voltage Differential Signaling Double Data Rate LVPECL Low-Voltage Positive Emitter-Coupled Logic MIMO Multiple Input Multiple Output MSB Most Significant Bit OTR OuT-of-Range SFDR Spurious-Free Dynamic Range SPI Serial Peripheral Interface SNR Signal-to-Noise Ratio TD-SCDMA Time Division-Synchronous Code Division Multiple Access WCDMA Wideband Code Division Multiple Access WiMAX Worldwide interoperability for Microwave Access ADC1443D_SER Data sheet © IDT 2012. All rights reserved. Rev. 3.4 — 10 October 2012 47 of 50 ADC1443D series Integrated Device Technology Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs 14. Revision history Table 60. Revision history Document ID Release date Data sheet status Change notice Supersedes ADC1443D_SER v.3.4 20121010 Data sheet - ADC1443D_SER v.3.3 ADC1443D_SER v.3.3 20120926 Objective data sheet - ADC1443D_SER v.3.2 ADC1443D_SER v.3.2 20120918 Objective data sheet - ADC1443D_SER v.3.1 ADC1443D_SER v.3.1 20120911 Objective data sheet - ADC1443D_SER v.3.0 ADC1443D_SER v.3.0 <tbd> Objective data sheet - ADC1443D_SER v.2.0 Modifications: • Text and drawings updated throughout entire data sheet. ADC1443D_SER v.2.0 20120630 Objective data sheet - ADC1443D_SER v.1.1 ADC1443_SER v.1.1 20110928 Objective data sheet - ADC1443D_SER v.1 ADC1443D_SER v.1 20110901 Objective data sheet - - Contact information 6024 Silver Creek Valley Road San Jose, California 95138 ADC1443D_SER Data sheet © IDT 2012. All rights reserved. Rev. 3.4 — 10 October 2012 48 of 50 ADC1443D series Integrated Device Technology Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs 15. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 10.1 10.2 10.2.1 10.2.2 10.2.3 10.3 10.3.1 10.3.2 10.3.3 10.3.4 10.3.5 11 11.1 11.1.1 11.1.2 11.1.3 11.1.4 11.1.5 11.1.6 11.2 11.2.1 11.2.2 11.2.3 11.2.4 11.3 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7 Thermal characteristics . . . . . . . . . . . . . . . . . . 7 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7 Dynamic characteristics . . . . . . . . . . . . . . . . . 10 Dynamic characteristics . . . . . . . . . . . . . . . . . 10 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . 12 SYSREF timing. . . . . . . . . . . . . . . . . . . . . . . . 13 SPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Typical dynamic performances . . . . . . . . . . . . 14 Typical FFT at 122.88 Msps . . . . . . . . . . . . . . 14 Typical FFT at 153.6 Msps . . . . . . . . . . . . . . . 15 Typical SNR performances . . . . . . . . . . . . . . . 16 Typical SFDR performances. . . . . . . . . . . . . . 17 Typical IMD3 performances . . . . . . . . . . . . . . 18 Application information. . . . . . . . . . . . . . . . . . 19 Analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . 19 Input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Common-mode input voltage (VI(cm)) . . . . . . . 19 Pin VCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Programmable full-scale . . . . . . . . . . . . . . . . . 20 Anti-kickback circuitry . . . . . . . . . . . . . . . . . . . 20 Transformer . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Drive modes . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Equivalent input circuit . . . . . . . . . . . . . . . . . . 23 JESD204B harmonic clocking . . . . . . . . . . . . 23 JESD204B Deterministic Latency (pins SYSREFN and SYSREFP or SYNCBP and SYNCBN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Digital outputs . . . . . . . . . . . . . . . . . . . . . . . . . 24 11.3.1 11.3.2 11.3.2.1 11.3.3 11.3.4 11.3.5 11.3.6 11.3.7 11.4 Digital output buffers . . . . . . . . . . . . . . . . . . . 24 JESD204A/JESD204B serializer . . . . . . . . . . 25 Digital JESD204A/JESD204B formatter . . . . 25 OuT-of-Range (OTR) . . . . . . . . . . . . . . . . . . . 27 Digital offset . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Test patterns . . . . . . . . . . . . . . . . . . . . . . . . . 28 Output data format selection . . . . . . . . . . . . . 28 Output codes versus input voltage. . . . . . . . . 28 Configuration pins (CFG0, CFG1, CFG2, CFG3) 29 11.5 Serial Peripheral Interface (SPI) . . . . . . . . . . 30 11.5.1 Register description . . . . . . . . . . . . . . . . . . . . 30 11.5.2 Register allocation map . . . . . . . . . . . . . . . . . 32 11.5.3 Detailed register description . . . . . . . . . . . . . 35 11.5.3.1 ADC control registers . . . . . . . . . . . . . . . . . . . 35 11.5.3.2 JESD204A/JESD204B control registers . . . . 39 12 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 46 13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 47 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . 48 15 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Disclaimer Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright, 2012. All rights reserved. ADC1443D series Integrated Device Technology Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs ADC1443D_SER Data sheet © IDT 2012. All rights reserved. Rev. 3.4 — 10 October 2012 50 of 50