FAN6520B Single Synchronous Buck PWM Controller Features Description ■ Accepts 1.5V to 5V for VIN The FAN6520B makes simple work out of implementing a complete control and protection scheme for a DC-DC stepdown converter. ■ Output Range 0.8V to VIN ■ ■ ■ ■ – 0.8V Internal Reference – ±1.5% Over Line Voltage and Temperature Drives N-Channel MOSFETs Simple Single-Loop Control Design – Voltage-Mode PWM Control Fast Transient Response – High-Bandwidth Error Amplifier – Full 0% to 100% Duty Cycle Small Converter Size – 300kHz Fixed Frequency Oscillator – Internal Soft-Start – 8-Lead SOIC Designed to drive N-channel MOSFETs in a synchronous buck topology, the FAN6520B integrates the control, output adjustment, and monitoring functions into a single 8-lead package. The FAN6520B is easy to use, employs a single feedback loop, and voltage-mode control with fast transient response. The output voltage can be precisely regulated to as low as 0.8V, with a maximum tolerance of ±1.5% over temperature and line voltage variations. A fixed frequency oscillator reduces design complexity, while balancing typical application cost. The error amplifier features a 15MHz gain-bandwidth product and an 8V/µs slew rate which enables high converter bandwidth for fast transient performance. The resulting PWM duty cycles range from 0% to 100%. Applications ■ Power Supplies for PC Subsystems and Peripherals The FAN6520B is rated for operation from 0° to +70°C with the FAN6520BI rated from –40° to +85°C. ■ MCH, GTL, and AGP Supplies ■ Cable Modems, Set Top Boxes, and DSL Modems ■ DSP, Memory ■ Low-Voltage Distributed Power Supplies ■ ACPI Power Control ■ 5V Input DC-DC Regulator Ordering Information Part Number Temperature Range Package Packing 0°C to 70°C SOIC-8 Rails FAN6520BMX 0°C to 70°C SOIC-8 Tape and Reel FAN6520BIM –40°C to 85°C SOIC-8 Rails FAN6520BIMX –40°C to 85°C SOIC-8 Tape and Reel FAN6520BM ©2006 Fairchild Semiconductor Corporation FAN6520B Rev. 1.0.3 1 www.fairchildsemi.com FAN6520B Single Synchronous Buck PWM Controller February 2006 BOOT 1 HDRV 2 GND 3 LDRV 4 FAN6520B 8 SW 7 COMP/SD 6 FB 5 VCC FAN6520BM 8-pin SOIC Package Pin Definitions Pin # Pin Name Pin Function Description 1 BOOT Bootstrap Supply Input. Provides a boosted voltage to the high-side MOSFET driver. Connect to bootstrap capacitor and diode as shown in Figure 1. 2 HDRV High Side Gate Drive Output. Connect to the gate of the high-side power MOSFET(s). This pin is also monitored by the adaptive shoot-through protection circuitry to determine when the upper MOSFET has turned off. 3 GND Ground. The signal and power ground for the IC. Tie this pin to the ground island/plane through the lowest impedance connection available. Connect directly to source of low-side MOSFET(s). 4 LDRV Low Side Gate Drive Output. Connect to the gate of the low-side power MOSFET(s). This pin is also monitored by the adaptive shoot-through protection circuitry to determine when the lower MOSFET has turned off. 5 VCC VCC. Provides bias power to the IC and the drive voltage for LDRV. Bypass with a good quality ceramic capacitor (X7R or X5R) as close to this pin as possible. 6 FB Feedback. This pin is the inverting input of the internal error amplifier. Use this pin, in combination with the COMP pin, to compensate the voltage-control feedback loop of the converter. 7 COMP/SD 8 SW COMP/SD. This is a multiplexed pin. During operation, the output of the error amplifier drives this pin. Pulling COMP to a level below 0.8V disables the controller. Disabling the controller causes the oscillator to stop, the HDRV and LDRV outputs to be held low, and the soft-start circuitry to re-arm. Connect a 75kΩ resistor between VCC and COMP/SD pin to pull up. Switch Node Input. Connect as shown in Figure 1. The SW pin provides return for the high-side bootstrapped driver, is a sense point for the adaptive shoot-thru protection. 2 FAN6520B Rev. 1.0.3 www.fairchildsemi.com FAN6520B Single Synchronous Buck PWM Controller Pin Configuration FAN6520B Single Synchronous Buck PWM Controller Typical Application +5V 1 VCC 2 8 FAN6520B RPULLUP CHF Q1 5 CVCC 3 7 6 RF CBULK HDRV LOUT SW Q2 4 COMP/SD BOOT Vin = 1.5V to 5V DBOOT CBOOT +VOUT COUT LDRV GND RS FB ROFFSET CF CI Figure 1. Typical Application VCC POR / SOFT START INHIBIT BOOT HDRV SW PWM COMP/SD PWM GATE CONTROL LOGIC FB 0.8V ERROR AMP VCC LDRV OSC GND Figure 2. Functional Block Diagram 3 FAN6520B Rev. 1.0.3 www.fairchildsemi.com Absolute maximum ratings are the values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Parameter Min. Max. Units VCC to GND 6 V VBOOT to GND 15 V HDRV (VBOOT – VSW) 6 V 6 V LDRV SW to PGND –0.5 Continuous –0.5 6 V –3 7 V 5.5 V Transient ( t < 50nsec) All other pins Thermal Information Parameter Min. Storage Temperature –65 Typ. Max. Units 150 °C Lead Soldering Temperature, 10 seconds 300 °C Vapor Phase, 60 seconds 215 °C Infrared, 15 seconds 220 °C Power Dissipation (PD), TA = 25°C 715 mW Thermal Resistance – Junction to Case θJC 40 °C/W Thermal Resistance – Junction to Ambient θJA 140 °C/W Recommended Operating Conditions Parameter Conditions Min. Typ. Max. Units 4.5 5 5.5 V Supply Voltage VCC VCC to PGND Ambient Temperature (TA) FAN6520B 0 70 °C FAN6520BI –40 85 °C –40 125 °C Junction Temperature (TJ) 4 FAN6520B Rev. 1.0.3 www.fairchildsemi.com FAN6520B Single Synchronous Buck PWM Controller Absolute Maximum Ratings Parameter Symbol Conditions Min. Typ. Max. Units • 1.5 2.4 3.8 mA • 4.00 4.22 4.45 V Supply Current VCC Current IVCC HDRV, LDRV open Power-On Reset Rising VCC POR Threshold POR VCC POR Threshold Hysteresis 170 mV Oscillator Frequency Ramp Amplitude FOSC FAN6520B • 250 300 340 kHz FAN6520BI • 230 300 340 kHz ∆VOSC • 1.5 Vp-p Reference Reference Voltage VREF TA = 0 to 70°C • 788 800 812 mV FAN6520BI • 780 800 820 mV Error Amplifier DC Gain Note 2 88 dB Gain – Bandwidth Product GBW Note 2 15 MHz Slew Rate S/R Note 2 8 V/µs Gate Drivers HDRV pull-up resistance RHUP 2.5 Ω HDRV pull-down resistance RHDN 2.0 Ω LDRV pull-up resistance RLUP 2.5 Ω LDRV pull-down resistance RLDN 1.0 Ω 800 mV Disable Disable Threshold VDISABLE Note 3 400 Notes: 1. All limits at operating temperature extremes are guaranteed by design, characterization and statistical quality control. 2. Specifications guaranteed by design/characterization (not production tested). 3. To ensure shutdown, COMP/SD pin should be held below 400mV while sinking 6mA of current. 5 FAN6520B Rev. 1.0.3 www.fairchildsemi.com FAN6520B Single Synchronous Buck PWM Controller Electrical Specifications VCC = 5V, and TA = 25°C using circuit in Figure 1 unless otherwise noted. The • denotes specifications which apply over the full operating temperature range. FAN6520B. If this current has nowhere to go—such as to other distributed loads on the VCC rail, through a voltage limiting protection device, or other methods—the capacitance on the VCC bus will absorb the current. This situation will allow the voltage level of the VCC rail to increase. If the voltage level of the rail is boosted to a level that exceeds the maximum voltage rating of the FAN6520B, then the IC will experience an irreversible failure and the converter will no longer be operational. Ensure that there is a path for the current to follow other than the capacitance on the rail to prevent this failure mode. Initialization The FAN6520B automatically initializes upon receipt of power. The Power-On Reset (POR) function continually monitors the bias voltage at the VCC pin. When the supply voltage exceeds its POR threshold, the IC initiates the soft-start operation. Soft-Start The POR function initiates the soft-start sequence. Softstart clamps the error amplifier output (COMP pin) and reference input (noninverting terminal of the error amp) to the internally generated soft-start voltage. Figure 3 shows a typical start up interval where the COMP pin has been released from a grounded (system shutdown) state. The clamp on the error amplifier (COMP pin) initially controls the converter’s output voltage during softstart. The oscillator’s triangular waveform is compared to the ramping error amplifier voltage. This generates SW pulses of increasing width that charge the output capacitor(s). When the internally generated soft-start voltage exceeds the feedback (FB pin) voltage, the output voltage is in regulation. This method provides a rapid and controlled output voltage rise. The entire startup sequence typically takes about 11ms. Application Guidelines Layout Considerations As in any high frequency switching converter, layout is very important. Switching current from one power device to another can generate voltage transients across the impedances of the interconnecting bond wires and circuit traces. Use wide, short-printed circuit traces to minimize these interconnecting impedances. The critical components should be located as close together as possible, using ground plane construction or single point grounding. Figure 4 shows the critical power components of the converter. To minimize the voltage overshoot, the interconnecting wires indicated by heavy lines should be part of a ground or power plane in a printed circuit board. The components shown in Figure 4 should be located as close together as possible. Please note that the capacitors CIN and COUT may each represent numerous physical capacitors. Locate the FAN6520B as close as possible to Q1 and Q2 MOSFETs. The circuit traces for the MOSFETs’ gate and source connections from the FAN6520B must be sized to handle up to 1A peak current. Vin FAN6520B Q1 CIN HDRV Figure 3. Soft-Start Interval LOUT Adaptive Gate Drive Q2 COUT LDRV When the converter is sinking current, it is behaving as a boost converter that is regulating its input voltage. This means that the converter is boosting current into the VCC rail, which supplies the bias voltage to the LOAD The FAN6520B incorporates a MOSFET shoot-through protection method which allows a converter to both sink and source current. Care should be exercised when designing a converter with the FAN6520B when it is known that the converter may sink current. Figure 4. Printed Circuit Board Power and Ground Planes or Islands 6 FAN6520B Rev. 1.0.3 +VOUT SW www.fairchildsemi.com FAN6520B Single Synchronous Buck PWM Controller Circuit Description VIN OSC Q1 CBOOT SW L OUT LOUT +VOUT SW PWM COUT Q2 VCC COUT Q2 LOAD FAN6520B DBOOT +5V +5V ZFB CVCC FB ZIN COMP GND ERROR AMP +VOUT ESR BOOT 0.8V Figure 5. PC Board Small Signal Layout Guidelines Figure 5 shows the circuit traces that require additional layout consideration. Use single point and ground plane construction for the circuits shown. Minimize any leakage current paths on the COMP pin and locate the resistor, RPULLUP close to the COMP pin. Provide local VCC decoupling between VCC and GND pins. Locate the capacitor, CBOOT as close as practical to the BOOT and PHASE pins. All components used for feedback compensation should be located as close to the IC as practical. DETAILED COMPENSATION COMPONENTS ZFB C1 C2 ZIN C3 R2 VOUT R3 R1 COMP FB ERROR AMP Feedback Compensation Figure 6 highlights the voltage-mode control loop for a synchronous-rectified buck converter. The output voltage (VOUT) is regulated to the reference voltage level. The error amplifier (Error Amp) output (VE/A) is compared with the oscillator (OSC) triangular wave to provide a pulse-width modulated (PWM) wave with an amplitude of VIN at the SW node. The PWM wave is smoothed by the output LC filter (LOUT and COUT). 0.8V Figure 6. Voltage Mode Buck Converter Compensation Design The modulator transfer function is the small-signal transfer function of VOUT/VCOMP. This function is dominated by a DC Gain and the output filter (LOUT and COUT), with a double pole break frequency at FLC and a zero at FESR. The DC Gain of the modulator is simply the input voltage (VIN) divided by the peak-to-peak oscillator voltage ∆VOSC. The compensation network consists of the error amplifier (internal to the FAN6520B) and the impedance networks ZIN and ZFB. The goal of the compensation network is to provide a closed loop transfer function with the highest 0dB crossing frequency (F0dB) and adequate phase margin. Phase margin is the difference between the closed loop phase at F0dB and 180 degrees. The equations below relate the compensation network’s poles, zeros and gain to the components (R1, R2, R3, C1, C2, and C3) in Figure 6. The following equations define the modulator break frequencies as a function of the output LC filter: 1 F Z1 = ---------------------2πR 2 C 1 1 F LC = ------------------------2π L × C (15) 1 F ESR = -----------------------------------2π × ESR × C (16) 1. 1 F P1 = ----------------------------------------C1 C2 2πR 2 -------------------- C 1 + C 2 7 FAN6520B Rev. 1.0.3 (17) (18) 1 F Z2 = ---------------------------------------2πC 3 ( R 1 + R 3 ) (19) 1 F P2 = ---------------------2πR 3 C 3 (20) www.fairchildsemi.com FAN6520B Single Synchronous Buck PWM Controller Vin 2. Output Capacitors (COUT) Pick gain (R2/R1) for the desired converter bandwidth. 1st Modern components and loads are capable of producing transient load rates above 1A/ns. High frequency capacitors initially supply the transient and slow the current load rate seen by the bulk capacitors. Effective Series Resistance (ESR) and voltage rating are typically the prime considerations for the bulk filter capacitors, rather than actual capacitance requirements. High-frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. Be careful not to add inductance in the circuit board wiring that could cancel the performance of these low inductance components. Consult with the load manufacturer on specific decoupling requirements. Use only specialized lowESR capacitors intended for switching-regulator applications for the bulk capacitors. The bulk capacitor’s ESR will determine the output ripple voltage and the initial voltage drop after a high slew-rate transient. An aluminum electrolytic capacitor’s ESR value is related to the case size with lower ESR available in larger case sizes. However, the Equivalent Series Inductance (ESL) of these capacitors increases with case size and can reduce the usefulness of the capacitor to high slew-rate transient loading. Unfortunately, ESL is not a specified parameter. Work with your capacitor supplier and measure the capacitor’s impedance with frequency to select a suitable component. In most cases, multiple electrolytic capacitors of small case size perform better than a single large case capacitor. zero below the filter’s double pole (~75% 3. Place FLC). 4. Place 2nd zero at filter’s double pole. 5. Place 1st pole at the ESR zero. 6. Place 2nd pole at half the switching frequency. 7. Check gain against the error amplifier’s open-loop gain. 8. Estimate phase margin. Repeat if necessary. Figure 7 shows an asymptotic plot of the DC-DC converter’s gain vs. frequency. The actual Modulator Gain has a high gain peak due to the high Q factor of the output filter and is not shown in Figure 7. Using the above guidelines should give a Compensation Gain similar to the curve plotted. The open loop error amplifier gain bounds the compensation gain. Check the compensation gain at FP2 with the capabilities of the error amplifier. The Closed Loop Gain is constructed on the graph of Figure 7 by adding the Modulator Gain (in dB) to the Compensation Gain (in dB). This is equivalent to multiplying the modulator transfer function by the compensation transfer function and plotting the gain. The compensation gain uses external impedance networks ZFB and ZIN to provide a stable, high bandwidth (BW) overall loop. A stable control loop has a gain crossing with a –20dB/decade slope and a phase margin greater than 45°. Include worst case component variations when determining phase margin. 100 FZ1 FZ2 FP1 Output Inductor (LOUT) The output inductor is selected to meet the output voltage ripple requirements and minimize the converter’s response time to the load transient. The inductor value determines the converter’s ripple current and the ripple voltage is a function of the ripple current. The ripple voltage (∆V) and current (∆I) are approximated by the following equations: FP2 80 OPEN LOOP ERROR AMP GAIN GAIN (dB) 60 40 20 20LOG (R2/R1) 0 V IN – V OUT ∆I = ----------------------------F SW × L 20LOG (VIN/DVOSC) MODULATOR GAIN -20 COMPENSATION GAIN FLC FESR -60 10 100 1K 10K 100K 1M 10M FREQUENCY (Hz) Figure 7. Asymptotic Bode Plot of Converter Gain An output capacitor is required to filter the output and supply the load transient current. The filtering requirements are a function of the switching frequency and the ripple current. The load transient requirements are a function of the slew rate (di/dt) and the magnitude of the transient load current. These requirements are generally met with a mix of capacitors and careful layout. 8 FAN6520B Rev. 1.0.3 (1) Increasing the inductance value reduces the ripple current and voltage. However, a large inductance value reduces the converter’s ability to quickly respond to a load transient. One of the parameters limiting the converter’s response to a load transient is the time required to change the inductor current. Given a sufficiently fast control loop design, the FAN6520B will provide either 0% or 100% duty cycle in response to a load transient. The response time is the time required to slew the inductor current from an initial current value to the transient current level. During this interval the difference between the inductor current and the transient current level must be supplied by the output capacitor. Minimizing the response time can minimize the output capacitance required. CLOSED LOOP GAIN -40 ∆V ≈ ESR × ∆I www.fairchildsemi.com FAN6520B Single Synchronous Buck PWM Controller Component Selection Use the following steps to locate the poles and zeros of the compensation network: L × I STEP T RISE = ----------------------------V IN – V OUT T FALL Thermal Considerations L × I STEP = -----------------------V OUT Total device dissipation: PD = PQ + PHDRV + PLDRV where TRISE is the response time to the application of a positive ISTEP, and TFALL is the response time to a load removal (negative ISTEP). The worst case response time can be either at the application or removal of load. Be sure to check both of these equations at the minimum and maximum output levels for the worst case response time. (4) where PQ represents quiescent power dissipation: PQ = VCC × 2.7mA (5) PHDRV represents internal power dissipation of the upper FET driver. PHDRV = PH(R) × PH(F) (6) Input Capacitor Selection Where PH(R) and PH(F) are internal dissipations for the rising and falling edges respectively: Use a mix of input bypass capacitors to control the voltage overshoot across the MOSFETs. Use small ceramic capacitors for high-frequency decoupling and bulk capacitors to supply the current needed each time Q1 turns on. Place the small ceramic capacitors physically close to the MOSFETs and between the drain of Q1 and the source of Q2. The important parameters for the bulk input capacitor are the voltage rating and the RMS current rating. For reliable operation, select the bulk capacitor with voltage and current ratings above the maximum input voltage and the largest RMS current required by the circuit. The capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage and a voltage rating of 1.5 times is a conservative guideline. 2 (8) (9) Where QG1 is total gate charge of Q1 for its applied VGS. As described in the equations above, the total power consumed in driving the gate is divided in proportion to the resistances in series with the MOSFET's internal gate node as shown in Figure 8. (2) BOOT Q1 RHUP through-hole design, several electrolytic capacitors may be needed. For surface-mount designs, solid tantalum capacitors can be used, but caution must be exercised with regard to the capacitor’s surge current rating. The capacitors must be capable of handling the surge current at power-up. Some capacitor series available from reputable manufacturers are surge current tested. HDRV RE RG G RHDN S SW Bootstrap Circuit Figure 8. Driver Dissipation Model The bootstrap circuit uses a charge storage capacitor (CBOOT) and the internal diode, as shown in Figure 1. Selection of these components should be done after the high-side MOSFET has been chosen. The required capacitance is determined using the following equation: RG is the polysilicon gate resistance, internal to the FET. RE is the external gate drive resistor implemented in many designs. Note that the introduction of RE can reduce driver power dissipation, but excess RE may cause errors in the “adaptive gate drive” circuitry. For more information please refer to Fairchild app note AN-6003, “Shoot-through” in Synchronous Buck Converters. (http://www.fairchildsemi.com/an/AN/AN-6003.pdf) (3) 9 FAN6520B Rev. 1.0.3 R HDN P H ( F ) = P Q1 × -------------------------------------------R HDN + R E + R G PQ1 = QG1 × VGS(Q1) × FSW V OUT where the converter duty cycle; D = -------------. For a V IN QG C BOOT = --------------------∆V BOOT (7) where: The RMS current rating requirement (IRMS) for the input capacitor of a buck regulator is: I RMS = I L ( D – D ) R HUP P H ( R ) = P Q1 × ------------------------------------------R HUP + R E + R G www.fairchildsemi.com FAN6520B Single Synchronous Buck PWM Controller where QG is the total gate charge of the high-side MOSFET, and ∆VBOOT is the voltage droop allowed on the high-side MOSFET drive. To prevent loss of gate drive, the bootstrap capacitance should be at least 50 times greater than the CISS of Q1. If FB is < 800mV for 32 consecutive cycles, then LDRV is turned on for ~1.6µs to charge the bootstrap capacitor. Depending upon the whether there is a load application or a load removal, the response time to a load transient (ISTEP) is different. The following equations give the approximate response time interval for application and removal of a transient load: PLDRV = PL(R) × PL(F) PUPPER = PSW + PCOND (10) Where PH(R) and PH(F) are internal dissipations for the rising and falling edges, respectively: R LUP P L ( R ) = P Q2 × ------------------------------------------R LUP + R E + R G (11) R LDN P L ( F ) = P Q2 × -------------------------------------------R HDN + R E + R G (12) (14) V OUT 2 P COND = -------------- × I OUT × R DS ( ON ) V IN (15) where: PUPPER is the upper MOSFET’s total losses, and PSW and PCOND are the switching and conduction losses for a given MOSFET. RDS(ON) is at the maximum junction temperature (TJ). tS is the switching period (rise or fall time) and is t2+t3 (Figure 9). where: PQ2 = QG2 × VGS(Q2) × FSW V DS × I L P SW = --------------------- × 2 × t s F SW 2 (13) Power MOSFET Selection The driver’s impedance and CISS determine t2 while t3’s period is controlled by the driver’s impedance and QGD. Since most of tS occurs when VGS = VSP we can use a constant current assumption for the driver to simplify the calculation of tS: For more information on MOSFET selection for synchronous buck regulators, refer to: AN-6005: Synchronous Buck MOSFET Loss Calculations. This Fairchild app note is located at: http://www.fairchildsemi.com/an/AN/AN-6005.pdf Losses in a MOSFET are the sum of its switching (PSW) and conduction (PCOND) losses. C ISS C GD QGS QGD C ISS VDS In typical applications, the FAN6520B converter's output voltage is low with respect to its input voltage, therefore the lower MOSFET (Q2) is conducting the full load current for most of the cycle. Therefore choose a MOSFET for Q2 which has low RDS(ON) to minimize conduction losses. ID In contrast, the high-side MOSFET (Q1) has a much shorter duty cycle, and its conduction loss will therefore have less of an impact. Q1, however, sees most of the switching losses, so Q1’s primary selection criteria should be gate charge. 4.5V V SP High-Side Losses V TH Figure 9 shows a MOSFET’s switching interval, with the upper graph being the voltage and current on the Drain to Source and the lower graph detailing VGS vs. time with a constant current charging the gate. The x-axis, therefore, is also representative of gate charge (QG) . CISS = CGD + CGS, and it controls t1, t2, and t4 timing. CGD receives the current from the gate driver during t3 (as VDS is falling). The gate charge (QG) parameters on the lower graph are either specified or can be derived from the MOSFET’s datasheet. QG(SW) VGS t1 t2 t3 t4 t5 Figure 9. Switching Losses and QG VIN 5V CGD RD Assuming switching losses are about the same for both the rising edge and falling edge, Q1’s switching losses, occur during the shaded time when the MOSFET has voltage across it and current through it. HDRV RGATE G CGS SW Figure 10. Drive Equivalent Circuit 10 FAN6520B Rev. 1.0.3 www.fairchildsemi.com FAN6520B Single Synchronous Buck PWM Controller These losses are given by: PLDRV is dissipation of the lower FET driver. Conduction losses for Q2 are given by: PCOND = (1-D) × IOUT2 × RDS(ON) (16) where RDS(ON) is the RDS(ON) of the MOSFET at the highest operating junction temperature and Most MOSFET vendors specify QGD and QGS. QG(SW) can be determined as: QG(SW) = QGD + QGS – QTH where QTH is the gate charge required to get the MOSFET to its threshold (VTH). For the high-side MOSFET, VDS = VIN, which can be as high as 20V in a typical portable application. Care should also be taken to include the delivery of the MOSFET’s gate power (PGATE) in calculating the power dissipation required for the FAN6520B: PGATE = QG × VCC × FSW V OUT is the minimum duty cycle for the converter. D = -------------V IN Since DMIN < 20% for portable computers, (1-D) ≈ 1 produces a conservative result, further simplifying the calculation. The maximum power dissipation (PD(MAX) ) is a function of the maximum allowable die temperature of the lowside MOSFET, the θJ-A, and the maximum allowable ambient temperature rise: (17) where QG is the total gate charge to reach VCC. T J ( MAX ) – T A ( MAX ) P D ( MAX ) = -----------------------------------------------θJ – A Low-Side Losses Q2, however, switches on or off with its parallel shottky diode conducting, therefore VDS ≈ 0.5V. Since PSW is proportional to VDS, Q2’s switching losses are negligible and we can select Q2 based on RDS(ON) only. (19) θJ-A, depends primarily on the amount of PCB area that can be devoted to heat sinking (see Fairchild app note AN-1029 for SO-8 MOSFET thermal information). 11 FAN6520B Rev. 1.0.3 (18) www.fairchildsemi.com FAN6520B Single Synchronous Buck PWM Controller Q G ( SW ) Q G ( SW ) t s ≈ --------------------- ≈ -----------------------------------------------------I DRIVER VCC – V SP ---------------------------------------------- R DRIVER + R GATE- FAN6520B Single Synchronous Buck PWM Controller Typical Application Circuit Vin = 3.3V +5V D1 VCC R5 C2 1 BOOT C6 C4 7 2 U1 FAN6520B C1 FB 8 4 6 C8 C5 Q1 COMP/SD R2 5 HDRV Vout = 1.2V, 10A L1 SW Q2 R6 LDRV C7 C9 3 R4 GND R1 C3 R3 Figure 11. 3.3V to 1.2V, 10A DC-DC Converter Typical Application Bill of Materials (1.2V, 10 Amps) Ref Des Description Manufacturer P/N Qty C1 Capacitor, 220pF, 10%, X7R, 0603 Any – 1 C2, C3 Capacitor, 22nF, 10%, X7R, 0603 Any – 2 C4 Capacitor, 1µF, 10%, X7R, 0805 Any – 1 C5, C9 Capacitor, 3900pF, 10%, X7R, 0603 Any – 2 C6 Capacitor, 0.1µF, 10%, X7R, 0603 Any – 1 C7 Capacitor, 560µF, 4V, 7mΩ, 8X11, 5.58A United Chemi-con PSA4VB560MH11 1 C8 Capacitor, 390µF, 6.3V, 8mΩ, 8X11, 5.08A United Chemi-con PSA6.3VB390MH11 2 D1 Diode, 200mA, 100V Fairchild MMSD4148 1 L1 Inductor, 1.8µ, 16A, 3.2mΩ Inter-Technical SC5018-1R8M 1 Q1 Mosfet, N, 30V, 50A, 11.3mΩ, DPAK Fairchild FDD6296 1 Q2 Mosfet, N, 30V, 94A, 6.8mΩ, DPAK Fairchild FDD8896 1 R1 Resistor, 1.00KΩ, 1%, 0603 Any – 1 R2 Resistor, 3.74KΩ, 1%, 0603 Any – 1 R3 Resistor, 120Ω, 5%, 0603 Any – 1 R4 Resistor, 2.00KΩ, 1%, 0603 Any – 1 R5 Resistor, 10KΩ, 5%, 0603 Any – 1 R6 Resistor, 1.5Ω, 5%, 0805 Any – 1 U1 IC, Single Synchronous Buck PWM, SOIC 8 Fairchild FAN6520B 1 Contact factory for the latest bill of materials. 12 FAN6520B Rev. 1.0.3 www.fairchildsemi.com 4.90±0.10 A 3.81 8 5 B 6.75 6.00 3.90±0.10 4.75 1.00 1 PIN ONE INDICATOR 4 0.51 0.35 (0.33) 0.25 M 1.27 C B A 1.27 0.50 3.81 LAND PATTERN RECOMMENDATION 1.75 MAX SEE DETAIL A 1.45+0.05 -0.20 0.25 0.19 C 0.10 C 0.15+0.10 -0.05 0.50 X 45° 0.25 (R0.10) NOTES: UNLESS OTHERWISE SPECIFIED GAGE PLANE (R0.10) A) THIS PACKAGE CONFORMS TO JEDEC MS-012, VARIATION AA, ISSUE C, DATED MAY 1990. B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS. D) STANDARD LEAD FINISH: 200 MICROINCHES / 5.08 MICRONS MIN. LEAD/TIN (SOLDER) ON COPPER. 0.36 8° 0° 0.70±0.20 SEATING PLANE (1.04) DETAIL A SCALE: 2:1 13 FAN6520B Rev. 1.0.3 www.fairchildsemi.com FAN6520B Single Synchronous Buck PWM Controller Dimensional Outline Drawing The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx™ FAST® ActiveArray™ FASTr™ Bottomless™ FPS™ Build it Now™ FRFET™ CoolFET™ GlobalOptoisolator™ CROSSVOLT™ GTO™ DOME™ HiSeC™ EcoSPARK™ I2C™ 2 E CMOS™ i-Lo™ EnSigna™ ImpliedDisconnect™ FACT™ IntelliMAX™ FACT Quiet Series™ Across the board. Around the world.™ The Power Franchise® Programmable Active Droop™ ISOPLANAR™ LittleFET™ MICROCOUPLER™ MicroFET™ MicroPak™ MICROWIRE™ MSX™ MSXPro™ OCX™ OCXPro™ OPTOLOGIC® OPTOPLANAR™ PACMAN™ POP™ Power247™ PowerEdge™ PowerSaver™ PowerTrench® QFET® QS™ QT Optoelectronics™ Quiet Series™ RapidConfigure™ RapidConnect™ µSerDes™ ScalarPump™ SILENT SWITCHER® SMART START™ SPM™ Stealth™ SuperFET™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TCM™ TinyLogic® TINYOPTO™ TruTranslation™ UHC™ UltraFET® UniFET™ VCX™ Wire™ DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. 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PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. I18 14 FAN6520B Rev. 1.0.3 www.fairchildsemi.com FAN6520B Single Synchronous Buck PWM Controller TRADEMARKS