Cypress CY2DP1502 1:2 lvpecl fanout buffer 20-ps maximum output-to-output skew Datasheet

CY2DP1502
1:2 LVPECL Fanout Buffer
Features
Functional Description
■
One low-voltage positive emitter-coupled logic (LVPECL) input
pair distributed to two LVPECL output pairs
■
20-ps maximum output-to-output skew
■
480-ps maximum propagation delay
■
0.15-ps maximum additive RMS phase jitter at 156.25 MHz
(12-kHz to 20-MHz offset)
The CY2DP1502 is an ultra-low noise, low-skew,
low-propagation delay 1:2 LVPECL fanout buffer targeted to
meet the requirements of high-speed clock distribution
applications. The device has a fully differential internal
architecture that is optimized to achieve low additive jitter and
low skew at operating frequencies of up to 1.5 GHz.
■
Up to 1.5-GHz operation
■
8-pin small outline integrated circuit (SOIC) or 8-pin thin shrunk
small outline package (TSSOP) package
■
2.5-V or 3.3-V operating voltage[1]
■
Commercial and industrial operating temperature range
Logic Block Diagram
VDD
VDD
VSS
Q0
Q0#
IN
IN#
Q1
Q1#
Note
1. Input AC-coupling capacitors are required for voltage-translation applications.
Cypress Semiconductor Corporation
Document Number: 001-56308 Rev. *G
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised April 19, 2011
CY2DP1502
Contents
Features.............................................................................
Functional Description.....................................................
Logic Block Diagram........................................................
Contents ............................................................................
Pinouts ..............................................................................
Absolute Maximum Ratings ............................................
Operating Conditions.......................................................
DC Electrical Specifications ............................................
AC Electrical Specifications ............................................
Ordering Information........................................................
Ordering Code Definition.............................................
Document Number: 001-56308 Rev. *G
1
1
1
2
3
3
3
4
5
8
8
Package Dimensions........................................................ 9
Acronyms ........................................................................ 11
Document Conventions ................................................. 11
Document History Page ................................................. 12
Sales, Solutions, and Legal Information ...................... 13
Worldwide Sales and Design Support....................... 13
Products .................................................................... 13
PSoC Solutions ......................................................... 13
Page 2 of 13
CY2DP1502
Pinouts
Q0
1
Q0#
2
Q1
3
Q1#
4
CY2DP1502
Figure 1. Pin Diagram – 8-Pin SOIC and 8-Pin TSSOP Package
8
V DD
7
IN
6
IN#
5
V SS
Table 1. Pin Definitions
Pin Number
Pin Name
Pin Type
Description
1,3
Q(0:1)
Output
LVPECL output clocks
2,4
Q(0:1)#
Output
LVPECL complementary output clocks
5
VSS
Power
Ground
6
IN#
Input
LVPECL complementary input clock
7
IN
Input
LVPECL input clock
8
VDD
Power
Power supply
Absolute Maximum Ratings
Parameter
Description
Condition
Min
Max
Unit
VDD
Supply voltage
Nonfunctional
–0.5
4.6
V
VIN[2]
Input voltage, relative to VSS
Nonfunctional
–0.5
lesser of 4.0
or VDD + 0.4
V
VOUT[2]
DC output or I/O voltage, relative to VSS
Nonfunctional
–0.5
lesser of 4.0
or VDD + 0.4
V
TS
Storage temperature
Nonfunctional
–55
150
°C
ESDHBM
Electrostatic discharge (ESD) protection
(Human body model)
JEDEC STD 22-A114-B
2000
–
V
LU
Latch up
UL–94
Flammability rating
MSL
Moisture sensitivity level
Meets or exceeds JEDEC Spec
JESD78B IC Latchup Test
At 1/8 in
V-0
3
Operating Conditions
Parameter
Description
VDD
Supply voltage
TA
Ambient operating temperature
tPU
Power ramp time
Min
Max
Unit
2.5-V supply
Condition
2.375
2.625
V
3.3-V supply
3.135
3.465
V
Commercial
0
70
°C
Industrial
–40
85
°C
Power-up time for VDD to reach
minimum specified voltage (power
ramp must be monotonic).
0.05
500
ms
Note
2. The voltage on any I/O pin cannot exceed the power pin during power up. Power supply sequencing is NOT required.
Document Number: 001-56308 Rev. *G
Page 3 of 13
CY2DP1502
DC Electrical Specifications
(VDD = 3.3 V ± 5% or 2.5 V ± 5%; TA = 0 °C to 70 °C (Commercial) or –40 °C to 85 °C (Industrial))
Parameter
Description
Condition
Min
Max
Unit
All LVPECL outputs floating (internal IDD)
–
45
mA
Input high voltage, LVPECL inputs
IN and IN#
–
VDD + 0.3
V
VIL
Input low voltage, LVPECL inputs
IN and IN#
–0.3
–
V
VID[3]
Input differential amplitude
See Figure 2 on page 6
0.4
1.0
V
VICM
Input common mode voltage
See Figure 2 on page 6
0.5
VDD – 0.2
V
IIH
Input high current, LVPECL inputs
IN and IN#
Input = VDD[4]
–
150
A
IIL
Input low current, LVPECL inputs
IN and IN#
Input = VSS[4]
–150
–
A
VOH
LVPECL output high voltage
Terminated with 50  to VDD – 2.0[5]
VDD – 1.20 VDD – 0.70
V
VOL
LVPECL output low voltage
Terminated with 50  to VDD – 2.0[5]
VDD – 2.0 VDD – 1.63
V
CIN
Input capacitance
Measured at 10 MHz; per pin
IDD
Operating supply current
VIH
–
3
pF
Notes
3. VID minimum of 400 mV is required to meet all output AC Electrical Specifications. The device is functional with VID minimum of greater than 200 mV.
4. Positive current flows into the input pin, negative current flows out of the input pin.
5. Refer to Figure 3 on page 6.
Document Number: 001-56308 Rev. *G
Page 4 of 13
CY2DP1502
AC Electrical Specifications
(VDD = 3.3 V ± 5% or 2.5 V ± 5%; TA = 0 °C to 70 °C (Commercial) or –40 °C to 85 °C (Industrial))
Parameter
Description
Condition
FIN
Input frequency
FOUT
Output frequency
VPP
LVPECL differential output voltage
Fout = DC to 150 MHz
peak to peak, single-ended. terminated
with 50  to VDD – 2.0[6]
Fout = >150 MHz to 1.5 GHz
FOUT = FIN
Min
Typ
Max
Unit
DC
–
1.5
GHz
DC
–
1.5
GHz
600
–
–
mV
400
–
–
mV
tPD[7]
Propagation delay input pair to output Input rise/fall time < 1.5 ns
pair
(20% to 80%)
–
–
480
ps
tODC[8]
Output duty cycle
50% duty cycle at input
Frequency range up to 1 GHz
48
–
52
%
tSK1[9]
Output-to-output skew
Any output to any output, with
same load conditions at DUT
–
–
20
ps
tSK1 D[9]
Device-to-device output skew
Any output to any output between
two or more devices. Devices
must have the same input and
have the same output load.
–
–
150
ps
PNADD
Additive RMS phase noise
156.25-MHz Input
Rise/fall time < 150 ps (20% to 80%)
VID > 400 mV
Offset = 1 kHz
–
–
–120
dBc/Hz
Offset = 10 kHz
–
–
–130
dBc/Hz
Offset = 100 kHz
–
–
–135
dBc/Hz
Offset = 1 MHz
–
–
–145
dBc/Hz
Offset = 10 MHz
–
–
–153
dBc/Hz
Offset = 20 MHz
–
–
–155
dBc/Hz
Additive RMS phase jitter (Random)
156.25 MHz, 12 kHz to 20 MHz
offset; input rise/fall time < 150 ps
(20% to 80%),
VID > 400 mV
–
–
0.15
ps
Output rise/fall time
50% duty cycle at input,
20% to 80% of full swing
(VOL to VOH)
Input rise/fall time < 1.5 ns
(20% to 80%)
–
–
250
ps
tJIT
[10]
tR, tF[11]
Notes
6. Refer to Figure 3 on page 6.
7. Refer to Figure 4 on page 6.
8. Refer to Figure 5 on page 6.
9. Refer to Figure 6 on page 7.
10. Refer to Figure 7 on page 7.
11. Refer to Figure 8 on page 7.
Document Number: 001-56308 Rev. *G
Page 5 of 13
CY2DP1502
Figure 2. Input Differential and Common Mode Voltages
VA
IN
VICM = (VA + VB)/2
VID
IN#
VB
Figure 3. Output Differential Voltage
VOH
Q
VPP
Q#
VOL
Figure 4. Input to Any Output Pair Propagation Delay
IN
IN #
QX
Q X#
t PD
Figure 5. Output Duty Cycle
QX
Q X#
tPW
tPERIOD
tODC =
Document Number: 001-56308 Rev. *G
tPW
tPERIOD
Page 6 of 13
CY2DP1502
Figure 6. Output-to-Output and Device-to-Device Skew
QX
Q X#
Device 1
QY
Q Y#
tSK1
QZ
Device 2
Q Z#
tSK1 D
Figure 7. RMS Phase Jitter
Phase noise
Noise Power
Phase noise mark
Offset Frequency
f2
f1
RMS Jitter 
Area Under the Masked Phase Noise Plot
Figure 8. Output Rise/Fall Time
QX
80% 80%
VPP
20%
QX#
20%
tR
Document Number: 001-56308 Rev. *G
tF
Page 7 of 13
CY2DP1502
Ordering Information
Part Number
Type
Production Flow
Pb-free
CY2DP1502SXC
8-Pin SOIC
Commercial, 0 °C to 70 °C
CY2DP1502SXCT
8-Pin SOIC tape and reel
Commercial, 0 °C to 70 °C
CY2DP1502SXI
8-Pin SOIC
Industrial, –40 °C to 85 °C
CY2DP1502SXIT
8-Pin SOIC tape and reel
Industrial, –40 °C to 85 °C
CY2DP1502ZXC
8-Pin TSSOP
Commercial, 0 °C to 70 °C
CY2DP1502ZXCT
8-Pin TSSOP tape and reel
Commercial, 0 °C to 70 °C
CY2DP1502ZXI
8-Pin TSSOP
Industrial, –40 °C to 85 °C
CY2DP1502ZXIT
8-Pin TSSOP tape and reel
Industrial, –40 °C to 85 °C
Ordering Code Definition
CY 2DP15 02 SX/ZX C/I T
Tape and reel
Temperature range
C = Commercial
I = Industrial
Pb-free packages
SX: SOIC
ZX: TSSOP
Number of differential output pairs
Base part number
Company ID: CY = Cypress
Document Number: 001-56308 Rev. *G
Page 8 of 13
CY2DP1502
Package Dimensions
Figure 9. 8-Pin (150-Mil) SOIC S8
51-85066 *D
Document Number: 001-56308 Rev. *G
Page 9 of 13
CY2DP1502
Figure 10. 8-Pin Thin Shrunk Small Outline Package (4.40 MM Body) Z8
51-85093 *C
Document Number: 001-56308 Rev. *G
Page 10 of 13
CY2DP1502
Acronyms
Document Conventions
Table 2. Acronyms Used in this Document
Table 3. Units of Measure
Acronym
Description
Symbol
Unit of Measure
ESD
electrostatic discharge
°C
degree Celsius
HBM
human body model
dBc
decibels relative to the carrier
JEDEC
Joint electron devices engineering council
GHz
giga hertz
LVDS
low-voltage differential signal
Hz
hertz
LVCMOS
low-voltage complementary metal oxide
semiconductor
k
kilo ohm
µA
microamperes
LVPECL
low-voltage positive emitter-coupled logic
µF
micro Farad
LVTTL
low-voltage transistor-transistor logic
OE
Output enable
RMS
root mean square
TSSOP
thin shrunk small outline package
Document Number: 001-56308 Rev. *G
µs
microsecond
mA
milliamperes
ms
millisecond
mV
millivolt
MHz
megahertz
ns
nanosecond

ohm
pF
pico Farad
ps
pico second
V
volts
W
watts
Page 11 of 13
CY2DP1502
Document History Page
Document Title: CY2DP1502 1:2 LVPECL Fanout Buffer
Document Number: 001-56308
Revision
ECN
Orig. of
Change
Submission
Date
Description of Change
**
2782891
CXQ
10/09/09
*A
2838916
CXQ
01/05/2010
Changed status from “ADVANCE” to “PRELIMINARY”.
Changed from 0.34 ps to 0.25 ps maximum additive jitter in “Features” on page
1 and in tJIT in the AC Electrical Specs table on page 4.
Added tPU spec to the Operating Conditions table on page 2.
Change VOH in the DC Electrical Specs table on page 3: minimum from VDD
- 1.15V to VDD - 1.20V; maximum from VDD - 0.75V to VDD - 0.70V.
Removed VOD spec from the DC Electrical Specs table on page 3.
Added RP spec in the DC Electrical Specs table on page 3. Min = 60 k, Max
= 140 k.
Added a measurement definition for CIN in the DC Electrical Specs table on
page 3.
Added VPP spec to the AC Electrical Specs table on page 4. VPP min = 600
mV for DC - 150 MHz and min = 400 mV for 150 MHz to 1.5 GHz.
Changed letter case and some names of all the timing parameters in the AC
Electrical Specs table on page 4 to be consistent with EROS.
Lowered all additive phase noise mask specs by 3 dB in the AC Electrical
Specs table on page 4.
Added condition to tR and tF specs in the AC Electrical specs table on page 4
that input rise/fall time must be less than 1.5 ns (20% to 80%).
Changed letter case and some names of all the timing parameters in Figures
3, 4, 5, 6 and 8, to be consistent with EROS.
*B
3011766
CXQ
08/20/2010
Changed from 0.25 ps to 0.11 ps maximum additive jitter in “Features” on page
1 and in tJIT in the AC Electrical Specs table.
Added note 3 to describe IIH and IIL specs.
Removed reference to data distribution from “Functional Description”.
Changed RP for differential inputs from 100 k to 150 k in the Logic Block
Diagram and from 60 k min / 140 k max to 90 k min / 210 k max in the
DC Electrical Specs table.
Added max VID of 1.0V in DC Electrical Specs table.
Updated phase noise specs for 1 k/10 k/100 k/1 M/10 M/20 MHz offset to
-120/-130/-135/-150/-150/-150dBc/Hz, respectively, in the AC Electrical
Specs table.
Added “Frequency range up to 1 GHz” condition to tODC spec.
Updated package diagrams.
Added Acronyms and Ordering Code Definition.
*C
3017258
CXQ
08/27/2010
Corrected Output Rise/Fall time diagram.
*D
3100234
CXQ
11/18/2010
Updated Phase jitter to 0.15ps max from 0.11ps max.
Changed VIN and VOUT specs from 4.0V to “lesser of 4.0 or VDD + 0.4”
Removed 200mA min LU spec, replaced with “Meets or exceeds JEDEC Spec
JESD78B IC Latchup Test”
Removed RP spec for differential input clock pins INX and INX#.
Changed CIN condition to “Measured at 10 MHz”.
Changed PNADD specs for 1MHz, 10MHz, and 20MHz offsets.
*E
3137726
CXQ
01/13/2011
Removed “Preliminary” status heading.
Removed resistors on IN/IN# from Logic Block Diagram.
01/13/2011
Rev’ed and posted
*F
3137726
CXQ
*G
3234654
VED
Document Number: 001-56308 Rev. *G
New Datasheet.
04/19/2011
Minor change, no content change.
Page 12 of 13
CY2DP1502
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
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© Cypress Semiconductor Corporation, 2009-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
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assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
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assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-56308 Rev. *G
Revised April 19, 2011
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Page 13 of 13
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