CY7C1141V18 CY7C1156V18 CY7C1143V18 CY7C1145V18 18-Mbit QDR™-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) Features Functional Description Separate Independent read and write data ports ❐ Supports concurrent transactions ■ 300 MHz to 375 MHz clock for high bandwidth ■ 4-Word Burst for reducing address bus frequency ■ Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 750 MHz) at 375 MHz ■ Read latency of 2.0 clock cycles ■ Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges only ■ Echo clocks (CQ and CQ) simplify data capture in high speed systems ■ Single multiplexed address input bus latches address inputs for both read and write ports ■ Separate Port Selects for depth expansion ■ Data valid pin (QVLD) to indicate valid data on the output ■ Synchronous internally self-timed writes ■ Available in x8, x9, x18, and x36 configurations ■ Full data coherency providing most current data [1] ■ Core VDD = 1.8V ± 0.1V; IO VDDQ = 1.4V to VDD ■ Available in 165-Ball FBGA package (13 x 15 x 1.4 mm) ■ Offered in both Pb-free and non Pb-free packages ■ Variable drive HSTL output buffers ■ JTAG 1149.1 compatible test access port ■ Delay Lock Loop (DLL) for accurate data placement The CY7C1141V18, CY7C1156V18, CY7C1143V18, and CY7C1145V18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II+ architecture. QDR-II+ architecture consists of two separate ports to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR-II+ architecture has separate data inputs and data outputs to completely eliminate the need to “turn-around” the data bus required with common IO devices. Access to each port is accomplished through a common address bus. Addresses for read and write addresses are latched on alternate rising edges of the input (K) clock. Accesses to the QDR-II+ read and write ports are completely independent of one another. To maximize data throughput, both read and write ports are equipped with Double Data Rate (DDR) interfaces. Each address location is associated with four 8-bit words (CY7C1141V18), or 9-bit words (CY7C1156V18), or 18-bit words (CY7C1143V18), or 36-bit words (CY7C1145V18) that burst sequentially into or out of the device. Because data can be transferred into and out of the device on every rising edge of both input clocks K and K, memory bandwidth is maximized while simplifying system design by eliminating bus “turn-arounds”. ■ Depth expansion is accomplished with Port Selects for each port. Port Selects enable each port to operate independently. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the K or K input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry. Configurations With Read Cycle Latency of 2.0 cycles: CY7C1141V18 – 2M x 8 CY7C1156V18 – 2M x 9 CY7C1143V18 – 1M x 18 CY7C1145V18 – 512K x 36 Selection Guide 375 MHz 333 MHz 300 MHz Unit Maximum Operating Frequency 375 333 300 MHz Maximum Operating Current 1020 920 850 mA Note 1. The QDR consortium specification for VDDQ is 1.5V + 0.1V. The Cypress QDR devices exceed the QDR consortium specification and are capable of supporting VDDQ = 1.4V to VDD. Cypress Semiconductor Corporation Document Number: 001-06583 Rev. *C • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised June 15, 2007 [+] Feedback CY7C1141V18 CY7C1156V18 CY7C1143V18 CY7C1145V18 Logic Block Diagram (CY7C1141V18) DOFF Write Reg Address Register Read Add. Decode CLK Gen. Write Reg 512K x 8 Array K K Write Reg 512K x 8 Array 19 Write Reg 512K x 8 Array Address Register 512K x 8 Array A(18:0) 8 Write Add. Decode D[7:0] A(18:0) 19 RPS Control Logic Read Data Reg. 32 VREF WPS CQ 16 Reg. Control Logic NWS[1:0] CQ 16 Reg. Q[7:0] Reg. 8 8 QVLD Logic Block Diagram (CY7C1156V18) DOFF VREF WPS BWS[0] Write Reg Address Register Read Add. Decode CLK Gen. Write Reg 512K x 9 Array K K Write Reg 512K x 9 Array 19 Write Reg 512K x 9 Array Address Register 512K x 9 Array A(18:0) 9 Write Add. Decode D[8:0] A(18:0) 19 RPS Control Logic Read Data Reg. 36 Control Logic CQ CQ 18 Reg. 18 Reg. Q[8:0] Reg. 9 9 Document Number: 001-06583 Rev. *C QVLD Page 2 of 28 [+] Feedback CY7C1141V18 CY7C1156V18 CY7C1143V18 CY7C1145V18 Logic Block Diagram (CY7C1143V18) DOFF Write Reg Address Register Read Add. Decode CLK Gen. Write Reg 256K x 18 Array K K Write Reg 256K x 18 Array 18 Write Reg 256K x 18 Array Address Register 256K x 18 Array A(17:0) 18 Write Add. Decode D[17:0] 18 A(17:0) RPS Control Logic Read Data Reg. 72 VREF WPS CQ 36 Reg. Control Logic BWS[1:0] CQ 36 Reg. Q[17:0] Reg. 18 18 QVLD Logic Block Diagram (CY7C1145V18) DOFF VREF WPS BWS[3:0] Address Register Read Add. Decode CLK Gen. Write Reg 128K x 36 Array K K Write Reg 128K x 36 Array 17 Write Reg 128K x 36 Array Address Register Write Reg 128K x 36 Array A(16:0) 36 Write Add. Decode D[35:0] 17 A(16:0) RPS Control Logic Read Data Reg. 144 Control Logic CQ CQ 72 Reg. 72 Reg. Q[35:0] Reg. 36 36 Document Number: 001-06583 Rev. *C QVLD Page 3 of 28 [+] Feedback CY7C1141V18 CY7C1156V18 CY7C1143V18 CY7C1145V18 Pin Configurations 165-Ball FBGA (13 x 15 x 1.4 mm) Pinout CY7C1141V18 (2M x 8) 1 2 3 4 5 6 7 8 9 10 11 A CQ NC/72M A WPS NWS1 K NC/144M RPS A NC/36M CQ B C D E F G H J K L M N P NC NC NC NC NC D4 NC NC NC A VSS VSS NC/288M A NWS0 A VSS A VSS VSS NC NC VSS K NC VSS NC NC NC Q3 D3 NC NC NC Q4 VDDQ VSS VSS VSS VDDQ NC D2 Q2 NC NC NC NC VDDQ VDD VSS VDD VDDQ NC NC DOFF NC D5 VREF NC Q5 VDDQ NC VDDQ VDDQ VDDQ VDD VDD VDD VSS VSS VSS VDD VDD VDD VDDQ VDDQ VDDQ NC NC VDDQ NC NC VREF Q1 NC ZQ D1 NC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC R NC NC Q6 D6 VDDQ VSS VSS VSS VDDQ NC NC Q0 NC NC NC D7 NC NC VSS VSS VSS A VSS A VSS A VSS VSS NC NC NC NC D0 NC NC NC Q7 A A QVLD A A NC NC NC TDO TCK A A A NC A A A TMS TDI CY7C1156V18 (2M x 9) 1 2 3 4 5 6 7 8 9 10 11 CQ NC/72M A WPS NC K NC/144M RPS A NC/36M CQ NC NC NC A NC/288M K BWS0 A NC NC Q4 NC NC NC D5 NC NC VSS VSS A NC VSS A VSS VSS VSS NC VSS NC NC D4 NC A B C D E F G H J K L M N P NC NC Q5 VDDQ VSS VSS VSS VDDQ NC D3 Q3 NC NC DOFF NC NC NC VDDQ VDD VSS VDDQ NC Q6 VDDQ NC VDDQ VDDQ VDDQ VDD VDD VDD VSS VSS VSS VDDQ VDDQ VDDQ NC NC VDDQ NC NC D6 VREF NC VDD VDD VDD VDD NC VREF Q2 NC ZQ D2 NC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC R NC NC Q7 D7 VDDQ VSS VSS VSS VDDQ NC NC Q1 NC NC NC D8 NC NC VSS VSS VSS A VSS A VSS A VSS VSS NC NC NC NC D1 NC NC NC Q8 A A QVLD A A NC D0 Q0 TDO TCK A A A NC A A A TMS TDI Document Number: 001-06583 Rev. *C Page 4 of 28 [+] Feedback CY7C1141V18 CY7C1156V18 CY7C1143V18 CY7C1145V18 Pin Configurations (continued) 165-Ball FBGA (13 x 15 x 1.4 mm) Pinout CY7C1143V18 (1M x 18) 1 A B C D E F G H J K L M N P R CQ 2 3 NC/144M NC/36M 4 5 6 7 8 9 10 11 WPS BWS1 K NC/288M RPS A NC/72M CQ NC Q9 D9 A NC K BWS0 A NC NC Q8 NC NC NC D11 D10 VSS VSS A VSS NC VSS A VSS VSS VSS NC Q10 Q7 NC D8 D7 NC NC NC Q11 VDDQ VSS VSS VSS VDDQ NC D6 Q6 NC Q12 D12 VDDQ VDD VSS VDD VDDQ NC NC Q5 NC D13 Q13 VDDQ VDD VSS VDD VDDQ NC D5 DOFF NC VREF NC VDDQ D14 VDDQ VDDQ VDD VDD VSS VSS VDD VDD VDDQ VDDQ NC VDDQ NC VREF Q4 ZQ D4 NC NC Q14 VDDQ VDD VSS VDD VDDQ NC D3 Q3 NC Q15 D15 VDDQ VSS VSS VSS VDDQ NC NC Q2 NC NC NC D17 D16 Q16 VSS VSS VSS A VSS A VSS A VSS VSS NC NC Q1 NC D2 D1 NC NC Q17 A A QVLD A A NC D0 Q0 TDO TCK A A A NC A A A TMS TDI 9 10 CY7C1145V18 (512K x 36) 1 A B C D E F G H J K L M N P R CQ 2 3 NC/288M NC/72M 4 5 6 7 8 WPS BWS2 K BWS1 RPS BWS3 A K BWS0 A VSS A D17 Q17 Q8 VSS VSS D16 Q16 Q7 D15 D8 D7 Q27 Q18 D18 A D27 D28 Q28 D20 D19 Q19 VSS VSS Q29 D29 Q20 Q30 D30 Q21 D21 DOFF D31 D22 VREF Q31 Q32 NC/36M NC/144M 11 CQ VSS NC VSS VDDQ VSS VSS VSS VDDQ Q15 D6 Q6 VDDQ VDD VSS VDD VDDQ Q14 Q22 VDDQ D23 VDDQ VDDQ VDDQ VDD VDD VDD VSS VSS VSS VDD VDD VDD VDDQ VDDQ VDDQ D14 Q13 VDDQ D12 D13 VREF Q4 Q5 D5 ZQ D4 D32 Q23 VDDQ VDD VSS VDD VDDQ Q12 D3 Q3 Q33 Q24 D24 VDDQ VSS VSS VSS VDDQ D11 Q11 Q2 D33 D34 Q34 D26 D25 Q25 VSS VSS VSS A VSS A VSS A VSS VSS D10 Q10 Q1 D9 D2 D1 Q35 D35 Q26 A A QVLD A A Q9 D0 Q0 TDO TCK A A A NC A A A TMS TDI Document Number: 001-06583 Rev. *C Page 5 of 28 [+] Feedback CY7C1141V18 CY7C1156V18 CY7C1143V18 CY7C1145V18 Pin Definitions Pin Name IO Pin Description D[x:0] InputData Input Signals. Sampled on the rising edge of K and K clocks during valid write operations. Synchronous CY7C1141V18−D[7:0] CY7C1156V18−D[8:0] CY7C1143V18−D[17:0] CY7C1145V18−D[35:0] WPS InputWrite Port Select − Active LOW. Sampled on the rising edge of the K clock. When asserted active, Synchronous a write operation is initiated. Deasserting deselects the write port. Deselecting the write port causes D[x:0] to be ignored. NWS0, NWS1, InputNibble Write Select 0, 1 − Active LOW.(CY7C1141V18 Only) Sampled on the rising edge of the K Synchronous and K clocks during write operations. This is used to select the nibble that is written into the device NWS0 controls D[3:0] and NWS1 controls D[7:4]. All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble Write Select causes the corresponding nibble of data to be ignored and not written into the device. BWS0, BWS1, BWS2, BWS3 InputByte Write Select 0, 1, 2, and 3 − Active LOW. Sampled on the rising edge of the K and K clocks Synchronous during write operations. This is used to select the byte that is written into the device during the current portion of the write operations. Bytes not written remain unaltered. CY7C1156V18 − BWS0 controls D[8:0] CY7C1143V18 − BWS0 controls D[8:0] and BWS1 controls D[17:9]. CY7C1145V18 − BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18], and BWS3 controls D[35:27]. All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select causes the corresponding byte of data to be ignored and not written into the device. A InputAddress Inputs. Sampled on the rising edge of the K clock during active read and write operations. Synchronous These address inputs are multiplexed for both read and write operations. Internally, the device is organized as 2M x 8 (4 arrays each of 512K x 8) for CY7C1141V18, 2M x 9 (4 arrays each of 512K x 9) for CY7C1156V18, 1M x 18 (4 arrays each of 256K x 18) for CY7C1143V18, and 512K x 36 (4 arrays each of 128K x 36) for CY7C1145V18. Therefore, only 19 address inputs are needed to access the entire memory array of CY7C1141V18 and CY7C1156V18, 18 address inputs for CY7C1143V18 and 17 address inputs for CY7C1145V18. These inputs are ignored when the appropriate port is deselected. Q[x:0] OutputsData Output signals. These pins drive out the requested data during a read operation. Valid data is Synchronous driven out on the rising edge of both the K and K clocks during read operations or K and K when in single clock mode. When the read port is deselected, Q[x:0] are automatically tri-stated. CY7C1141V18−Q[7:0] CY7C1156V18−Q[8:0] CY7C1143V18−Q[17:0] CY7C1145V18−Q[35:0] RPS InputRead Port Select − Active LOW. Sampled on the rising edge of Positive Input Clock (K). When Synchronous active, a read operation is initiated. Deasserting causes the read port to be deselected. When deselected, the pending access is enabled to complete and the output drivers are automatically tri-stated following the next rising edge of the K clock. Each read access consists of a burst of four sequential transfers. QVLD Valid output indicator Valid Output Indicator. The Q Valid indicates valid output data. QVLD is edge aligned with CQ and CQ. K InputClock Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device and to drive out data through Q[x:0] when in single clock mode. All accesses are initiated on the rising edge of K. K InputClock Negative Input Clock Input. K is used to capture synchronous inputs presented to the device and to drive out data through Q[x:0] when in single clock mode. Echo Clock Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input clock (K) of the QDR-II+. The timings for the echo clocks are shown in the “Switching Characteristics” on page 23. CQ Document Number: 001-06583 Rev. *C Page 6 of 28 [+] Feedback CY7C1141V18 CY7C1156V18 CY7C1143V18 CY7C1145V18 Pin Definitions Pin Name (continued) IO Pin Description CQ Echo Clock Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input clock (K) of the QDR-II+. The timings for the echo clocks are shown in the “Switching Characteristics” on page 23. ZQ Input Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus impedance. CQ, CQ and Q[x:0] output impedance are set to 0.2 x RQ, where RQ is a resistor connected between ZQ and ground. Alternatively, connect this pin directly to VDDQ, which enables the minimum impedance mode. This pin cannot be connected directly to GND or left unconnected. DOFF Input DLL Turn Off − Active LOW. Connecting this pin to ground turns off the DLL inside the device. The timings in the DLL turned off operationis different from those listed in this data sheet. For normal operation, connect this pin to a pull up through a 10 KΩ or less pull up resistor. The device behaves in QDR-I mode when the DLL is turned off. In this mode, operate the device at a frequency of up to 167 MHz with QDR-I timing. TDO Output TCK Input TCK pin for JTAG. TDI Input TDI pin for JTAG. TMS Input TMS pin for JTAG. NC N/A Not connected to the die. Tie to any voltage level. NC/36M N/A Not connected to the die. Tie to any voltage level. NC/72M N/A Not connected to the die. Tie to any voltage level. NC/144M N/A Not connected to the die. Tie to any voltage level. NC/288M N/A Not connected to the die. Tie to any voltage level. VREF VDD VSS VDDQ InputReference TDO for JTAG. Reference Voltage Input. Static input used to set the reference level for HSTL inputs, outputs, and AC measurement points. Power Supply Power supply inputs to the core of the device. Ground Ground for the device. Power Supply Power supply inputs for the outputs of the device. Document Number: 001-06583 Rev. *C Page 7 of 28 [+] Feedback CY7C1141V18 CY7C1156V18 CY7C1143V18 CY7C1145V18 Functional Overview Write Operations The CY7C1141V18, CY7C1156V18, CY7C1143V18, and CY7C1145V18 are synchronous pipelined Burst SRAMs equipped with both a read port and a write port. The read port is dedicated to read operations and the write port is dedicated to write operations. Data flows into the SRAM through the write port and out through the read port. These devices multiplex the address inputs in order to minimize the number of address pins required. By having separate read and write ports, the QDR-II+ completely eliminates the need to “turn-around” the data bus and avoids any possible data contention, thereby simplifying system design. Each access consists of four 8-bit data transfers in the case of CY7C1141V18, four 9-bit data transfers in the case of CY7C1156V18, four 18-bit data transfers in the case of CY7C1143V18, and four 36-bit data transfers in the case of CY7C1145V18 in two clock cycles. Write operations are initiated by asserting WPS active at the rising edge of the Positive Input Clock (K). On the following K clock rise the data presented to D[17:0] is latched and stored into the lower 18-bit Write Data register, provided BWS[1:0] are both asserted active. On the subsequent rising edge of the Negative Input Clock (K) the information presented to D[17:0] is also stored into the Write Data register, provided BWS[1:0] are both asserted active. This process continues for one more cycle until four 18-bit words (a total of 72 bits) of data are stored in the SRAM. The 72 bits of data are then written into the memory array at the specified location. Therefore, write accesses to the device cannot be initiated on two consecutive K clock rises. The internal logic of the device ignores the second write request. Initiate write accesses on every other rising edge of the Positive Input Clock (K). This pipelines the data flow such that 18 bits of data can be transferred into the device on every rising edge of the input clocks (K and K). Accesses for both ports are initiated on the Positive Input Clock (K). All synchronous input and output timing refer to the rising edge of the Input clocks (K/K). All synchronous data inputs (D[x:0]) pass through input registers controlled by the input clocks (K and K). All synchronous data outputs (Q[x:0]) pass through output registers controlled by the rising edge of the Input clocks (K and K) as well. All synchronous control (RPS, WPS, BWS[x:0]) inputs pass through input registers controlled by the rising edge of the input clocks (K/K). CY7C1143V18 is described in the following sections. The same basic descriptions apply to CY7C1141V18, CY7C1156V18, and CY7C1145V18. Read Operations The CY7C1143V18 is organized internally as four arrays of 256K x 18. Accesses are completed in a burst of four sequential 18-bit data words. Read operations are initiated by asserting RPS active at the rising edge of the Positive Input Clock (K). The address presented to Address inputs are stored in the read address register. Following the next two K clock rise, the corresponding lowest order 18-bit word of data is driven onto the Q[17:0] using K as the output timing reference. On the subsequent rising edge of K the next 18-bit data word is driven onto the Q[17:0]. This process continues until all four 18-bit data words are driven out onto Q[17:0]. The requested data is valid 0.45 ns from the rising edge of the Input clock K or K. To maintain the internallogic, each read access must be allowed to complete. Each read access consists of four 18-bit data words and takes two clock cycles to complete. Therefore, read accesses to the device cannot be initiated on two consecutive K clock rises. The internal logic of the device ignores the second read request. Initiate read accesses on every other K clock rise. This pipelines the data flow such that data is transferred out of the device on every rising edge of the input clocks K and K. When the read port is deselected, the CY7C1143V18 first completes the pending read transactions. Synchronous internal circuitry automatically tri-states the outputs following the next rising edge of the Positive Input Clock (K). This enables for a seamless transition between devices without the insertion of wait states in a depth expanded memory. Document Number: 001-06583 Rev. *C When deselected, the write port ignores all inputs after the pending write operations are completed. Byte Write Operations Byte Write operations are supported by the CY7C1143V18. A write operation is initiated as described in the Write Operations. The bytes that are written are determined by BWS0 and BWS1, which are sampled with each set of 18-bit data words. Asserting the appropriate Byte Write Select input during the data portion of a write enables the data being presented to be latched and written into the device. Deasserting the Byte Write Select input during the data portion of a write enables the data stored in the device for that byte to remain unaltered. Use this feature to simplify read/modify/write operations to a Byte Write operation. Concurrent Transactions The read and write ports on the CY7C1143V18 operate independently of one another. Because each port latches the address inputs on different clock edges, the user can read or write to any location, regardless of the transaction on the other port. If the ports access the same location when a read follows a write in successive clock cycles, the SRAM delivers the most recent information associated with the specified address location. This includes forwarding data from a write cycle that was initiated on the previous K clock rise. Read accesses and write access must be scheduled such that one transaction is initiated on any clock cycle. If both ports are selected on the same K clock rise, the arbitration depends on the previous state of the SRAM. If both ports were deselected, the read port takes priority. If a read was initiated on the previous cycle, the write port is based on priority (since read operations cannot be initiated on consecutive cycles). If a write was initiated on the previous cycle, the read port is based on priority (since write operations cannot be initiated on consecutive cycles). Therefore, asserting both port selects active from a deselected state results in alternating read/write operations initiated, with the first access being a read. Page 8 of 28 [+] Feedback CY7C1141V18 CY7C1156V18 CY7C1143V18 CY7C1145V18 Depth Expansion The CY7C1143V18 has a Port Select input for each port. This enables easy depth expansion. Both Port Selects are sampled on the rising edge of the Positive Input Clock only (K). Each port select input can deselect the specified port. Deselecting a port does not affect the other port. All pending transactions (read and write) are completed before the device is deselected. Programmable Impedance An external resistor, RQ, must be connected between the ZQ pin on the SRAM and VSS to enable the SRAM to adjust its output driver impedance. The value of RQ must be 5X the value of the intended line impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching with a tolerance of ±15% is between 175Ω and 350Ω, with VDDQ = 1.5V. The output impedance is adjusted every 1024 cycles upon power up to account for drifts in supply voltage and temperature. Echo Clocks Echo clocks are provided on the QDR-II+ to simplify data capture on high speed systems. Two echo clocks are generated by the QDR-II+. CQ is referenced with respect to K and CQ is referenced with respect to K. These are free running Document Number: 001-06583 Rev. *C clocks and are synchronized to the input clock of the QDR-II+. The timings for the echo clocks are shown in the AC timing table. Valid Data Indicator (QVLD) QVLD is provided on the QDR-II+ to simplify data capture on high speed systems. The QVLD is generated by the QDR-II+ device along with data output. This signal is also edge-aligned with the echo clock and follows the timing of any data pin. This signal is asserted half a cycle before valid data arrives. DLL These chips use a Delay Lock Loop (DLL) that is designed to function between 120 MHz and the specified maximum clock frequency. The DLL may be disabled by applying ground to the DOFF pin. When the DLL is turned off, the device behaves in QDR-I mode (with 1.0 cycle latency and a longer access time). For more information, refer to the application note, “DLL Considerations in QDRII/DDRII/QDRII+/DDRII+”. The DLL can also be reset by slowing or stopping the input clocks K and K for a minimum of 30 ns. However, it is not necessary for the DLL to be reset to lock to the desired frequency. During power up, when the DOFF is tied HIGH, the DLL gets locked after 2048 cycles of stable clock. Page 9 of 28 [+] Feedback CY7C1141V18 CY7C1156V18 CY7C1143V18 CY7C1145V18 Application Example Figure 1 shows the four QDR-II+ used in an application. Figure 1. Appliation Example ZQ CQ/CQ SRAM #1 Q D A RPS WPS BWS K K Vt R RQ = 250ohms ZQ CQ/CQ SRAM #4 Q RPS WPS BWS K K D A DATA IN DATA OUT Address R R BUS MASTER RPS (CPU or ASIC) WPS RQ = 250ohms Vt Vt BWS CLKIN/CLKIN Source K Source K R = 50ohms, Vt = VDDQ /2 Truth Table The truth table for the CY7C1141V18, CY7C1156V18, CY7C1143V18, and CY7C1145V18 follows.[2, 3, 4, 5, 6, 7] Operation K RPS WPS DQ DQ DQ DQ Write Cycle: Load address on the rising edge of K; input write data on two consecutive K and K rising edges L-H H[8] Read Cycle: (2.0 cycle Latency) Load address on the rising edge of K; wait one and a half cycle; read data on two consecutive K and K rising edges L-H L[9] X Q(A) at K(t + 2) ↑ Q(A + 1) at K(t + 2) ↑ Q(A + 2) at K(t + 3)↑ Q(A + 3) at K(t + 3) ↑ NOP: No Operation L-H H H D=X Q = High-Z D=X Q = High-Z D=X Q = High-Z D=X Q = High-Z Stopped X X Previous State Previous State Previous State Previous State Standby: Clock Stopped L[9] D(A) at K(t + 1) ↑ D(A + 1) at K(t + 1) ↑ D(A + 2) at K(t + 2) ↑ D(A + 3) at K(t + 2) ↑ Notes 2. X = “Don't Care,” H = Logic HIGH, L = Logic LOW, ↑ represents rising edge. 3. Device powers up deselected and the outputs in a tri-state condition. 4. “A” represents address location latched by the devices when transaction was initiated. A + 1, A + 2, and A + 3 represents the address sequence in the burst. 5. “t” represents the cycle at which a Read/Write operation is started. t + 1, t + 2, and t + 3 are the first, second, and third clock cycles respectively succeeding the “t” clock cycle. 6. Data inputs are registered at K and K rising edges. Data outputs are delivered on K and K rising edges. 7. IDo K = K = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically. 8. If this signal was LOW to initiate the previous cycle, this signal becomes a “Don’t Care” for this operation. 9. This signal was HIGH on previous K clock rise. Initiating consecutive read or write operations on consecutive K clock rises is not permitted. The device ignores the second read orwrite request. Document Number: 001-06583 Rev. *C Page 10 of 28 [+] Feedback CY7C1141V18 CY7C1156V18 CY7C1143V18 CY7C1145V18 Write Cycle Descriptions The write cycle descriptions of CY7C1141V18 and CY7C1143V18 follows. [2, 10] BWS0/ BWS1/ K K L L–H – L L – L H L–H L H – H L L–H H L – H H L–H H H – NWS0 NWS1 L Comments During the data portion of a write sequence : CY7C1141V18 − both nibbles (D[7:0]) are written into the device, CY7C1143V18 − both bytes (D[17:0]) are written into the device. L-H During the data portion of a write sequence : CY7C1141V18 − both nibbles (D[7:0]) are written into the device, CY7C1143V18 − both bytes (D[17:0]) are written into the device. – During the data portion of a write sequence : CY7C1141V18 − only the lower nibble (D[3:0]) is written into the device, D[7:4] remains unaltered. CY7C1143V18 − only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered. L–H During the data portion of a write sequence : CY7C1141V18 − only the lower nibble (D[3:0]) is written into the device, D[7:4] remains unaltered. CY7C1143V18 − only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered. – During the data portion of a write sequence : CY7C1141V18 − only the upper nibble (D[7:4]) is written into the device, D[3:0] remains unaltered. CY7C1143V18 − only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered. L–H During the data portion of a write sequence : CY7C1141V18 − only the upper nibble (D[7:4]) is written into the device, D[3:0] remains unaltered. CY7C1143V18 − only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered. – No data is written into the devices during this portion of a write operation. L–H No data is written into the devices during this portion of a write operation. The write cycle descriptions of CY7C1156V18 follows.[2, 10] BWS0 K K L L–H – During the data portion of a write sequence, the single byte (D[8:0]) is written into the device. L – L–H During the data portion of a write sequence, the single byte (D[8:0]) is written into the device. H L–H – No data is written into the device during this portion of a write operation. H – L–H No data is written into the device during this portion of a write operation. Note 10. Is based on a Write cycle was initiated in accordance with the Write Cycle Description Truth Table. Alter NWS0, NWS1, BWS0, BWS1, BWS2, and BWS3 on different portions of a Write cycle, as long as the setup and hold requirements are achieved. Document Number: 001-06583 Rev. *C Page 11 of 28 [+] Feedback CY7C1141V18 CY7C1156V18 CY7C1143V18 CY7C1145V18 The write cycle descriptions of CY7C1145V18 follows.[2, 10] BWS0 BWS1 BWS2 BWS3 K K Comments L L L L L–H – During the data portion of a write sequence, all four bytes (D[35:0]) are written into the device. L L L L – L H H H L–H L H H H – H L H H L–H H L H H – H H L H L–H H H L H – H H H L L–H H H H L – H H H H L–H H H H H – Document Number: 001-06583 Rev. *C L–H During the data portion of a write sequence, all four bytes (D[35:0]) are written into the device. – During the data portion of a write sequence, only the lower byte (D[8:0]) is written into the device. D[35:9] remains unaltered. L–H During the data portion of a write sequence, only the lower byte (D[8:0]) is written into the device. D[35:9] remains unaltered. – During the data portion of a write sequence, only the byte (D[17:9]) is written into the device. D[8:0] and D[35:18] remains unaltered. L–H During the data portion of a write sequence, only the byte (D[17:9]) is written into the device. D[8:0] and D[35:18] remains unaltered. – During the data portion of a write sequence, only the byte (D[26:18]) is written into the device. D[17:0] and D[35:27] remains unaltered. L–H During the data portion of a write sequence, only the byte (D[26:18]) is written into the device. D[17:0] and D[35:27] remains unaltered. – During the data portion of a write sequence, only the byte (D[35:27]) is written into the device. D[26:0] remains unaltered. L–H During the data portion of a write sequence, only the byte (D[35:27]) is written into the device. D[26:0] remains unaltered. – No data is written into the device during this portion of a write operation. L–H No data is written into the device during this portion of a write operation. Page 12 of 28 [+] Feedback CY7C1141V18 CY7C1156V18 CY7C1143V18 CY7C1145V18 IEEE 1149.1 Serial Boundary Scan (JTAG) These SRAMs incorporate a serial boundary scan test access port (TAP) in the FBGA package. This part is fully compliant with IEEE Standard #1149.1-2001. The TAP operates using JEDEC standard 1.8V IO logic levels. Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be connected to VDD through a pull up resistor. TDO must be left unconnected. Upon power up, the device comes up in a reset state which does not interfere with the operation of the device. Test Access Port—Test Clock The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. Test Mode Select The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this pin unconnected if the TAP is not used. The pin is pulled up internally, resulting in a logic HIGH level. Test Data-In (TDI) The TDI pin is used to serially input information into the registers and connect to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information about loading the instruction register, see “TAP Controller State Diagram” on page 15 TDI is internally pulled up and unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSb) on any register. Instruction Register Serially load three-bit instructions into the instruction register. This register is loaded when it is placed between the TDI and TDO pins as shown in “TAP Controller Block Diagram” on page 16. Upon power up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section. When the TAP controller is in the Capture IR state, the two least significant bits are loaded with a binary “01” pattern to enable for fault isolation of the board level serial test path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between TDI and TDO pins. This enables data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Boundary Scan Register The boundary scan register is connected to all of the input and output pins on the SRAM. Several no connect (NC) pins are also included in the scan register to reserve pins for higher density devices. The boundary scan register is loaded with the contents of the RAM input and output ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO pins when the controller is moved to the Shift-DR state. Use the EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions to capture the contents of the input and output ring. The “Boundary Scan Order” on page 19 shows the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSb of the register is connected to TDI, and the LSb is connected to TDO. Test Data-Out (TDO) Identification (ID) Register The TDO output pin is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine (see “Instruction Codes” on page 18). The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSb) of any register. The ID register is loaded with a vendor-specific 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in the “Identification Register Definitions” on page 18. Performing a TAP Reset A Reset is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating. At power up, the TAP is reset internally to ensure that TDO comes up in a high-Z state. TAP Instruction Set TAP Registers Eight different instructions are possible with the three-bit instruction register. All combinations are listed in the “Instruction Codes” on page 18. Three of these instructions are listed as RESERVED and must not be used. The other five instructions are described in this section. Registers are connected between the TDI and TDO pins and enable data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction registers. Data is serially loaded into the TDI pin on the rising edge of TCK. Data is output on the TDO pin on the falling edge of TCK. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO pins. To execute the instruction after it is shifted in, the TAP controller must be moved into the Update-IR state. IDCODE The IDCODE instruction causes a vendor-specific 32-bit code to be loaded into the instruction register. It also places the Document Number: 001-06583 Rev. *C Page 13 of 28 [+] Feedback CY7C1141V18 CY7C1156V18 CY7C1143V18 CY7C1145V18 instruction register between the TDI and TDO pins and enables the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register upon power up or whenever the TAP controller is supplied a test logic reset state. SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO pins when the TAP controller is in a Shift-DR state. The SAMPLE Z command puts the output bus into a High-Z state until the next command is supplied during the Update IR state. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required—that is, while data captured is shifted out, shift the preloaded data in. BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. EXTEST The EXTEST instruction enables the preloaded data to be driven out through the system output pins. This instruction also selects the boundary scan register to be connected for serial access between the TDI and TDO in the shift-DR controller state. EXTEST OUTPUT BUS TRI-STATE IEEE Standard 1149.1 mandates that the TAP controller be able to put the output bus into a tri-state mode. The user must be aware that the TAP controller clock can only operate at a frequency up to 20 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output undergoes a transition. The TAP may then try to capture a signal while in transition (metastable state). This does not harm the device, but there is no guarantee as to the value that is captured. Repeatable results may not be possible. The boundary scan register has a special bit located at bit number 47. When this scan cell, called the “extest output bus tri-state”, is latched into the preload register during the Update-DR state in the TAP controller, it directly controls the state of the output (Q-bus) pins, when the EXTEST is entered as the current instruction. When HIGH, it enables the output buffers to drive the output bus. When LOW, this bit places the output bus into a High-Z condition. To guarantee that the boundary scan register captures the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller's capture setup plus hold times (tCS and tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK captured in the boundary scan register. Set this bit by entering the SAMPLE/PRELOAD or EXTEST command, and then shifting the desired bit into that cell, during the Shift-DR state. During Update-DR, the value loaded into that shift-register cell latches into the preload register. When the EXTEST instruction is entered, this bit directly controls the output Q-bus pins. Note that this bit is preset HIGH to enable the output when the device is powered up, and also when the TAP controller is in the Test-Logic-Reset state. After the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. Reserved PRELOAD enables an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells before the selection of another boundary scan test operation. Document Number: 001-06583 Rev. *C These instructions are not implemented but are reserved for future use. Do not use these instructions. Page 14 of 28 [+] Feedback CY7C1141V18 CY7C1156V18 CY7C1143V18 CY7C1145V18 TAP Controller State Diagram Figure 2. Tap Controller State Diagram[11] 1 TEST-LOGIC RESET 0 0 TEST-LOGIC/ IDLE 1 1 SELECT DR-SCAN SELECT IR-SCAN 0 0 1 1 CAPTURE-DR CAPTURE-IR 0 0 0 SHIFT-DR 1 1 EXIT1-DR 1 EXIT1-IR 0 0 PAUSE-DR 0 0 PAUSE-IR 1 1 0 EXIT2-DR EXIT2-IR 1 1 UPDATE-DR 1 0 SHIFT-IR 1 0 1 0 UPDATE-IR 1 0 Note 11. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document Number: 001-06583 Rev. *C Page 15 of 28 [+] Feedback CY7C1141V18 CY7C1156V18 CY7C1143V18 CY7C1145V18 TAP Controller Block Diagram Figure 3. Tap Controller Block Diagram 0 Bypass Register Selection Circuitry TDI 2 1 0 1 0 Instruction Register 31 30 29 . . 2 Selection Circuitry TDO Identification Register 106 . . . . 2 1 0 Boundary Scan Register TCK TMS TAP Controller TAP Electrical Characteristics The Tap Electrical Characteristics table over the operating range follows.[12, 13, 14] Parameter Description Test Conditions Min Max Unit VOH1 Output HIGH Voltage IOH = −2.0 mA 1.4 V VOH2 Output HIGH Voltage IOH = −100 µA 1.6 V VOL1 Output LOW Voltage IOL = 2.0 mA 0.4 V VOL2 Output LOW Voltage IOL = 100 µA 0.2 V VIH Input HIGH Voltage VIL Input LOW Voltage IX Input and Output Load Current 0.65 VDD VDD + 0.3 GND ≤ VI ≤ VDD V –0.3 0.35 VDD V –5 5 µA Notes 12. These characteristic pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics table. 13. Overshoot: VIH(AC) < VDDQ + 0.35V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > −0.3V (Pulse width less than tCYC/2). 14. All voltage refer to ground. Document Number: 001-06583 Rev. *C Page 16 of 28 [+] Feedback CY7C1141V18 CY7C1156V18 CY7C1143V18 CY7C1145V18 TAP AC Switching Characteristics The Tap AC Switching Characteristics over the operating range follows. [15, 16] Parameter Description Min Max Unit tTCYC TCK Clock Cycle Time 50 ns tTF TCK Clock Frequency tTH TCK Clock HIGH 20 ns tTL TCK Clock LOW 20 ns tTMSS TMS Setup to TCK Clock Rise 5 ns tTDIS TDI Setup to TCK Clock Rise 5 ns tCS Capture Setup to TCK Rise 5 ns tTMSH TMS Hold after TCK Clock Rise 5 ns tTDIH TDI Hold after Clock Rise 5 ns tCH Capture Hold after Clock Rise 5 ns 20 MHz Setup Times Hold Times Output Times tTDOV TCK Clock LOW to TDO Valid tTDOX TCK Clock LOW to TDO Invalid 10 ns 0 ns TAP Timing and Test Condition The Tap Timing and Test Conditions for the CY7C1141V18, CY7C1156V18, CY7C1143V18, and CY7C1145V18 follows.[16] Figure 4. Tap Timing and Test Condition 0.9V ALL INPUT PULSES 50Ω 1.8V 0.9V TDO 0V Z0 = 50Ω (a) CL = 20 pF tTH GND tTL Test Clock TCK tTMSH tTMSS tTCYC Test Mode Select TMS tTDIS tTDIH Test Data In TDI Test Data Out TDO tTDOV tTDOX Notes 15. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register. 16. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns. Document Number: 001-06583 Rev. *C Page 17 of 28 [+] Feedback CY7C1141V18 CY7C1156V18 CY7C1143V18 CY7C1145V18 Identification Register Definitions Instruction Field Value CY7C1141V18 CY7C1156V18 CY7C1143V18 CY7C1145V18 000 000 000 000 Revision Number (31:29) Description Version number. Cypress Device ID 11010010101000101 11010010101001101 11010010101010101 11010010101100101 Defines the type of (28:12) SRAM. Cypress JEDEC ID (11:1) 00000110100 00000110100 00000110100 00000110100 1 1 1 1 ID Register Presence (0) Enables unique identification of SRAM vendor. Indicates the presence of an ID register. Scan Register Sizes Register Name Bit Size Instruction 3 Bypass 1 ID 32 Boundary Scan 107 Instruction Codes Instruction Code Description EXTEST 000 Captures the input and output ring contents. IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operation. SAMPLE Z 010 Captures the input and output contents. Places the boundary scan register between TDI and TDO. This forces all SRAM output drivers to a High-Z state. RESERVED 011 Do Not Use: This instruction is reserved for future use. SAMPLE/PRELOAD 100 Captures the input and output ring contents. Places the boundary scan register between TDI and TDO. This operation does not affect the SRAM operation. RESERVED 101 Do not use: this instruction is reserved for future use. RESERVED 110 Do not use: this instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operation. Document Number: 001-06583 Rev. *C Page 18 of 28 [+] Feedback CY7C1141V18 CY7C1156V18 CY7C1143V18 CY7C1145V18 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 1 6P 27 11H 54 7B 81 3G 28 10G 55 6B 82 2G 2 6N 29 9G 56 6A 83 1J 3 7P 30 11F 57 5B 84 2J 4 7N 31 11G 58 5A 85 3K 5 7R 32 9F 59 4A 86 3J 6 8R 33 10F 60 5C 87 2K 7 8P 34 11E 61 4B 88 1K 8 9R 35 10E 62 3A 89 2L 9 11P 36 10D 63 1H 90 3L 10 10P 37 9E 64 1A 91 1M 11 10N 38 10C 65 2B 92 1L 12 9P 39 11D 66 3B 93 3N 13 10M 40 9C 67 1C 94 3M 14 11N 41 9D 68 1B 95 1N 15 9M 42 11B 69 3D 96 2M 16 9N 43 11C 70 3C 97 3P 17 11L 44 9B 71 1D 98 2N 18 11M 45 10B 72 2C 99 2P 19 9L 46 11A 73 3E 100 1P 20 10L 47 Internal 74 2D 101 3R 21 11K 48 9A 75 2E 102 4R 22 10K 49 8B 76 1E 103 4P 23 9J 50 7C 77 2F 104 5P 24 9K 51 6C 78 3F 105 5N 25 10J 52 8A 79 1G 106 5R 26 11J 53 7A 80 1F Document Number: 001-06583 Rev. *C Page 19 of 28 [+] Feedback CY7C1141V18 CY7C1156V18 CY7C1143V18 CY7C1145V18 Power Up Sequence in QDR-II+ SRAM During Power Up, when the DOFF is tied HIGH, the DLL gets locked after 2048 cycles of stable clock. QDR-II+ SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. Power Up Sequence ■ Apply power with DOFF tied HIGH (all other inputs can be HIGH or LOW) DLL Constraints ■ DLL uses K clock as its synchronizing input. The input must have low phase jitter, which is specified as tKC Var. ■ The DLL functions at frequencies down to 120 MHz. ■ If the input clock is unstable and the DLL is enabled, then the DLL may lock onto an incorrect frequency, causing unstable SRAM behavior. To avoid this, provide 2048 cycles stable clock to relock to the desired clock frequency. — Apply VDD before VDDQ — Apply VDDQ before VREF or at the same time as VREF ■ Provide stable power and clock (K, K) for 2048 cycles to lock the DLL Power Up Waveforms ~ ~ Figure 5. Power Up Waveforms K ~ ~ K Unstable Clock > 2048 Stable Clock Start Normal Operation Clock Start (Clock Starts after VDD/VDDQ is Stable) VDD/VDDQ DOFF Document Number: 001-06583 Rev. *C VDD/VDDQ Stable (< + 0.1V DC per 50 ns) Fix HIGH (tie to VDDQ) Page 20 of 28 [+] Feedback CY7C1141V18 CY7C1156V18 CY7C1143V18 CY7C1145V18 Maximum Ratings Current into Outputs (LOW)......................................... 20 mA Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Storage Temperature ................................ –65°C to + 150°C Ambient Temperature with Power Applied. –55°C to + 125°C Static Discharge Voltage (MIL-STD-883, M. 3015).. > 2001V Latch up Current.................................................... > 200 mA Operating Range Supply Voltage on VDD Relative to GND .......–0.5V to + 2.9V Supply Voltage on VDDQ Relative to GND ..... –0.5V to + VDD DC Applied to Outputs in High-Z ........ –0.5V to VDDQ + 0.3V DC Input Voltage[13] .............................–0.5V to VDDQ + 0.3V Range Commercial Industrial Ambient Temperature (TA) VDD[17] VDDQ[17] 0°C to +70°C 1.8 ± 0.1V 1.4V to VDD –40°C to +85°C Electrical Characteristics The DC Electrical Characteristics over the operating range follows. [14] Parameter Description VDD Power Supply Voltage VDDQ IO Supply Voltage VOH Output HIGH Voltage VOL VOH(LOW) Test Conditions Min Typ Max Unit 1.7 1.8 1.9 V 1.4 1.5 VDD V Note 18 VDDQ/2 – 0.12 VDDQ/2 + 0.12 V Output LOW Voltage Note 19 VDDQ/2 – 0.12 VDDQ/2 + 0.12 V Output HIGH Voltage IOH = −0.1 mA, Nominal Impedance VDDQ – 0.2 VDDQ V VOL(LOW) Output LOW Voltage IOL = 0.1 mA, Nominal Impedance VIH Input HIGH Voltage VIL Input LOW Voltage IX Input Leakage Current GND ≤ VI ≤ VDDQ IOZ Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled VREF Input Reference Voltage[20] Typical Value = 0.75V IDD VDD Operating Supply ISB1 Automatic Power Down Current VSS 0.2 V VREF + 0.1 VDDQ + 0.15 V –0.15 VREF – 0.1 V −2 2 µA 2 µA 0.95 V VDD = Max, IOUT = 0 mA, 300 MHz f = fmax = 1/tCYC 333 MHz 663 mA 708 mA 375 MHz 766 mA 300 MHz 201 mA 333 MHz 212 mA 375 MHz 227 mA Max VDD, Both Ports Deselected, VIN ≥ VIH or VIN ≤ VIL f = fmax =1/tCYC, Inputs Static −2 0.68 0.75 AC Electrical Characteristics The AC Electrical Characteristics over the operating range follows.[13] Parameter Description Test Conditions Min Typ Max Unit VIH Input HIGH Voltage VREF + 0.2 – VDDQ + 0.24 V VIL Input LOW Voltage –0.24 – VREF – 0.2 V Notes 17. Power up: Is based on a linear ramp from 0V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD. 18. Output are impedance controlled. IOH = −(VDDQ/2)/(RQ/5) for values of 175Ω <= RQ <= 350Ω. 19. Output are impedance controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175Ω <= RQ <= 350Ω. 20. VREF(min) = 0.68V or 0.46VDDQ, whichever is larger, VREF(max) = 0.95V or 0.54 VDDQ, whichever is smaller. Document Number: 001-06583 Rev. *C Page 21 of 28 [+] Feedback CY7C1141V18 CY7C1156V18 CY7C1143V18 CY7C1145V18 Capacitance Tested initially and after any design or process change that may affect these parameters. Parameter Description Test Conditions CIN Input Capacitance CCLK Clock Input Capacitance CO Output Capacitance TA = 25°C, f = 1 MHz, VDD = 1.8V VDDQ = 1.5V Max Unit 5 pF 6 pF 7 pF 165 FBGA Package Unit 13.48 °C/W 4.15 °C/W Thermal Resistance Tested initially and after any design or process change that may affect these parameters. Parameter Description ΘJA Thermal Resistance (junction to ambient) ΘJC Thermal Resistance (junction to case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with EIA/JESD51. AC Test Loads and Waveforms Figure 6. AC Test Loads and Waveforms VREF = 0.75V VREF 0.75V VREF OUTPUT Z0 = 50Ω Device Under Test ZQ RL = 50Ω VREF = 0.75V R = 50Ω ALL INPUT PULSES 1.25V 0.75V OUTPUT Device Under Test ZQ RQ = 250Ω (a) 0.75V INCLUDING JIG AND SCOPE 5 pF [21] 0.25V Slew Rate = 2 V/ns RQ = 250Ω (b) Notes 21. Unless otherwise noted, test conditions are based on signal transition time of 2V/ns, timing reference levels of 0.75V, Vref = 0.75V, RQ = 250Ω, VDDQ = 1.5V, input pulse levels of 0.25V to 1.25V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of AC Test Loads. Document Number: 001-06583 Rev. *C Page 22 of 28 [+] Feedback CY7C1141V18 CY7C1156V18 CY7C1143V18 CY7C1145V18 Switching Characteristics Over the operating range[21, 22] Cypress Consortium Parameter Parameter Description VDD(Typical) to the First Access[23] tPOWER 375 MHz 333 MHz 300 MHz Min Max Min Max Min Max 1 – tCYC tKHKH K Clock Cycle Time 2.66 8.40 tKH tKHKL Input Clock (K/K) HIGH 0.425 tKL tKLKH Input Clock (K/K) LOW tKHKH tKHKH K Clock Rise to K Clock Rise (rising edge to rising edge) 1 – 1 – Unit ms 3.0 8.40 3.3 8.40 ns – 0.425 – 0.425 – tCYC 0.425 – 0.425 – 0.425 – tCYC 1.13 – 1.28 – 1.40 – ns Setup Times tSA tAVKH Address Setup to K Clock Rise 0.4 – 0.4 – 0.4 – ns tSC tIVKH Control Setup to K Clock Rise (RPS, WPS) 0.4 – 0.4 – 0.4 – ns tSCDDR tIVKH Double Data Rate Control Setup to Clock (K, K) Rise (BWS0, BWS1, BWS2, BWS3) 0.28 – 0.28 – 0.28 – ns tSD tDVKH D[X:0] Setup to Clock (K/K) Rise 0.28 – 0.28 – 0.28 – ns 0.4 – 0.4 – 0.4 – ns Hold Times tHA tKHAX Address Hold after K Clock Rise tHC tKHIX Control Hold after K Clock Rise (RPS, WPS) 0.4 – 0.4 – 0.4 – ns tHCDDR tKHIX Double Data Rate Control Hold after Clock (K/K) Rise (BWS0, BWS1, BWS2, BWS3) 0.28 – 0.28 – 0.28 – ns tHD tKHDX D[X:0] Hold after Clock (K/K) Rise 0.28 – 0.28 – 0.28 – ns Output Times tCO tCHQV K/K Clock Rise to Data Valid tDOH tCHQX Data Output Hold after Output K/K Clock Rise (Active to Active) tCCQO tCHCQV K/K Clock Rise to Echo Clock Valid tCQOH tCHCQX Echo Clock Hold after K/K Clock Rise tCQD tCQHQV Echo Clock High to Data Valid 0.2 ns tCQDOH tCQHQX Echo Clock High to Data Invalid –0.2 – –0.2 – –0.2 – ns tCQH tCQHCQL Output Clock (CQ/CQ) HIGH[24] 0.88 – 1.03 – 1.15 – ns tCQHCQH tCQHCQH 0.88 – 1.03 – 1.15 – ns tCHZ tCHQZ CQ Clock Rise to CQ Clock Rise[24] (rising edge to rising edge) Clock (K/K) Rise to High-Z (Active to High-Z)[25, 26] – 0.45 – 0.45 – 0.45 ns tCLZ tCHQX1 Clock (K/K) Rise to Low-Z[25, 26] –0.45 – –0.45 – –0.45 – ns tQVLD tQVLD Echo Clock High to QVLD Valid[27] –0.20 0.20 –0.20 0.20 –0.20 0.20 – 0.45 – 0.45 – 0.45 ns –0.45 – –0.45 – –0.45 – ns – 0.45 – 0.45 – 0.45 ns –0.45 – –0.45 – –0.45 – ns 0.2 0.2 ns DLL Timing tKC Var tKC Var Clock Phase Jitter – 0.20 – 0.20 – 0.20 ns tKC lock tKC lock DLL Lock Time (K) 2048 – 2048 – 2048 – Cycles tKC Reset tKC Reset 30 – 30 – 30 – ns K Static to DLL Reset[28] Notes 22. When a part with a maximum frequency above 300 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is being operated and outputs data with the output timings of that frequency range. 23. This part has a voltage regulator internally; tPOWER is the time that the power must be supplied above VDD minimum initially before a Read or Write operation can be initiated. 24. These parameters are extrapolated from the input timing parameters (tKHKH – 250 ps, where 250 ps is the internal jitter. An input jitter of 200 ps (tKC Var) is already included in the tKHKH). These parameters are only guaranteed by design and are not tested in production 25. tCHZ, tCLZ are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 100 mV from steady-state voltage. 26. At any given voltage and temperature tCHZ is less than tCLZ and tCHZ less than tCO. 27. tQVLD spec is applicable for both rising and falling edges of QVLD signal. 28. Hold to >VIH or <VIL. Document Number: 001-06583 Rev. *C Page 23 of 28 [+] Feedback CY7C1141V18 CY7C1156V18 CY7C1143V18 CY7C1145V18 Switching Waveforms Read/Write/Deselect Sequence Figure 7. Waveform for 2.0 Cycle Read Latency [29, 30, 31] NOP 1 WRITE 3 READ 2 READ 4 NOP 6 WRITE 5 7 8 K t KH t CYC t KL t KHKH K RPS tHC t SC t SC t HC WPS A A0 t SA A1 A3 A2 t HD t HA t SD D t HD t SD D10 D11 D12 D13 D30 D31 D32 D33 t QVLD t QVLD QVLD t tDOH t CLZ Q CO Q00 (Read Latency = 2.0 Cycles) tCQDOH tCQD Q01 Q02 Q03 Q20 Q21 Q22 tCHZ Q23 tCCQO tCQOH CQ t CQH t CQHCQH tCQOH t CCQO CQ DON’T CARE UNDEFINED Notes 29. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, i.e., A0+1. 30. Outputs are disabled (High-Z) one clock cycle after a NOP. 31. In this example, if address A2 = A1, then data Q20 = D10 and Q21 = D11. Write data is forwarded immediately as read results. This note applies to the whole diagram. Document Number: 001-06583 Rev. *C Page 24 of 28 [+] Feedback CY7C1141V18 CY7C1156V18 CY7C1143V18 CY7C1145V18 Ordering Information Not all of the speed, package and temperature ranges are available. Contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) 375 Ordering Code CY7C1141V18-375BZC Package Diagram Package Type 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Operating Range Commercial CY7C1156V18-375BZC CY7C1143V18-375BZC CY7C1145V18-375BZC CY7C1141V18-375BZXC 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free CY7C1156V18-375BZXC CY7C1143V18-375BZXC CY7C1145V18-375BZXC CY7C1141V18-375BZI 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Industrial CY7C1156V18-375BZI CY7C1143V18-375BZI CY7C1145V18-375BZI CY7C1141V18-375BZXI 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free CY7C1156V18-375BZXI CY7C1143V18-375BZXI CY7C1145V18-375BZXI 333 CY7C1141V18-333BZC 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Commercial CY7C1156V18-333BZC CY7C1143V18-333BZC CY7C1145V18-333BZC CY7C1141V18-333BZXC 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free CY7C1156V18-333BZXC CY7C1143V18-333BZXC CY7C1145V18-333BZXC CY7C1141V18-333BZI 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Industrial CY7C1156V18-333BZI CY7C1143V18-333BZI CY7C1145V18-333BZI CY7C1141V18-333BZXI 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free CY7C1156V18-333BZXI CY7C1143V18-333BZXI CY7C1145V18-333BZXI Document Number: 001-06583 Rev. *C Page 25 of 28 [+] Feedback CY7C1141V18 CY7C1156V18 CY7C1143V18 CY7C1145V18 Ordering Information (continued) Not all of the speed, package and temperature ranges are available. Contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) 300 Ordering Code CY7C1141V18-300BZC Package Diagram Package Type 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Operating Range Commercial CY7C1156V18-300BZC CY7C1143V18-300BZC CY7C1145V18-300BZC CY7C1141V18-300BZXC 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free CY7C1156V18-300BZXC CY7C1143V18-300BZXC CY7C1145V18-300BZXC CY7C1141V18-300BZI 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Industrial CY7C1156V18-300BZI CY7C1143V18-300BZI CY7C1145V18-300BZI CY7C1141V18-300BZXI 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free CY7C1156V18-300BZXI CY7C1143V18-300BZXI CY7C1145V18-300BZXI Document Number: 001-06583 Rev. *C Page 26 of 28 [+] Feedback CY7C1141V18 CY7C1156V18 CY7C1143V18 CY7C1145V18 Package Diagram Figure 8. 165-Ball FBGA (13 x 15 x 1.4 mm), 51-85180 BOTTOM VIEW PIN 1 CORNER TOP VIEW Ø0.05 M C Ø0.25 M C A B PIN 1 CORNER Ø0.50 -0.06 (165X) +0.14 1 2 3 4 5 6 7 8 9 10 11 11 9 8 7 6 5 4 3 2 1 A B B C C 1.00 A D D E F F G G H J 14.00 E 15.00±0.10 15.00±0.10 10 H J K L L 7.00 K M M N N P P R R A A 1.00 5.00 10.00 B B 13.00±0.10 13.00±0.10 1.40 MAX. 0.15 C 0.53±0.05 0.25 C 0.15(4X) NOTES : SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD) PACKAGE WEIGHT : 0.475g JEDEC REFERENCE : MO-216 / DESIGN 4.6C PACKAGE CODE : BB0AC 0.35±0.06 0.36 SEATING PLANE C Document Number: 001-06583 Rev. *C 51-85180-*A Page 27 of 28 [+] Feedback CY7C1141V18 CY7C1156V18 CY7C1143V18 CY7C1145V18 Document History Page Document Title: CY7C1141V18/CY7C1156V18/CY7C1143V18/CY7C1145V18, 18-Mbit QDR™-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) Document Number: 001-06583 REV. ECN No. Issue Date Orig. of Change ** 430351 See ECN NXR New data sheet *A 461654 See ECN NXR Revised the MPNs from CY7C1156BV18 to CY7C1156V18 CY7C1143BV18 to CY7C1143V18 CY7C1145BV18 to CY7C1145V18 Changed tTH and tTL from 40 ns to 20 ns, changed tTMSS, tTDIS, tCS, tTMSH, tTDIH, tCH from 10 ns to 5 ns and changed tTDOV from 20 ns to 10 ns in TAP AC Switching Characteristics table Modified Power Up waveform *B 497629 See ECN NXR Changed the VDDQ operating voltage to 1.4V to VDD in the Features section, in Operating Range table and in the DC Electrical Characteristics table Added foot note in page 1 Changed the Maximum rating of Ambient Temperature with Power Applied from –10°C to +85°C to –55°C to +125°C Changed VREF (max) spec from 0.85V to 0.95V in the DC Electrical Characteristics table and in the note below the table Updated foot note 22 to specify Overshoot and Undershoot Spec Updated ΘJA and ΘJC values Removed x9 part and its related information Updated footnote 25 *C 1167806 See ECN VKN/KKVTMP Converted from preliminary to final Added x8 and x9 parts Changed IDD values from 766 mA to 1020 mA for 375 MHz, 708 mA to 920 mA for 333 MHz, 663 mA to 850 mA for 300 MHz Changed ISB values from 227 mA to 290 mA for 375 MHz, 212 mA to 260 mA for 333 MHz, 201 mA to 250 mA for 300 MHz Changed tCYC(max) spec to 8.4 ns for all speed bins Changed ΘJA value from 13.48 °C/W to 17.2 °C/W Updated Ordering Information table Description of Change © Cypress Semiconductor Corporation, 2006-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-06583 Rev. *C Revised June 15, 2007 Page 28 of 28 QDR™ is a trademark of Cypress Semiconductor Corp. QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this document are the trademarks of their respective holders. [+] Feedback