AS6C1616 FEBRUARY 2009 January 2007 512K X 8 BI T LOW 1024K X 16 BIT LOW POWER CMOS SRAMPOWER FEATURES CMOS SRAM GENERAL DESCRIPTION The AS6C1616 is a 16,777,216-bit low power CMOS static random access memory organized as 1,048,576 words by 16 bits. It is fabricated using very high performance, high reliability CMOS technology. Its standby current is stable within the range of operating temperature. Fast access time : 55/70ns Low power consumption: Operating current : 45/30mA (TYP.) Standby current : 4μA (TYP.) SL-version Single 2.7V ~ 3.6V power supply All inputs and outputs TTL compatible Fully static operation Tri-state output Data byte control : LB# (DQ0 ~ DQ7) UB# (DQ8 ~ DQ15) Data retention voltage : 1.2V (MIN.) Lead free and green package available Package : 48-ball 6mm x 8mm TFBGA The AS6C1616 is well designed for low power application, and particularly well suited for battery back-up nonvolatile memory application. The AS6C16 16 operates from a singlepower supply of 2.7V ~ 3.6V and all inputs and outputs are fully TTL compatible PRODUCT FAMILY Product Family AS6C1616(I) Operating Temperature o -40 ~ 85 C Vcc Range 2.7 ~ 3.6V FUNCTIONAL BLOCK DIAGRAM Speed 55/70ns Power Dissipation Standby(ISB1,TYP.) Operating (Icc,TYP.) 4µA 45/30mA PIN DESCRIPTION SYMBOL A0 - A19 Vcc Vss A0-A19 DQ0-DQ7 Lower Byte DQ8-DQ15 Upper Byte CE# CE2 WE# OE# LB# UB# DECODER I/O DATA CIRCUIT 1024Kx16 MEMORY ARRAY DESCRIPTION Address Inputs DQ0 – DQ15 Data Inputs/Outputs CE#, CE2 Chip Enable Input WE# Write Enable Input OE# Output Enable Input LB# Lower Byte Control UB# Upper Byte Control VCC Power Supply VSS Ground COLUMN I/O CONTROL CIRCUIT FEBRUARY/2009, V 1.a Alliance Memory Inc. Page 1 of 11 FEBRUARY 2009 January 2007 AS6C1616 512K X 8 BI T LOW 1024K X 16 BIT LOW POWER CMOS SRAMPOWER CMOS SRAM PIN CONFIGURATION A LB# OE# A0 B DQ8 UB# A3 C DQ9 DQ10 A2 CE2 A4 CE# DQ0 A5 A6 DQ1 DQ2 D Vss DQ11 A17 A7 DQ3 Vcc E Vcc DQ12 NC A16 DQ4 Vss F DQ14 DQ13 A14 A15 DQ5 DQ6 G DQ15 A19 A12 A13 WE# DQ7 A18 A8 A9 A10 1 2 3 4 TFBGA H A1 A11 NC 5 6 ABSOLUTE MAXIMUN RATINGS* PARAMETER SYMBOL Voltage on VCC relative to VSS Voltage on any other pin relative to VSS Operating Temperature Storage Temperature Power Dissipation DC Output Current Soldering Temperature (under 10 sec) VT1 V T2 TA TSTG PD 1 IOUT 50 TSOLDER 260 RATING -0.5 to 4.6 -0.5 to VCC +0.5 V -40 to 85(I grade) -65 to 150 UNIT V ℃ ℃ W mA ℃ *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability. FEBRUARY/2009, V 1.a Alliance Memory Inc. Page 2 of 11 AS6C1616 FEBRUARY 2009 January 2007 512K X 8 BI T LOW 1024K X 16 BIT LOW POWER CMOS SRAMPOWER CMOS SRAM TRUTH TABLE MODE Standby Output Disable Read Write Note: H = V IH , L = V IL , CE# H X X L L L L L L L L CE2 X L X H H H H H H H H X = Don'tcare. OE# WE# X X X H H L L L X X X X X X H H H H H L L L LB# X X H L X L H L L H L UB# X X H X L H L L H L L I/O OPERATION DQ0-DQ7 DQ8-DQ15 High – Z High – Z High – Z High – Z High – Z High – Z High – Z High – Z High – Z High – Z High – Z DOUT High – Z DOUT DOUT DOUT High – Z DIN High – Z DIN DIN DIN SUPPLY CURRENT ISB,I SB1 ICC ,I CC1 ICC ,I CC1 ICC ,I CC1 DC ELECTRICAL CHARACTERISTICS PARAMETER Supply Voltage Input High Voltage Input Low Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage AverageOperating Power supply Current Standby Power Supply Current SYMBOL TEST CONDITION VCC *1 VIH *2 VIL ILI V CC ≧ V IN ≧ VSS VCC ≧ V OUT ≧ VSS ILO Output Disabled VOH I OH = -1mA VOL I OL = 2mA Cycle time =Min. -55 CE# =V IL and CE2 = VIH ICC -70 II/O = 0mA Other pins at VIL or VIH Cycle time = 1µs CE#≦0.2V and CE2≧ VCC -0.2V ICC1 II/O = 0mA Other pins at 0.2V or V CC -0.2V CE# =VIH or CE2 =VIL ISB Other pins at VIL or VIH CE# VCC ≧ -0.2V ISB1 -SLI or CE2≦0.2V Other pins at 0.2V or VCC -0.2V MIN. 2.7 2.2 - 0.2 -1 TYP. 3.0 - *4 MAX. 3.6 VCC +0.3 0.6 1 UNIT V V V µA µA -1 - 1 2.2 - 2.7 - 0.4 V V 45 60 mA - 30 45 mA - 8 16 mA - 0.3 2 mA 40 µA - 6 Notes: 1. VIH(max) = VCC + 3.0V for pulse width less than 10ns. 2. VIL(min) = VSS - 3.0V for pulse width less than 10ns. 3. Over/Undershoot specifications are characterized, not 100% tested. 4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(TYP.) and TA = 25℃ FEBRUARY/2009, V 1.a Alliance Memory Inc. Page 3 of 11 FEBRUARY 2009 January 2007 AS6C1616 512K X 8 BI T LOW 1024K X 16 BIT LOW POWER CMOS SRAMPOWER CMOS SRAM TIMING WAVEFORMS READ CYCLE 1 (Address Controlled) (1,2) tRC Address tAA Dout READ CYCLE 2 tOH Previous Data Valid Data Valid (CE# and CE2 and OE# Controlled) (1,3,4,5) tRC Address tAA CE# tACE CE2 LB#,UB# tBA OE# tBLZ tCLZ Dout High-Z tOLZ tOE tOH tOHZ tBHZ tCHZ Data Valid High-Z Notes : 1.WE#is high for read cycle. 2.Device is continuously selected OE# = low, CE# = low, CE2 = high, LB# or UB# = low . 3.Address must be valid prior to or coincident with CE# = low, CE2 = high, LB# or UB# = low transition; otherwise t AA is the limiting parameter. 4.t CLZ , t BLZ, tOLZ , t CHZ, tBHZ and t OHZ are specified with C L = 5pF. Transition is measured ±500mV from steady state. 5.At any given temperature and voltage condition, t CHZ is less than t CLZ, t BHZ is less than t BLZ, t OHZ is less than t OLZ. FEBRUARY/2009, V 1.a Alliance Memory Inc. Page 5 of 11 AS6C1616 FEBRUARY 2009 January 2007 512K X 8 BI T LOW 1024K X 16 BIT LOW POWER CMOS SRAMPOWER WRITE CYCLE 1 CMOS SRAM (WE# Controlled) (1,2,3,5,6) tWC Address tAW CE# tCW CE2 tBW LB#,UB# tAS tWP tWR WE# tWHZ Dout TOW High-Z (4) tDW tDH Data Valid Din WRITE CYCLE 2 (4) (CE# an d CE2 Co ntrolled) (1,2,5,6) tWC Address tAW CE# tAS tWR tCW CE2 tBW LB#,UB# tWP WE# tWHZ Dout (4) High-Z tDW Din FEBRUARY/2009, V 1.a tDH Data Valid Alliance Memory Inc. Page 6 of 11 AS6C1616 FEBRUARY 2009 January 2007 512K X 8 BI T LOW 1024K X 16 BIT LOW POWER CMOS SRAMPOWER WRITE CYCLE 3 CMOS SRAM (LB#,UB# Controlled) (1,2,5,6) tWC Address tAW tWR CE# tCW tAS CE2 tBW LB#,UB# tWP WE# tWHZ Dout (4) High-Z tDW Din tDH Data Valid Notes : 1.WE#,CE#, LB#, UB# must be high or CE2 must be low during all address transitions. 2.A write occurs during the overlap of a low CE#, high CE2, low WE#, LB# or UB# = low. 3.During a WE# controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be placed on the bus. 4.During this period, I/O pins are in the output state, and input signals must not be applied. 5.If the CE#, LB#, UB# low transition and CE2 high transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state. 6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. FEBRUARY/2009, V 1.a Alliance Memory Inc. Page 7 of 11 AS6C1616 FEBRUARY 2009 January 2007 512K X 8 BI T LOW 1024K X 16 BIT LOW POWER CMOS SRAMPOWER CMOS SRAM DATA RETENTION CHARACTERISTICS PARAMETER SYMBOL VCC for Data Retention VDR Data Retention Current IDR Chip Disable to Data Retention Time Recovery Time tRC* = Read Cycle Time tCDR tR TEST CONDITION CE#≧ VCC - 0.2V or CE2≦0.2V VCC = 1.2V CE# ≧VCC-0.2V or CE2≦0.2V -SLI other pins at 0.2V or VCC-0.2V See Data Retention Waveforms (below) DATA RETENTION WAVEFORM Low Vcc Data Retention Waveform (1) MIN. 1.2 TYP. - MAX. 3.6 UNIT V - 4 40 µA 0 - - ns tRC* - - ns (CE# controlled) VDR ≧ 1.2V Vcc Vcc(min.) Vcc(min.) tCDR CE# VIH Low Vcc Data Retention Waveform (2) tR CE# ≧V cc-0.2V VIH (CE2 controlled) VDR ≧ 1.2V Vcc Vcc(min.) Vcc(min.) tCDR CE2 VIL Low Vcc Data Retention Waveform (3) tR CE2 ≦ 0.2V VIL (LB#, UB#ontrolled) c VDR ≧ 1.2V Vcc Vcc(min.) Vcc(min.) tCDR LB#,UB# VIH FEBRUARY/2009, V 1.a tR LB#,UB# ≧ Vcc-0.2V Alliance Memory Inc. VIH Page 8 of 11 AS6C1616 FEBRUARY 2009 January 2007 512K X 8 BI T LOW 1024K X 16 BIT LOW POWER CMOS SRAMPOWER CMOS SRAM PACKAGE OUTLINE DIMENSION 48-ball 6mm × 8mm TFBGA Package Outline Dimension FEBRUARY/2009, V 1.a Alliance Memory Inc. Page 9 of 11 FEBRUARY 2009 AS6C1616 1024K X 16 BIT LOW POWER CMOS SRAM Ordering Information Alliance Organization VCC Range Package Operating Temp Speed ns AS6C1616-70BIN 1024K x 16 2.7 - 3.6V 48ball TFBGA Industrial ~ -40 C – 85 C) 70 AS6C1616-55BIN 1024K x 16 2.7 - 3.6V 48ball TFBGA Industrial ~ -40 C – 85 C) 55 Part Numbering System AS6C 1616 low power SRAM prefix Device Number 16 = 16M 16 = x16 FEBRUARY/2009, V1.a -70 X Access Time Package Option 48ball TFBGA Alliance Memory Inc. X N Temperature Range N = Lead Free I = Industrial RoHS compliant (-40 to + 85 C) part Page 10 of 11 AS6C1616 FEBRUARY 2009 January 2007 512K X 8 BI T LOW 1024K X 16 BIT LOW POWER CMOS SRAMPOWER Alliance Memory, Inc 511 Taylor Way, San Carlos, CA 94070, USA Phone: 650-610-6800 Fax: 650-620-9211 www.alliancememory.com CMOS SRAM Copyright © Alliance Memory All Rights Reserved © Copyright 2009 Alliance Memory, Inc. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at anytime, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use. FEBRUARY/2009, V 1.a Alliance Memory Inc. Page 11 of 11