ADS61JB46 www.ti.com SBAS611B – SEPTEMBER 2013 – REVISED OCTOBER 2013 14-Bit, Input-Buffered, 160-MSPS, Analog-to-Digital Converter with JESD204A Output Interface Check for Samples: ADS61JB46 FEATURES APPLICATIONS • • • 1 2 • • • • • • • • • Output Interface: – Single-Lane and Dual-Lane Interfaces – Maximum Data Rate: 3.125 Gbps – Meets JEDEC JESD204A Specification – CML Outputs with Current Programmable from 2 mA to 32 mA Power Dissipation: – 583 mW at 160 MSPS in Dual-Lane Mode – Power Scales Down with Clock Rate Input Interface: Buffered Analog Inputs SNR at 185-MHz IF: –72.7 dBFS Analog Input Dynamic Range: 2 VPP Reference Support: External and Internal (Trimmed) Supply: – Analog and Digital: 1.8 V – Input Buffer: 3.3 V Programmable Digital Gain: 0 dB to 6 dB Output: Straight Offset Binary or Twos Complement Package: 6-mm × 6-mm QFN-40 Wireless Base-Station Infrastructures Test and Measurement Instrumentation DESCRIPTION The ADS61JB46 is a high-performance, low-power, single-channel, analog-to-digital converter with an integrated JESD204A output interface. Available in a 6-mm × 6-mm QFN package, with both single-lane and dual-lane output modes, the device offers an unprecedented level of compactness. The output interface is compatible to the JESD204A standard, with an additional mode (as per the IEEE standard 802.3-2002 part 3, clause 36.2.4.12) to interface seamlessly to the TI TLK family of SERDES transceivers. Equally impressive is the inclusion of an on-chip analog input buffer, providing isolation between the sample-and-hold switches and higher and more consistent input impedance. The device is specified over the temperature range (–40°C to +85°C). industrial 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2013, Texas Instruments Incorporated ADS61JB46 SBAS611B – SEPTEMBER 2013 – REVISED OCTOBER 2013 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ABSOLUTE MAXIMUM RATINGS (1) Supply voltage range VALUE UNIT AVDD –0.3 to +2.2 V DRVDD –0.3 to +2.2 V IOVDD –0.3 to +2.2 V AVDD_3V –0.3 to +3.9 V Voltage between AGND and DRGND Voltage applied to: –0.3 to +0.3 V External VCM pin –0.3 to +2.2 V Analog input pins –0.3 to min (3, AVDD_3V + 0.3) V Digital input pins –0.3 to AVDD + 0.3 V Clock input pins (2) Operating free-air temperature range, TA Junction temperature (1) (2) –0.3 to AVDD + 0.3 V –40 to +85 °C +105 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. When AVDD is turned off, TI recommends switching off the input clock (or ensuring the voltage on CLKP, CLKM is less than |0.3 V|). This setting prevents the electrostatic discharge (ESD) protection diodes at the clock input pins from turning on. THERMAL INFORMATION THERMAL METRIC (1) ADS61JB46 RHA (QFN) θJA Junction-to-ambient thermal resistance θJCtop Junction-to-case (top) thermal resistance 17 θJB Junction-to-board thermal resistance 5.7 ψJT Junction-to-top characterization parameter 0.2 ψJB Junction-to-board characterization parameter 5.7 θJCbot Junction-to-case (bottom) thermal resistance 1 (1) 2 UNITS 30.7 °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS61JB46 ADS61JB46 www.ti.com SBAS611B – SEPTEMBER 2013 – REVISED OCTOBER 2013 RECOMMENDED OPERATING CONDITIONS MIN TYP MAX UNIT SUPPLIES, ANALOG INPUTS, AND REFERENCE VOLTAGES AVDD Analog supply voltage 1.7 1.8 1.9 V DRVDD Digital supply voltage 1.7 1.8 1.9 V IOVDD CML buffer supply voltage 1.7 1.8 1.9 V AVDD_3V Analog buffer supply voltage 3.0 3.3 3.6 Differential input voltage range 2 Input common-mode voltage VCM (output), internal reference mode (1) VCM (input), external reference mode V VPP VCM ± 0.05 V 1.95 V 1.4 V CLOCK INPUT In JESD204A single-lane mode Input clock rate In JESD204A dual-lane mode Sine wave, ac-coupled Input clock amplitude differential (VCLKP – VCLKM) 15.625 156.3 MSPS 31.25 160 MSPS 0.2 3.0 VPP LVPECL, ac-coupled 1.6 VPP LVDS, ac-coupled 0.7 VPP CMOS, single-ended, accoupled 1.5 V Input clock duty cycle 35% 50% 65% In single-lane mode 312.5 20x (sample rate) 3125 Mbps In dual-lane mode 312.5 10x (sample rate) 1600 Mbps DIGITAL OUTPUTS Output data rate CLOAD Maximum external load capacitance from each pin to DRGND RLOAD External termination from each output pin to IOVDD TA Operating free-air temperature (1) 5 pF Ω 50 –40 +85 °C Typical VCM reduces to 1.85 V after HIGH_SFDR_MODE (register address 02h) is written. Table 1. HIGH_SFDR_MODE Summary MODE HIGH_SFDR_MODE DESCRIPTION Write register 02h, value 71h, to obtain best HD3 for input frequencies between 150 MHz to 250 MHz. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS61JB46 3 ADS61JB46 SBAS611B – SEPTEMBER 2013 – REVISED OCTOBER 2013 www.ti.com ELECTRICAL CHARACTERISTICS Typical values are at +25°C, minimum and maximum values are across the full temperature range of TMIN = –40°C to TMAX = +85°C, AVDD = 1.8 V, AVDD_3V = 3.3 V, DRVDD = 1.8 V, IOVDD = 1.8 V, clock frequency = 160 MSPS, 10x mode, 50% clock duty cycle, –1-dBFS differential analog input, internal reference mode, and CML buffer current setting = 16 mA, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT REFERENCE VOLTAGES (Internal) VCM analog input common-mode voltage (output) VCM output current (resulting in a VCM change of ±50 mV) 1.95 V 2.5 mA REFERENCE VOLTAGES (External) VCM reference voltage (input) 1.4 ± 0.1 V ANALOG INPUT Differential input voltage range 2.0 Differential input capacitance VPP 3 Analog input bandwidth pF 480 Analog input common-mode range Analog input common-mode current (per input pin) MHz VCM ± 0.05 V 1.6 µA DC ACCURACY EO Offset error –20 20 mV EGREF Gain error due to internal reference inaccuracy alone –2.5 2.5 %FS EGCHAN Gain error of channel alone 5 Gain error temperature coefficient PSRR AC power-supply rejection ratio 50-mVPP signal on AVDD supply %FS 0.006 mV/°C > 30 dB POWER-DOWN MODES Complete power-down mode 10 mW Fast recovery power-down mode 230 mW Power with no clock 115 mW ±0.6 LSB DNL Differential nonlinearity INL Integral nonlinearity –0.95 ±2 ±4.5 LSB 132 160 mA POWER-SUPPLY CURRENTS IAVDD AVDD current IAVDD_3V AVDD_3V current 42 55 mA IDRVDD DRVDD current 79 100 mA IIOVDD IOVDD current (in 10x mode) 31 40 mA 583 700 mW Total power DYNAMIC PERFORMANCE (1) (2) SFDR SNR Signal-to-noise ratio SINAD HD3 HD2 Spurious-free dynamic range Signal-to-noise and distortion ratio Third-order harmonic distortion Second-order harmonic distortion Worst spur (excluding HD2, HD3) (1) (2) 4 fIN = 10 MHz fIN = 185 MHz 75 71.5 fIN = 10 MHz fIN = 185 MHz 69.2 dBc 77 dBc 75 dBFS 72.7 dBFS fIN = 10 MHz 72.1 dBFS fIN = 185 MHz 71.5 dBFS fIN = 10 MHz fIN = 185 MHz 71.5 fIN = 10 MHz fIN = 185 MHz 71.5 fIN = 10 MHz fIN = 185 MHz 81 75 dBc 77 dBc 90 dBc 81 dBc 95 dBc 90 dBc HIGH_SFDR_MODE is enabled. fS = 156.25 MSPS, 20x mode. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS61JB46 ADS61JB46 www.ti.com SBAS611B – SEPTEMBER 2013 – REVISED OCTOBER 2013 DIGITAL CHARACTERISTICS The dc specifications refer to the condition where the digital outputs do not switch, but are permanently at a valid logic level '0' or '1'. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DIGITAL INPUTS VIH High-level input voltage VIL Low-level input voltage IIH IIL 1.2 V 0.6 High-level input current Low-level input current V 0 μA SCLK, SDATA, RESET, PDN, PDN_ANA 10 μA SEN 10 μA 0 μA SEN SCLK, SDATA, RESET, PDN, PDN_ANA DIGITAL OUTPUTS (SDOUT) VOH High-level output voltage VOL Low-level output voltage DRVDD – 0.1 DRVDD V 0 0.1 V 1.8 1.9 V CML OUTPUTS (50-Ω single-ended external termination to IOVDD) IOVDD supply range 1.7 High-level output voltage IOVDD V Low-level output voltage IOVDD – 0.4 V 0.4 V IOVDD – 0.2 V |VOD| Output differential voltage VOCM Output common-mode voltage Transmitter short-circuit current Transmitter terminals shorted to any voltage between –0.25 V and 1.45 V –90 Single-ended output impedance UI Unit interval TJ Total jitter tRISE, tFALL Rise time, Fall time 50 mA 3200 UI Ω 50 625 5-pF, single-ended load capacitance to ground 0.35 p-pUI 175 ps WAKE-UP TIMING CHARACTERISTICS PARAMETER tWAKE Wake-up time TEST CONDITIONS MIN TYP MAX UNIT Time to valid data after coming out of complete power-down mode 50 μs Time to valid data after coming out of fast-recovery power-down mode 50 μs Time to valid data after coming out of software power-down mode 10 μs 5 μs Time to valid data after stopping and restarting the input clock Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS61JB46 5 ADS61JB46 SBAS611B – SEPTEMBER 2013 – REVISED OCTOBER 2013 www.ti.com PARAMETRIC MEASUREMENT INFORMATION JESD204A OUTPUT INTERFACE The 14-bit analog-to-digital converter (ADC) output is padded with four zeros on the LSB side to form a 16-bit output. Two 8B10B codes are formed; one from the eight MSBs and the other from the six LSBs and the two padded zeros, as shown in Figure 1. ADCOUT[13:6] ADCOUT[5:0], 0, 0 8B10B Code 1 MSB Octet 8B10B Code 2 LSB Octet Figure 1. ADC Output Mapping to Two 8B10B Codes The two octets can be either transmitted on the same lane (single-lane interface, Figure 2) or on two lanes (duallane interface, Figure 3). By default, the device operates in single-lane interface. Conversion Clock (CLKP - CLKM) CML Output Lane 1 (ADC_OUTP0 - ADC_OUTM0) Dx.y (ADC Data N, MSB Octet) Dx.y (ADC Data N, LSB Octet) Dx.y (ADC Data N+1, MSB Octet) Dx.y (ADC Data N+1, LSB Octet) Figure 2. Single-Lane Interface Timing Diagram Conversion Clock (CLKP - CLKM) CML Output Lane 1 (ADC_OUTP0 - ADC_OUTM0) Dx.y (ADC Data N, MSB Octet) Dx.y (ADC Data N+1, MSB Octet) Dx.y (ADC Data N+2, MSB Octet) Dx.y (ADC Data N+3, MSB Octet) Dx.y (ADC Data N, LSB Octet) Dx.y (ADC Data N+1, LSB Octet) Dx.y (ADC Data N+2, LSB Octet) Dx.y (ADC Data N+3, LSB Octet) CML Output Lane 2 (ADC_OUTP1 - ADC_OUTM1) Figure 3. Dual-Lane Interface Timing Diagram 6 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS61JB46 ADS61JB46 www.ti.com SBAS611B – SEPTEMBER 2013 – REVISED OCTOBER 2013 PARAMETRIC MEASUREMENT INFORMATION (continued) A detailed dual-lane mode timing diagram is shown in Figure 4. Sample N N+3 N+2 N+1 N+4 N+21 N+22 N+20 Input Signal tA Input Clock CLKP CLKM 20 Clock Cycles (1) tPDI CML Output Data Lane 1 N-21 N-20 N-19 N-18 N-17 N-1 N N+1 N+2 N-21 N-20 N-19 N-18 N-17 N-1 N N+1 N+2 CML Output Data Lane 2 (1) These clock cycles comprise the ADC latency. At higher sampling frequencies, tPDI > 1 clock cycle and overall latency = ADC latency + 1. Figure 4. Dual-Lane Mode Timing Diagram PARAMETER 30 MSPS 40 MSPS 60 MSPS 160 MSPS UNIT TA Aperture delay 560 560 560 560 ps TJ Aperture jitter (RMS) 125 125 125 125 fS Latency 20 20 20 20 Clocks 33.3 26.2 18.9 15.3 ns tPDI Data propagation delay Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS61JB46 7 ADS61JB46 SBAS611B – SEPTEMBER 2013 – REVISED OCTOBER 2013 www.ti.com The receiver issues a synchronization request through the SYNC~P, SYNC~M pins whenever the frame boundary of the output data stream must be synchronized to. Figure 5 shows how the transmission switches from normal data (D) to code group synchronization symbols K28.5 symbols during and after a synchronization request. N+2 Sample N Input Signal Input Clock N+3 N+4 N+5 N+6 N+7 N+8 N+9 N+1 CLKP CLKM tCLK-INT Internal Clock for Latching SYNC~ (CLK_INT) tSYNC-SU tSYNC-H SYNC~ Input (SYNC~P) - (SYNC~M) tSYNC-PDI SYNC~ Active Latency = 9 Clock Cycles CML Output Data Lane 1 N-21 N-20 N-19 N-18 N-17 N-16 N-15 N-14 N-13 N-12 K28.5 N-20 N-19 N-18 N-17 N-16 N-15 N-14 N-13 N-12 K28.5 CML Output Data Lane 2 N-21 Figure 5. SYNC~ Active Timing Diagram Table 2. SYNC~ Falling Edge Timing at 160 MSPS PARAMETER tCLK-INT DESCRIPTION TYP UNIT Delay from the input clock rising edge to the internal clock (CLK_INT) rising edge used to latch the SYNC~ falling edge 10.5 ns tSYNC-SU SYNC~ active edge setup time Minimum delay required from SYNC~ falling edge to CLK_INT rising edge 2 ns tSYNC-H SYNC~ active edge hold time Minimum delay required from CLK_INT rising edge to SYNC~ falling edge 2 ns SYNC~ active latency Number of clocks for K28.5 to appear at the output after a SYNC~ request 9 clocks SYNC~ data propagation delay Similar to data propagation delay tSYNC-PDI 8 Submit Documentation Feedback 15.3 ns Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS61JB46 ADS61JB46 www.ti.com SBAS611B – SEPTEMBER 2013 – REVISED OCTOBER 2013 N+2 Input Signal Input Clock N+3 N+4 N+5 N+7 N+6 N+8 N+9 N+1 Sample N CLKP CLKM tCLK-INT Internal Clock for Latching SYNC (CLK_INT) tSYNCZ-SU tSYNCZ-H SYNC~ Input (SYNC~P) - (SYNC~M) SYNC~ De-Active Latency = 8 Clock Cycles tSYNCZ-PDI CML Output Data Lane 1 K28.5 K28.5 K28.5 K28.5 K28.5 K28.5 K28.5 K28.5 K28.5 N-12 N-11 K28.5 K28.5 K28.5 K28.5 K28.5 K28.5 K28.5 K28.5 K28.5 N-12 N-11 CML Output Data Lane 2 Figure 6. SYNC~ De-Active Timing Diagram Table 3. SYNC~ Rising Edge Timing at 160 MSPS PARAMETER DESCRIPTION Delay from input clock rising edge to the internal clock (CLK_INT) rising edge used to latch the SYNC~ rising edge tCLK-INT TYP UNIT 10.5 ns tSYNCZ-SU SYNC~ active edge setup time Minimum delay required from SYNC~ rising edge to CLK_INT rising edge 2 ns tSYNCZ-H SYNC~ active edge hold time Minimum delay required from CLK_INT rising edge to SYNC~ rising edge 2 ns SYNC~ de-active latency Number of clocks for normal data to appear at the output after a SYNC~ de-activate request 8 Clocks SYNC~ de-active data propagation delay Similar to data propagation delay tSYNCZ-PDI 15.3 ns Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS61JB46 9 ADS61JB46 SBAS611B – SEPTEMBER 2013 – REVISED OCTOBER 2013 www.ti.com 4-LEVEL CONTROL The DFS_EXTREF and MODE pins function as 4-level control pins in the device, as described in Table 4 and Table 5. A simple scheme to generate a 4-level voltage is shown in Figure 7. AVDD (5/8) AVDD 3R (5/8) AVDD 2R AVDD GND (3/8) AVDD 3R To Parallel Pin (3/8) AVDD GND Figure 7. Simple Scheme to Configure 4-Level Control Pins Table 4. DFS_EXTREF Pin (Pin 3) DFS_EXTREF DESCRIPTION 0 +150 mV / 0 mV EXTREF = 0, DFS = 0 (3/8) AVDD ±150 mV EXTREF = 1, DFS = 0 (5/8) AVDD ±150 mV EXTREF = 1, DFS = 1 AVDD 0 mV / –150 mV EXTREF = 0, DFS = 1 Key: EXTREF: 0 = Internal reference mode, 1 = External reference mode DFS: 0 = Twos complement output, 1 = Offset binary output 10 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS61JB46 ADS61JB46 www.ti.com SBAS611B – SEPTEMBER 2013 – REVISED OCTOBER 2013 PIN CONFIGURATION OVR DETECT0 DETECT1 DETECT2 DETECT3 ADC_OUTP0 ADC_OUTM0 IOVDD ADC_OUTP1 ADC_OUTM1 RHA PACKAGE QFN-40 (Top View) 40 39 38 37 36 35 34 33 32 31 SYNC~M 1 30 DRVDD SYNC~P 2 29 DRGND DFS_EXTREF 3 28 SDOUT_TEST1 PDN_ANA 4 27 DRVDD AVDD 5 26 RESET Thermal Pad 23 SEN_FALIGN_IDLE AGND 9 22 AVDD VCM 10 21 PDN 11 12 13 14 15 16 17 18 19 20 FAVDD 8 MODE CLKM AVDD SDATA_TEST0 AVDD_3V 24 AGND 7 AVDD CLKP AGND SCLK_SERF0_SCR INM 25 INP 6 AGND AGND NOTE: The thermal pad is connected to DRGND. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS61JB46 11 ADS61JB46 SBAS611B – SEPTEMBER 2013 – REVISED OCTOBER 2013 www.ti.com PIN FUNCTIONS PIN DESCRIPTION NAME NO. ADC_OUTM0 34 CML output lane 1, negative output ADC_OUTM1 31 CML output lane 2, negative output ADC_OUTP0 35 CML output lane 1, positive output ADC_OUTP1 32 CML output lane 2, positive output AGND 5, 6, 9, 11, 14, 16, AVDD 15, 18, 22 AVDD_3V 17 Analog supply for input buffer, 3.3 V CLKM 8 Conversion clock, negative input CLKP 7 Conversion clock, positive input DETECT3 36 DETECT2 37 DETECT1 38 DETECT0 39 Analog ground Analog supply, 1.8 V Signal level-detect output pins in 1.8-V CMOS logic level. These pins can be used to either output a 4-bit ADC code with low latency or to output a 16-level RMS power estimate. DFS_EXTREF 3 4-level analog control for data format selection and internal and external reference mode DRGND 29 Digital ground DRVDD 27, 30 FAVDD 20 Fuse supply, connect externally to AVDD, 1.8 V INM 13 Analog input, Negative INP 12 Analog input, Positive IOVDD 33 CML buffer supply, 1.7 V to 1.9 V MODE 19 4-level control for selecting the serial and parallel interface modes OVR 40 Over-range output in 1.8-V CMOS logic levels. PDN 21 Full chip power-down (also referred to as complete power-down mode) PDN_ANA 4 Analog section power-down; JESD interface is still active. This mode is referred to as fast-recovery power-down mode. RESET 26 Serial interface RESET input. When using the serial interface mode, the internal registers must be initialized through a hardware RESET by applying a high pulse on this pin or by using the S_RESET register bit; refer to the Serial Interface section. In parallel interface mode, the RESET pin must be permanently tied high. In this mode, the SEN_FALIGN_IDLE, SCLK_SERF0_SCR, and SDATA_TEST0 pins function as parallel pins with their functionality described in Table 6, Table 7, and Table 8, respectively. SCLK_SERF0_SCR 25 Serial clock input in serial interface mode. In parallel interface mode, this pin provides a 4-level control for all JESD modes (single-lane, dual-lane, and scrambling modes). SDATA_TEST0 24 Serial data input in serial interface mode. In parallel interface mode, this pin provides a JESD test mode. SDOUT_TEST1 28 Serial data out in serial interface mode. In parallel interface mode, this pin provides a JESD test mode. SEN_FALIGN_IDLE 23 Serial enable input in serial interface mode. In parallel interface mode, this pin provides a 4-level control for JESD modes. SYNC~M 1 JESD synchronization request, negative input SYNC~P 2 JESD synchronization request, positive input VCM 10 Common-mode output for setting the input common-mode. 1.95 V, reference input in external reference mode. 12 Digital supply, 1.8 V Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS61JB46 ADS61JB46 www.ti.com SBAS611B – SEPTEMBER 2013 – REVISED OCTOBER 2013 IOVDD SYNC~P SYNC~M DRVDD DRGND CLKP CLKM AVDD AGND AVDD_3 V FUNCTIONAL BLOCK DIAGRAM CLOCKGEN PLL 10X, 20X CML Outputs ADC_OUTP[0] INP Buffer ADC_OUTM[0] JESD204A Digital 14-Bit ADC ADC_OUTP[1] INM ADC_OUTM[1] Signal Level Detect VCM OVR DETECT[3:0] Control Interface Reference PDN PDN_ANA DFS_EXTREF SDATA_TEST0 SDOUT_TEST1 SEN_FALIGN_IDLE SCLK_SERF0_SCR RESET CMOS Outputs Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS61JB46 13 ADS61JB46 SBAS611B – SEPTEMBER 2013 – REVISED OCTOBER 2013 www.ti.com TYPICAL CHARACTERISTICS At +25°C, AVDD = 1.8 V, AVDD_3V = 3.3 V, DRVDD = 1.8 V, IOVDD = 1.8 V, fS = 153.6 MSPS, sine-wave input clock, 1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, 16-mA CML current, and 32kpoint FFT, unless otherwise noted. Note that after reset, the device is in 0-dB gain mode. 0 0 SFDR = 74.8 dBc SNR = 75.0 dBFS SINAD = 72.3 dBFS THD = 74.7 dBc SFDR Non HD2, HD3 = 94.6 dBc −20 −20 −40 Amplitude (dBFS) Amplitude (dBFS) −40 −60 −60 −80 −80 −100 −100 −120 SFDR = 74.0 dBc SNR = 74.8 dBFS SINAD = 71.8 dBFS THD = 73.7 dBc SFDR Non HD2, HD3 = 97.0 dBc 0 10 20 30 40 50 60 −120 70 76.8 Frequency (MHz) 0 40 50 60 70 76.8 Frequency (MHz) G002 0 SFDR = 81.1 dBc SNR = 72.9 dBFS SINAD = 72.2 dBFS THD = 79.9 dBc SFDR Non HD2, HD3 = 89.87 dBc −20 SFDR = 67.8 dBc SNR = 71.0 dBFS SINAD = 65.5 dBFS THD = 65.9 dBc SFDR Non HD2, HD3 = 83.44 dBc −20 −40 Amplitude (dBFS) −40 Amplitude (dBFS) 30 Figure 9. AMPLITUDE vs FREQUENCY (70-MHz IF) 0 −60 −60 −80 −80 −100 −100 0 10 20 30 40 50 60 Frequency (MHz) 70 76.8 −120 0 G003 Figure 10. AMPLITUDE vs FREQUENCY (190-MHz IF) 14 20 G001 Figure 8. AMPLITUDE vs FREQUENCY (20-MHz IF) −120 10 Submit Documentation Feedback 10 20 30 40 50 60 Frequency (MHz) 70 76.8 G004 Figure 11. AMPLITUDE vs FREQUENCY (300-MHz IF) Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS61JB46 ADS61JB46 www.ti.com SBAS611B – SEPTEMBER 2013 – REVISED OCTOBER 2013 TYPICAL CHARACTERISTICS (continued) At +25°C, AVDD = 1.8 V, AVDD_3V = 3.3 V, DRVDD = 1.8 V, IOVDD = 1.8 V, fS = 153.6 MSPS, sine-wave input clock, 1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, 16-mA CML current, and 32kpoint FFT, unless otherwise noted. Note that after reset, the device is in 0-dB gain mode. 0 0 Each Tone at −7 dBFS Amplitude fIN1 = 190 MHz fIN2 = 185 MHz IMD3 = 79.9 dBFS −10 −20 −30 −20 −30 −40 Amplitude (dBFS) Amplitude (dBFS) −40 −50 −60 −70 −50 −60 −70 −80 −80 −90 −90 −100 −100 −110 −110 −120 Each Tone at −36 dBFS Amplitude fIN1 = 190 MHz fIN2 = 185 MHz IMD3 = 106.9 dBFS −10 0 10 20 30 40 50 60 −120 70 76.8 Frequency (MHz) 0 30 40 50 60 70 76.8 Frequency (MHz) G006 Figure 13. AMPLITUDE vs FREQUENCY (Two-Tone Input Signal) 95 100 Digital gain = 0 dB Digital gain = 2 dB Digital gain = 6 dB 90 Digital gain = 0 dB Digital gain = 2 dB Digital gain = 6 dB 98 96 SFDR Non HD2, HD3 (dB) 85 80 SFDR (dBc) 20 G005 Figure 12. AMPLITUDE vs FREQUENCY (Two-Tone Input Signal) 75 70 65 60 94 92 90 88 86 84 55 50 10 82 0 50 100 150 200 250 300 350 400 450 500 Input Frequency (MHz) 80 0 100 150 200 250 300 350 400 450 Input Frequency (MHz) G007 Figure 14. SPURIOUS-FREE DYNAMIC RANGE vs INPUT FREQUENCY 50 500 G008 Figure 15. SPURIOUS-FREE DYNAMIC RANGE (NON HD2, HD3) vs INPUT FREQUENCY Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS61JB46 15 ADS61JB46 SBAS611B – SEPTEMBER 2013 – REVISED OCTOBER 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) At +25°C, AVDD = 1.8 V, AVDD_3V = 3.3 V, DRVDD = 1.8 V, IOVDD = 1.8 V, fS = 153.6 MSPS, sine-wave input clock, 1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, 16-mA CML current, and 32kpoint FFT, unless otherwise noted. Note that after reset, the device is in 0-dB gain mode. 130 78.5 76 Input Frequency = 40MHz Digital gain = 0 dB Digital gain = 2 dB Digital gain = 6 dB 75 SNR(dBFS) SFDR(dBc) SFDR(dBFS) 78 77.5 74 120 110 100 77 SNR (dBFS) SNR (dBFS) 72 71 70 69 68 76.5 90 76 80 75.5 70 75 60 74.5 50 74 40 73.5 30 73 20 SFDR (dBc,dBFS) 73 67 66 65 72.5 −80 0 50 100 150 200 250 300 350 400 450 −40 −30 −20 −10 0 10 G010 G009 Figure 17. PERFORMANCE ACROSS INPUT AMPLITUDE 77 105 20 MHz 70 MHz 150 MHz 100 220 MHz 270 MHz 300 MHz 400 MHz 500 MHz 20 MHz 70 MHz 150 MHz 76 75 95 220 MHz 270 MHz 300 MHz 400 MHz 500 MHz 74 90 73 SNR (dBFS) 85 SFDR (dBc) −50 Amplitude (dBFS) Figure 16. SIGNAL-TO-NOISE RATIO vs INPUT FREQUENCY 80 75 70 72 71 70 69 65 68 60 67 55 66 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Digital Gain (dB) 6 65 0 0.5 1 1.5 2 2.5 3 3.5 Digital Gain (dB) G011 Figure 18. SPURIOUS-FREE DYNAMIC RANGE vs DIGITAL GAIN 16 −60 500 Input Frequency (MHz) 50 −70 4 4.5 5 5.5 6 G012 Figure 19. SIGNAL-TO-NOISE RATIO vs DIGITAL GAIN Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS61JB46 ADS61JB46 www.ti.com SBAS611B – SEPTEMBER 2013 – REVISED OCTOBER 2013 TYPICAL CHARACTERISTICS (continued) At +25°C, AVDD = 1.8 V, AVDD_3V = 3.3 V, DRVDD = 1.8 V, IOVDD = 1.8 V, fS = 153.6 MSPS, sine-wave input clock, 1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, 16-mA CML current, and 32kpoint FFT, unless otherwise noted. Note that after reset, the device is in 0-dB gain mode. 78 90 20 MHz 70 MHz 150 MHz 76 220 MHz 270 MHz 300 MHz 400 MHz 500 MHz 74 AVDD = 1.85 V AVDD = 1.9 V AVDD = 1.95 V 86 72 84 70 SFDR (dBc) SINAD (dBFS) AVDD = 1.7 V AVDD = 1.75 V AVDD = 1.8 V 88 68 66 82 80 78 64 76 62 60 74 58 72 Input Frequency = 190 MHz 56 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 70 −40 6 Digital Gain (dB) −15 10 35 60 85 Temperature (°C) G013 Figure 20. SIGNAL-TO-NOISE AND DISTORTION RATIO vs DIGITAL GAIN G014 Figure 21. SPURIOUS-FREE DYNAMIC RANGE vs AVDD SUPPLY AND TEMPERATURE 73.9 88 AVDD = 1.7 V AVDD = 1.75 V AVDD = 1.8 V 73.7 AVDD = 1.85 V AVDD = 1.9 V AVDD = 1.95 V AVDD_3V = 3 V AVDD_3V = 3.1 V AVDD_3V = 3.2 V AVDD_3V = 3.3 V 87 86 AVDD_3V = 3.4 V AVDD_3V = 3.5 V AVDD_3V = 3.6 V 73.5 85 84 SFDR (dBc) SNR (dBFS) 73.3 73.1 72.9 83 82 81 72.7 80 72.5 79 72.3 78 Input Frequency = 190 MHz 72.1 −40 −15 10 Input Frequency = 190 MHz 35 60 Temperature (°C) 85 77 −40 10 35 60 Temperature (°C) G015 Figure 22. SIGNAL-TO-NOISE RATIO vs AVDD SUPPLY AND TEMPERATURE −15 85 G016 Figure 23. SPURIOUS-FREE DYNAMIC RANGE vs AVDD_3V SUPPLY AND TEMPERATURE Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS61JB46 17 ADS61JB46 SBAS611B – SEPTEMBER 2013 – REVISED OCTOBER 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) At +25°C, AVDD = 1.8 V, AVDD_3V = 3.3 V, DRVDD = 1.8 V, IOVDD = 1.8 V, fS = 153.6 MSPS, sine-wave input clock, 1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, 16-mA CML current, and 32kpoint FFT, unless otherwise noted. Note that after reset, the device is in 0-dB gain mode. 89 73.8 AVDD_3V = 3 V AVDD_3V = 3.1 V AVDD_3V = 3.2 V AVDD_3V = 3.3 V 73.6 AVDD_3V = 3.4 V AVDD_3V = 3.5 V AVDD_3V = 3.6 V AVDD = 1.75 V AVDD = 1.8 V AVDD = 1.85 V 88 87 AVDD = 1.9 V AVDD = 1.95 V 86 73.4 85 SFDR (dBc) SNR (dBFS) 73.2 73 84 83 82 72.8 81 80 72.6 79 72.4 78 Input Frequency = 190 MHz 72.2 −40 −15 10 Input Frequency = 190 MHz 35 60 77 −40 85 Temperature (°C) −15 10 35 60 85 Temperature (°C) G017 Figure 24. SIGNAL-TO-NOISE RATIO vs AVDD_3V SUPPLY AND TEMPERATURE G018 Figure 25. SPURIOUS-FREE DYNAMIC RANGE vs DRVDD SUPPLY AND TEMPERATURE 82 78 73.8 AVDD = 1.75 V AVDD = 1.8 V AVDD = 1.85 V 73.6 Input Frequency = 40MHz AVDD = 1.9 V AVDD = 1.95 V SNR SFDR 77.5 79 77 76 76.5 73 76 70 75.5 67 75 64 74.5 61 74 58 SNR (dBFS) SNR (dBFS) 73.2 73 72.8 72.6 SFDR (dBc) 73.4 72.4 73.5 1.85 Input Frequency = 190 MHz 72.2 −40 −15 10 35 60 Temperature (°C) 85 1.91 1.94 1.97 Input Common−Mode Voltage (V) 2 55 G020 G001 Figure 26. SIGNAL-TO-NOISE RATIO vs DRVDD SUPPLY AND TEMPERATURE 18 1.88 Submit Documentation Feedback Figure 27. PERFORMANCE vs INPUT COMMON-MODE VOLTAGE Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS61JB46 ADS61JB46 www.ti.com SBAS611B – SEPTEMBER 2013 – REVISED OCTOBER 2013 TYPICAL CHARACTERISTICS (continued) At +25°C, AVDD = 1.8 V, AVDD_3V = 3.3 V, DRVDD = 1.8 V, IOVDD = 1.8 V, fS = 153.6 MSPS, sine-wave input clock, 1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, 16-mA CML current, and 32kpoint FFT, unless otherwise noted. Note that after reset, the device is in 0-dB gain mode. SNR SFDR Input Frequency = 40 MHz 74 87 77.5 76 73 84 77 74 72 81 76.5 72 71 78 76 70 70 75 75.5 68 69 72 75 66 68 69 74.5 64 67 66 74 62 63 73.5 1.2 1.88 1.91 1.94 1.97 2 Input Common−Mode Voltage (V) SFDR (dBc) SNR (dBFS) 78 66 1.85 1.25 88 84 74 82 73.5 80 73 78 72.5 76 72 74 71 1.2 SFDR (dBc) SNR (dBFS) 74.5 72 71.5 1.25 1.3 1.35 1.4 1.45 1.5 1.55 1.6 1.65 External Reference Voltage (V) 1.45 1.5 1.55 1.6 1.65 60 1.7 External Reference Voltage (V) 75 86 75 1.4 G022 90 76 90 SNR SFDR 75.5 1.35 78 Figure 29. PERFORMANCE vs EXTERNAL REFERENCE VOLTAGE 76 Input Frequency = 190 MHz 1.3 G021 Figure 28. PERFORMANCE vs INPUT COMMON-MODE VOLTAGE SNR (dBFS) SNR SFDR 90 75 SNR (dBFS) 80 78.5 70 1.7 Input Frequency = 190MHz SNR SFDR 88 74 86 73 84 72 82 71 80 70 78 69 76 68 74 67 72 66 70 65 68 64 66 63 64 62 62 61 0.1 0.4 G023 Figure 30. PERFORMANCE vs EXTERNAL REFERENCE VOLTAGE 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 3.1 60 3.4 Differential Clock Amplitude (Vpp) Product Folder Links: ADS61JB46 G024 Figure 31. PERFORMANCE vs DIFFERENTIAL CLOCK AMPLITUDE Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated SFDR (dBc) Input Frequency = 190MHz SFDR (dBc) 93 76 19 ADS61JB46 SBAS611B – SEPTEMBER 2013 – REVISED OCTOBER 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) At +25°C, AVDD = 1.8 V, AVDD_3V = 3.3 V, DRVDD = 1.8 V, IOVDD = 1.8 V, fS = 153.6 MSPS, sine-wave input clock, 1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, 16-mA CML current, and 32kpoint FFT, unless otherwise noted. Note that after reset, the device is in 0-dB gain mode. 45 78 77.5 Input Frequency = 20MHz SNR THD 77 77.5 40 77 76.5 35 THD (dBc) SNR (dBFS) 76 75.5 75.5 75 75 74.5 74.5 74 Code Occurrence (%) 76.5 76 74 73.5 30 25 20 15 10 73.5 73 5 70 80 73 8152 8151 8150 G025 8149 0 Input Clock Duty Cycle (%) 8148 60 8147 50 8146 40 8145 30 8144 20 8143 72.5 Output Codes (LSB) Figure 32. PERFORMANCE vs INPUT CLOCK DUTY CYCLE 0 0 fIN = 20 MHz SFDR = 75 dBc fPSRR = 10 MHz 50 − mVPP Amplitude(fIN) = −1 dBFS Amplitude(fPSRR) = −104 dBFS Amplitude(fIN + fPSRR) = −96 dBFS Amplitude(fIN − fPSRR) = −98 dBFS Amplitude (dBFS) −40 −40 −60 −80 −100 −100 15 30 45 Frequency (MHz) 60 75 −120 0 15 30 45 Frequency (MHz) G054 Figure 34. POWER-SUPPLY REJECTION RATIO SPECTRUM FOR AVDD SUPPLY 20 −60 −80 0 fIN = 20 MHz SFDR = 74 dBc fCM = 10 MHz 50 − mVPP Amplitude(fIN) = −1 dBFS Amplitude(fCM) = −94.6 dBFS Amplitude(fIN + fCM) = −88 dBFS Amplitude(fIN − fCM) = −89 dBFS −20 Amplitude (dBFS) −20 −120 G026 Figure 33. OUTPUT CODES HISTOGRAM WITH IDLE CHANNEL INPUT 60 75 G055 Figure 35. COMMON-MODE REJECTION RATIO SPECTRUM FOR AVDD SUPPLY Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS61JB46 ADS61JB46 www.ti.com SBAS611B – SEPTEMBER 2013 – REVISED OCTOBER 2013 TYPICAL CHARACTERISTICS (continued) At +25°C, AVDD = 1.8 V, AVDD_3V = 3.3 V, DRVDD = 1.8 V, IOVDD = 1.8 V, fS = 153.6 MSPS, sine-wave input clock, 1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, 16-mA CML current, and 32kpoint FFT, unless otherwise noted. Note that after reset, the device is in 0-dB gain mode. 0.66 0.33 Total Power AVDD Power AVDD_3V Power DRVDD Power IOVDD Power 0.3 0.6 0.27 0.24 0.54 Power (W) Power (W) 0.21 0.48 0.42 0.18 0.15 0.12 0.36 0.09 0.06 0.3 0.03 0.24 0 20 40 60 80 100 120 140 0 160 Sampling Speed (MSPS) 0 20 40 60 80 100 120 140 Sampling Speed (MSPS) G056 Figure 36. TOTAL POWER vs SAMPLING SPEED 160 G057 Figure 37. POWER BREAK-UP vs SAMPLING SPEED 0.1 IOVDD Power Dual−Lane(10x Mode) Single−Lane(20x Mode) 0.09 0.08 Power (W) 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0 0 20 40 60 80 100 120 140 Sampling Speed (MSPS) 160 G058 Figure 38. IOVDD POWER vs SAMPLING SPEED Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS61JB46 21 ADS61JB46 SBAS611B – SEPTEMBER 2013 – REVISED OCTOBER 2013 www.ti.com TYPICAL CHARACTERISTICS: CONTOUR At +25°C, AVDD = 1.8 V, AVDD_3V = 3.3 V, DRVDD = 1.8 V, IOVDD = 1.8 V, fS = 153.6 MSPS, sine-wave input clock, 1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, 16-mA CML current, and 32kpoint FFT, unless otherwise noted. Note that after reset, the device is in 0-dB gain mode. 79 140 fS - Sampling Frequency - MSPS 64 73 76 70 76 58 61 67 120 79 79 100 82 76 80 76 58 61 67 70 76 79 60 79 82 79 40 64 73 82 50 100 150 70 73 76 250 200 61 64 67 300 350 58 400 450 500 fIN - Input Frequency - MHz 65 60 70 75 80 SFDR - dBc M0049-33 Figure 39. SFDR ACROSS INPUT AND SAMPLING FREQUENCIES 140 77 81 fS - Sampling Frequency - MSPS 85 73 120 89 100 77 85 81 73 80 89 81 89 60 77 89 40 50 100 85 150 81 200 77 250 69 300 350 400 450 500 fIN - Input Frequency - MHz 75 70 80 85 SFDR - dBc M0049-34 Figure 40. SFDR ACROSS INPUT AND SAMPLING FREQUENCIES (6-dB Gain) 22 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS61JB46 ADS61JB46 www.ti.com SBAS611B – SEPTEMBER 2013 – REVISED OCTOBER 2013 TYPICAL CHARACTERISTICS: CONTOUR (continued) At +25°C, AVDD = 1.8 V, AVDD_3V = 3.3 V, DRVDD = 1.8 V, IOVDD = 1.8 V, fS = 153.6 MSPS, sine-wave input clock, 1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, 16-mA CML current, and 32kpoint FFT, unless otherwise noted. Note that after reset, the device is in 0-dB gain mode. 140 75 73 fS - Sampling Frequency - MSPS 74 72 71 70 120 69 68 100 75 73 74 72 71 70 80 69 68 67 66 60 75 40 74 50 100 71 72 73 150 69 70 250 200 68 300 67 65 66 400 350 64 450 500 fIN - Input Frequency - MHz 68 66 64 70 72 74 SNR - dBFS M0048-33 Figure 41. SNR ACROSS INPUT AND SAMPLING FREQUENCIES 66 140 fS - Sampling Frequency - MSPS 69 68 120 67 66 100 69 68 70 67 80 66 65 60 68 69 70 40 50 100 150 67 250 200 300 64 450 65 400 350 500 fIN - Input Frequency - MHz 64 65 66 67 68 69 SNR - dBFS 70 M0048-34 Figure 42. SNR ACROSS INPUT AND SAMPLING FREQUENCIES (6-dB Gain) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS61JB46 23 ADS61JB46 SBAS611B – SEPTEMBER 2013 – REVISED OCTOBER 2013 www.ti.com DEVICE CONFIGURATION PARALLEL INTERFACE MODE The device operates in parallel interface mode when a suitable voltage is applied on the MODE pin, as described in Table 5. In parallel interface mode, the SEN, SDATA, SCLK, and SDOUT pins functionality differs from the serial interface mode. In this mode, the SEN_FALIGN_IDLE and SCLK_SERF0_SCR pins turn into four levelcontrol pins for the JESD interface (as described in Table 6 and Table 7), whereas the SDATA_TEST0 and SDOUT_TEST1 pins turn into 2-level control pins, as described in Table 8. Table 5. MODE Pin (Pin 19) MODE DESCRIPTION 0 +150 mV/–0 mV (3/8)AVDD ±150 mV (5/8)AVDD ±150 mV AVDD +0 mV/–150 mV Serial interface mode. Pins 23, 24, and 25 are configured as SEN, SDATA, SCLK. Pins 36, 37, 38, and 39 are configured to output either an early-signal estimate or a signal power estimate (selection is based on register settings). Do not use Parallel interface mode. Pins 23, 24 and 25 are configured as parallel input pins for controlling the JESD204A modes. Pins 36, 37, 38, and 39 always output an early-signal estimate. Do not use Table 6. SEN_FALIGN_IDLE Pin, in Parallel Interface Mode (Pin 23) SEN_FALIGN_IDLE DESCRIPTION 0 +150 mV / 0 mV FALIGN = 0, IDLE = 0 (3/8) AVDD ±150 mV FALIGN = 1, IDLE = 0 (5/8) AVDD ±150 mV FALIGN = 1, IDLE = 1 AVDD 0 mV / –150 mV FALIGN = 0, IDLE = 1 Key: FALIGN: When the last octet of the current frame is the same as the last octet of the previous frame, then FALIGN determines whether the last octet of the current frame is transmitted as is, or if the last octet is replaced by a K28.7 control symbol. 0 = Last octet transmitted as is 1 = Last octet is replaced with a K28.7 control symbol IDLE: IDLE determines the synchronization characters transmitted during and immediately after a SYNC event. 0 = The device transmits K28.5 as per the JESD204A specification 1 = The device alternately transmits K28.5 and D5.6/D16.2 characters as per the IEEE standard 802.3-2002 (part 3, clause 36.2.4.12). This setting is the case for both single- and dual-lane modes. 24 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS61JB46 ADS61JB46 www.ti.com SBAS611B – SEPTEMBER 2013 – REVISED OCTOBER 2013 Table 7. SCLK_SERF0_SCR Pin, in Parallel Interface Mode (Pin 25) SCLK_SERF0_SCR DESCRIPTION 0 +150 mV / 0 mV SERF0 = 0, SCR = 0 (3/8) AVDD ±150 mV SERF0 = 1, SCR = 0 (5/8) AVDD ±150 mV SERF0 = 1, SCR = 1 AVDD 0 mV / –150 mV SERF0 = 0, SCR = 1 Key: SERF0: Output serialization factor. 0 = The device transmits two octets per frame (an entire ADC channel in a single lane) with an output serialization factor of 20 1 = The device transmits one octet per frame (one ADC channel over two lanes) with an output serialization factor of 10 0 = Scrambling disabled 1 = Scrambling enabled (as per JESD204A) SCR: Table 8. SDATA_TEST0 and SDOUT_TEST1 Pins, in Parallel Interface Mode (Pins 24 and 28) TEST1 TEST0 0 0 Normal mode. JESD204A encoder input is ADC data. MODE 0 1 JESD204A encoder input is B5B5. Output is a stream of D21.5 (alternating 1s and 0s). 1 0 JESD204A encoder input is FF00. 1 1 JESD204A encoder input is a pseudo random pattern 1 + X14 + X15 (regardless of whether the scrambler is enabled or not). Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS61JB46 25 ADS61JB46 SBAS611B – SEPTEMBER 2013 – REVISED OCTOBER 2013 www.ti.com SERIAL INTERFACE The analog-to-digital converter (ADC) has a set of internal registers that can be accessed by the serial interface formed by the serial interface enable (SEN), serial interface clock (SCLK), and serial interface data (SDATA) pins. Serially shifting bits into the device is enabled when SEN is low. SDATA serial data are latched at every SCLK falling edge when SEN is active (low). The serial data are loaded into the register at every 16th SCLK falling edge when SEN is low. If the word length exceeds a multiple of 16 bits, the excess bits are ignored. Data can be loaded in multiples of 16-bit words within a single active SEN pulse. The first eight bits form the register address and the remaining eight bits are the register data. The interface can function with SCLK frequencies from 20 MHz down to very low speeds (of few Hertz) and also with a non-50% SCLK duty cycle. Register Initialization After power-up, the internal registers must be initialized to the default values. This initialization can be accomplished in one of two ways: 1. Either through a hardware reset by applying a high-going pulse on RESET pin (of widths greater than 10 ns), as shown in Figure 43, or 2. By applying a software reset. Using the serial interface, set the S_RESET bit (bit D1 in register 00h) high. This setting initializes the internal registers to the default values and then self-resets the S_RESET bit low. In this case, the RESET pin is kept low. Register Address SDATA A7 A6 A5 A4 A3 Register Data A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 tDH tSCLK tDSU SCLK tSLOADS tSLOADH SEN RESET Figure 43. Serial Interface Timing Diagram Table 9. Timing Characteristics for Figure 43 (1) PARAMETER MIN MAX UNIT 20 MHz fSCLK SCLK frequency (= 1/ tSCLK) tSLOADS SEN to SCLK setup time 25 ns tSLOADH SCLK to SEN hold time 25 ns tDS SDATA setup time 25 ns tDH SDATA hold time 25 ns (1) 26 > DC TYP Typical values are at TA = +25°C, minimum and maximum values are across the full temperature range of TMIN = –40°C to TMAX = +85°C, AVDD = 1.8 V, AVDD_3V = 3.3 V, DRVDD = 1.8 V, and IOVDD = 1.8 V, unless otherwise noted. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS61JB46 ADS61JB46 www.ti.com SBAS611B – SEPTEMBER 2013 – REVISED OCTOBER 2013 Serial Register Readout The device includes an option where the contents of the internal registers can be read back. This readback may be useful as a diagnostic check to verify the serial interface communication between the external controller and the ADC. 1. First, set the SERIAL_READOUT register bit = 1. This setting also disables any further register writes (except for writes to the SERIAL_READOUT register bit). 2. Initiate a serial interface cycle specifying the address of the register (A[7:0]) whose content must be read. 3. The device outputs the contents (D[7:0]) of the selected register on the SDOUT_TEST1 pin. 4. The external controller latches the contents at the SCLK falling edge. 5. To enable register writes, reset the SERIAL_READOUT register bit = 0. Reset Timing Figure 44 shows a reset timing diagram. Power Supply (AVDD, DRVDD) t1 RESET t2 t3 SEN NOTE: A high-going pulse on the RESET pin is required for initialization through a hardware reset. Figure 44. Reset Timing Diagram Table 10. Timing Characteristics for Figure 44 (1) PARAMETER CONDITIONS MIN t1 Power-on delay Delay from power-up of AVDD and DRVDD to RESET pulse active t2 Reset pulse duration Pulse duration of the active RESET signal that resets the serial registers t3 Serial interface delay Delay from RESET disable to SEN active (1) TYP MAX 1 UNIT ms 10 100 ns Typical values are at TA = +25°C and minimum and maximum values are across the full temperature range of TMIN = –40°C to TMAX = +85°C, unless otherwise noted. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS61JB46 27 ADS61JB46 SBAS611B – SEPTEMBER 2013 – REVISED OCTOBER 2013 www.ti.com SERIAL INTERFACE REGISTER MAP BIT LOCATION REGISTER BIT NAME ADDRESS (Hex) BIT S_RESET 00 1 Software reset. This mode has the same function as a hardware reset. SERIAL_READOUT 00 0 0 = Serial interface write (default) 1 = Serial readout HIGH_SFDR_MODE 02 6:4, 0 DFS_OVERRIDE 3C 7 DESCRIPTION Set these bits to obtain the best HD3 when the input frequency is between 150 MHz to 250 MHz. This bit provides the override control mode for the DFS_EXTREF pin when controlling the DFS select mode. This bit controls the DFS_EXTREF pin with the DFS_REG register bit. 0 = DFS functionality determined by DFS_EXTREF pin 1 = DFS functionality determined by DFS_REG pin This bit is the register bit for DFS control. 0 = Output format is twos complement. 1 = Output format is offset binary. This setting takes effect when DFS_OVERRIDE is set to ‘1’. DFS_REG 3C 6 CUSTOM_PAT[13:6] 3E 7:0 Eight MSBs of the 14-bit custom pattern can be programmed. CUSTOM_PAT[5:0] 3F 7:2 Six LSBs of the 14-bit custom pattern can be programmed. INT_REF_OVERRIDE 44 3 This bit is the override control for DFS_EXTREF pin when controlling the internal/external reference select mode. This bit controls the DFS_EXTREF pin with the INT_REF_REG register bit. 0 = Internal/external reference mode is determined by the DFS_EXTREF pin 1 = Internal/external reference mode is determined by the INT_REF_REG This bit is the register bit for internal/external reference mode control. INT_REF_REG 44 2 0 = Internal reference mode. 1 = External reference mode. This setting takes effect when INT_REF_OVERRIDE is set to ‘1’. S_PDN 44 6 Software power-down. FINE_GAIN[3:0] 45 7:4 BYPASS_FINE_GAIN 45 0-dB to 6-dB digital gain in 0.5-dB steps (default gain is 0 dB). Refer to the Fine-Gain Control section for further details. Digital gain bypass. Digital gain is enabled by default. When this bit set to '1', digital gain (fine gain) is bypassed. These bits control the output test patterns. ADC_TEST_PAT[2:0] 45 2:0 TXMIT_LINKDATA_EN A0 0 S_FALIGN A0 1 000 = ADC output data bus is input to JESD204A encoder block 001 = ADC bus is replaced by the minimum code (00000000000000 in offset binary). 010 = ADC bus replaced by the maximum code (11111111111111 in offset binary). 100 = ADC bus replaced by a ramping code pattern that increments by 1 LSB every four clocks (and folds back to the minimum code when the maximum code is reached). 101 = ADC bus is replaced by custom patterns. The patterns are programmed by registers 3E and 3F. 011, 110, 111 = Do not use 0 = Initial lane alignment sequence is not transmitted (default) 1 = Initial lane alignment sequence (as per JESD204A) is sent after the code group sync in both single- and dual-lane interfaces Software Frame Align control. This bit enables frame alignment monitoring. When scrambling is enabled and this bit is ‘1’, this bit is encoded as K28.7 when the last scrambled octet in a frame equals FC. S_FALIGN bit control is similar to the FALIGN pin control. When this bit is 0 = There is no replacement. 1 = When scrambling is off, if the last octet in the previous frame is the same as the last octet in the current frame, then the last octet in the current frame is replaced with a frame alignment symbol K28.7 MFALIGN 28 A0 2 Multiframe align control. This bit functions similarly to S_FALIGN, but refers to multiframe instead. The multiframe alignment symbol is K28.3. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS61JB46 ADS61JB46 www.ti.com SBAS611B – SEPTEMBER 2013 – REVISED OCTOBER 2013 BIT LOCATION REGISTER BIT NAME ADDRESS (Hex) DESCRIPTION BIT FLIP_ADC_BUS A0 3 By default, the last octet in the frame is derived from the data octet on the LSB side. The occurrence of consecutive last octets may be rare because the LSB octets usually switch more (frame-to-frame) than the MSB octets. This condition can lead to an infrequent occurrence of frame alignment symbols. To increase the rate of consecutive last octets (and thereby the rate of frame and multiframe alignment symbols), this bit can be set to '1'. Setting this bit to '1' flips the bit order of the ADC inputs (N bits) to the JESD204A logic. Note that the two zeros padded at the end to cause the JESD204A logic input to remain unchanged. TESTMODE_EN A0 4 This bit enables the transmission of the test sequence mentioned in the JESD204A document. Software idle generation control. Normally the output during code group synchronization is K28.5. When S_IDLE is set to '1', the device output is a K28.5 comma followed by either a D5.6 or a D16.2 alignment symbol. This configuration is as per IEEE standard 802.3-2002 (part 3, clause 36.2.4.12) and enables compatibility with TI’s TLK family of devices. This bit control is similar to the IDLE pin control (see Table 6). S_IDLE A0 5 S_TEST0 A0 6 S_TEST1 A0 7 These two bit controls are similar to the TEST1 and TEST0 pin controls. CTRL_F A1 0 This bit enables writes into register A6h, bits 7:0. CTRL_K A1 1 This bit enables writes into register A7h, bits 4:0. S_SCR A5 7 Software scrambling enable. This bit control is similar to the SCR pin control. F[7:0] A6 7:0 These bits control the number of octets per frame. Default is set to 00000001 (2 – 1), which is two octets per frame (single-lane mode). For a two-lane output (one octet per frame), set these bits to 00000000. Note that in order to override default, CTRL_F must be set to '1'. K[4:0] A7 4:0 These bits control the number of frames per each multiframe (minus 1). Default depends on value of bits F[7:0]. When F = 0 (10x mode), K = 16 (17 frames per multiframe) When F = 1 (20x mode), K = 8 (nine frames per multiframe) Note that to override the default value of bits K[4:0], CTRL_K must be set to '1'. When CTRL_K is set to '1', the value programmed in bits A7[4:0] denotes the number of frames per multiframe (minus 1). For example, to set the number of frames per multiframe to 23, set CTRL_K = 1 and A7[4:0] = 10110. CML_I[3:0] B0 3:0 CML buffer current select. Default (0000) is 16 mA. Current is calculated as: 16 mA +16 mA × bit 3 – 8 mA × bit 2 – 4 mA × bit 1 – 2 mA × bit 0 FORCE_OUT_LANE1 B4 3 This bit replaces the output of the 8b/10b coder (corresponding to the MSB octet) with a 10-bit word specified in the OUT_WORD_LANE1[9:0] bits. B6 7:0 B7 7:6 B4 6 B8 7:4 B9 7:2 These bits are a 10-bit word replacing the output of the 8b/10b coder when FORCE_OUT_LANE2 is set to ‘1’. D6 0 This bit outputs a 4-bit ADC code with low latency on the DETECT[3:0] bits. This bit outputs a 4-bit average power estimate of the input signal on the DETECT[3:0] bits. Power estimate is in dB scale in steps of approximately 1 dB. Refer to the Signal Power Estimation section. OUT_WORD_LANE1[9:0] FORCE_OUT_LANE2 OUT_WORD_LANE2[9:0] EN_SIG_EST EN_PWR_EST D6 5 SAMPLES_PWR_EST[2:0] D6 4:2 These bits are a 10-bit word replacing the output of the 8b/10b coder when FORCE_OUT_LANE1 is set to ‘1’. This bit replaces the output of the 8b/10b coder (corresponding to the LSB octet) with a 10-bit word specified in the OUT_WORD_LANE2[9:0] bits. These bits determine the number of samples to average for power estimation. These bits are programmable from 1K to 16K. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS61JB46 29 ADS61JB46 SBAS611B – SEPTEMBER 2013 – REVISED OCTOBER 2013 www.ti.com REGISTER MODES A brief summary of different register modes and respective locations in the digital processing flow of the ADS61JB46 is shown in Figure 45 and Figure 46. ADC Digital Block (Data Format, Digital Gain) ADC FINE_GAIN[3:0] DFS ADC Test Pattern Generator To Frame to Octet Conversion JESD Test Pattern Generator JESD Test Mode Generator ADC_TEST_PAT[2:0] TEST0, TEST1 TESTMODE_EN Figure 45. Register Modes Before Frame to Octet Conversion Block MSB octet TXMIT_LINKDATA_EN SYNC~ SYNC~ Decoder To SERDES TX Controller ILAS Generator OUT_WORD_LANE1[9:0] 8B, 10B Coder Frame to Octet Stream Conversion FORCE_OUT_LANE1 Scrambler Alignment Character Generator LSB octet To SERDES OUT_WORD_LANE2[9:0] FLIP_ADC_BUS SCR SCR, FALIGN, MALIGN FORCE_OUT_LANE2 Figure 46. Register Modes After Frame to Octet Conversion Block 30 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS61JB46 ADS61JB46 www.ti.com SBAS611B – SEPTEMBER 2013 – REVISED OCTOBER 2013 INITIAL LANE ALIGNMENT SEQUENCE By default, the initial lane alignment sequence is not transmitted. To enable transmission of the initial lane alignment sequence, for the two settings of F, the mapping of the link configuration fields to octets of the JESD204A specification is shown in Table 11. Table 11. Link Configuration Fields Mapping to Octets CONFIGURATION OCTET NO. MSB 6 5 4 3 2 1 X X X 2 X X X LID[4:0] = 00000 3 SCR[0], set by S_SCR X X L[4:0] = 00000 X X X 1 LSB F = 1 (20x Mode) 0 DID[7:0] = 00000000 4 5 X BID[3:0] = 0000 F[7:0] = 00000001 6 K[4:0] = 01000 (or programmed value of A7[4:0] if CTRL_K = 1) M[7:0] = 00000000 7 X N[4:0] = 01101 X X X N'[4:0] = 01111 9 X X X S[4:0] = 00000 10 HD[0] = 0 X X CF[4:0] = 00000 8 CS[1:0] = 00 11 RES1[7:0], set to all 0s 12 RES2[7:0], set to all 0s 13 FCHK[7:0] F = 0 (10x Mode) 0 DID[7:0] = 00000000 1 X X X 2 X X X LID[4:0] = 00000 for lane 1 and 00001 for lane 2 3 SCR[0], set by S_SCR X X L[4:0] = 00001 X X X 4 5 X BID[3:0] = 0000 F[7:0] = 00000000 6 K[4:0] = 10000 (or programmed value of A7[4:0] if CTRL_K = 1) M[7:0] = 00000000 7 X N[4:0] = 01101 X X X N'[4:0] = 01111 9 X X X S[4:0] = 00000 10 HD[0] = 0 X X CF[4:0] = 00000 8 CS[1:0] = 00 11 RES1[7:0], set to all 0s 12 RES2[7:0], set to all 0s 13 FCHK[7:0] Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS61JB46 31 ADS61JB46 SBAS611B – SEPTEMBER 2013 – REVISED OCTOBER 2013 www.ti.com APPLICATION INFORMATION THEORY OF OPERATION The ADS61JB46 is a buffered analog input, ultralow power ADC with maximum sampling rates up to 160 MSPS. The conversion process is initiated by a rising edge of the external input clock and the analog input signal is also sampled. The sampled signal is sequentially converted by a series of small-resolution stages, with the outputs combined in a digital correction logic block. At every clock edge the sample propagates through the pipeline, resulting in a data latency of 20 clock cycles. The output is available as 14-bit data, coded in either straight offset binary or binary twos complement format, with a JESD207A interface in CML logic levels. ANALOG INPUTS The analog input pins have analog buffers (running off of the AVDD3V supply) that internally drive the differential sampling circuit. As a result of the analog buffer, the input pins present high input impedance to the external driving source (10-kΩ dc resistance and 3-pF input capacitance). The buffer helps isolate the external driving source from the switching currents of the sampling circuit. This buffering makes driving buffered inputs easier when compared to an ADC without the buffer. The input common-mode is set internally using a 5-kΩ resistor from each input pin to 1.95 V, so the input signal can be ac-coupled to the pins. Each input pin (INP, INM) must swing symmetrically between (VCM + 0.5 V) and (VCM – 0.5 V), resulting in a 2-VPP differential input swing. The input sampling circuit has a high 3-dB bandwidth that extends up to 450 MHz (measured from the input pins to the sampled voltage). Figure 47 shows an equivalent circuit for the analog input. LPIN1 1 nH (±0.2 nH) ROUTE1 15 W (±3 W) INP_PIN INP_ADC 5 pF (±0.5 pF) CBUF1 0.5 pF CESD1 5000 W (±600 W) RVCM1 5 W (±2 W) RBUF1 0.5 pF CPBUF1 5000 W (±600 W) RVCM2 LPIN2 1 nH (±0.2 nH) ROUTE2 15 W (±3 W) INM_PIN INM_ADC 5 pF (±0.5 pF) CBUF2 0.5 pF CESD2 5 W (±2 W) RBUF2 0.5 pF CPBUF2 Figure 47. Analog Input Equivalent Circuit 32 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS61JB46 ADS61JB46 www.ti.com SBAS611B – SEPTEMBER 2013 – REVISED OCTOBER 2013 DRIVE CIRCUIT REQUIREMENTS For optimum performance, the analog inputs must be driven differentially. This technique improves the commonmode noise immunity and even-order harmonic rejection. A small resistor (5 Ω) in series with each input pin is recommended to damp out ringing caused by package parasitics. Figure 48 and Figure 49 show the differential impedance (ZIN = RIN || CIN) at the ADC input pins. The presence of the analog input buffer results in an almost constant input capacitance up to 1 GHz. INP CIN RIN INM Note that at frequency (f), the real part of input impedance (input resistance) = RIN, the imaginary part of input impedance = 1 / (2 × πF × CIN), and input capacitance = CIN. Figure 48. Analog Input Equivalent Impedance Model Frequency - MHz Frequency - MHz Frequency - MHz Figure 49. RIN and CIN versus Frequency Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS61JB46 33 ADS61JB46 SBAS611B – SEPTEMBER 2013 – REVISED OCTOBER 2013 www.ti.com EXAMPLE DRIVING CIRCUITS Two example driving circuit configurations are shown in Figure 50 and Figure 51, one optimized for low input frequencies and the other for high input frequencies. The presence of internal analog buffers makes the ADS61JB46 simple to drive by absorbing any ADC kick-back noise. The mismatch in the transformer parasitic capacitance (between the windings) results in degraded even-order harmonic performance. Connecting two identical RF transformers back-to-back helps minimize this mismatch and good performance is obtained in the input frequency range of interest. The drive circuit for low input frequencies (< 200 MHz) in Figure 50 uses two back-to-back connected ADT1-1 transformers terminated by 50 Ω near the ADC side. An additional termination resistor pair may be required between the two transformers to improve even-order harmonic performance, as shown in drive circuit for high input frequencies (> 200 MHz) in Figure 51. The center point of this termination is connected to ground to improve the balance between the P (positive) and M (negative) sides. The example circuit in Figure 51 uses two back-to-back connected ADTL2-18 transformers with a 200-Ω termination between them and a secondary 100 Ω at the second transformer to obtain an effective 50 Ω (for a 50-Ω source impedance). The ac-coupling capacitors allow the analog inputs to self-bias around the required common-mode voltage. 0.1 mF 5W INP 0.1 mF 25 W 25 W INM 5W 1:1 1:1 Figure 50. Drive Circuit with Low Bandwidth (for Low Input Frequencies) 0.1 mF 5W INP 100 W 0.1 mF 50 W 50 W 100 W INM 5W 1:2 2:1 Figure 51. Drive Circuit with High Bandwidth (for High Input Frequencies) 34 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS61JB46 ADS61JB46 www.ti.com SBAS611B – SEPTEMBER 2013 – REVISED OCTOBER 2013 CLOCK INPUT The ADS61JB46 clock inputs can be driven differentially by a sine, LVPECL, or LVDS source with little or no difference in performance between them. The common-mode voltage of the clock inputs is set to 0.95 V using internal 5-kΩ resistors, as shown in Figure 52. This setting allows the use of transformer-coupled drive circuits for a sine-wave clock or ac-coupling for LVPECL and LVDS clock sources (see Figure 53, Figure 54, and Figure 55). For best performance, the clock inputs must be driven differentially, thereby reducing susceptibility to common-mode noise. TI recommends keeping the differential voltage between clock inputs less than 1.8 VPP to obtain best performance. For high input frequency sampling, TI recommends using a clock source with very low jitter. Band-pass filtering of the clock source can help reduce the effects of jitter. There is no change in performance with a non-50% duty cycle clock input. Clock Buffer LPKG ~ 2 nH 20 Ω CLKP CBOND ~ 1 pF CEQ RESR ~ 100 Ω CEQ 5 kΩ 0.95V LPKG ~ 2 nH 5 kΩ 20 Ω CLKM CBOND ~ 1 pF RESR ~ 100 Ω NOTE: CEQ is 1 pF to 3 pF and is the equivalent input capacitance of the clock buffer. Figure 52. Internal Clock Buffer 0.1 μF Zo 0.1 μF CLKP Differential Sine-Wave Clock Input CLKP Typical LVDS Clock Input RT 100 Ω Zo 0.1 μF CLKM 0.1 μF CLKM Figure 54. LVDS Clock Driving Circuit Figure 53. Differential Sine-Wave Clock Driving Circuit Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS61JB46 35 ADS61JB46 SBAS611B – SEPTEMBER 2013 – REVISED OCTOBER 2013 www.ti.com Zo 0.1 μF CLKP 150 Ω Typical LVPECL Clock Input 100 Ω Zo 0.1 μF CLKM 150 Ω Figure 55. LVPECL Clock Driving Circuit FINE-GAIN CONTROL The ADS61JB46 includes gain settings that can be used to obtain improved SFDR performance (compared to no gain). The gain is programmable from 0 dB to 6 dB (in 0.5-dB steps). For each gain setting, the analog input fullscale range scales proportionally, as shown in Table 12. SFDR improvement is achieved at the expense of SNR; for each gain setting, SNR degrades approximately 0.5 dB. SNR degradation is reduced at high input frequencies. As a result, fine gain is very useful at high input frequencies because SFDR improvement is significant with marginal degradation in SNR. Therefore, fine gain can be used to trade-off between SFDR and SNR. Note that the default gain after reset is 0 dB. Table 12. Full-Scale Range Across Gains FINE_GAIN[3:0] GAIN (dB) 0000 0 TYPE FULL-SCALE (VPP) 2.00 0001 0.5 1.89 0010 1 1.78 0011 1.5 1.68 0100 2 1.59 0101 2.5 1.5 Fine gain, programmable (default after reset) 0110 3 0111 3.5 1.42 1.34 1000 4 1.26 1001 4.5 1.19 1010 5 1.12 1011 5.5 1.06 1100 6 1.00 1101 1110 Do not use 1111 36 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS61JB46 ADS61JB46 www.ti.com SBAS611B – SEPTEMBER 2013 – REVISED OCTOBER 2013 SIGNAL POWER ESTIMATION The device includes a power estimation circuit that can be used to obtain a coarse power estimate (accurate to within a dB) of the input signal averaged over a programmable number of samples. Enable the EN_PWR_EST bit in order to make the power estimate available on the DETECT[3:0] pins. The states of the DETECT[3:0] bits map to the input signal power as shown in Table 13. Table 13. State of DETECT[3:0] Versus Input Signal Power INPUT SIGNAL POWER RANGE (dBFS) DETECT[3:0] INPUT SIGNAL POWER RANGE (dBFS) DETECT[3:0] –Inf to –12.5 0001 –6.5 to –5.5 1000 –12.5 to –11.5 0010 –5.5 to –4.5 1001 –11.5 to –10.5 0011 –4.5 to –3.5 1010 –10.5 to –9.5 0100 –3.5 to –2.5 1011 –9.5 to –8.5 0101 –2.5 to –1.5 1100 –8.5 to –7.5 0110 –1.5 to 0 1101 –7.5 to –6.5 0111 0 to +1 1110 The number of samples used for computing the average power is set by SAMPLES_PWR_EST[2:0], as shown in Table 14. Table 14. Number of Samples Used for Power Estimation SAMPLES_PWR_EST[2:0] NUMBER OF SAMPLES 000 1K 001 2K 010 4K 011 8K 100 16K Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS61JB46 37 ADS61JB46 SBAS611B – SEPTEMBER 2013 – REVISED OCTOBER 2013 www.ti.com DEFINITION OF SPECIFICATIONS Analog Bandwidth: The analog input frequency at which the power of the fundamental is reduced by 3 dB with respect to the low-frequency value. Aperture Delay: The delay in time between the rising edge of the input sampling clock and the actual time at which the sampling occurs. This delay is different across channels. The maximum variation is specified as aperture delay variation (channel-to-channel). Aperture Uncertainty (Jitter): The sample-to-sample variation in aperture delay. Clock Pulse Duration and Duty Cycle: The duty cycle of a clock signal is the ratio of the time the clock signal remains at a logic high (clock pulse duration) to the period of the clock signal. Duty cycle is typically expressed as a percentage. A perfect differential sine-wave clock results in a 50% duty cycle. Maximum Conversion Rate: The maximum sampling rate at which certified operation is given. All parametric testing is performed at this sampling rate unless otherwise noted. Minimum Conversion Rate: The minimum sampling rate at which the ADC functions. Differential Nonlinearity (DNL): An ideal ADC exhibits code transitions at analog input values spaced exactly 1 LSB apart. DNL is the deviation of any single step from this ideal value, measured in units of LSBs. Integral Nonlinearity (INL): INL is the deviation of the ADC transfer function from a best-fit line determined by a least-squares-curve fit of that transfer function, measured in units of LSBs. Gain Error: Gain error is the deviation of the ADC actual input full-scale range from its ideal value. Gain error is given as a percentage of the ideal input full-scale range. Gain error has two components: error resulting from reference inaccuracy and error resulting from the channel. Both errors are specified independently as EGREF and EGCHAN, respectively. To a first-order approximation, the total gain error is ETOTAL ~ EGREF + EGCHAN. For example, if ETOTAL = ±0.5%, the full-scale input varies from (1 – 0.5 / 100) × FSideal to (1 + 0.5 / 100) × FSideal. Offset Error: Offset error is the difference, given in number of LSBs, between the ADC actual average idle channel output code and the ideal average idle channel output code. This quantity is often mapped into millivolts. Temperature Drift: The temperature drift coefficient (with respect to gain and offset error) specifies the change per degree Celsius of the parameter from TMIN to TMAX. The coefficient is calculated by dividing the maximum deviation of the parameter across the TMIN to TMAX range by the difference of TMAX – TMIN. Signal-to-Noise Ratio (SNR): SNR is the ratio of the power of the fundamental (PS) to the noise floor power (PN), excluding the power at dc and the first nine harmonics. SNR = 10Log10 PS PN (1) SNR is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full-scale) when the power of the fundamental is extrapolated to the converter fullscale range. Signal-to-Noise and Distortion (SINAD): SINAD is the ratio of the power of the fundamental (PS) to the power of all other spectral components including noise (PN) and distortion (PD), but excluding dc. SINAD = 10Log10 PS PN + PD (2) SINAD is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full-scale) when the power of the fundamental is extrapolated to the converter fullscale range. 38 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS61JB46 ADS61JB46 www.ti.com SBAS611B – SEPTEMBER 2013 – REVISED OCTOBER 2013 Effective Number of Bits (ENOB): ENOB is a measure of the converter performance as compared to the theoretical limit based on quantization noise. ENOB = SINAD - 1.76 6.02 (3) Total Harmonic Distortion (THD): THD is the ratio of the power of the fundamental (PS) to the power of the first nine harmonics (PD). THD = 10Log10 PS PN (4) THD is typically given in units of dBc (dB to carrier). Spurious-Free Dynamic Range (SFDR): SFDR is the ratio of the power of the fundamental to the highest other spectral component (either spur or harmonic). SFDR is typically given in units of dBc (dB to carrier). Two-Tone Intermodulation Distortion (IMD3): IMD3 is the ratio of the power of the fundamental (at frequencies f1 and f2) to the power of the worst spectral component at either frequency (2f1 – f2) or (2f2 – f1). IMD3 is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full-scale) when the power of the fundamental is extrapolated to the converter full-scale range. DC Power-Supply Rejection Ratio (DC PSRR): DC PSSR is the ratio of the change in offset error to a change in analog supply voltage. DC PSRR is typically given in units of millivolts per volt. AC Power-Supply Rejection Ratio (AC PSRR): AC PSRR is the measure of rejection of variations in the supply voltage by the ADC. If ΔVSUP is the change in supply voltage and ΔVOUT is the resultant change of the ADC output code (referred to the input), then: DVOUT PSRR = 20Log 10 (Expressed in dBc) DVSUP (5) Voltage Overload Recovery: The number of clock cycles taken to recover to less than 1% error after an overload on the analog inputs. This overload recovery is tested by separately applying a sine-wave signal with a 6-dB positive and negative overload. The deviation of the first few samples after the overload (from the expected values) is noted. Common Mode Rejection Ratio (CMRR): CMRR is the measure of rejection of variation in the analog input common-mode by the ADC. If ΔVCM_IN is the change in the common-mode voltage of the input pins and ΔVOUT is the resultant change of the ADC output code (referred to the input), then: DVOUT CMRR = 20Log10 (Expressed in dBc) DVCM (6) Crosstalk (only for multichannel ADCs): Crosstalk is a measure of the internal coupling of a signal from adjacent channel into the channel of interest. Crosstalk is specified separately for coupling from the immediate neighboring channel (near-channel) and for coupling from a channel across the package (far-channel). Crosstalk is usually measured by applying a full-scale signal in the adjacent channel. Crosstalk is the ratio of the power of the coupling signal (as measured at the output of the channel of interest) to the power of the signal applied at the adjacent channel input. Crosstalk is typically expressed in dBc (dB to carrier). Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS61JB46 39 ADS61JB46 SBAS611B – SEPTEMBER 2013 – REVISED OCTOBER 2013 www.ti.com REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (October 2013) to Revision B Page • Changed document status from Product Preview to Production Data ................................................................................. 1 • Changed Power-Down Modes, Fast recovery power-down mode, DNL, and INL parameter specifications in Electrical Characteristics table .............................................................................................................................................. 4 • Changed Power-Supply Currents, IIOVDD parameter name in Electrical Characteristics table .............................................. 4 • Changed fS value in footnote 2 of Electrical Characteristics table ........................................................................................ 4 • Changed CML Outputs, IOVDD supply range parameter minimum specification in Digital Characteristics table ............... 5 • Changed description of DETECT[3:0], OVR, and RESET pins in Pin Functions table ...................................................... 12 • Changed DAC to ADC in functional block diagram ............................................................................................................ 13 • Deleted Differential Nonlinearity (DNL) and Integrated Nonlinearity (INL) curves from Typical Characteristics ................ 19 • Changed legend in Figure 38 ............................................................................................................................................. 21 • Changed footnote 1 in Table 9 ........................................................................................................................................... 26 • Changed Serial Register Readout section into two sections: Serial Register Readout and Reset Timing ........................ 27 • Changed number of clock cycles for data latency in Theory of Operation section ............................................................ 32 • Changed 2-pF input capacitance to 3-pF input capacitance in Analog Inputs section ....................................................... 32 Changes from Original (September 2013) to Revision A Page • Changed data rate value in 1st Features bullet .................................................................................................................... 1 • Changed dual-lane mode value in 2nd Features bullet ........................................................................................................ 1 • Changed 4th and 5th Features bullets ................................................................................................................................. 1 • Added Recommended Operating Conditions table and Table 1 .......................................................................................... 3 • Added Electrical Characteristics tables ................................................................................................................................ 4 • Added Parametric Measurement Information section ........................................................................................................... 6 • Added Pin Configuration section ........................................................................................................................................ 11 • Added Functional Block Diagram section ........................................................................................................................... 13 • Added Typical Characteristics sections .............................................................................................................................. 14 • Added Device Configuration section ................................................................................................................................... 24 • Added Application Information section ............................................................................................................................... 32 40 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS61JB46 PACKAGE OPTION ADDENDUM www.ti.com 18-Oct-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) ADS61JB46IRHAR ACTIVE VQFN RHA 40 2500 Green (RoHS & no Sb/Br) CU NIPDAU | Call TI Level-3-260C-168 HR -40 to 85 61JB46 ADS61JB46IRHAT ACTIVE VQFN RHA 40 250 Green (RoHS & no Sb/Br) CU NIPDAU | Call TI Level-3-260C-168 HR -40 to 85 61JB46 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 18-Oct-2013 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADS61JB46IRHAR VQFN RHA 40 2500 330.0 16.4 6.3 6.3 1.5 12.0 16.0 Q2 ADS61JB46IRHAT VQFN RHA 40 250 330.0 16.4 6.3 6.3 1.5 12.0 16.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS61JB46IRHAR VQFN RHA 40 2500 336.6 336.6 28.6 ADS61JB46IRHAT VQFN RHA 40 250 336.6 336.6 28.6 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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