AD ADG3245BRU 2.5 v/3.3 v, 8-bit, 2-port level translating, bus switch Datasheet

2.5 V/3.3 V, 8-Bit, 2-Port
Level Translating, Bus Switch
ADG3245
FEATURES
225 ps Propagation Delay through the Switch
4.5 ⍀ Switch Connection between Ports
Data Rate 1.244 Gbps
2.5 V/3.3 V Supply Operation
Selectable Level Shifting/Translation
Level Translation
3.3 V to 2.5 V
3.3 V to 1.8 V
2.5 V to 1.8 V
Small Signal Bandwidth 610 MHz
20-Lead TSSOP and LFCSP Packages
FUNCTIONAL BLOCK DIAGRAM
APPLICATIONS
3.3 V to 1.8 V Voltage Translation
3.3 V to 2.5 V Voltage Translation
2.5 V to 1.8 V Voltage Translation
Bus Switching
Bus Isolation
Hot Swap
Hot Plug
Analog Switch Applications
A0
B0
A7
B7
BE
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The ADG3245 is a 2.5 V or 3.3 V, 8-bit, 2-port digital switch.
It is designed on Analog Devices’ low voltage CMOS process,
which provides low power dissipation yet gives high switching
speed and very low on resistance, allowing inputs to be connected
to outputs without additional propagation delay or generating
additional ground bounce noise.
1.
2.
3.
4.
5.
3.3 V or 2.5 V supply operation
Extremely low propagation delay through switch
4.5 W switches connect inputs to outputs
Level/voltage translation
20-lead TSSOP and LFCSP (4 mm ¥ 4 mm) packages
The switches are enabled by means of the bus enable (BE) input
signal. These digital switches allow bidirectional signals to be
switched when ON. In the OFF condition, signal levels up to
the supplies are blocked.
This device is ideal for applications requiring level translation.
When operated from a 3.3 V supply, level translation from 3.3 V
inputs to 2.5 V outputs is allowed. Similarly, if the device is
operated from a 2.5 V supply and 2.5 V inputs are applied, the
device will translate the outputs to 1.8 V. In addition to this, a
level translating select pin (SEL) is included. When SEL is low,
VCC is reduced internally, allowing for level translation between
3.3 V inputs and 1.8 V outputs. This makes the device suited to
applications requiring level translation between different supplies,
such as converter to DSP/microcontroller interfacing.
Rev. B
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ADG3245–SPECIFICATIONS1
Parameter
Symbol
DC ELECTRICAL CHARACTERISTICS
Input High Voltage
VINH
VINH
Input Low Voltage
VINL
VINL
Input Leakage Current
II
OFF State Leakage Current
IOZ
ON State Leakage Current
Maximum Pass Voltage
VP
CAPACITANCE3
A Port Off Capacitance
B Port Off Capacitance
A, B Port On Capacitance
Control Input Capacitance
SWITCHING CHARACTERISTICS3
Propagation Delay A to B or B to A, tPD4
Propagation Delay Matching5
Bus Enable Time BE to A or B6
Bus Disable Time BE to A or B6
Bus Enable Time BE to A or B6
Bus Disable Time BE to A or B6
Bus Enable Time BE to A or B6
Bus Disable Time BE to A or B6
Maximum Data Rate
Channel Jitter
Operating Frequency—Bus Enable
DIGITAL SWITCH
On Resistance
On Resistance Matching
POWER REQUIREMENTS
VCC
Quiescent Power Supply Current
Increase in ICC per Input7
(VCC = 2.3 V to 3.6 V, GND = 0 V, all specifications TMIN to TMAX, unless
otherwise noted.)
Conditions
Min
VCC = 2.7 V to 3.6 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 2.3 V to 2.7 V
2.0
1.7
0 £ A, B £ VCC
0 £ A, B £ VCC
VA/VB = VCC = SEL = 3.3 V, IO = –5 mA
VA/VB = VCC = SEL = 2.5 V, IO= –5 mA
VA/VB = VCC = 3.3 V, SEL = 0 V, IO= –5 mA
CA OFF
CB OFF
CA, CB ON
CIN
f = 1 MHz
f = 1 MHz
f = 1 MHz
f = 1 MHz
tPHL, tPLH
CL = 50 pF, VCC = SEL = 3 V
tPZH, tPZL
tPHZ, tPLZ
tPZH, tPZL
tPHZ, tPLZ
tPZH, tPZL
tPHZ, tPLZ
VCC = 3.0 V to 3.6 V; SEL = VCC
VCC = 3.0 V to 3.6 V; SEL = VCC
VCC = 3.0 V to 3.6 V; SEL = 0 V
VCC = 3.0 V to 3.6 V; SEL = 0 V
VCC = 2.3 V to 2.7 V; SEL = VCC
VCC = 2.3 V to 2.7 V; SEL = VCC
VCC = SEL = 3.3 V; VA/VB = 2 V
VCC = SEL = 3.3 V; VA/VB = 2 V
2.0
1.5
1.5
B Version
Typ2
Max
± 0.01
± 0.01
± 0.01
2.5
1.8
1.8
5
5
10
6
1
1
0.5
0.5
0.5
0.5
3.2
3.2
2.2
1.7
2.2
1.75
1.244
50
fBE
RON
⌬RON
VCC = 3 V, SEL = VCC, VA = 0 V, IBA = 8 mA
VCC = 3 V, SEL = VCC, VA = 1.7 V, IBA = 8 mA
VCC = 2.3 V, SEL = VCC, VA = 0 V, IBA = 8 mA
VCC = 2.3 V, SEL = VCC, VA = 1 V, IBA = 8 mA
VCC = 3 V, SEL = 0 V VA = 0 V, IBA = 8 mA
VCC = 3 V, SEL = 0 V, VA = 1 V, IBA = 8 mA
VCC = 3 V, SEL = VCC, VA = 0 V, IBA = 8 mA
VCC = 3 V, SEL = VCC, VA = 1 V, IBA = 8 mA
4.5
15
5
11
5
14
0.45
0.65
⌬ICC
Digital Inputs = 0 V or VCC; SEL = VCC
Digital Inputs = 0 V or VCC ; SEL = 0 V
VCC = 3.6 V, BE = 3.0 V; SEL = VCC
0.001
0.65
V
V
V
V
mA
mA
mA
V
V
V
pF
pF
pF
pF
0.225
22.5
4.8
4.8
3.3
2.9
3
2.6
10
2.3
ICC
0.8
0.7
±1
±1
±1
2.9
2.1
2.1
Unit
ns
ps
ns
ns
ns
ns
ns
ns
Gbps
ps p-p
MHz
8
28
9
18
8
W
W
W
W
W
W
W
W
3.6
1
1.2
130
V
mA
mA
mA
NOTES
1
Temperature range is as follows: B Version: –40rC to +85rC.
2
Typical values are at 25rC, unless otherwise stated.
3
Guaranteed by design, not subject to production test.
4
The digital switch contributes no propagation delay other than the RC delay of the typical R ON of the switch and the load capacitance when driven by an ideal voltage
source. Since the time constant is much smaller than the rise/fall times of typical driving signals, it adds very little propagation delay to the system. Propagation delay
of the digital switch when used in a system is determined by the driving circuit on the driving side of the switch and its interaction with the load on the driven side.
5
Propagation delay matching between channels is calculated from the on resistance matching and load capacitance of 50 pF.
6
See Timing Measurement Information section.
7
This current applies to the control pin BE only. The A and B ports contribute no significant ac or dc currents as they transition.
Specifications subject to change without notice.
–2–
REV. B
ADG3245
LFCSP Package
␪JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . .30.4°C/W
TSSOP Package
␪JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 143°C/W
Lead Temperature, Soldering (10 seconds) . . . . . . . . . . 300°C
IR Reflow, Peak Temperature (<20 seconds) . . . . . . . . 235°C
ABSOLUTE MAXIMUM RATINGS*
(TA = 25°C, unless otherwise noted.)
VCC to GND . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +4.6 V
Digital Inputs to GND . . . . . . . . . . . . . . . . . –0.5 V to +4.6 V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.5 V to +4.6 V
DC Output Current . . . . . . . . . . . . . . . . . . 25 mA per channel
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.
Table I. Pin Description
Mnemonic
BE
SEL
Ax
Bx
EP
Description
Bus Enable (Active Low)
Level Translation Select
Port A, Inputs or Outputs
Port B, Inputs or Outputs
Exposed Pad. It is recommended
that the exposed pad be thermally
connected to a copper plane for
enhanced thermal performance.
The pad should be grounded as
well.
Table II. Truth Table
BE
SEL*
Function
L
L
H
L
H
X
A = B, 3.3 V to 1.8 V Level Shifting
A = B, 3.3 V to 2.5 V/2.5 V to 1.8 V Level Shifting
Disconnect
*SEL = 0 V only when V DD = 3.3 V ± 10%
20
19
18
17
16
A3
A2
A1
A0
VCC
PIN CONFIGURATION
20-Lead LFCSP and TSSOP
1
2
3
4
5
ADG3245
TOP VIEW
(Not to Scale)
15
14
13
12
11
BE
B0
B1
B2
B3
20
VCC
A0 2
19
BE
A1 3
18
B0
A2 4
17
B1
A3 5
16
B2
ADG3245
TOP VIEW 15 B3
(Not to Scale)
14 B4
A5 7
A4 6
GND 6
B7 7
B6 8
B5 9
B4 10
SEL
A4
A5
A6
A7
SEL 1
NOTES
1. IT IS RECOMMENDED THAT THE EXPOSED PAD BE
THERMALLY CONNECTED TO A COPPER PLANE
FOR ENHANCED THERMAL PERFORMANCE. THE
PAD SHOULD BE GROUNDED AS WELL.
A6 8
13
A7 9
12
B6
GND 10
11
B7
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADG3245 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
EP
REV. A
REV. B
ExposedPad.Itis
recommendedthat
theexposedpadbe
thermallyconnected
toacopperplanefor
enhancedthermal
performance.Thepad
shouldbegroundedas
well.
–11–
–3–
B5
ADG3245
TERMINOLOGY
VCC
GND
VINH
VINL
II
IOZ
IOL
VP
RON
⌬RON
CX OFF
CX ON
CIN
ICC
⌬ICC
tPLH, tPHL
tPZH, tPZL
tPHZ, tPLZ
Max Data Rate
Channel Jitter
fBE
Positive Power Supply Voltage.
Ground (0 V) Reference.
Minimum Input Voltage for Logic 1.
Maximum Input Voltage for Logic 0.
Input Leakage Current at the Control Inputs.
OFF State Leakage Current. It is the maximum leakage current at the switch pin in the OFF state.
ON State Leakage Current. It is the maximum leakage current at the switch pin in the ON state.
Maximum Pass Voltage. The maximum pass voltage relates to the clamped output voltage of an NMOS device
when the switch input voltage is equal to the supply voltage.
Ohmic Resistance Offered by a Switch in the ON State. It is measured at a given voltage by forcing a specified
amount of current through the switch.
On Resistance Match between Any Two Channels, i.e., RON Max – RON Min.
OFF Switch Capacitance.
ON Switch Capacitance.
Control Input Capacitance. This consists of BE and SEL.
Quiescent Power Supply Current. This current represents the leakage current between the VCC and ground pins.
It is measured when all control inputs are at a logic HIGH or LOW level and the switches are OFF.
Extra power supply current component for the BE control input when the input is not driven at the supplies.
Data Propagation Delay through the Switch in the ON State. Propagation delay is related to the RC time constant
RON ¥ CL, where CL is the load capacitance.
Bus Enable Times. These are the times taken to cross the VT voltage at the switch output when the switch turns on
in response to the control signal, BE.
Bus Disable Times. This is the time taken to place the switch in the high impedance OFF state in response to the control
signal. It is measured as the time taken for the output voltage to change by V⌬ from the original quiescent level,
with reference to the logic level transition at the control input. (Refer to Figure 3 for enable and disable times.)
Maximum Rate at which Data Can Be Passed through the Switch.
Peak-to-Peak Value of the Sum of the Deterministic and Random Jitter of the Switch Channel.
Operating Frequency of Bus Enable. This is the maximum frequency at which bus enable (BE) can be toggled.
–4–
REV. B
Typical Performance Characteristics–ADG3245
40
40
VCC = 3V
TA = 25ⴗC
SEL = VCC
35
TA = 25ⴗC
SEL = VCC
35
30
30
VCC = 3.3V
20
RON – ⍀
25
25
VCC = 2.5V
20
15
VCC = 3V
TA = 25ⴗC
SEL = 0V
35
30
RON – ⍀
RON – ⍀
40
VCC = 2.3V
25
VCC = 3.3V
20
15
15
VCC = 3.6V
VCC = 2.7V
10
VCC = 3.6V
5
0
0
0.5
1.0
2.0
1.5
VA/VB – V
3.0
2.5
10
10
5
5
0
3.5
0
0
TPC 1. On Resistance vs.
Input Voltage
0.5
1.0
2.0
1.5
VA/VB – V
2.5
3.0
0
1.0
2.0
1.5
VA/VB – V
3.0
15
VCC = 3.3V
3.0
3.5
SEL = VCC
VCC = 3.6V
TA = 25ⴗC
SEL = VCC
IO = –5␮A
VCC = 2.5V
SEL = VCC
2.5
TPC 3. On Resistance vs.
Input Voltage
TPC 2. On Resistance vs.
Input Voltage
20
0.5
2.5
10
ⴙ85ⴗC
10
VOUT – V
RON – ⍀
RON – ⍀
15
ⴙ85ⴗC
VCC = 3.3V
VCC = 3V
1.5
1.0
5
5
2.0
ⴚ40ⴗC
ⴙ25ⴗC
ⴙ25ⴗC
0.5
ⴚ40ⴗC
0
0
1.0
VA/VB – V
0.5
0
2.0
1.5
TPC 4. On Resistance vs. Input
Voltage for Different Temperatures
0.5
VA/VB – V
1.2
1.0
TPC 5. On Resistance vs. Input
Voltage for Different Temperatures
2.5
0
0.5
1.0
2.0
1.5
VCC – V
2.5
3.0
3.5
TPC 6. Pass Voltage vs. VCC
1800
2.5
TA = 25ⴗC
SEL = VCC
IO = –5␮A
2.0
TA = 25ⴗC
SEL = 0V
IO = –5␮A
VCC = 2.7V
2.0
VCC = 3.6V
TA = 25ⴗC
1600
1400
VCC = 2.5V
VCC = 2.3V
1.0
1.5
VCC = 3.3V
VCC = 3V
1.0
ICC – ␮A
1200
1.5
VOUT – V
VOUT – V
0
0
VCC = 3.3V, SEL = 0V
1000
800
600
0.5
VCC = SEL = 3.3V
400
0.5
VCC = SEL = 2.5V
200
0
0
0.5
1.0
2.0
1.5
VCC – V
2.5
TPC 7. Pass Voltage vs. VCC
REV. B
3.0
0
0
0.5
1.0
1.5
2.0
VCC – V
2.5
3.0
TPC 8. Pass Voltage vs. VCC
–5–
3.5
0
0
2
4
6
8 10 12 14 16 18 20
ENABLE FREQUENCY – MHz
TPC 9. ICC vs. Enable Frequency
ADG3245
3.0
3.0
TA = 25ⴗC
VA = 0V
BE = 0
2.5
1.5
VCC = SEL = 3.3V
1.0 V = SEL = 2.5V
CC
0.5
0.5
0.02
0.04
0.06
IO – A
0.08
TPC 10. Output Low Characteristic
–0.06
–0.04
IO – A
–0.02
0
0
–6
–8
–10
–12
–40
–50
–30
–60
–70
0.03
0.1
TPC 13. Bandwidth vs. Frequency
–50
–90
1
10
100
FREQUENCY – MHz
ENABLE
VCC = 3.3V, SEL = 0V
1.5
1000
VCC = SEL = 3.3V
VIN = 2V p-p
20dB ATTENUATION
70
DISABLE
JITTER – ps
DISABLE
TIME – ns
TIME – ns
2.0
80
VCC = SEL = 2.5V
2.5
ENABLE
1
10
100
FREQUENCY – MHz
TPC 15. Off Isolation vs.
Frequency
90
2.0
0.1
100
2.5
DISABLE
TA = 25ⴗC
VCC = 3.3V/2.5V
SEL = V CC
VIN = 0dBm
N/W ANALYZER:
RL = RS = 50⍀
0.03
1000
TPC 14. Crosstalk vs. Frequency
VCC = SEL = 3.3V
3.0
–100
0.1
ENABLE
3.0
2.5
–70
–90
0.03
3.5
1.5
2.0
VA/VB – V
–60
–80
1000
1
10
100
FREQUENCY – MHz
–40
–80
–100
–14
1.0
TPC 12. Charge Injection vs.
Source Voltage
ATTENUATION – dB
–4
0.5
–20
TA = 25ⴗC
VCC = 3.3V/2.5V
SEL = V CC
ADJACENT CHANNELS
VIN = 0dBm
N/W ANALYZER:
RL = RS = 50⍀
–30
ATTENUATION – dB
ATTENUATION – dB
–2.0
–0.08
–20
TA = 25ⴗC
VCC = 3.3V/2.5V
SEL = V CC
VIN = 0dBm
N/W ANALYZER:
RL = RS = 50⍀
VCC = 3.3V
–1.8
TPC 11. Output High Characteristic
0
–2
–1.0
–1.2
–1.6
0
–0.10
0.10
VCC = 2.5V
–0.8
–1.4
VCC = 3.3V; SEL = 0V
VCC = SEL = 2.5V
0
–0.6
1.5
1.0
0
SEL = VCC
ON OFF
CL = InF
–0.4
VCC = SEL = 3.3V
2.0
VCC = 3.3V; SEL = 0V
VOUT – V
VOUT – V
2.0
TA = 25ⴗC
–0.2
QINJ – pC
2.5
0
TA = 25ⴗC
VA = VCC
BE = 0
1.5
1.0
60
50
40
30
1.0
20
0.5
0.5
10
0
–40
–20
0
20
40
60
TEMPERATURE – ⴗC
80
100
TPC 16. Enable/Disable Time
vs. Temperature
0
–40
–20
0
20
40
60
TEMPERATURE – ⴗC
80
100
TPC 17. Enable/Disable Time
vs. Temperature
–6–
0
0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
DATA RATE – Gbps
TPC 18. Jitter vs. Data Rate;
PRBS 31
REV. B
ADG3245
100
95
VCC = SEL = 3.3V
VIN = 2V p-p
20dB ATTENUATION
EYE WIDTH – %
90
85
80
75
70
65
35mV/DIV
100ps/DIV
60
% EYE WIDTH = ((CLOCK PERIOD –
JITTER p-p)/CLOCK PERIOD) ⴛ 100%
55
VCC = 3.3V
SEL = 3.3V
VIN = 2V p-p
20dB
ATTENUATION
TA = 25ⴗC
37mV/DIV
200ps/DIV
VCC = 2.5V
SEL = 2.5V
VIN = 2V p-p
20dB
ATTENUATION
TA = 25ⴗC
50
0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
DATA RATE – Gbps
TPC 19. Eye Width vs. Data
Rate; PRBS 31
50.1mV/DIV
50ps/DIV
TA = 25ⴗC
TPC 20. Eye Pattern; 1.244 Gbps,
VCC = 3.3 V, PRBS 31
20dB
ATTENUATION
VCC = 3.3V
SEL = 3.3V
VIN = 2V p-p
TPC 22. Jitter @ 1.244 Gbps,
PRBS 31
REV. B
–7–
TPC 21. Eye Pattern; 1 Gbps,
VCC = 2.5 V, PRBS 31
ADG3245
TIMING MEASUREMENT INFORMATION
For the following load circuit and waveforms, the notation that is used is VIN and VOUT where
VIN = VA and VOUT = VB or VIN = VB and VOUT = VA
VCC
PULSE
GENERATOR
CONTROL
INPUT BE
GND
RL
VOUT
VIN
VIH
2 ⴛ VCC
SW1
tPLH
tPLH
VH
VT
VOUT
D.U.T.
VL
RL
CL
RT
VT
0V
Figure 2. Propagation Delay
NOTES
PULSE GENERATOR FOR ALL PULSES: tR ⱕ 2.5ns, tF ⱕ 2.5ns,
FREQUENCY ⱕ 10MHz.
CL INCLUDES BOARD, STRAY, AND LOAD CAPACITANCES.
RT IS THE TERMINATION RESISTOR, SHOULD BE EQUAL TO ZOUT
OF THE PULSE GENERATOR.
Figure 1. Load Circuit
Test Conditions
Symbol
VCC = 3.3 V ± 0.3 V (SEL = VCC)
VCC = 2.5 V ± 0.2 V (SEL = VCC)
VCC = 3.3 V ± 0.3 V (SEL = 0 V)
Unit
RL
V⌬
CL
VT
500
300
50
1.5
500
150
30
0.9
500
150
30
0.9
W
mV
pF
V
DISABLE
ENABLE
VINH
CONTROL INPUT BE
VT
Table III. Switch Position
0V
tPZL
VIN = 0V
VOUT
SW1 @ 2VCC
tPLZ
VCC
VCC
VT
VL + V⌬
VL
tPZH
VIN = VCC
VOUT
SW1 @ GND
TEST
S1
tPLZ, tPZL
tPHZ, tPZH
2 ¥ VCC
GND
tPHZ
VH
VT
0V
VH – V⌬
0V
Figure 3. Enable and Disable Times
–8–
REV. B
ADG3245
BUS SWITCH APPLICATIONS
Mixed Voltage Operation, Level Translation
2.5 V to 1.8 V Translation
When VCC is 2.5 V (SEL = 2.5 V) and the input signal range is
0 V to VCC, the maximum output signal will, as before, be clamped
to within a voltage threshold below the VCC supply.
Bus switches can be used to provide an ideal solution for interfacing between mixed voltage systems. The ADG3245 is suitable
for applications where voltage translation from 3.3 V technology
to a lower voltage technology is needed. This device can translate
from 3.3 V to 1.8 V, from 2.5 V to 1.8 V, or bidirectionally
from 3.3 V directly to 2.5 V.
2.5V
3.3V
3.3V
2.5V
3.3V ADC
ADG3245
Figure 4 shows a block diagram of a typical application in which
a user needs to interface between a 3.3 V ADC and a 2.5 V
microprocessor. The microprocessor may not have 3.3 V tolerant inputs, therefore placing the ADG3245 between the two
devices allows the devices to communicate easily. The bus
switch directly connects the two blocks, thus introducing
minimal propagation delay, timing skew, or noise.
2.5V
MICROPROCESSOR
ADG3245
2.5V
1.8V
Figure 7. 2.5 V to 1.8 V Voltage Translation, SEL = 2.5 VCC
In this case, the output will be limited to approximately
1.8 V, as shown in Figure 7.
VOUT
2.5V SUPPLY
SEL = 2.5V
SWITCH
OUTPUT
1.8V
Figure 4. Level Translation between a 3.3 V ADC
and a 2.5 V Microprocessor
3.3 V to 2.5 V Translation
0V
When VCC is 3.3 V (SEL = 3.3 V) and the input signal range is
0 V to VCC, the maximum output signal will be clamped to
within a voltage threshold below the VCC supply.
SWITCH
INPUT
VIN
2.5V
Figure 8. 2.5 V to 1.8 V Voltage Translation, SEL = VCC
3.3 V to 1.8 V Translation
The ADG3245 offers the option of interfacing between a 3.3 V
device and a 1.8 V device. This is possible through use of the
SEL pin.
3.3V
3.3V
SEL pin: An active low control pin. SEL activates internal
circuitry in the ADG3245 that allows voltage translation
between 3.3 V devices and 1.8 V devices.
2.5V
ADG3245
2.5V
2.5V
3.3V
Figure 5. 3.3 V to 2.5 V Voltage Translation, SEL = VCC
In this case, the output will be limited to 2.5 V, as shown in
Figure 6.
VOUT
3.3V
ADG3245
1.8V
3.3V SUPPLY
SEL = 3.3V
2.5V
SWITCH
OUTPUT
Figure 9. 3.3 V to 1.8 V Voltage Translation, SEL = 0 V
0V
SWITCH
INPUT
When VCC is 3.3 V and the input signal range is 0 V to VCC, the
maximum output signal will be clamped to 1.8 V, as shown in
Figure 9. To do this, the SEL pin must be tied to Logic 0. If
SEL is unused, it should be tied directly to VCC.
VIN
3.3V
Figure 6. 3.3 V to 2.5 V Voltage Translation, SEL = VCC
This device can be used for translation from 2.5 V to 3.3 V
devices and also between two 3.3 V devices.
REV. B
–9–
VOUT
3.3V SUPPLY
SEL = 0V
1.8V
SWITCH
OUTPUT
CPU
0V
RAM
SWITCH
INPUT
VIN
3.3V
ADG3245 ADG3245
ADG3245
PLUG-IN
CARD (1)
CARD I/O
PLUG-IN
CARD (2)
CARD I/O
Figure 10. 3.3 V to 1.8 V Voltage Translation, SEL = 0 V
Bus Isolation
A common requirement of bus architectures is low capacitance
loading of the bus. Such systems require bus bridge devices that
extend the number of loads on the bus without exceeding the
specifications. Because the ADG3245 is designed specifically for
applications that do not need drive yet require simple logic
functions, it solves this requirement. The device isolates access
to the bus, thus minimizing capacitance loading.
LOAD A
LOAD C
LOAD B
There are many systems that require the ability to handle hot
swapping, such as docking stations, PCI boards for servers, and
line cards for telecommunications switches. If the bus can be
isolated prior to insertion or removal, then there is more control
over the hot swap event. This isolation can be achieved using a
bus switch. The bus switches are positioned on the hot swap card
between the connector and the devices. During hot swap, the
ground pin of the hot swap card must connect to the ground pin
of the back plane before any other signal or power pins.
Analog Switching
BUS/
BACKPLANE
BUS SWITCH
LOCATION
Figure 12. ADG3245 in a Hot Plug Application
Bus switches can be used in many analog switching applications;
for example, video graphics. Bus switches can have lower on
resistance, smaller ON and OFF channel capacitance and thus
improved frequency performance than their analog counterparts.
The bus switch channel itself consisting solely of an NMOS
switch limits the operating voltage (see TPC 1 for a typical
plot), but in many cases, this does not present an issue.
LOAD D
Figure 11. Location of Bus Switched in a Bus
Isolation Application
Hot Plug and Hot Swap Isolation
The ADG3245 is suitable for hot swap and hot plug applications.
The output signal of the ADG3245 is limited to a voltage that is
below the VCC supply, as shown in Figures 6, 8, and 10. Therefore
the switch acts like a buffer to take the impact from hot insertion,
protecting vital and expensive chipsets from damage.
In hot-plug applications, the system cannot be shutdown when
new hardware is being added. To overcome this, a bus switch can
be positioned on the backplane between the bus devices and the
hot plug connectors. The bus switch is turned off during hot plug.
Figure 12 shows a typical example of this type of application.
High Impedance During Power-Up/Power-Down
To ensure the high impedance state during power-up or powerdown, BE should be tied to VCC through a pull-up resistor; the
minimum value of the resistor is determined by the currentsinking capability of the driver.
PACKAGE AND PINOUT
The ADG3245 is packaged in both a small 20-lead TSSOP or a
tiny 20-lead LFCSP package. The area of the TSSOP option is
37.5 mm2, while the area of the LFCSP option is 16 mm2. This
leads to a 57% savings in board space when using the LFCSP package compared with the TSSOP package. This makes the LFCSP
option an excellent choice for space-constrained applications.
The ADG3245 in the TSSOP package offers a flowthrough
pinout. The term flowthrough signifies that all the inputs are on
opposite sides from the outputs. A flowthrough pinout simplifies
the PCB layout.
–10–
REV. B
ADG3245
OUTLINE DIMENSIONS
4.10
4.00 SQ
3.90
PIN 1
INDICATOR
20
16
15
0.50
BSC
1
EXPOSED
PAD
2.30
2.10 SQ
2.00
11
TOP VIEW
0.80
0.75
0.70
5
0.20 MIN
BOTTOM VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
6
10
0.65
0.60
0.55
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
08-16-2010-B
PIN 1
INDICATOR
0.30
0.25
0.18
COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-1.
Figure 12. 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
4 mm × 4 mm Body, Very Very Thin Quad
(CP-20-6)
Dimensions shown in millimeters
6.60
6.50
6.40
20
11
4.50
4.40
4.30
6.40 BSC
1
10
PIN 1
0.65
BSC
1.20 MAX
0.15
0.05
COPLANARITY
0.10
0.30
0.19
0.20
0.09
SEATING
PLANE
8°
0°
COMPLIANT TO JEDEC STANDARDS MO-153-AC
Figure 13. 20-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-20)
Dimensions shown in millimeters
REV. B
–11–
0.75
0.60
0.45
ADG3245
ORDERING GUIDE
Model1
ADG3245BCPZ
ADG3245BRU
ADG3245BRU-REEL7
ADG3245BRUZ
ADG3245BRUZ-REEL7
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
20-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
20-Lead Thin Shrink Small Outline Package [TSSOP]
20-Lead Thin Shrink Small Outline Package [TSSOP]
20-Lead Thin Shrink Small Outline Package [TSSOP]
20-Lead Thin Shrink Small Outline Package [TSSOP]
Package Option
CP-20-6
RU-20
RU-20
RU-20
RU-20
Z = RoHS Compliant Part.
REVISION HISTORY
4/13—Rev. A to Rev. B
Change to LFCSP Package Figure .................................................. 3
Change to Ordering Guide .............................................................12
10/12—Rev. 0 to Rev. A
Added EPAD Note ............................................................................. 3
Updated Outline Dimensions .......................................................11
Changes to Ordering Guide .......................................................... 12
5/03—Revision 0—Initial Version
©2003–2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D03011-0-/13(A)
–12–
REV. B