9 kHz to 30 GHz, Silicon SPDT Switch ADRF5021 Data Sheet FUNCTIONAL BLOCK DIAGRAM RF2 ADRF5021 VSS EN 50Ω RFC CTRL 50Ω VDD RF1 14580-001 Ultrawideband frequency range: 9 kHz to 30 GHz Nonreflective 50 Ω design Low insertion loss: 2.0 dB to 30 GHz High isolation: 60 dB to 30 GHz High input linearity 1 dB power compression (P1dB): 28 dBm typical Third-order intercept (IP3): 52 dBm typical High power handling 24 dBm through path 24 dBm terminated path ESD sensitivity: Class 1, 1 kV human body model (HBM) 20-terminal, 3 mm × 3 mm land grid array package No low frequency spurious Radio frequency (RF) settling time (to 0.1 dB of final RF output): 6.2 µs DRIVER FEATURES Figure 1. APPLICATIONS Test instrumentation Microwave radios and very small aperture terminals (VSATs) Military radios, radars, electronic counter measures (ECMs) Broadband telecommunications systems GENERAL DESCRIPTION The ADRF5021 is a general-purpose single-pole, double-throw (SPDT) switch manufactured using a silicon process. It comes in a 3 mm × 3 mm, 20-terminal land grid array (LGA) package and provides high isolation and low insertion loss from 9 kHz to 30 GHz. Rev. A This broadband switch requires dual supply voltages, +3.3 V and −2.5 V, and provides CMOS/LVTTL logic-compatible control. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2016–2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADRF5021 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Interface Schematics .....................................................................6 Applications ....................................................................................... 1 Typical Performance Characterics ..................................................7 Functional Block Diagram .............................................................. 1 Insertion Loss, Return Loss, and Isolation ................................7 General Description ......................................................................... 1 Input Power Compression and Third-Order Intercept (IP3) ..8 Revision History ............................................................................... 2 Theory of Operation .........................................................................9 Specifications..................................................................................... 3 Applications Information .............................................................. 10 Absolute Maximum Ratings ............................................................ 5 Evaluation Board ........................................................................ 10 Power Derating Curves ................................................................ 5 Probe Matrix Board ................................................................... 11 ESD Caution .................................................................................. 5 Outline Dimensions ....................................................................... 12 Pin Configuration and Function Descriptions ............................. 6 Ordering Guide .......................................................................... 12 REVISION HISTORY 2/2017—Rev. 0 to Rev. A Changed VEN = 3.3 V to 5 V to VEN = 0 V or 3.3 V to 5 V .......... 3 7/2016—Revision 0: Initial Version Rev. A | Page 2 of 12 Data Sheet ADRF5021 SPECIFICATIONS VDD = 3.3 V to 5 V, VSS = −2.5 V, VCTRL = 0 V or 3.3 V to 5 V, VEN = 0 V or 3.3 V to 5 V, TCASE = 25°C, 50 Ω system, unless otherwise noted. Table 1. Parameter FREQUENCY RANGE INSERTION LOSS Between RFC and RF1/RF2 Symbol ISOLATION Between RFC and RF1/RF2 Between RF1 and RF2 RETURN LOSS RFC and RF1/RF2 (On) RF1/RF2 (Off ) SWITCHING Rise and Fall Time On and Off Time RF Settling Time 0.1 dB 0.05 dB INPUT LINEARITY1 Power Compression 0.1 dB 1 dB Third-Order Intercept SUPPLY CURRENT Positive Negative DIGITAL CONTROL INPUTS Voltage Low High Current Low and High tRISE, tFALL tON, tOFF P0.1dB P1dB IP3 IDD ISS VINL VINH Test Conditions/Comments Min 0.009 Typ Max 30,000 Unit MHz 9 kHz to 10 GHz 10 GHz to 20 GHz 20 GHz to 30 GHz 1.1 1.4 2.0 dB dB dB 9 kHz to 10 GHz 10 GHz to 20 GHz 20 GHz to 30 GHz 9 kHz to 10 GHz 10 GHz to 20 GHz 20 GHz to 30 GHz 65 60 60 70 65 60 dB dB dB dB dB dB 9 kHz to 10 GHz 10 GHz to 20 GHz 20 GHz to- 30 GHz 9 kHz to 10 GHz 10 GHz to 20 GHz 20 GHz to 30 GHz 23 17 13 30 18 8 dB dB dB dB dB dB 10% to 90% of RF output 50% VCTL to 90% of RF output 1.0 1.1 µs µs 50% VCTL to 0.1 dB of final RF output 50% VCTL to 0.05 dB of final RF output 1 MHz to 30 GHz 6.2 10 µs µs 27 28 52 dBm dBm dBm Two-tone input power = 14 dBm each tone, Δf = 1 MHz VDD, VSS pins VDD = 3.3 V VDD = 5 V VSS = −2.5 V CTRL, EN pins VDD = 3.3 V VDD = 5 V VDD = 3.3 V VDD = 5 V IINL, IINH 80 100 <1 0 1.2 1.7 <1 Rev. A | Page 3 of 12 300 600 10 µA µA µA 0.8 0.9 3.3 5.0 V V V V µA ADRF5021 Parameter RECOMMENDED OPERATING CONDITONS Supply Voltage Positive Negative Digital Control Voltage RF Input Power2 Through Path Data Sheet Symbol VDD VSS VCTL PIN Terminated Path Hot Switching Case Temperature 1 2 Test Conditions/Comments Min 3.0 −2.75 0 f = 1 MHz to 30 GHz, TCASE = 85°C RF signal is applied to RFC or through connected RF1/RF2 RF signal is applied to terminated RF1/RF2 RF signal is present at RFC while switching between RF1 and RF2 TCASE −40 For input linearity performance at frequencies less than 1 MHz, see Figure 15 to Figure 17. For power derating at frequencies less than 1 MHz, see Figure 2 to Figure 4. Rev. A | Page 4 of 12 Typ Max Unit 5.4 −2.25 VDD V V V 24 dBm 24 18 dBm dBm +85 °C Data Sheet ADRF5021 ABSOLUTE MAXIMUM RATINGS 4 For recommended operating conditions, see Table 1. TCASE = 85°C 2 Table 2. POWER DERATING (dB) −0.3 V to +5.5 V −2.75 V to +0.3 V −0.3 V to VDD + 0.3 V 135°C −65°C to +150°C 260°C 1G 10G 30G 14580-003 100M TCASE = 85°C 2 420°C/W 160°C/W 0 1 kV (Class 1) –6 –8 –14 10k 100k 1M 10M 100M FREQUENCY (Hz) 1G 10G 30G Figure 4. Power Derating for Hot Switching vs. Frequency, TCASE = 85°C ESD CAUTION –2 –4 –6 –8 –10 14580-002 –12 10G 30G –4 –12 0 1G –2 –10 TCASE = 85°C POWER DERATING (dB) 10M 4 2 100M 1M Figure 3. Power Derating for Terminated Path vs. Frequency, TCASE = 85°C 4 10M 100k FREQUENCY (Hz) POWER DERATING CURVES FREQUENCY (Hz) –8 –14 10k Only one absolute maximum rating can be applied at any one time. 1M –6 –12 Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. 100k –4 –10 27 dBm 25 dBm 21 dBm For power derating at frequencies less than 1 MHz, see Figure 2 to Figure 4. –14 10k –2 14580-004 1 0 Rating POWER DERATING (dB) Parameter Supply Voltage Positive Negative Digital Control Input Voltage RF Input Power1 (f = 1 MHz to 30 GHz, TCASE = 85°C) Through Path Terminated Path Hot Switching Temperature Junction (TJ) Storage Reflow (MSL3 Rating) Junction to Case Thermal Resistance, θJC Through Path Terminated Path ESD Sensitivity HBM Figure 2. Power Derating for Through Path vs. Frequency, TCASE = 85°C Rev. A | Page 5 of 12 ADRF5021 Data Sheet GND RF2 GND GND 20 19 18 17 16 GND 1 15 VSS GND 2 14 EN RFC 3 GND 4 GND 5 ADRF5021 9 10 GND GND 8 RF1 7 GND 6 GND TOP VIEW (Not to Scale) 13 GND 12 CTRL 11 VDD NOTES 1. THE EXPOSED PAD MUST BE CONNECTED TO THE RF/DC GROUND OF THE PRINTED CIRCUIT BOARD (PCB). 14580-005 GND PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 5. Pin Configuration (Top View) Table 3. Pin Function Descriptions Pin No. 1, 2, 4 to 7, 9, 10, 13, 16, 17, 19, 20 3 Mnemonic GND Description Ground. These pins must be connected to the RF/dc ground of the printed circuit board (PCB). RFC 8 RF1 11 12 14 15 18 VDD CTRL EN VSS RF2 RF Common Port. This pin is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking capacitor is necessary when the RF line potential is equal to 0 V dc. See Figure 6 for the interface schematic. RF1 Port. This pin is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking capacitor is necessary when the RF line potential is equal to 0 V dc. See Figure 6 for the interface schematic. Positive Supply Voltage. Control Input. See Figure 7 for the interface schematic. Enable Input. See Figure 7 for the interface schematic. Negative Supply Voltage. RF2 Port. This pin is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking capacitor is necessary when the RF line potential is equal to 0 V dc. See Figure 6 for the interface schematic. Exposed Pad. The exposed pad must be connected to the RF/dc ground of the PCB. EPAD INTERFACE SCHEMATICS VDD CTRL, EN 14580-007 RFC, RF1, RF2 14580-006 VDD Figure 7. Digital Pins (CTRL and EN) Interface Schematic Figure 6. RFC, RF1, and RF2 Pins Interface Schematic Rev. A | Page 6 of 12 Data Sheet ADRF5021 TYPICAL PERFORMANCE CHARACTERICS INSERTION LOSS, RETURN LOSS, AND ISOLATION Insertion loss and return loss measured on the probe matrix board using the ground, signal, ground (GSG) probes close to the RF pins; isolation measured on an evaluation board because signal coupling between the probes limits the isolation performance of the ADRF5021 on the probe matrix board (see the Applications Information section for details of evaluation and probe matrix boards). 0 0 TCASE = +85°C TCASE = +25°C TCASE = –40°C –5 –10 –1.5 –15 –2.0 –2.5 –3.0 –3.5 –25 –30 –35 –4.0 –40 –4.5 –45 –5.0 0 5 10 15 20 25 30 35 40 FREQUENCY (GHz) RFC RF1 ON RF2 OFF –50 0 5 10 15 20 25 30 35 40 FREQUENCY (GHz) Figure 8. Insertion Loss Between RFC and RF1/RF2 vs. Frequency over Temperature Figure 10. Return Loss vs. Frequency (RFC, RF1 On, and RF2 Off) 0 TCASE = +85°C TCASE = +25°C TCASE = –40°C –20 –30 –30 ISOLATION (dB) –20 –40 –50 –60 –40 –50 –60 –70 –70 –80 –80 –90 –100 5 10 15 20 25 30 35 40 FREQUENCY (GHz) 14580-009 –90 –100 0 TCASE = +85°C TCASE = +25°C TCASE = –40°C –10 0 5 10 15 20 25 30 35 40 FREQUENCY (GHz) Figure 9. Isolation Between RFC and RF1/RF2 vs. Frequency over Temperature Figure 11. Isolation Between RF1 and RF2 vs. Frequency over Temperature Rev. A | Page 7 of 12 14580-011 0 –10 ISOLATION (dB) –20 14580-010 RETURN LOSS (dB) –1.0 14580-008 INSERTION LOSS (dB) –0.5 ADRF5021 Data Sheet INPUT POWER COMPRESSION AND THIRD-ORDER INTERCEPT (IP3) All large signal performance parameters were measured on the evaluation board. 30 28 26 26 INPUT P0.1dB (dBm) 28 24 22 20 18 20 18 14 14 12 12 5 10 15 20 25 30 FREQUENCY (GHz) Figure 12. Input 0.1 dB Power Compression (P0.1dB) vs. Frequency over Temperature 10 10k 100k 1M 10M 100M 1G FREQUENCY (Hz) Figure 15. Input 0.1 dB Power Compression (P0.1dB) vs. Frequency over Temperature (Low Frequency Detail) 32 32 30 30 28 28 26 26 INPUT P1dB (dBm) 24 22 20 18 16 24 22 20 18 16 14 14 0 5 10 15 20 25 30 FREQUENCY (GHz) 10 10k 14580-013 10 1M 10M 100M 1G Figure 16. Input 1 dB Power Compression (P1dB) vs. Frequency over Temperature (Low Frequency Detail) 60 TCASE = +85°C TCASE = +25°C TCASE = –40°C 55 100k FREQUENCY (Hz) Figure 13. Input 1 dB Power Compression (P1dB) vs. Frequency over Temperature 60 TCASE = +85°C TCASE = +25°C TCASE = –40°C 12 14580-016 TCASE = +85°C TCASE = +25°C TCASE = –40°C 12 55 50 INPUT IP3 (dBm) 50 45 40 35 45 40 35 30 30 25 25 0 5 10 15 20 25 FREQUENCY (GHz) Figure 14. Input IP3 vs. Frequency over Temperature 30 20 10k 14580-014 20 TCASE = +85°C TCASE = +25°C TCASE = –40°C 100k 1M 10M FREQUENCY (Hz) 100M 1G 14580-017 INPUT P1dB (dBm) 22 16 10 INPUT IP3 (dBm) 24 16 0 TCASE = +85°C TCASE = +25°C TCASE = –40°C 30 14580-012 INPUT P0.1dB (dBm) 32 TCASE = +85°C TCASE = +25°C TCASE = –40°C 14580-015 32 Figure 17. Input IP3 vs. Frequency over Temperature (Low Frequency Detail) Rev. A | Page 8 of 12 Data Sheet ADRF5021 THEORY OF OPERATION The ADRF5021 requires a positive supply voltage applied to the VDD pin and a negative supply voltage applied to the VSS pin. Bypassing capacitors are recommended on the supply lines to minimize RF coupling. The ADRF5021 is internally matched to 50 Ω at the RF common port (RFC) and the RF throw ports (RF1 and RF2); therefore, no external matching components are required. All of the RF ports are dc-coupled to 0 V, and no dc blocking is required at the RF ports when the RF line potential is equal to 0 V. The design is bidirectional; the RF input signal can be applied to the RFC port while the RF throw port (RF1 or RF2) is output or vice versa. The ADRF5021 incorporates a driver to perform logic functions internally and to provide the user with the advantage of a simplified control interface. The driver features two digital control input pins, CTRL and EN. When the EN pin is logic low, the RF1 to RFC path is in an insertion loss state, and the RF2 to RFC path is in an isolation state, or vice versa, depending on the logic level applied to the CTRL pin. The insertion loss path (for example, RF1 to RFC) conducts the RF signal equally well in both directions between its throw port (for example, RF1) and common port (RFC). The isolation path (for example, RF2 to RFC) provides high loss between the insertion loss path and its throw port (for example, RF2) terminated to an internal 50 Ω resistor. When the EN pin is logic high, both the RF1 to RFC path and the RF2 to RFC path are in an isolation state regardless of the logic state of CTRL. RF1 and RF2 ports are terminated to internal 50 Ω resistors, and RFC becomes open reflective. The ideal power-up sequence is as follows: 1. 2. 3. 4. Power up GND. Power up VDD and VSS. The relative order is not important. Power up the digital control inputs. The relative order of the logic control inputs is not important. However, powering the digital control inputs before the VDD supply can inadvertently forward bias and damage the internal ESD protection structures. Apply an RF input signal. Table 4. Control Voltage Truth Table EN Low Low High High Digital Control Input CTRL Low High Low High RF1 to RFC Isolation (off ) Insertion loss (on) Isolation (off ) Isolation (off ) Rev. A | Page 9 of 12 RF Paths RF2 to RFC Insertion loss (on) Isolation (off ) Isolation (off ) Isolation (off ) ADRF5021 Data Sheet APPLICATIONS INFORMATION EVALUATION BOARD Figure 20 shows the actual ADRF5021 evaluation board with component placement. Two power supply ports are connected to the VDD and VSS test points, TP5 and TP2, and the ground reference is connected to the GND test point, TP1. On each supply trace, a 100 pF bypass capacitor is used, and unpopulated components positions are available for applying extra bypass capacitors. Figure 18 and Figure 19 show the top and cross sectional views of the evaluation board, which uses 4-layer construction with a copper thickness of 0.5 oz (0.7 mil) and dielectric materials between each copper layer. EDGE PLATING 5 × 520mil R 32mil 828mil 940mil 570mil 14580-018 40mil 40mil 1500mil Figure 18. Evaluation Board Layout (Top View) G = 5mil W = 14mil 0.5oz Cu (0.7mil) RO4003 0.5oz Cu (0.7mil) T = 0.7mil 14580-020 0.5oz Cu (0.7mil) H = 8mil Figure 20. Populated Evaluation Board TOTAL THICKNESS ~62mil 0.5oz Cu (0.7mil) FR4 FR4 0.5oz Cu (0.7mil) 14580-019 0.5oz Cu (0.7mil) Figure 19. Evaluation Board (Cross Sectional View) All RF and dc traces are routed on the top copper layer whereas the inner and bottom layers are grounded planes that provide a solid ground for the RF transmission lines. Top dielectric material is 8 mil Rogers RO4003, offering good high frequency performance. The middle and bottom dielectric materials are FR-4 type materials to achieve an overall board thickness of 62 mil. Two control ports are connected to the EN and CTRL test points, TP3 and TP4. On each control trace, a resistor position is available to improve the isolation between the RF and control signals. The RF ports are connected to the RFC, RF1, and RF2 connectors (J1, J2, and J3) that are end launch 2.4 mm RF connectors. A through transmission line that connects unpopulated RF connectors (J7 and J8) is also available to measure the loss of the PCB. Figure 21 and Table 5 are the evaluation board schematic and bill of materials, respectively. The evaluation board shown in Figure 20 is available from Analog Devices, Inc., upon request. The RF transmission lines were designed using a coplanar waveguide (CPWG) model with a width of 14 mil and ground spacing of 5 mil to have a characteristic impedance of 50 Ω. For good RF and thermal grounding, as many plated through vias as possible are arranged around transmission lines and under the exposed pad of the package. Rev. A | Page 10 of 12 Data Sheet ADRF5021 J7 THR_CAL J8 DEPOP J3 DEPOP RF2 20 GND GND GND GND RF2 VSS C4 100pF 16 1 15 2 14 U1 3 13 VSS EN CTRL 4 12 5 VDD 11 GND 6 7 8 9 C3 100nF DEPOP TP2 C6 10µF DEPOP R1 0Ω EN R2 0Ω CTRL TP3 GND VDD C5 100pF 10 GND RFC 17 GND J1 RFC 18 RF1 GND 19 GND GND GND GND TP1 C2 100pF DEPOP TP4 TP5 C1 10µF DEPOP 14580-021 RF1 J2 Figure 21. Evaluation Board Schematic Table 5. Bill of Materials, Evaluation Board Components PROBE MATRIX BOARD Component J1, J2, J3 J7, J8 TP1 to TP5 C4, C5 C2, C3 C1, C6 R1, R2 U1 PCB Figure 22 and Figure 23 show the top and cross sectional views of the probe matrix board that measures the s-parameters of the ADRF5021 at close proximity to RF pins using the GSG probes. The actual board duplicates the same layout in matrix form to assemble multiple devices and uses RF traces for through, reflect, and line (TRL) calibration. 220mil 14580-022 Description End launch connectors, 2.4 mm Unpopulated end launch connectors, 2.4 mm Through hole mount test points 100 pF capacitors, 0402 package Unpopulated capacitors, 0402 package Unpopulated capacitors, 0603 package 0 Ω resistors, 0402 package ADRF5021 SPDT switch 600-01583-00-1 evaluation PCB 340mil Figure 22. Probe Board Layout (Top View) G = 5mil W = 14mil 0.5oz Cu RO4003 0.5oz Cu T = 0.7mil H = 8mil 0.5oz Cu Figure 23. Probe Matrix Board (Cross Sectional View) Rev. A | Page 11 of 12 14580-023 0.5oz Cu ADRF5021 Data Sheet OUTLINE DIMENSIONS 0.25 0.20 0.15 0.30 0.25 0.20 16 CHAMFERED PIN 1 (0.3 × 45°) 1 1.60 REF SQ 1.70 1.60 SQ 1.50 EXPOSED PAD 11 0.40 BSC TOP VIEW 5 10 6 0.13BOTTOM VIEW REF 0.530 REF SIDE VIEW 0.236 0.196 0.156 PKG-004908 0.776 0.726 0.676 0.70 REF 20 15 FOR PROPER CONNECTION OF THE EXPOSED PADS, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 05-25-2016-B PIN 1 CORNER AREA 3.10 3.00 2.90 Figure 24. 20-Terminal Land Grid Array [LGA] 3 mm × 3 mm Body and 0.72 mm Package Height (CC-20-3) Dimensions shown in millimeters ORDERING GUIDE Model1 ADRF5021BCCZN Temperature Range −40°C to +85°C MSL Rating2 MSL3 Package Description 20-Terminal Land Grid Array [LGA] Package Option CC-20-3 ADRF5021BCCZN-R7 −40°C to +85°C MSL3 20-Terminal Land Grid Array [LGA] CC-20-3 ADRF5021-EVALZ Evaluation Board Z = RoHS-Compliant Part. See the Absolute Maximum Ratings section. 3 XXXX is the 4-digit lot number. 1 2 ©2016–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D14580-0-2/17(A) Rev. A | Page 12 of 12 Branding3 021 XXXX 021 XXXX