DS1248/DS1248P 1024k NV SRAM with Phantom Clock www.maxim-ic.com FEATURES § § § § § § § § § § § § PIN ASSIGNMENT Real-time clock (RTC) keeps track of hundredths of seconds, minutes, hours, days, date of the month, months, and years 128k x 8 NV SRAM directly replaces volatile static RAM or EEPROM Embedded lithium energy cell maintains calendar operation and retains RAM data Watch function is transparent to RAM operation Month and year determine the number of days in each month; valid up to 2100 Full 10% operating range Operating temperature range: 0°C to +70°C Over 10 years of data retention in the absence of power Lithium energy source is electrically disconnected to retain freshness until power is applied for the first time DIP Module only Standard 32-pin JEDEC pinout PowerCap® Module Board only - Surface mountable package for direct connection to PowerCap containing battery and crystal - Replaceable battery (PowerCap) - Pin for pin compatible with DS1244P and DS1251P RST A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 32 31 30 29 28 27 26 25 24 23 22 21 VCC A15 NC WE A13 A8 A9 A11 OE A10 CE A0 1 2 3 4 5 6 7 8 9 10 11 12 DQ0 13 20 DQ6 DQ1 DQ2 14 19 DQ5 15 DQ4 GND 16 18 17 DQ7 DQ3 32-Pin Encapsulated Package 740mil Flush RST A15 A16 NC VCC WE OE CE DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 X1 GND VBAT X2 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 NC NC A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 34-Pin PowerCap Module Board (Uses DS9034PCX PowerCap) PowerCap is a registered trademark of Dallas Semiconductor. 1 of 21 112801 DS1248/DS1248P ORDERING INFORMATION DS1248YP–XXXY (5V) - IND Industrial - 70 70ns access P blank 32-Pin DIP Module 34-Pin PowerCap Module board* DS1248WP-XXXY (3.3V) - IND Industrial - 120 120ns access P PIN DESCRIPTION A0–A16 CE OE WE VCC GND DQ0–DQ7 NC X1, X2 VBAT RST - Address Inputs - Chip Enable - Output Enable - Write Enable - Power Supply Input - Ground - Data In/Data Out - No Connection - Crystal Connection - Battery Connection - Reset blank 32-Pin DIP Module 34-Pin PowerCap Module board* *DS9034PCX (PowerCap) Required: (Must be ordered separately.) DESCRIPTION The DS1248 1024k NV SRAM with Phantom Clock is a fully static nonvolatile RAM (organized as 128k words by 8 bits) with a built-in real-time clock. The DS1248 has a self-contained lithium energy source and control circuitry, which constantly monitors VCC for an out-of-tolerance condition. When such a condition occurs, the lithium energy source is automatically switched on and writes protection is unconditionally enabled to prevent garbled data in both the memory and real-time clock. PACKAGES The DS1248 is available in two packages: 32-pin DIP and 34-pin PowerCap module. The 32-pin DIP style module integrates the crystal, lithium energy source, and silicon in one package. The 34-pin PowerCap module board is designed with contacts for connection to a separate PowerCap (DS9034PCX) that contains the crystal and battery. This design allows the PowerCap to be mounted on top of the DS1248P after completion of the surface mount process. Mounting the PowerCap after the surface mount process prevents damage to the crystal and battery because of the high temperatures required for solder reflow. The PowerCap is keyed to prevent reverse insertion. The PowerCap module board and PowerCap are ordered separately and shipped in separate containers. 2 of 21 DS1248/DS1248P RAM READ MODE The DS1248 executes a read cycle whenever WE (write enable) is inactive (high) and CE (chip enable) is active (low). The unique address specified by the 17 address inputs (A0–A16) defines which of the 128k bytes of data is to be accessed. Valid data will be available to the eight data-output drivers within tACC (access time) after the last address input signal is stable, providing that CE and OE (output enable) access times and states are also satisfied. If OE and CE access times are not satisfied, then data access must be measured from the later occurring signal ( CE or OE ) and the limiting parameter is either tCO for CE or tOE for OE , rather than address access. RAM WRITE MODE The DS1248 is in the write mode whenever the WE and CE signals are in the active (low) state after address inputs are stable. The latter occurring falling edge of CE or WE will determine the start of the write cycle. The write cycle is terminated by the earlier rising edge of CE or WE . All address inputs must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time (tWR ) before another cycle can be initiated. The OE control signal should be kept inactive (high) during write cycles to avoid bus contention. However, if the output bus has been enabled ( CE and OE active) then WE will disable the outputs in tODW from its falling edge. DATA RETENTION MODE The 5V device is fully accessible and data can be written or read only when VCC is greater than VPF. However, when VCC is below the power-fail point, VPF (point at which write protection occurs), the internal clock registers and SRAM are blocked from any access. When VCC falls below the battery switch point, VSO (battery supply level), device power is switched from the VCC pin to the backup battery. RTC operation and SRAM data are maintained from the battery until VCC is returned to nominal levels. The 3.3V device is fully accessible and data can be written or read only when VCC is greater than VPF. When VCC falls below VPF, access to the device is inhibited. If VPF is less than VBAT, the device power is switched from VCC to the backup supply (VBAT) when VCC drops below VPF. If VPF is greater than VBAT, the device power is switched from VCC to the backup supply (VBAT) when VCC drops below VBAT. RTC operation and SRAM data are maintained from the battery until VCC is returned to nominal levels. All control, data, and address signals must be powered down when VCC is powered-down. PHANTOM CLOCK OPERATION Communication with the phantom clock is established by pattern recognition on a serial bit stream of 64 bits, which must be matched by executing 64 consecutive write cycles containing the proper data on DQ0. All accesses that occur prior to recognition of the 64-bit pattern are directed to memory. After recognition is established, the next 64 read or write cycles either extract or update data in the phantom clock, and memory access is inhibited. Data transfer to and from the timekeeping function is accomplished with a serial bit stream under control of chip enable, output enable, and write enable. Initially, a read cycle to any memory location using the CE and OE control of the phantom clock starts the pattern recognition sequence by moving a pointer to 3 of 21 DS1248/DS1248P the first bit of the 64-bit comparison register. Next, 64 consecutive write cycles are executed using the CE and WE control of the SmartWatch. These 64 write cycles are used only to gain access to the phantom clock. Therefore, any address to the memory in the socket is acceptable. However, the write cycles generated to gain access to the phantom clock are also writing data to a location in the mated RAM. The preferred way to manage this requirement is to set aside just one address location in RAM as a phantom clock scratch pad. When the first write cycle is executed, it is compared to bit 0 of the 64-bit comparison register. If a match is found, the pointer increments to the next location of the comparison register and awaits the next write cycle. If a match is not found, the pointer does not advance and all subsequent write cycles are ignored. If a read cycle occurs at any time during pattern recognition, the present sequence is aborted and the comparison register pointer is reset. Pattern recognition continues for a total of 64 write cycles as described above until all the bits in the comparison register have been matched (Figure 1). With a correct match for 64 bits, the phantom clock is enabled and data transfer to or from the timekeeping registers can proceed. The next 64 cycles will cause the phantom clock to either receive or transmit data on DQ0, depending on the level of the OE pin or the WE pin. Cycles to other locations outside the memory block can be interleaved with CE cycles without interrupting the pattern recognition sequence or data transfer sequence to the phantom clock. PHANTOM CLOCK REGISTER INFORMATION The phantom clock information is contained in eight registers of 8 bits, each of which is sequentially accessed 1 bit at a time after the 64-bit pattern recognition sequence has been completed. When updating the phantom clock registers, each register must be handled in groups of 8 bits. Writing and reading individual bits within a register could produce erroneous results. These read/write registers are defined in Figure 2. Data contained in the phantom clock register is in binary-coded decimal format (BCD). Reading and writing the registers is always accomplished by stepping through all eight registers, starting with bit 0 of register 0 and ending with bit 7 of register 7. 4 of 21 DS1248/DS1248P PHANTOM CLOCK REGISTER DEFINITION Figure 1 Note: The pattern recognition in Hex is C5, 3A, A3, 5C, C5, 3A, A3, 5C. The odds of this pattern being accidentally duplicated and causing inadvertent entry to the phantom clock is less than 1 in 1019. This pattern is sent to the phantom clock LSB to MSB. 5 of 21 DS1248/DS1248P PHANTOM CLOCK REGISTER DEFINITION Figure 2 AM/PM/12/24 MODE Bit 7 of the hours register is defined as the 12-hour or 24-hour mode-select bit. When high, the 12-hour mode is selected. In the 12-hour mode, bit 5 is the AM/PM bit with logic high being PM. In the 24-hour mode, bit 5 is the second 10-hour bit (20–23 hours). OSCILLATOR AND RESET BITS Bits 4 and 5 of the day register are used to control the RESET and oscillator functions. Bit 4 controls the RESET (pin 1). When the RESET bit is set to logic 1, the RESET input pin is ignored. When the RESET bit is set to logic 0, a low input on the RESET pin will cause the phantom clock to abort data transfer without changing data in the watch registers. Bit 5 controls the oscillator. When set to logic 1, the oscillator is off. When set to logic 0, the oscillator turns on and the watch becomes operational. These bits are shipped from the factory set to a logic 1. ZERO BITS Registers 1, 2, 3, 4, 5, and 6 contain one or more bits which will always read logic 0. When writing these locations, either a logic 1 or 0 is acceptable. 6 of 21 DS1248/DS1248P BATTERY LONGEVITY The DS1248 has a lithium power source that is designed to provide energy for clock activity and clock and RAM data retention when the VCC supply is not present. The capability of this internal power supply is sufficient to power the DS1248 continuously for the life of the equipment in which it is installed. For specification purposes, the life expectancy is 10 years at +25°C with the internal clock oscillator running in the absence of VCC power. Each DS1248 is shipped from Dallas Semiconductor with its lithium energy source disconnected, guaranteeing full energy capacity. When VCC is first applied at a level greater than VPF, the lithium energy source is enabled for battery-backup operation. Actual life expectancy of the DS1248 will be much longer than 10 years since no lithium battery energy is consumed when VCC is present. CLOCK ACCURACY (DIP MODULE) The DS1248 is guaranteed to keep time accuracy to within ±1 minute per month at +25°C. The clock is calibrated at the factory by Dallas Semiconductor using special calibration nonvolatile tuning elements and does not require additional calibration. For this reason, methods of field clock calibration are not available and not necessary. CLOCK ACCURACY (POWERCAP MODULE) The DS1248P and DS9034PCX are each individually tested for accuracy. Once mounted together, the module will typically keep time accuracy to within ±1.53 minutes per month (35ppm) at +25°C. 7 of 21 DS1248/DS1248P ABSOLUTE MAXIMUM RATINGS* Voltage Range on Any Pin Relative to Ground Storage Temperature Range Soldering Temperature Range -0.3V to +6.0V -40ºC to +85ºC +260°C for 10 seconds (DIP) (Note 13) See IPC/JEDEC Standard J-STD-020A for Surface Mount Devices OPERATING RANGE RANGE Commercial Industrial TEMP. RANGE (ºC) 0 to +70 -40 to +85 VCC (V) 3.3 ± 10% or 5 ± 10% 3.3 ± 10% or 5 ± 10% * This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time can affect reliability. RECOMMENDED DC OPERATING CONDITIONS PARAMETER VCC = 5V ± 10% Logic 1 V = 3.3V ± 10% CC Logic 0 VCC = 5V ± 10% VCC = 3.3V ± 10% SYMBOL VIH VIL MIN 2.2 TYP Write Protection Voltage Battery Switchover Voltage MAX VCC + 0.3V 2.0 -0.3 -0.3 VCC + 0.3V 0.8 0.6 DC ELECTRICAL CHARACTERISTICS PARAMETER Input Leakage Current I/O Leakage Current CE ³ VIH ≤ VCC Output Current @ 2.4V Output Current @ 0.4V Standby Current CE = 2.2V Standby Current CE = VCC - 0.5V Operating Current tCYC = 70ns Over the operating range NOTES V 11 V 11 Over the operating range (5V) SYMBOL IIL IIO MIN -1.0 -1.0 IOH IOL ICCS1 -1.0 2.0 ICCS2 TYP MAX +1.0 +1.0 UNITS mA mA 5 10 mA mA mA 3.0 5.0 mA 85 mA 4.50 V V ICC01 VPF VSO UNITS 4.25 8 of 21 4.37 VBAT NOTES 12 11 11 DS1248/DS1248P DC ELECTRICAL CHARACTERISTICS PARAMETER Input Leakage Current I/O Leakage Current CE ³ VIH ≤ VCC Output Current @ 2.4V Output Current @ 0.4V Standby Current CE = 2.2V Standby Current CE = VCC - 0.5V Operating Current tCYC = 70ns Write Protection Voltage Battery Switchover Voltage Over the operating range (3.3V) SYMBOL IIL IIO MIN -1.0 -1.0 IOH IOL ICCS1 ICCS2 -1.0 2.0 ICC01 VPF VSO TYP MAX +1.0 +1.0 UNITS mA mA 7 3.0 mA mA mA mA 5 2.0 2.80 2.86 VBAT or VPF 50 2.97 mA V V CAPACITANCE PARAMETER Input Capacitance Input/Output Capacitance NOTES 12 11 11 (TA = +25°C) SYMBOL CIN CI/O MIN TYP 5 5 MAX 10 10 UNITS pF pF NOTES MEMORY AC ELECTRICAL CHARACTERISTICS Over the operating range (5V) PARAMETER Read Cycle Time Access Time OE to Output Valid CE to Output Valid OE or CE to Output Active Output High-Z from Deselection Output Hold from Address Change Write Cycle Time Write Pulse Width Address Setup Time Write Recovery Time Output High-Z from WE Output Active from WE Data Setup Time Data Hold Time from WE SYMBOL tRC tACC tOE tCO tCOE tOD tOH tWC tWP tAW tWR tODW tOEW tDS tDH DS1248Y-70 MIN MAX 70 70 35 70 5 25 5 70 50 0 0 25 5 30 5 9 of 21 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns NOTES 5 5 3 5 5 4 4 DS1248/DS1248P PHANTOM CLOCK AC ELECTRICAL CHARACTERISTICS Over the operating range (5V) PARAMETER Read Cycle Time CE Access Time OE Access Time CE to Output Low-Z OE to Output Low-Z CE to Output High-Z OE to Output High-Z Read Recovery Write Cycle Time Write Pulse Width Write Recovery Data Setup Time Data Hold Time CE Pulse Width RESET Pulse Width SYMBOL tRC tCO tOE tCOE tOEE tOD tODO tRR tWC tWP tWR tDS tDH tCW tRST MIN 65 TYP MAX 55 55 5 5 25 25 10 65 55 10 30 0 60 65 POWER-DOWN/POWER-UP TIMING UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns NOTES 5 5 3 10 4 4 Over the operating range (3.3V) PARAMETER CE at VIH before Power-Down VCC Slew from VPF(max) to VPF(min)( CE at VPF) VCC Slew from VPF(min) to VSO VCC Slew from VPF(max) to VPF(min)( CE at VPF) CE at VIH after Power-Up SYMBOL tPD tF MIN 0 300 tFB tR 10 0 tREC 1.5 PARAMETER Expected Data Retention Time SYMBOL tDR MIN 10 TYP MAX UNITS ms ms NOTES ms ms 2.5 ms MAX UNITS years (TA = +25°C) TYP NOTES 9 Warning: Under no circumstances are negative undershoots of any amplitude allowed when device is in battery-backup mode. 10 of 21 DS1248/DS1248P MEMORY AC ELECTRICAL CHARACTERISTICS Over the operating range (3.3V) PARAMETER Read Cycle Time Access Time OE to Output Valid CE to Output Valid OE or CE to Output Active Output High-Z from Deselection Output Hold from Address Change Write Cycle Time Write Pulse Width Address Setup Time Write Recovery Time Output High-Z from WE Output Active from WE Data Setup Time Data Hold Time from WE DS1248W-120 MIN MAX 120 120 60 120 5 40 5 120 90 0 20 40 5 50 20 SYMBOL tRC tACC tOE tCO tCOE tOD tOH tWC tWP tAW tWR tODW tOEW tDS tDH UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns NOTES 5 5 3 10 5 5 4 4 PHANTOM CLOCK AC ELECTRICALCHARACTERISTICS Over the operating range (3.3V) PARAMETER Read Cycle Time CE Access Time OE Access Time CE to Output Low-Z OE to Output Low-Z CE to Output High-Z OE to Output High-Z Read Recovery Write Cycle Time Write Pulse Width Write Recovery Data Setup Time Data Hold Time CE Pulse Width RESET Pulse Width SYMBOL tRC tCO tOE tCOE tOEE tOD tODO tRR tWC tWP tWR tDS tDH tCW tRST MIN 120 TYP MAX 100 100 5 5 40 40 20 120 100 20 45 0 105 120 11 of 21 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns NOTES 5 5 3 10 4 4 DS1248/DS1248P POWER-DOWN/POWER-UP TIMING Over the operating range (3.3V) PARAMETER CE at VIH before Power-Down VCC Slew from VPF(MAX) to VPF(MIN)( CE at VIH) VCC Slew from VPF(MAX) to VPF(MIN)( CE at VIH) CE at VIH after Power-Up SYMBOL tPD tF MIN 0 300 tR 0 tREC 1.5 PARAMETER Expected Data Retention Time SYMBOL tDR MIN 10 TYP MAX UNITS ms ms NOTES ms 2.5 ms MAX UNITS years (TA = +25°C) TYP NOTES 9 Warning: Under no circumstances are negative undershoots, of any amplitude, allowed when device is in battery-backup mode. 12 of 21 DS1248/DS1248P MEMORY READ CYCLE (Note 1) MEMORY WRITE CYCLE 1 (Notes 2, 6, and 7) 13 of 21 DS1248/DS1248P MEMORY WRITE CYCLE 2 (Notes 2 and 8) RESET FOR PHANTOM CLOCK READ CYCLE TO PHANTOM CLOCK 14 of 21 DS1248/DS1248P WRITE CYCLE TO PHANTOM CLOCK POWER-DOWN/POWER-UP CONDITION (5V) 15 of 21 DS1248/DS1248P POWER-DOWN/POWER-UP CONDITION (3.3V) 16 of 21 DS1248/DS1248P AC TEST CONDITIONS Output Load: 50pF + 1TTL Gate Input Pulse Levels: 0V to 3V Timing Measurement Reference Levels Input: 1.5V Output: 1.5V Input Pulse Rise and Fall Times: 5ns NOTES: 1) WE is high for a read cycle. 2) OE = VIH or VIL. If CE = VIH during write cycle, the output buffers remain in a high impedance state. 3) tWP is specified as the logical AND of CE and WE . tWP is measured from the latter of CE or WE going low to the earlier of CE or WE going high. 4) tDH, tDS are measured from the earlier of CE or WE going high. 5) These parameters are sampled with a 50pF load and are not 100% tested. 6) If the CE low transition occurs simultaneously with or later than the WE low transition in Write Cycle 1, the output buffers remain in a high impedance state during this period. 7) If the CE high transition occurs prior to or simultaneously with the WE high transition, the output buffers remain in a high impedance state during this period. 8) If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition, the output buffers remain in a high impedance state during this period. 9) The expected tDR is defined as cumulative time in the absence of VCC with the clock oscillator running. 10) tWR is a function of the latter occurring edge of WE or CE . 11) Voltages are referenced to ground. 12) RST (Pin 1) has an internal pullup resistor. 13) Real-time clock modules can be successfully processed through conventional wave-soldering techniques as long as temperature exposure to the lithium energy source contained within does not exceed +85°C. Post-solder cleaning with water-washing techniques is acceptable, provided that ultrasonic vibration is not used. In addition, for the PowerCap: 1) Dallas Semiconductor recommends that PowerCap Module bases experience one pass through solder reflow oriented with the label side up (“live-bug”). 2) Hand soldering and touch-up: Do not touch or apply the soldering iron to leads for more than three seconds. - To solder, apply flux to the pad, heat the lead frame pad, and apply solder. To remove the part, apply flux, heat the lead frame pad until the solder reflows, and use a solder wick to remove solder. 17 of 21 DS1248/DS1248P DS1248 4096k NV SRAM WITH PHANTOM CLOCK KG DIM A IN. MM B IN. MM C IN. MM D IN. MM E IN. MM F IN. MM G IN. MM H IN. MM J IN. MM K IN. MM 32-PIN MIN MAX 1.680 1.740 42.67 44.20 0.715 0.740 18.16 18.80 0.335 0.365 8.51 9.27 0.075 0.105 1.91 2.67 0.015 0.030 0.38 0.76 0.140 0.180 3.56 4.57 0.090 0.110 2.29 2.79 0.590 0.630 14.99 16.00 0.010 0.018 0.25 0.46 0.015 0.025 0.38 0.64 18 of 21 DS1248/DS1248P DS1248P PKG DIM A B C D E F G MIN 0.920 0.980 0.052 0.048 0.015 0.025 INCHES NOM 0.925 0.985 0.055 0.050 0.020 0.027 MAX 0.930 0.990 0.080 0.058 0.052 0.025 0.030 Note: Dallas Semiconductor recommends that PowerCap Module bases experience one pass through solder reflow oriented with the label side up (“live-bug”). Hand soldering and touch-up: Do not touch or apply the soldering iron to leads for more than three seconds. To solder, apply flux to the pad, heat the lead frame pad, and apply solder. To remove the part, apply flux, heat the lead frame pad until the solder reflows, and use a solder wick to remove solder. 19 of 21 DS1248/DS1248P DS1248P WITH DS9034PCX ATTACHED PKG DIM A B C D E F G COMPONENTS AND PLACEMENT MAY VARY FROM EACH DEVICE TYPE 20 of 21 MIN 0.920 0.955 0.240 0.052 0.048 0.015 0.020 INCHES NOM 0.925 0.960 0.245 0.055 0.050 0.020 0.025 MAX 0.930 0.965 0.250 0.058 0.052 0.025 0.030 DS1248/DS1248P RECOMMENDED POWERCAP MODULE LAND PATTERN PKG DIM A B C D E 21 of 21 MIN - INCHES NOM MAX 1.050 0.826 0.050 0.030 0.112 -