[ /Title (CD74 HC354 , CD74 HCT35 4) /Subject (High Speed CMOS Logic 8-Input Multip lexer/ Regis- CD54HC354, CD74HC354, CD74HCT354 Semiconductor 8-Line to 1-Line Data Selector/Multiplexer/Register With 3-State Outputs SCHS277D - November 1997 - Revised May 2003 Features Description • HC/HCT354 - Transparent Data and Select Latches • Buffered Inputs • Three-State Complementary Outputs • Bus Line Driving Capability • Typical Propagation Delay: VCC = 5V, CL = 15pF, TA = 25oC - Data to Output = 18ns • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wide Operating Temperature Range . . . -55oC to 125oC • Balanced Propagation Delay and Transition Times • Significant Power Reduction Compared to LSTTL Logic ICs • HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V • HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH The CD54HC354, CD74HC354, and CD74HCT354 are data selectors/multiplexers that select one of eight sources. In both types, the data select bits S0, S1 and S2 are stored in transparent latches that are enabled by a low latch enable input, LE. In the HC/HCT354 the data enable input, E, controls transparent latches that pass data to the outputs when E is high and latches in new data when E is low. In both types the three-state outputs are controlled by three output-enable inputs OE1, OE2, and OE3. Ordering Information PART NUMBER TEMP. RANGE (oC) CD54HC354F3A -55 TO 125 20 Ld CERDIP CD74HC354E -55 to 125 20 Ld PDIP CD74HCT354E -55 to 125 20 Ld PDIP Pinout CD54HC354 (CERDIP) CD74HC354, CD74HCT354 (PDIP) TOP VIEW D7 1 20 VCC D6 2 19 Y D5 3 18 Y D4 4 17 OE3 D3 5 16 OE2 D2 6 15 OE1 D1 7 14 S0 D0 8 13 S1 E 9 12 S2 GND 10 11 LE CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, Texas Instruments Incorporated 1 PACKAGE CD54HC354, CD74HC354, CD74HCT354 Functional Diagram S0 14 S1 13 S2 12 D0 D1 D2 D3 D4 D5 D6 D7 8 19 7 Y 6 5 4 3 18 2 Y 1 11 LE 15 OE1 16 OE2 17 OE3 9 E TRUTH TABLE INPUTS ENABLE DATA SELECT (NOTE 1 ) OUTPUT ENABLES OUTPUTS S2 S1 S0 E OE1 OE2 OE3 Y Y X X X X H X X Z Z X X X X X H X Z Z X X X X X X L Z Z L L L L L L H D0 D0 L L L H L L H D0n D0n L L H L L L H D1 D1 L L H H L L H D1n D1n L H L L L L H D2 D2 L H L H L L H D2n D2n L H H L L L H D3 D3 L H H H L L H D3n D3n H L L L L L H D4 D4 H L L H L L H D4n D4n H L H L L L H D5 D5 H L H H L L H D5n D5n H H L L L L H D6 D6 H H L H L L H D6n D6n 2 CD54HC354, CD74HC354, CD74HCT354 TRUTH TABLE (Continued) INPUTS ENABLE DATA SELECT (NOTE 1 ) OUTPUT ENABLES OUTPUTS S2 S1 S0 E OE1 OE2 OE3 Y Y H H H L L L H D7 D7 H H H H L L H D7n D7n H = High Voltage Level (Steady State); L = Low Voltage Level (Steady State); X = Don’t Care; Z = High Impedance State (Off State); D0n...D7n = the level of steady-state inputs D0 through D7, respectively, before the most recent low-to-high transition of data control. NOTE: 1. This column shows the input address setup with LE low. Block Diagram 15 OE1 ENABLE LOGIC 16 OE2 17 OE3 E 9 8 D0 7 D1 D A T A O F R E G I S T E R S S E L E C T O R 6 D2 5 D3 4 D4 3 D5 2 1 D6 1 D7 11 LE 14 S0 13 S1 12 S2 A D D R E S S 18 8 R E G I S T E R ADDRESS DECODE 3 Y 19 Y BUFFERS CD54HC354, CD74HC354, CD74HCT354 Logic Diagram 15 OE1 16 OE2 OE3 1 OF 8 LATCHES VCC 17 P E 8 (7, 6, 5, 4, 3, 2, 1) E D0 P N 18 Y N P N GND E P N E E E VCC P 19 Y N 9 TO 7 OTHER LATCHES E OTHER 7 LATCH OUTPUTS CONNECT HERE SEL0 GND TO OTHER 7 LATCHES SEL0 SEL1 SEL2 SEL3 20 VCC 10 GND LE P N LE 14 S0 13 S1 12 S2 P N LE LE LE LE P N SL0 SL0 P N LE LE LE LE P N SL1 SL1 LE P N SL2 SL2 LE 11 LE LE LE FIGURE 1. HC/HCT354 LOGIC DIAGRAM 4 SEL4 SEL5 SEL6 SEL7 CD54HC354, CD74HC354, CD74HCT354 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Drain Current, per Output, IO For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±35mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA Thermal Resistance (Typical, Note 2) θJA (oC/W) E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 2. The package thermal impedance is calculated in accordance with JESD 51-7. DC Electrical Specifications TEST CONDITIONS PARAMETER SYMBOL VI (V) VIH - 25oC IO (mA) VCC (V) -40oC TO 85oC -55oC TO 125oC MIN TYP MAX MIN MAX MIN MAX UNITS 2 1.5 - - 1.5 - 1.5 - V 4.5 3.15 - - 3.15 - 3.15 - V 6 4.2 - - 4.2 - 4.2 - V HC TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads VIL VOH - VIH or VIL High Level Output Voltage TTL Loads (Bus Driver) Low Level Output Voltage CMOS Loads VOL VIH or VIL Low Level Output Voltage TTL Loads (Bus Driver) Input Leakage Current II VCC or GND - - 2 - - 0.5 - 0.5 - 0.5 V 4.5 - - 1.35 - 1.35 - 1.35 V 6 - - 1.8 - 1.8 - 1.8 V -0.02 2 1.9 - - 1.9 - 1.9 - V -0.02 4.5 4.4 - - 4.4 - 4.4 - V -0.02 6 5.9 - - 5.9 - 5.9 - V -6 4.5 3.98 - - 3.84 - 3.7 - V -7.8 6 5.48 - - 5.34 - 5.2 - V 0.02 2 - - 0.1 - 0.1 - 0.1 V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 0.02 6 - - 0.1 - 0.1 - 0.1 V 6 4.5 - - 0.26 - 0.33 - 0.4 V 7.8 6 - - 0.26 - 0.33 - 0.4 V - 6 - - ±0.1 - ±1 - ±1 µA 5 CD54HC354, CD74HC354, CD74HCT354 DC Electrical Specifications (Continued) TEST CONDITIONS SYMBOL VI (V) Quiescent Device Current ICC VCC or GND 0 Three-State Leakage Current IOZ VIL or VIH High Level Input Voltage VIH Low Level Input Voltage High Level Output Voltage CMOS Loads PARAMETER 25oC IO (mA) VCC (V) -40oC TO 85oC -55oC TO 125oC MIN TYP MAX MIN MAX MIN MAX UNITS 6 - - 8 - 80 - 160 µA VO = VCC or GND 6 - - ±0.5 - ±5.0 - ±10 µA - - 4.5 to 5.5 2 - - 2 - 2 - V VIL - - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 V VOH VIH or VIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V -4 4.5 3.98 - - 3.84 - 3.7 - V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 4 4.5 - - 0.26 - 0.33 - 0.4 V HCT TYPES High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VIH or VIL Low Level Output Voltage TTL Loads II VCC to GND - 5.5 - - ±0.1 - ±1 - ±1 µA ICC VCC or GND 0 5.5 - - 8 - 80 - 160 µA Additional Quiescent Device Current Per Input Pin: 1 Unit Load ∆ICC (Note 3) VCC -2.1 - 4.5 to 5.5 - 100 360 - 450 - 490 µA Three-State Leakage Current IOZ VIL or VIH VO = VCC or GND 5.5 - - ±0.5 - ±5.0 - ±10 µA Input Leakage Current Quiescent Device Current NOTE: 3. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. HCT Input Loading Table INPUT UNIT LOADS D0-D7 0.50 S0, S1, S3 0.70 OE1, OE2 0.80 OE3 0.25 LE 0.25 E 0.60 NOTE: Unit Load is ∆ICC limit specified in DC Electrical Specifications table, e.g., 360µA max at 25oC. 6 CD54HC354, CD74HC354, CD74HCT354 Prerequisite For Switching Specifications PARAMETER 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL TEST CONDITIONS VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS tPLH, tPHL - 2 80 - - 100 - 120 - ns 4.5 16 - - 20 - 24 - ns 6 14 - - 17 - 20 - ns 2 80 - - 100 - 120 - ns 4.5 16 - - 20 - 24 - ns 6 14 - - 17 - 20 - ns 2 50 - - 65 - 75 - ns 4.5 10 - - 13 - 15 - ns 6 9 - - 11 - 13 - ns 2 50 - - 65 - 75 - ns 4.5 10 - - 13 - 15 - ns 6 9 - - 11 - 13 - ns 2 45 - - 55 - 70 - ns 4.5 9 - - 11 - 14 - ns 6 8 - - 9 - 12 - ns 2 45 - - 55 - 70 - ns 4.5 9 - - 11 - 14 - ns 6 8 - - 9 - 12 - ns HC TYPES E Pulse Width LE Pulse Width tPLH, tPHL Set-up Times Dn → E tSU Set-up Times Sn → LE - tSU Hold Times Dn → E - tH Hold Times Sn → LE - - tH - HCT TYPES E Pulse Width tPLH, tPHL - 4.5 16 - - 20 - 24 - ns LE Pulse Width tPLH, tPHL - 4.5 16 - - 20 - 24 - ns Set-up Times Dn → E tSU - 4.5 10 - - 13 - 15 - ns Set-up Times Sn → LE tSU - 4.5 10 - - 13 - 15 - ns Hold Times Dn → E tH - 4.5 9 - - 11 - 14 - ns Hold Times Sn → LE tH - 4.5 9 - - 11 - 14 - ns Switching Specifications PARAMETER Input tr, tf = 6ns SYMBOL TEST CONDITIONS tPLH, tPHL CL = 50pF 25oC -40oC TO 85oC -55oC TO 125oC VCC (V) TYP MAX MAX MAX UNITS 2 - 210 265 315 ns 4.5 - 42 53 63 ns 6 - 36 45 54 ns CL = 15pF 5 18 - - - ns CL = 50pF 2 - 250 315 375 ns 4.5 - 50 63 75 ns 6 - 43 54 64 ns 5 21 - - - ns HC TYPES Propagation Delay, Dn → Y, Y Propagation Delay, E → Y, Y tPLH, tPHL CL = 15pF 7 CD54HC354, CD74HC354, CD74HCT354 Switching Specifications PARAMETER Propagation Delay, Sn → Y, Y Propagation Delay, LE → Y, Y Output Disabling Time, OEn to Y, Y Output Disabling Time, OE3 to Y, Y Output Enabling Time, OEn to Y, Y Output Enabling Time, OE3 to Y, Y Output Transition Time Input tr, tf = 6ns (Continued) SYMBOL TEST CONDITIONS tPLH, tPHL CL = 50pF tPLH, tPHL tPLZ, tPHZ tPLZ, tPHZ tPZL, tPZH tPZL, tPZH tTLH, tTHL 25oC -40oC TO 85oC -55oC TO 125oC VCC (V) TYP MAX MAX MAX UNITS 2 - 260 325 390 ns 4.5 - 52 65 78 ns 6 - 44 55 66 ns CL = 15pF 5 22 - - - ns CL = 50pF 2 - 290 365 435 ns 4.5 - 58 73 87 ns 6 - 49 62 74 ns CL = 15pF 5 24 - - - ns CL = 50pF 2 - 155 195 235 ns 4.5 - 31 39 47 ns 6 - 26 33 40 ns CL = 15pF 5 13 - - - ns CL = 50pF 2 - 155 195 235 ns 4.5 - 31 39 47 ns 6 - 26 33 40 ns CL = 15pF 5 13 - - - ns CL = 50pF 2 - 150 190 225 ns 4.5 - 30 38 45 ns 6 - 26 33 38 ns CL = 15pF 5 12, 13 - - - ns CL = 50pF 2 - 160 200 240 ns 4.5 - 32 40 48 ns 6 - 27 34 41 ns CL = 15pF 5 12, 13 - - - ns CL = 50pF 2 - 60 75 90 ns 4.5 - 12 15 18 ns 6 - 10 13 15 ns Input Capacitance CI - - - 10 10 10 pF Three-State Capacitance CO - - - 20 20 20 pF Power Dissipation Capacitance (Notes 4, 5) CPD - 5 90 - - - pF CL = 50pF 4.5 - 47 59 71 ns CL = 15pF 5 20 - - - ns CL = 50pF 4.5 - 54 68 81 ns CL = 15pF 5 23 - - - ns HCT TYPES Propagation Delay, Dn → Y, Y tPLH, tPHL Propagation Delay, E → Y, Y tPLH, tPHL 8 CD54HC354, CD74HC354, CD74HCT354 Switching Specifications Input tr, tf = 6ns (Continued) SYMBOL TEST CONDITIONS Propagation Delay, Sn → Y, Y tPLH, tPHL Propagation Delay, LE → Y, Y tPLH, tPHL Output Disabling Time, OEn to Y, Y tPLZ, tPHZ Output Disabling Time, OE3 to Y, Y tPLZ, tPHZ Output Enabling Time, OEn to Y, Y tPZL, tPZH Output Enabling Time, OE3 to Y, Y tPZL, tPZH Output Transition Time tTLH, tTHL PARAMETER 25oC -40oC TO 85oC -55oC TO 125oC VCC (V) TYP MAX MAX MAX UNITS CL = 50pF 4.5 - 59 74 89 ns CL = 15pF 5 25 - - - ns CL = 50pF 4.5 - 63 79 94 ns CL = 15pF 5 25 - - - ns CL = 50pF 4.5 - 33 41 50 ns CL = 15pF 5 13, 16 - - - ns CL = 50pF 4.5 - 39 49 59 ns CL = 15pF 5 13, 16 - - - ns CL = 50pF 4.5 - 34 43 51 ns CL = 15pF 5 14 - - - ns CL = 50pF 4.5 - 34 43 51 ns CL = 15pF 5 14 - - - ns CL = 50pF 4.5 - 12 15 18 ns Input Capacitance CIN - - - 10 10 10 pF Three-State Capacitance CO - - - 20 20 20 pF Power Dissipation Capacitance (Notes 4, 5) CPD - 5 92 - - - pF NOTES: 4. CPD is used to determine the dynamic power consumption, per device. 5. PD = VCC2 (CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage. Test Circuits and Waveforms tfCL trCL CLOCK 90% 10% tWL + tWH = I fCL tWL 50% tfCL = 6ns I fCL 3V VCC 50% 10% tWL + tWH = trCL = 6ns CLOCK 50% 2.7V 0.3V GND 1.3V 0.3V tWL tWH NOTE: Outputs should be switching from 10% VCC to 90% VCC in accordance with device truth table. For fMAX, input duty cycle = 50%. 1.3V 1.3V GND tWH NOTE: Outputs should be switching from 10% VCC to 90% VCC in accordance with device truth table. For fMAX, input duty cycle = 50%. FIGURE 2. HC CLOCK PULSE RISE AND FALL TIMES AND PULSE WIDTH FIGURE 3. HCT CLOCK PULSE RISE AND FALL TIMES AND PULSE WIDTH 9 CD54HC354, CD74HC354, CD74HCT354 Test Circuits and Waveforms tr = 6ns (Continued) tf = 6ns 90% 50% 10% INPUT GND tTLH 90% INVERTING OUTPUT tPHL FIGURE 4. HC AND HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC trCL VCC 90% GND tH(H) 3V 2.7V 1.3V 0.3V GND tH(H) tH(L) VCC DATA INPUT DATA INPUT 50% tH(L) 3V 1.3V 1.3V 1.3V GND tSU(H) tSU(H) tSU(L) tTLH 90% OUTPUT tTHL 90% 50% 10% tTLH 90% 1.3V OUTPUT tREM 3V SET, RESET OR PRESET GND tTHL 1.3V 10% FIGURE 6. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS tPHL 1.3V GND IC CL 50pF GND 90% tPLH 50% IC tSU(L) tPHL tPLH tREM VCC SET, RESET OR PRESET tfCL CLOCK INPUT 50% 10% tPLH FIGURE 5. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC tfCL trCL tTLH 1.3V 10% tPLH tPHL GND tTHL 90% 50% 10% INVERTING OUTPUT 3V 2.7V 1.3V 0.3V INPUT tTHL CLOCK INPUT tf = 6ns tr = 6ns VCC CL 50pF FIGURE 7. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS 10 CD54HC354, CD74HC354, CD74HCT354 Test Circuits and Waveforms 6ns (Continued) 6ns OUTPUT DISABLE tr VCC 90% 50% 10% OUTPUTS ENABLED OUTPUT HIGH TO OFF 50% OUTPUTS DISABLED FIGURE 8. HC THREE-STATE PROPAGATION DELAY WAVEFORM OTHER INPUTS TIED HIGH OR LOW OUTPUT DISABLE IC WITH THREESTATE OUTPUT GND 1.3V tPZH 90% OUTPUTS ENABLED OUTPUTS ENABLED 0.3 10% tPHZ tPZH 90% 3V tPZL tPLZ OUTPUT LOW TO OFF 50% OUTPUT HIGH TO OFF 6ns GND 10% tPHZ tf 2.7 1.3 tPZL tPLZ OUTPUT LOW TO OFF 6ns OUTPUT DISABLE 1.3V OUTPUTS DISABLED OUTPUTS ENABLED FIGURE 9. HCT THREE-STATE PROPAGATION DELAY WAVEFORM OUTPUT RL = 1kΩ CL 50pF VCC FOR tPLZ AND tPZL GND FOR tPHZ AND tPZH NOTE: Open drain waveforms tPLZ and tPZL are the same as those for three-state shown on the left. The test circuit is Output RL = 1kΩ to VCC, CL = 50pF. FIGURE 10. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT 11 PACKAGE OPTION ADDENDUM www.ti.com 9-Oct-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type CD54HC354F3A ACTIVE CDIP J 20 1 TBD A42 SNPB N / A for Pkg Type CD74HC354E ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74HC354EE4 ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74HCT354E ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74HCT354EE4 ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. 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